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sata_promise: handle ATAPI_NODATA ourselves
[linux-2.6/btrfs-unstable.git] / drivers / ata / sata_promise.c
blob551644a948617c65a4d24c8dd5d8ee8751653aaf
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include <asm/io.h>
47 #include "sata_promise.h"
48
49 #define DRV_NAME "sata_promise"
50 #define DRV_VERSION "1.05"
51
52
53 enum {
54 /* register offsets */
55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
65 PDC_FLASH_CTL = 0x44, /* Flash control register */
66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
72
73 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
74 (1<<8) | (1<<9) | (1<<10),
75
76 board_2037x = 0, /* FastTrak S150 TX2plus */
77 board_20319 = 1, /* FastTrak S150 TX4 */
78 board_20619 = 2, /* FastTrak TX4000 */
79 board_2057x = 3, /* SATAII150 Tx2plus */
80 board_40518 = 4, /* SATAII150 Tx4 */
81
82 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
83
84 /* Sequence counter control registers bit definitions */
85 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
86
87 /* Feature register values */
88 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
89 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
90
91 /* Device/Head register values */
92 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
93
94 /* PDC_CTLSTAT bit definitions */
95 PDC_DMA_ENABLE = (1 << 7),
96 PDC_IRQ_DISABLE = (1 << 10),
97 PDC_RESET = (1 << 11), /* HDMA reset */
98
99 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
100 ATA_FLAG_MMIO |
101 ATA_FLAG_PIO_POLLING,
102
103 /* hp->flags bits */
104 PDC_FLAG_GEN_II = (1 << 0),
105 };
106
107
108 struct pdc_port_priv {
109 u8 *pkt;
110 dma_addr_t pkt_dma;
111 };
112
113 struct pdc_host_priv {
114 unsigned long flags;
115 unsigned long port_flags[ATA_MAX_PORTS];
116 };
117
118 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
119 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
121 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
122 static void pdc_eng_timeout(struct ata_port *ap);
123 static int pdc_port_start(struct ata_port *ap);
124 static void pdc_port_stop(struct ata_port *ap);
125 static void pdc_pata_phy_reset(struct ata_port *ap);
126 static void pdc_qc_prep(struct ata_queued_cmd *qc);
127 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
128 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
129 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
130 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc);
131 static void pdc_irq_clear(struct ata_port *ap);
132 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
133 static void pdc_host_stop(struct ata_host *host);
134 static void pdc_freeze(struct ata_port *ap);
135 static void pdc_thaw(struct ata_port *ap);
136 static void pdc_error_handler(struct ata_port *ap);
137 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
138
139
140 static struct scsi_host_template pdc_ata_sht = {
141 .module = THIS_MODULE,
142 .name = DRV_NAME,
143 .ioctl = ata_scsi_ioctl,
144 .queuecommand = ata_scsi_queuecmd,
145 .can_queue = ATA_DEF_QUEUE,
146 .this_id = ATA_SHT_THIS_ID,
147 .sg_tablesize = LIBATA_MAX_PRD,
148 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
149 .emulated = ATA_SHT_EMULATED,
150 .use_clustering = ATA_SHT_USE_CLUSTERING,
151 .proc_name = DRV_NAME,
152 .dma_boundary = ATA_DMA_BOUNDARY,
153 .slave_configure = ata_scsi_slave_config,
154 .slave_destroy = ata_scsi_slave_destroy,
155 .bios_param = ata_std_bios_param,
156 };
157
158 static const struct ata_port_operations pdc_sata_ops = {
159 .port_disable = ata_port_disable,
160 .tf_load = pdc_tf_load_mmio,
161 .tf_read = ata_tf_read,
162 .check_status = ata_check_status,
163 .exec_command = pdc_exec_command_mmio,
164 .dev_select = ata_std_dev_select,
165 .check_atapi_dma = pdc_check_atapi_dma,
166
167 .qc_prep = pdc_qc_prep,
168 .qc_issue = pdc_qc_issue_prot,
169 .freeze = pdc_freeze,
170 .thaw = pdc_thaw,
171 .error_handler = pdc_error_handler,
172 .post_internal_cmd = pdc_post_internal_cmd,
173 .data_xfer = ata_mmio_data_xfer,
174 .irq_handler = pdc_interrupt,
175 .irq_clear = pdc_irq_clear,
176
177 .scr_read = pdc_sata_scr_read,
178 .scr_write = pdc_sata_scr_write,
179 .port_start = pdc_port_start,
180 .port_stop = pdc_port_stop,
181 .host_stop = pdc_host_stop,
182 };
183
184 /* First-generation chips need a more restrictive ->check_atapi_dma op */
185 static const struct ata_port_operations pdc_old_sata_ops = {
186 .port_disable = ata_port_disable,
187 .tf_load = pdc_tf_load_mmio,
188 .tf_read = ata_tf_read,
189 .check_status = ata_check_status,
190 .exec_command = pdc_exec_command_mmio,
191 .dev_select = ata_std_dev_select,
192 .check_atapi_dma = pdc_old_check_atapi_dma,
193
194 .qc_prep = pdc_qc_prep,
195 .qc_issue = pdc_qc_issue_prot,
196 .freeze = pdc_freeze,
197 .thaw = pdc_thaw,
198 .error_handler = pdc_error_handler,
199 .post_internal_cmd = pdc_post_internal_cmd,
200 .data_xfer = ata_mmio_data_xfer,
201 .irq_handler = pdc_interrupt,
202 .irq_clear = pdc_irq_clear,
203
204 .scr_read = pdc_sata_scr_read,
205 .scr_write = pdc_sata_scr_write,
206 .port_start = pdc_port_start,
207 .port_stop = pdc_port_stop,
208 .host_stop = pdc_host_stop,
209 };
210
211 static const struct ata_port_operations pdc_pata_ops = {
212 .port_disable = ata_port_disable,
213 .tf_load = pdc_tf_load_mmio,
214 .tf_read = ata_tf_read,
215 .check_status = ata_check_status,
216 .exec_command = pdc_exec_command_mmio,
217 .dev_select = ata_std_dev_select,
218 .check_atapi_dma = pdc_check_atapi_dma,
219
220 .phy_reset = pdc_pata_phy_reset,
221
222 .qc_prep = pdc_qc_prep,
223 .qc_issue = pdc_qc_issue_prot,
224 .data_xfer = ata_mmio_data_xfer,
225 .eng_timeout = pdc_eng_timeout,
226 .irq_handler = pdc_interrupt,
227 .irq_clear = pdc_irq_clear,
228
229 .port_start = pdc_port_start,
230 .port_stop = pdc_port_stop,
231 .host_stop = pdc_host_stop,
232 };
233
234 static const struct ata_port_info pdc_port_info[] = {
235 /* board_2037x */
236 {
237 .sht = &pdc_ata_sht,
238 .flags = PDC_COMMON_FLAGS,
239 .pio_mask = 0x1f, /* pio0-4 */
240 .mwdma_mask = 0x07, /* mwdma0-2 */
241 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
242 .port_ops = &pdc_old_sata_ops,
243 },
244
245 /* board_20319 */
246 {
247 .sht = &pdc_ata_sht,
248 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
249 .pio_mask = 0x1f, /* pio0-4 */
250 .mwdma_mask = 0x07, /* mwdma0-2 */
251 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
252 .port_ops = &pdc_old_sata_ops,
253 },
254
255 /* board_20619 */
256 {
257 .sht = &pdc_ata_sht,
258 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
259 .pio_mask = 0x1f, /* pio0-4 */
260 .mwdma_mask = 0x07, /* mwdma0-2 */
261 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
262 .port_ops = &pdc_pata_ops,
263 },
264
265 /* board_2057x */
266 {
267 .sht = &pdc_ata_sht,
268 .flags = PDC_COMMON_FLAGS,
269 .pio_mask = 0x1f, /* pio0-4 */
270 .mwdma_mask = 0x07, /* mwdma0-2 */
271 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
272 .port_ops = &pdc_sata_ops,
273 },
274
275 /* board_40518 */
276 {
277 .sht = &pdc_ata_sht,
278 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
279 .pio_mask = 0x1f, /* pio0-4 */
280 .mwdma_mask = 0x07, /* mwdma0-2 */
281 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
282 .port_ops = &pdc_sata_ops,
283 },
284 };
285
286 static const struct pci_device_id pdc_ata_pci_tbl[] = {
287 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
288 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
289 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
290 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
291 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
292 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
293 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
294 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
295 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
296 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
297
298 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
299 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
300 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
301 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
302 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
303 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
304
305 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
306
307 { } /* terminate list */
308 };
309
310
311 static struct pci_driver pdc_ata_pci_driver = {
312 .name = DRV_NAME,
313 .id_table = pdc_ata_pci_tbl,
314 .probe = pdc_ata_init_one,
315 .remove = ata_pci_remove_one,
316 };
317
318
319 static int pdc_port_start(struct ata_port *ap)
320 {
321 struct device *dev = ap->host->dev;
322 struct pdc_host_priv *hp = ap->host->private_data;
323 struct pdc_port_priv *pp;
324 int rc;
325
326 /* fix up port flags and cable type for SATA+PATA chips */
327 ap->flags |= hp->port_flags[ap->port_no];
328 if (ap->flags & ATA_FLAG_SATA)
329 ap->cbl = ATA_CBL_SATA;
330
331 rc = ata_port_start(ap);
332 if (rc)
333 return rc;
334
335 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
336 if (!pp) {
337 rc = -ENOMEM;
338 goto err_out;
339 }
340
341 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
342 if (!pp->pkt) {
343 rc = -ENOMEM;
344 goto err_out_kfree;
345 }
346
347 ap->private_data = pp;
348
349 /* fix up PHYMODE4 align timing */
350 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
351 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
352 unsigned int tmp;
353
354 tmp = readl(mmio + 0x014);
355 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
356 writel(tmp, mmio + 0x014);
357 }
358
359 return 0;
360
361 err_out_kfree:
362 kfree(pp);
363 err_out:
364 ata_port_stop(ap);
365 return rc;
366 }
367
368
369 static void pdc_port_stop(struct ata_port *ap)
370 {
371 struct device *dev = ap->host->dev;
372 struct pdc_port_priv *pp = ap->private_data;
373
374 ap->private_data = NULL;
375 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
376 kfree(pp);
377 ata_port_stop(ap);
378 }
379
380
381 static void pdc_host_stop(struct ata_host *host)
382 {
383 struct pdc_host_priv *hp = host->private_data;
384
385 ata_pci_host_stop(host);
386
387 kfree(hp);
388 }
389
390
391 static void pdc_reset_port(struct ata_port *ap)
392 {
393 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
394 unsigned int i;
395 u32 tmp;
396
397 for (i = 11; i > 0; i--) {
398 tmp = readl(mmio);
399 if (tmp & PDC_RESET)
400 break;
401
402 udelay(100);
403
404 tmp |= PDC_RESET;
405 writel(tmp, mmio);
406 }
407
408 tmp &= ~PDC_RESET;
409 writel(tmp, mmio);
410 readl(mmio); /* flush */
411 }
412
413 static void pdc_pata_cbl_detect(struct ata_port *ap)
414 {
415 u8 tmp;
416 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
417
418 tmp = readb(mmio);
419
420 if (tmp & 0x01) {
421 ap->cbl = ATA_CBL_PATA40;
422 ap->udma_mask &= ATA_UDMA_MASK_40C;
423 } else
424 ap->cbl = ATA_CBL_PATA80;
425 }
426
427 static void pdc_pata_phy_reset(struct ata_port *ap)
428 {
429 pdc_pata_cbl_detect(ap);
430 pdc_reset_port(ap);
431 ata_port_probe(ap);
432 ata_bus_reset(ap);
433 }
434
435 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
436 {
437 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
438 return 0xffffffffU;
439 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
440 }
441
442
443 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
444 u32 val)
445 {
446 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
447 return;
448 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
449 }
450
451 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
452 {
453 struct ata_port *ap = qc->ap;
454 dma_addr_t sg_table = ap->prd_dma;
455 unsigned int cdb_len = qc->dev->cdb_len;
456 u8 *cdb = qc->cdb;
457 struct pdc_port_priv *pp = ap->private_data;
458 u8 *buf = pp->pkt;
459 u32 *buf32 = (u32 *) buf;
460 unsigned int dev_sel, feature, nbytes;
461
462 /* set control bits (byte 0), zero delay seq id (byte 3),
463 * and seq id (byte 2)
464 */
465 switch (qc->tf.protocol) {
466 case ATA_PROT_ATAPI_DMA:
467 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
468 buf32[0] = cpu_to_le32(PDC_PKT_READ);
469 else
470 buf32[0] = 0;
471 break;
472 case ATA_PROT_ATAPI_NODATA:
473 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
474 break;
475 default:
476 BUG();
477 break;
478 }
479 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
480 buf32[2] = 0; /* no next-packet */
481
482 /* select drive */
483 if (sata_scr_valid(ap)) {
484 dev_sel = PDC_DEVICE_SATA;
485 } else {
486 dev_sel = ATA_DEVICE_OBS;
487 if (qc->dev->devno != 0)
488 dev_sel |= ATA_DEV1;
489 }
490 buf[12] = (1 << 5) | ATA_REG_DEVICE;
491 buf[13] = dev_sel;
492 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
493 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
494
495 buf[16] = (1 << 5) | ATA_REG_NSECT;
496 buf[17] = 0x00;
497 buf[18] = (1 << 5) | ATA_REG_LBAL;
498 buf[19] = 0x00;
499
500 /* set feature and byte counter registers */
501 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
502 feature = PDC_FEATURE_ATAPI_PIO;
503 /* set byte counter register to real transfer byte count */
504 nbytes = qc->nbytes;
505 if (!nbytes)
506 nbytes = qc->nsect << 9;
507 if (nbytes > 0xffff)
508 nbytes = 0xffff;
509 } else {
510 feature = PDC_FEATURE_ATAPI_DMA;
511 /* set byte counter register to 0 */
512 nbytes = 0;
513 }
514 buf[20] = (1 << 5) | ATA_REG_FEATURE;
515 buf[21] = feature;
516 buf[22] = (1 << 5) | ATA_REG_BYTEL;
517 buf[23] = nbytes & 0xFF;
518 buf[24] = (1 << 5) | ATA_REG_BYTEH;
519 buf[25] = (nbytes >> 8) & 0xFF;
520
521 /* send ATAPI packet command 0xA0 */
522 buf[26] = (1 << 5) | ATA_REG_CMD;
523 buf[27] = ATA_CMD_PACKET;
524
525 /* select drive and check DRQ */
526 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
527 buf[29] = dev_sel;
528
529 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
530 BUG_ON(cdb_len & ~0x1E);
531
532 /* append the CDB as the final part */
533 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
534 memcpy(buf+31, cdb, cdb_len);
535 }
536
537 static void pdc_qc_prep(struct ata_queued_cmd *qc)
538 {
539 struct pdc_port_priv *pp = qc->ap->private_data;
540 unsigned int i;
541
542 VPRINTK("ENTER\n");
543
544 switch (qc->tf.protocol) {
545 case ATA_PROT_DMA:
546 ata_qc_prep(qc);
547 /* fall through */
548
549 case ATA_PROT_NODATA:
550 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
551 qc->dev->devno, pp->pkt);
552
553 if (qc->tf.flags & ATA_TFLAG_LBA48)
554 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
555 else
556 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
557
558 pdc_pkt_footer(&qc->tf, pp->pkt, i);
559 break;
560
561 case ATA_PROT_ATAPI:
562 ata_qc_prep(qc);
563 break;
564
565 case ATA_PROT_ATAPI_DMA:
566 ata_qc_prep(qc);
567 /*FALLTHROUGH*/
568 case ATA_PROT_ATAPI_NODATA:
569 pdc_atapi_pkt(qc);
570 break;
571
572 default:
573 break;
574 }
575 }
576
577 static void pdc_freeze(struct ata_port *ap)
578 {
579 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
580 u32 tmp;
581
582 tmp = readl(mmio + PDC_CTLSTAT);
583 tmp |= PDC_IRQ_DISABLE;
584 tmp &= ~PDC_DMA_ENABLE;
585 writel(tmp, mmio + PDC_CTLSTAT);
586 readl(mmio + PDC_CTLSTAT); /* flush */
587 }
588
589 static void pdc_thaw(struct ata_port *ap)
590 {
591 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
592 u32 tmp;
593
594 /* clear IRQ */
595 readl(mmio + PDC_INT_SEQMASK);
596
597 /* turn IRQ back on */
598 tmp = readl(mmio + PDC_CTLSTAT);
599 tmp &= ~PDC_IRQ_DISABLE;
600 writel(tmp, mmio + PDC_CTLSTAT);
601 readl(mmio + PDC_CTLSTAT); /* flush */
602 }
603
604 static void pdc_error_handler(struct ata_port *ap)
605 {
606 ata_reset_fn_t hardreset;
607
608 if (!(ap->pflags & ATA_PFLAG_FROZEN))
609 pdc_reset_port(ap);
610
611 hardreset = NULL;
612 if (sata_scr_valid(ap))
613 hardreset = sata_std_hardreset;
614
615 /* perform recovery */
616 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
617 ata_std_postreset);
618 }
619
620 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
621 {
622 struct ata_port *ap = qc->ap;
623
624 if (qc->flags & ATA_QCFLAG_FAILED)
625 qc->err_mask |= AC_ERR_OTHER;
626
627 /* make DMA engine forget about the failed command */
628 if (qc->err_mask)
629 pdc_reset_port(ap);
630 }
631
632 static void pdc_eng_timeout(struct ata_port *ap)
633 {
634 struct ata_host *host = ap->host;
635 u8 drv_stat;
636 struct ata_queued_cmd *qc;
637 unsigned long flags;
638
639 DPRINTK("ENTER\n");
640
641 spin_lock_irqsave(&host->lock, flags);
642
643 qc = ata_qc_from_tag(ap, ap->active_tag);
644
645 switch (qc->tf.protocol) {
646 case ATA_PROT_DMA:
647 case ATA_PROT_NODATA:
648 ata_port_printk(ap, KERN_ERR, "command timeout\n");
649 drv_stat = ata_wait_idle(ap);
650 qc->err_mask |= __ac_err_mask(drv_stat);
651 break;
652
653 default:
654 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
655
656 ata_port_printk(ap, KERN_ERR,
657 "unknown timeout, cmd 0x%x stat 0x%x\n",
658 qc->tf.command, drv_stat);
659
660 qc->err_mask |= ac_err_mask(drv_stat);
661 break;
662 }
663
664 spin_unlock_irqrestore(&host->lock, flags);
665 ata_eh_qc_complete(qc);
666 DPRINTK("EXIT\n");
667 }
668
669 static inline unsigned int pdc_host_intr( struct ata_port *ap,
670 struct ata_queued_cmd *qc)
671 {
672 unsigned int handled = 0;
673 u32 tmp;
674 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
675
676 tmp = readl(mmio);
677 if (tmp & PDC_ERR_MASK) {
678 qc->err_mask |= AC_ERR_DEV;
679 pdc_reset_port(ap);
680 }
681
682 switch (qc->tf.protocol) {
683 case ATA_PROT_DMA:
684 case ATA_PROT_NODATA:
685 case ATA_PROT_ATAPI_DMA:
686 case ATA_PROT_ATAPI_NODATA:
687 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
688 ata_qc_complete(qc);
689 handled = 1;
690 break;
691
692 default:
693 ap->stats.idle_irq++;
694 break;
695 }
696
697 return handled;
698 }
699
700 static void pdc_irq_clear(struct ata_port *ap)
701 {
702 struct ata_host *host = ap->host;
703 void __iomem *mmio = host->mmio_base;
704
705 readl(mmio + PDC_INT_SEQMASK);
706 }
707
708 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
709 {
710 struct ata_host *host = dev_instance;
711 struct ata_port *ap;
712 u32 mask = 0;
713 unsigned int i, tmp;
714 unsigned int handled = 0;
715 void __iomem *mmio_base;
716
717 VPRINTK("ENTER\n");
718
719 if (!host || !host->mmio_base) {
720 VPRINTK("QUICK EXIT\n");
721 return IRQ_NONE;
722 }
723
724 mmio_base = host->mmio_base;
725
726 /* reading should also clear interrupts */
727 mask = readl(mmio_base + PDC_INT_SEQMASK);
728
729 if (mask == 0xffffffff) {
730 VPRINTK("QUICK EXIT 2\n");
731 return IRQ_NONE;
732 }
733
734 spin_lock(&host->lock);
735
736 mask &= 0xffff; /* only 16 tags possible */
737 if (!mask) {
738 VPRINTK("QUICK EXIT 3\n");
739 goto done_irq;
740 }
741
742 writel(mask, mmio_base + PDC_INT_SEQMASK);
743
744 for (i = 0; i < host->n_ports; i++) {
745 VPRINTK("port %u\n", i);
746 ap = host->ports[i];
747 tmp = mask & (1 << (i + 1));
748 if (tmp && ap &&
749 !(ap->flags & ATA_FLAG_DISABLED)) {
750 struct ata_queued_cmd *qc;
751
752 qc = ata_qc_from_tag(ap, ap->active_tag);
753 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
754 handled += pdc_host_intr(ap, qc);
755 }
756 }
757
758 VPRINTK("EXIT\n");
759
760 done_irq:
761 spin_unlock(&host->lock);
762 return IRQ_RETVAL(handled);
763 }
764
765 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
766 {
767 struct ata_port *ap = qc->ap;
768 struct pdc_port_priv *pp = ap->private_data;
769 unsigned int port_no = ap->port_no;
770 u8 seq = (u8) (port_no + 1);
771
772 VPRINTK("ENTER, ap %p\n", ap);
773
774 writel(0x00000001, ap->host->mmio_base + (seq * 4));
775 readl(ap->host->mmio_base + (seq * 4)); /* flush */
776
777 pp->pkt[2] = seq;
778 wmb(); /* flush PRD, pkt writes */
779 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
780 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
781 }
782
783 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
784 {
785 switch (qc->tf.protocol) {
786 case ATA_PROT_ATAPI_NODATA:
787 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
788 break;
789 /*FALLTHROUGH*/
790 case ATA_PROT_ATAPI_DMA:
791 case ATA_PROT_DMA:
792 case ATA_PROT_NODATA:
793 pdc_packet_start(qc);
794 return 0;
795
796 default:
797 break;
798 }
799
800 return ata_qc_issue_prot(qc);
801 }
802
803 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
804 {
805 WARN_ON (tf->protocol == ATA_PROT_DMA ||
806 tf->protocol == ATA_PROT_NODATA);
807 ata_tf_load(ap, tf);
808 }
809
810
811 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
812 {
813 WARN_ON (tf->protocol == ATA_PROT_DMA ||
814 tf->protocol == ATA_PROT_NODATA);
815 ata_exec_command(ap, tf);
816 }
817
818 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
819 {
820 u8 *scsicmd = qc->scsicmd->cmnd;
821 int pio = 1; /* atapi dma off by default */
822
823 /* Whitelist commands that may use DMA. */
824 switch (scsicmd[0]) {
825 case WRITE_12:
826 case WRITE_10:
827 case WRITE_6:
828 case READ_12:
829 case READ_10:
830 case READ_6:
831 case 0xad: /* READ_DVD_STRUCTURE */
832 case 0xbe: /* READ_CD */
833 pio = 0;
834 }
835 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
836 if (scsicmd[0] == WRITE_10) {
837 unsigned int lba;
838 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
839 if (lba >= 0xFFFF4FA2)
840 pio = 1;
841 }
842 return pio;
843 }
844
845 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc)
846 {
847 struct ata_port *ap = qc->ap;
848
849 /* First generation chips cannot use ATAPI DMA on SATA ports */
850 if (sata_scr_valid(ap))
851 return 1;
852 return pdc_check_atapi_dma(qc);
853 }
854
855 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
856 {
857 port->cmd_addr = base;
858 port->data_addr = base;
859 port->feature_addr =
860 port->error_addr = base + 0x4;
861 port->nsect_addr = base + 0x8;
862 port->lbal_addr = base + 0xc;
863 port->lbam_addr = base + 0x10;
864 port->lbah_addr = base + 0x14;
865 port->device_addr = base + 0x18;
866 port->command_addr =
867 port->status_addr = base + 0x1c;
868 port->altstatus_addr =
869 port->ctl_addr = base + 0x38;
870 }
871
872
873 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
874 {
875 void __iomem *mmio = pe->mmio_base;
876 struct pdc_host_priv *hp = pe->private_data;
877 int hotplug_offset;
878 u32 tmp;
879
880 if (hp->flags & PDC_FLAG_GEN_II)
881 hotplug_offset = PDC2_SATA_PLUG_CSR;
882 else
883 hotplug_offset = PDC_SATA_PLUG_CSR;
884
885 /*
886 * Except for the hotplug stuff, this is voodoo from the
887 * Promise driver. Label this entire section
888 * "TODO: figure out why we do this"
889 */
890
891 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
892 tmp = readl(mmio + PDC_FLASH_CTL);
893 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
894 if (!(hp->flags & PDC_FLAG_GEN_II))
895 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
896 writel(tmp, mmio + PDC_FLASH_CTL);
897
898 /* clear plug/unplug flags for all ports */
899 tmp = readl(mmio + hotplug_offset);
900 writel(tmp | 0xff, mmio + hotplug_offset);
901
902 /* mask plug/unplug ints */
903 tmp = readl(mmio + hotplug_offset);
904 writel(tmp | 0xff0000, mmio + hotplug_offset);
905
906 /* don't initialise TBG or SLEW on 2nd generation chips */
907 if (hp->flags & PDC_FLAG_GEN_II)
908 return;
909
910 /* reduce TBG clock to 133 Mhz. */
911 tmp = readl(mmio + PDC_TBG_MODE);
912 tmp &= ~0x30000; /* clear bit 17, 16*/
913 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
914 writel(tmp, mmio + PDC_TBG_MODE);
915
916 readl(mmio + PDC_TBG_MODE); /* flush */
917 msleep(10);
918
919 /* adjust slew rate control register. */
920 tmp = readl(mmio + PDC_SLEW_CTL);
921 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
922 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
923 writel(tmp, mmio + PDC_SLEW_CTL);
924 }
925
926 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
927 {
928 static int printed_version;
929 struct ata_probe_ent *probe_ent = NULL;
930 struct pdc_host_priv *hp;
931 unsigned long base;
932 void __iomem *mmio_base;
933 unsigned int board_idx = (unsigned int) ent->driver_data;
934 int pci_dev_busy = 0;
935 int rc;
936 u8 tmp;
937
938 if (!printed_version++)
939 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
940
941 rc = pci_enable_device(pdev);
942 if (rc)
943 return rc;
944
945 rc = pci_request_regions(pdev, DRV_NAME);
946 if (rc) {
947 pci_dev_busy = 1;
948 goto err_out;
949 }
950
951 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
952 if (rc)
953 goto err_out_regions;
954 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
955 if (rc)
956 goto err_out_regions;
957
958 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
959 if (probe_ent == NULL) {
960 rc = -ENOMEM;
961 goto err_out_regions;
962 }
963
964 probe_ent->dev = pci_dev_to_dev(pdev);
965 INIT_LIST_HEAD(&probe_ent->node);
966
967 mmio_base = pci_iomap(pdev, 3, 0);
968 if (mmio_base == NULL) {
969 rc = -ENOMEM;
970 goto err_out_free_ent;
971 }
972 base = (unsigned long) mmio_base;
973
974 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
975 if (hp == NULL) {
976 rc = -ENOMEM;
977 goto err_out_free_ent;
978 }
979
980 probe_ent->private_data = hp;
981
982 probe_ent->sht = pdc_port_info[board_idx].sht;
983 probe_ent->port_flags = pdc_port_info[board_idx].flags;
984 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
985 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
986 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
987 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
988
989 probe_ent->irq = pdev->irq;
990 probe_ent->irq_flags = IRQF_SHARED;
991 probe_ent->mmio_base = mmio_base;
992
993 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
994 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
995
996 probe_ent->port[0].scr_addr = base + 0x400;
997 probe_ent->port[1].scr_addr = base + 0x500;
998
999 /* notice 4-port boards */
1000 switch (board_idx) {
1001 case board_40518:
1002 hp->flags |= PDC_FLAG_GEN_II;
1003 /* Fall through */
1004 case board_20319:
1005 probe_ent->n_ports = 4;
1006
1007 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
1008 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
1009
1010 probe_ent->port[2].scr_addr = base + 0x600;
1011 probe_ent->port[3].scr_addr = base + 0x700;
1012 break;
1013 case board_2057x:
1014 hp->flags |= PDC_FLAG_GEN_II;
1015 /* Fall through */
1016 case board_2037x:
1017 /* TX2plus boards also have a PATA port */
1018 tmp = readb(mmio_base + PDC_FLASH_CTL+1);
1019 if (!(tmp & 0x80)) {
1020 probe_ent->n_ports = 3;
1021 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
1022 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
1023 printk(KERN_INFO DRV_NAME " PATA port found\n");
1024 } else
1025 probe_ent->n_ports = 2;
1026 hp->port_flags[0] = ATA_FLAG_SATA;
1027 hp->port_flags[1] = ATA_FLAG_SATA;
1028 break;
1029 case board_20619:
1030 probe_ent->n_ports = 4;
1031
1032 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
1033 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
1034
1035 probe_ent->port[2].scr_addr = base + 0x600;
1036 probe_ent->port[3].scr_addr = base + 0x700;
1037 break;
1038 default:
1039 BUG();
1040 break;
1041 }
1042
1043 pci_set_master(pdev);
1044
1045 /* initialize adapter */
1046 pdc_host_init(board_idx, probe_ent);
1047
1048 /* FIXME: Need any other frees than hp? */
1049 if (!ata_device_add(probe_ent))
1050 kfree(hp);
1051
1052 kfree(probe_ent);
1053
1054 return 0;
1055
1056 err_out_free_ent:
1057 kfree(probe_ent);
1058 err_out_regions:
1059 pci_release_regions(pdev);
1060 err_out:
1061 if (!pci_dev_busy)
1062 pci_disable_device(pdev);
1063 return rc;
1064 }
1065
1066
1067 static int __init pdc_ata_init(void)
1068 {
1069 return pci_register_driver(&pdc_ata_pci_driver);
1070 }
1071
1072
1073 static void __exit pdc_ata_exit(void)
1074 {
1075 pci_unregister_driver(&pdc_ata_pci_driver);
1076 }
1077
1078
1079 MODULE_AUTHOR("Jeff Garzik");
1080 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1081 MODULE_LICENSE("GPL");
1082 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1083 MODULE_VERSION(DRV_VERSION);
1084
1085 module_init(pdc_ata_init);
1086 module_exit(pdc_ata_exit);
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