drivers/net/dsa/mv88e6xxx.c

   1 /*
   2  * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
   3  * Copyright (c) 2008 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/if_bridge.h>
  13 #include <linux/jiffies.h>
  14 #include <linux/list.h>
  15 #include <linux/module.h>
  16 #include <linux/netdevice.h>
  17 #include <linux/phy.h>
  18 #include <net/dsa.h>
  19 #include "mv88e6xxx.h"
  20
  21 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
  22  * use all 32 SMI bus addresses on its SMI bus, and all switch registers
  23  * will be directly accessible on some {device address,register address}
  24  * pair.  If the ADDR[4:0] pins are not strapped to zero, the switch
  25  * will only respond to SMI transactions to that specific address, and
  26  * an indirect addressing mechanism needs to be used to access its
  27  * registers.
  28  */
  29 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
  30 {
  31         int ret;
  32         int i;
  33
  34         for (i = 0; i < 16; i++) {
  35                 ret = mdiobus_read(bus, sw_addr, 0);
  36                 if (ret < 0)
  37                         return ret;
  38
  39                 if ((ret & 0x8000) == 0)
  40                         return 0;
  41         }
  42
  43         return -ETIMEDOUT;
  44 }
  45
  46 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
  47 {
  48         int ret;
  49
  50         if (sw_addr == 0)
  51                 return mdiobus_read(bus, addr, reg);
  52
  53         /* Wait for the bus to become free. */
  54         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
  55         if (ret < 0)
  56                 return ret;
  57
  58         /* Transmit the read command. */
  59         ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg);
  60         if (ret < 0)
  61                 return ret;
  62
  63         /* Wait for the read command to complete. */
  64         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
  65         if (ret < 0)
  66                 return ret;
  67
  68         /* Read the data. */
  69         ret = mdiobus_read(bus, sw_addr, 1);
  70         if (ret < 0)
  71                 return ret;
  72
  73         return ret & 0xffff;
  74 }
  75
  76 /* Must be called with SMI mutex held */
  77 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
  78 {
  79         struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  80         int ret;
  81
  82         if (bus == NULL)
  83                 return -EINVAL;
  84
  85         ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
  86         if (ret < 0)
  87                 return ret;
  88
  89         dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  90                 addr, reg, ret);
  91
  92         return ret;
  93 }
  94
  95 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
  96 {
  97         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
  98         int ret;
  99
 100         mutex_lock(&ps->smi_mutex);
 101         ret = _mv88e6xxx_reg_read(ds, addr, reg);
 102         mutex_unlock(&ps->smi_mutex);
 103
 104         return ret;
 105 }
 106
 107 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
 108                           int reg, u16 val)
 109 {
 110         int ret;
 111
 112         if (sw_addr == 0)
 113                 return mdiobus_write(bus, addr, reg, val);
 114
 115         /* Wait for the bus to become free. */
 116         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
 117         if (ret < 0)
 118                 return ret;
 119
 120         /* Transmit the data to write. */
 121         ret = mdiobus_write(bus, sw_addr, 1, val);
 122         if (ret < 0)
 123                 return ret;
 124
 125         /* Transmit the write command. */
 126         ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg);
 127         if (ret < 0)
 128                 return ret;
 129
 130         /* Wait for the write command to complete. */
 131         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
 132         if (ret < 0)
 133                 return ret;
 134
 135         return 0;
 136 }
 137
 138 /* Must be called with SMI mutex held */
 139 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
 140                                 u16 val)
 141 {
 142         struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
 143
 144         if (bus == NULL)
 145                 return -EINVAL;
 146
 147         dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 148                 addr, reg, val);
 149
 150         return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
 151 }
 152
 153 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
 154 {
 155         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 156         int ret;
 157
 158         mutex_lock(&ps->smi_mutex);
 159         ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
 160         mutex_unlock(&ps->smi_mutex);
 161
 162         return ret;
 163 }
 164
 165 int mv88e6xxx_config_prio(struct dsa_switch *ds)
 166 {
 167         /* Configure the IP ToS mapping registers. */
 168         REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
 169         REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
 170         REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
 171         REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
 172         REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
 173         REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
 174         REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
 175         REG_WRITE(REG_GLOBAL, 0x17, 0xffff);
 176
 177         /* Configure the IEEE 802.1p priority mapping register. */
 178         REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);
 179
 180         return 0;
 181 }
 182
 183 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
 184 {
 185         REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
 186         REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
 187         REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
 188
 189         return 0;
 190 }
 191
 192 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
 193 {
 194         int i;
 195         int ret;
 196
 197         for (i = 0; i < 6; i++) {
 198                 int j;
 199
 200                 /* Write the MAC address byte. */
 201                 REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 | (i << 8) | addr[i]);
 202
 203                 /* Wait for the write to complete. */
 204                 for (j = 0; j < 16; j++) {
 205                         ret = REG_READ(REG_GLOBAL2, 0x0d);
 206                         if ((ret & 0x8000) == 0)
 207                                 break;
 208                 }
 209                 if (j == 16)
 210                         return -ETIMEDOUT;
 211         }
 212
 213         return 0;
 214 }
 215
 216 int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
 217 {
 218         if (addr >= 0)
 219                 return mv88e6xxx_reg_read(ds, addr, regnum);
 220         return 0xffff;
 221 }
 222
 223 int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
 224 {
 225         if (addr >= 0)
 226                 return mv88e6xxx_reg_write(ds, addr, regnum, val);
 227         return 0;
 228 }
 229
 230 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
 231 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
 232 {
 233         int ret;
 234         unsigned long timeout;
 235
 236         ret = REG_READ(REG_GLOBAL, 0x04);
 237         REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);
 238
 239         timeout = jiffies + 1 * HZ;
 240         while (time_before(jiffies, timeout)) {
 241                 ret = REG_READ(REG_GLOBAL, 0x00);
 242                 usleep_range(1000, 2000);
 243                 if ((ret & 0xc000) != 0xc000)
 244                         return 0;
 245         }
 246
 247         return -ETIMEDOUT;
 248 }
 249
 250 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
 251 {
 252         int ret;
 253         unsigned long timeout;
 254
 255         ret = REG_READ(REG_GLOBAL, 0x04);
 256         REG_WRITE(REG_GLOBAL, 0x04, ret | 0x4000);
 257
 258         timeout = jiffies + 1 * HZ;
 259         while (time_before(jiffies, timeout)) {
 260                 ret = REG_READ(REG_GLOBAL, 0x00);
 261                 usleep_range(1000, 2000);
 262                 if ((ret & 0xc000) == 0xc000)
 263                         return 0;
 264         }
 265
 266         return -ETIMEDOUT;
 267 }
 268
 269 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 270 {
 271         struct mv88e6xxx_priv_state *ps;
 272
 273         ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
 274         if (mutex_trylock(&ps->ppu_mutex)) {
 275                 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
 276
 277                 if (mv88e6xxx_ppu_enable(ds) == 0)
 278                         ps->ppu_disabled = 0;
 279                 mutex_unlock(&ps->ppu_mutex);
 280         }
 281 }
 282
 283 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 284 {
 285         struct mv88e6xxx_priv_state *ps = (void *)_ps;
 286
 287         schedule_work(&ps->ppu_work);
 288 }
 289
 290 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
 291 {
 292         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 293         int ret;
 294
 295         mutex_lock(&ps->ppu_mutex);
 296
 297         /* If the PHY polling unit is enabled, disable it so that
 298          * we can access the PHY registers.  If it was already
 299          * disabled, cancel the timer that is going to re-enable
 300          * it.
 301          */
 302         if (!ps->ppu_disabled) {
 303                 ret = mv88e6xxx_ppu_disable(ds);
 304                 if (ret < 0) {
 305                         mutex_unlock(&ps->ppu_mutex);
 306                         return ret;
 307                 }
 308                 ps->ppu_disabled = 1;
 309         } else {
 310                 del_timer(&ps->ppu_timer);
 311                 ret = 0;
 312         }
 313
 314         return ret;
 315 }
 316
 317 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
 318 {
 319         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 320
 321         /* Schedule a timer to re-enable the PHY polling unit. */
 322         mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
 323         mutex_unlock(&ps->ppu_mutex);
 324 }
 325
 326 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
 327 {
 328         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 329
 330         mutex_init(&ps->ppu_mutex);
 331         INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
 332         init_timer(&ps->ppu_timer);
 333         ps->ppu_timer.data = (unsigned long)ps;
 334         ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 335 }
 336
 337 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
 338 {
 339         int ret;
 340
 341         ret = mv88e6xxx_ppu_access_get(ds);
 342         if (ret >= 0) {
 343                 ret = mv88e6xxx_reg_read(ds, addr, regnum);
 344                 mv88e6xxx_ppu_access_put(ds);
 345         }
 346
 347         return ret;
 348 }
 349
 350 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
 351                             int regnum, u16 val)
 352 {
 353         int ret;
 354
 355         ret = mv88e6xxx_ppu_access_get(ds);
 356         if (ret >= 0) {
 357                 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
 358                 mv88e6xxx_ppu_access_put(ds);
 359         }
 360
 361         return ret;
 362 }
 363 #endif
 364
 365 void mv88e6xxx_poll_link(struct dsa_switch *ds)
 366 {
 367         int i;
 368
 369         for (i = 0; i < DSA_MAX_PORTS; i++) {
 370                 struct net_device *dev;
 371                 int uninitialized_var(port_status);
 372                 int link;
 373                 int speed;
 374                 int duplex;
 375                 int fc;
 376
 377                 dev = ds->ports[i];
 378                 if (dev == NULL)
 379                         continue;
 380
 381                 link = 0;
 382                 if (dev->flags & IFF_UP) {
 383                         port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
 384                         if (port_status < 0)
 385                                 continue;
 386
 387                         link = !!(port_status & 0x0800);
 388                 }
 389
 390                 if (!link) {
 391                         if (netif_carrier_ok(dev)) {
 392                                 netdev_info(dev, "link down\n");
 393                                 netif_carrier_off(dev);
 394                         }
 395                         continue;
 396                 }
 397
 398                 switch (port_status & 0x0300) {
 399                 case 0x0000:
 400                         speed = 10;
 401                         break;
 402                 case 0x0100:
 403                         speed = 100;
 404                         break;
 405                 case 0x0200:
 406                         speed = 1000;
 407                         break;
 408                 default:
 409                         speed = -1;
 410                         break;
 411                 }
 412                 duplex = (port_status & 0x0400) ? 1 : 0;
 413                 fc = (port_status & 0x8000) ? 1 : 0;
 414
 415                 if (!netif_carrier_ok(dev)) {
 416                         netdev_info(dev,
 417                                     "link up, %d Mb/s, %s duplex, flow control %sabled\n",
 418                                     speed,
 419                                     duplex ? "full" : "half",
 420                                     fc ? "en" : "dis");
 421                         netif_carrier_on(dev);
 422                 }
 423         }
 424 }
 425
 426 static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
 427 {
 428         int ret;
 429         int i;
 430
 431         for (i = 0; i < 10; i++) {
 432                 ret = REG_READ(REG_GLOBAL, 0x1d);
 433                 if ((ret & 0x8000) == 0)
 434                         return 0;
 435         }
 436
 437         return -ETIMEDOUT;
 438 }
 439
 440 static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
 441 {
 442         int ret;
 443
 444         /* Snapshot the hardware statistics counters for this port. */
 445         REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 | port);
 446
 447         /* Wait for the snapshotting to complete. */
 448         ret = mv88e6xxx_stats_wait(ds);
 449         if (ret < 0)
 450                 return ret;
 451
 452         return 0;
 453 }
 454
 455 static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
 456 {
 457         u32 _val;
 458         int ret;
 459
 460         *val = 0;
 461
 462         ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 | stat);
 463         if (ret < 0)
 464                 return;
 465
 466         ret = mv88e6xxx_stats_wait(ds);
 467         if (ret < 0)
 468                 return;
 469
 470         ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
 471         if (ret < 0)
 472                 return;
 473
 474         _val = ret << 16;
 475
 476         ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
 477         if (ret < 0)
 478                 return;
 479
 480         *val = _val | ret;
 481 }
 482
 483 void mv88e6xxx_get_strings(struct dsa_switch *ds,
 484                            int nr_stats, struct mv88e6xxx_hw_stat *stats,
 485                            int port, uint8_t *data)
 486 {
 487         int i;
 488
 489         for (i = 0; i < nr_stats; i++) {
 490                 memcpy(data + i * ETH_GSTRING_LEN,
 491                        stats[i].string, ETH_GSTRING_LEN);
 492         }
 493 }
 494
 495 void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
 496                                  int nr_stats, struct mv88e6xxx_hw_stat *stats,
 497                                  int port, uint64_t *data)
 498 {
 499         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 500         int ret;
 501         int i;
 502
 503         mutex_lock(&ps->stats_mutex);
 504
 505         ret = mv88e6xxx_stats_snapshot(ds, port);
 506         if (ret < 0) {
 507                 mutex_unlock(&ps->stats_mutex);
 508                 return;
 509         }
 510
 511         /* Read each of the counters. */
 512         for (i = 0; i < nr_stats; i++) {
 513                 struct mv88e6xxx_hw_stat *s = stats + i;
 514                 u32 low;
 515                 u32 high = 0;
 516
 517                 if (s->reg >= 0x100) {
 518                         int ret;
 519
 520                         ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
 521                                                  s->reg - 0x100);
 522                         if (ret < 0)
 523                                 goto error;
 524                         low = ret;
 525                         if (s->sizeof_stat == 4) {
 526                                 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
 527                                                          s->reg - 0x100 + 1);
 528                                 if (ret < 0)
 529                                         goto error;
 530                                 high = ret;
 531                         }
 532                         data[i] = (((u64)high) << 16) | low;
 533                         continue;
 534                 }
 535                 mv88e6xxx_stats_read(ds, s->reg, &low);
 536                 if (s->sizeof_stat == 8)
 537                         mv88e6xxx_stats_read(ds, s->reg + 1, &high);
 538
 539                 data[i] = (((u64)high) << 32) | low;
 540         }
 541 error:
 542         mutex_unlock(&ps->stats_mutex);
 543 }
 544
 545 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 546 {
 547         return 32 * sizeof(u16);
 548 }
 549
 550 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 551                         struct ethtool_regs *regs, void *_p)
 552 {
 553         u16 *p = _p;
 554         int i;
 555
 556         regs->version = 0;
 557
 558         memset(p, 0xff, 32 * sizeof(u16));
 559
 560         for (i = 0; i < 32; i++) {
 561                 int ret;
 562
 563                 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
 564                 if (ret >= 0)
 565                         p[i] = ret;
 566         }
 567 }
 568
 569 #ifdef CONFIG_NET_DSA_HWMON
 570
 571 int  mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
 572 {
 573         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 574         int ret;
 575         int val;
 576
 577         *temp = 0;
 578
 579         mutex_lock(&ps->phy_mutex);
 580
 581         ret = mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
 582         if (ret < 0)
 583                 goto error;
 584
 585         /* Enable temperature sensor */
 586         ret = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
 587         if (ret < 0)
 588                 goto error;
 589
 590         ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
 591         if (ret < 0)
 592                 goto error;
 593
 594         /* Wait for temperature to stabilize */
 595         usleep_range(10000, 12000);
 596
 597         val = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
 598         if (val < 0) {
 599                 ret = val;
 600                 goto error;
 601         }
 602
 603         /* Disable temperature sensor */
 604         ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
 605         if (ret < 0)
 606                 goto error;
 607
 608         *temp = ((val & 0x1f) - 5) * 5;
 609
 610 error:
 611         mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
 612         mutex_unlock(&ps->phy_mutex);
 613         return ret;
 614 }
 615 #endif /* CONFIG_NET_DSA_HWMON */
 616
 617 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
 618 {
 619         unsigned long timeout = jiffies + HZ / 10;
 620
 621         while (time_before(jiffies, timeout)) {
 622                 int ret;
 623
 624                 ret = REG_READ(reg, offset);
 625                 if (!(ret & mask))
 626                         return 0;
 627
 628                 usleep_range(1000, 2000);
 629         }
 630         return -ETIMEDOUT;
 631 }
 632
 633 int mv88e6xxx_phy_wait(struct dsa_switch *ds)
 634 {
 635         return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x18, 0x8000);
 636 }
 637
 638 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
 639 {
 640         return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x0800);
 641 }
 642
 643 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
 644 {
 645         return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x8000);
 646 }
 647
 648 /* Must be called with SMI lock held */
 649 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
 650 {
 651         unsigned long timeout = jiffies + HZ / 10;
 652
 653         while (time_before(jiffies, timeout)) {
 654                 int ret;
 655
 656                 ret = _mv88e6xxx_reg_read(ds, reg, offset);
 657                 if (ret < 0)
 658                         return ret;
 659                 if (!(ret & mask))
 660                         return 0;
 661
 662                 usleep_range(1000, 2000);
 663         }
 664         return -ETIMEDOUT;
 665 }
 666
 667 /* Must be called with SMI lock held */
 668 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
 669 {
 670         return _mv88e6xxx_wait(ds, REG_GLOBAL, 0x0b, ATU_BUSY);
 671 }
 672
 673 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum)
 674 {
 675         int ret;
 676
 677         REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 | (addr << 5) | regnum);
 678
 679         ret = mv88e6xxx_phy_wait(ds);
 680         if (ret < 0)
 681                 return ret;
 682
 683         return REG_READ(REG_GLOBAL2, 0x19);
 684 }
 685
 686 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
 687                                  u16 val)
 688 {
 689         REG_WRITE(REG_GLOBAL2, 0x19, val);
 690         REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 | (addr << 5) | regnum);
 691
 692         return mv88e6xxx_phy_wait(ds);
 693 }
 694
 695 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
 696 {
 697         int reg;
 698
 699         reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
 700         if (reg < 0)
 701                 return -EOPNOTSUPP;
 702
 703         e->eee_enabled = !!(reg & 0x0200);
 704         e->tx_lpi_enabled = !!(reg & 0x0100);
 705
 706         reg = REG_READ(REG_PORT(port), 0);
 707         e->eee_active = !!(reg & 0x0040);
 708
 709         return 0;
 710 }
 711
 712 static int mv88e6xxx_eee_enable_set(struct dsa_switch *ds, int port,
 713                                     bool eee_enabled, bool tx_lpi_enabled)
 714 {
 715         int reg, nreg;
 716
 717         reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
 718         if (reg < 0)
 719                 return reg;
 720
 721         nreg = reg & ~0x0300;
 722         if (eee_enabled)
 723                 nreg |= 0x0200;
 724         if (tx_lpi_enabled)
 725                 nreg |= 0x0100;
 726
 727         if (nreg != reg)
 728                 return mv88e6xxx_phy_write_indirect(ds, port, 16, nreg);
 729
 730         return 0;
 731 }
 732
 733 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 734                       struct phy_device *phydev, struct ethtool_eee *e)
 735 {
 736         int ret;
 737
 738         ret = mv88e6xxx_eee_enable_set(ds, port, e->eee_enabled,
 739                                        e->tx_lpi_enabled);
 740         if (ret)
 741                 return -EOPNOTSUPP;
 742
 743         return 0;
 744 }
 745
 746 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
 747 {
 748         int ret;
 749
 750         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid);
 751         if (ret < 0)
 752                 return ret;
 753
 754         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x0b, cmd);
 755         if (ret < 0)
 756                 return ret;
 757
 758         return _mv88e6xxx_atu_wait(ds);
 759 }
 760
 761 static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
 762 {
 763         int ret;
 764
 765         ret = _mv88e6xxx_atu_wait(ds);
 766         if (ret < 0)
 767                 return ret;
 768
 769         return _mv88e6xxx_atu_cmd(ds, fid, ATU_CMD_FLUSH_NONSTATIC_FID);
 770 }
 771
 772 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
 773 {
 774         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 775         int reg, ret;
 776         u8 oldstate;
 777
 778         mutex_lock(&ps->smi_mutex);
 779
 780         reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), 0x04);
 781         if (reg < 0)
 782                 goto abort;
 783
 784         oldstate = reg & PSTATE_MASK;
 785         if (oldstate != state) {
 786                 /* Flush forwarding database if we're moving a port
 787                  * from Learning or Forwarding state to Disabled or
 788                  * Blocking or Listening state.
 789                  */
 790                 if (oldstate >= PSTATE_LEARNING && state <= PSTATE_BLOCKING) {
 791                         ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
 792                         if (ret)
 793                                 goto abort;
 794                 }
 795                 reg = (reg & ~PSTATE_MASK) | state;
 796                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x04, reg);
 797         }
 798
 799 abort:
 800         mutex_unlock(&ps->smi_mutex);
 801         return ret;
 802 }
 803
 804 /* Must be called with smi lock held */
 805 static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
 806 {
 807         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 808         u8 fid = ps->fid[port];
 809         u16 reg = fid << 12;
 810
 811         if (dsa_is_cpu_port(ds, port))
 812                 reg |= ds->phys_port_mask;
 813         else
 814                 reg |= (ps->bridge_mask[fid] |
 815                        (1 << dsa_upstream_port(ds))) & ~(1 << port);
 816
 817         return _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x06, reg);
 818 }
 819
 820 /* Must be called with smi lock held */
 821 static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
 822 {
 823         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 824         int port;
 825         u32 mask;
 826         int ret;
 827
 828         mask = ds->phys_port_mask;
 829         while (mask) {
 830                 port = __ffs(mask);
 831                 mask &= ~(1 << port);
 832                 if (ps->fid[port] != fid)
 833                         continue;
 834
 835                 ret = _mv88e6xxx_update_port_config(ds, port);
 836                 if (ret)
 837                         return ret;
 838         }
 839
 840         return _mv88e6xxx_flush_fid(ds, fid);
 841 }
 842
 843 /* Bridge handling functions */
 844
 845 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
 846 {
 847         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 848         int ret = 0;
 849         u32 nmask;
 850         int fid;
 851
 852         /* If the bridge group is not empty, join that group.
 853          * Otherwise create a new group.
 854          */
 855         fid = ps->fid[port];
 856         nmask = br_port_mask & ~(1 << port);
 857         if (nmask)
 858                 fid = ps->fid[__ffs(nmask)];
 859
 860         nmask = ps->bridge_mask[fid] | (1 << port);
 861         if (nmask != br_port_mask) {
 862                 netdev_err(ds->ports[port],
 863                            "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
 864                            fid, br_port_mask, nmask);
 865                 return -EINVAL;
 866         }
 867
 868         mutex_lock(&ps->smi_mutex);
 869
 870         ps->bridge_mask[fid] = br_port_mask;
 871
 872         if (fid != ps->fid[port]) {
 873                 ps->fid_mask |= 1 << ps->fid[port];
 874                 ps->fid[port] = fid;
 875                 ret = _mv88e6xxx_update_bridge_config(ds, fid);
 876         }
 877
 878         mutex_unlock(&ps->smi_mutex);
 879
 880         return ret;
 881 }
 882
 883 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
 884 {
 885         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 886         u8 fid, newfid;
 887         int ret;
 888
 889         fid = ps->fid[port];
 890
 891         if (ps->bridge_mask[fid] != br_port_mask) {
 892                 netdev_err(ds->ports[port],
 893                            "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
 894                            fid, br_port_mask, ps->bridge_mask[fid]);
 895                 return -EINVAL;
 896         }
 897
 898         /* If the port was the last port of a bridge, we are done.
 899          * Otherwise assign a new fid to the port, and fix up
 900          * the bridge configuration.
 901          */
 902         if (br_port_mask == (1 << port))
 903                 return 0;
 904
 905         mutex_lock(&ps->smi_mutex);
 906
 907         newfid = __ffs(ps->fid_mask);
 908         ps->fid[port] = newfid;
 909         ps->fid_mask &= (1 << newfid);
 910         ps->bridge_mask[fid] &= ~(1 << port);
 911         ps->bridge_mask[newfid] = 1 << port;
 912
 913         ret = _mv88e6xxx_update_bridge_config(ds, fid);
 914         if (!ret)
 915                 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
 916
 917         mutex_unlock(&ps->smi_mutex);
 918
 919         return ret;
 920 }
 921
 922 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
 923 {
 924         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 925         int stp_state;
 926
 927         switch (state) {
 928         case BR_STATE_DISABLED:
 929                 stp_state = PSTATE_DISABLED;
 930                 break;
 931         case BR_STATE_BLOCKING:
 932         case BR_STATE_LISTENING:
 933                 stp_state = PSTATE_BLOCKING;
 934                 break;
 935         case BR_STATE_LEARNING:
 936                 stp_state = PSTATE_LEARNING;
 937                 break;
 938         case BR_STATE_FORWARDING:
 939         default:
 940                 stp_state = PSTATE_FORWARDING;
 941                 break;
 942         }
 943
 944         netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
 945
 946         /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
 947          * so we can not update the port state directly but need to schedule it.
 948          */
 949         ps->port_state[port] = stp_state;
 950         set_bit(port, &ps->port_state_update_mask);
 951         schedule_work(&ps->bridge_work);
 952
 953         return 0;
 954 }
 955
 956 static void mv88e6xxx_bridge_work(struct work_struct *work)
 957 {
 958         struct mv88e6xxx_priv_state *ps;
 959         struct dsa_switch *ds;
 960         int port;
 961
 962         ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
 963         ds = ((struct dsa_switch *)ps) - 1;
 964
 965         while (ps->port_state_update_mask) {
 966                 port = __ffs(ps->port_state_update_mask);
 967                 clear_bit(port, &ps->port_state_update_mask);
 968                 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
 969         }
 970 }
 971
 972 int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port)
 973 {
 974         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 975         int ret, fid;
 976
 977         mutex_lock(&ps->smi_mutex);
 978
 979         /* Port Control 1: disable trunking, disable sending
 980          * learning messages to this port.
 981          */
 982         ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x05, 0x0000);
 983         if (ret)
 984                 goto abort;
 985
 986         /* Port based VLAN map: give each port its own address
 987          * database, allow the CPU port to talk to each of the 'real'
 988          * ports, and allow each of the 'real' ports to only talk to
 989          * the upstream port.
 990          */
 991         fid = __ffs(ps->fid_mask);
 992         ps->fid[port] = fid;
 993         ps->fid_mask &= ~(1 << fid);
 994
 995         if (!dsa_is_cpu_port(ds, port))
 996                 ps->bridge_mask[fid] = 1 << port;
 997
 998         ret = _mv88e6xxx_update_port_config(ds, port);
 999         if (ret)
1000                 goto abort;
1001
1002         /* Default VLAN ID and priority: don't set a default VLAN
1003          * ID, and set the default packet priority to zero.
1004          */
1005         ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x07, 0x0000);
1006 abort:
1007         mutex_unlock(&ps->smi_mutex);
1008         return ret;
1009 }
1010
1011 int mv88e6xxx_setup_common(struct dsa_switch *ds)
1012 {
1013         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1014
1015         mutex_init(&ps->smi_mutex);
1016         mutex_init(&ps->stats_mutex);
1017         mutex_init(&ps->phy_mutex);
1018
1019         ps->fid_mask = (1 << DSA_MAX_PORTS) - 1;
1020
1021         INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
1022
1023         return 0;
1024 }
1025
1026 static int __init mv88e6xxx_init(void)
1027 {
1028 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1029         register_switch_driver(&mv88e6131_switch_driver);
1030 #endif
1031 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1032         register_switch_driver(&mv88e6123_61_65_switch_driver);
1033 #endif
1034 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
1035         register_switch_driver(&mv88e6352_switch_driver);
1036 #endif
1037 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1038         register_switch_driver(&mv88e6171_switch_driver);
1039 #endif
1040         return 0;
1041 }
1042 module_init(mv88e6xxx_init);
1043
1044 static void __exit mv88e6xxx_cleanup(void)
1045 {
1046 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1047         unregister_switch_driver(&mv88e6171_switch_driver);
1048 #endif
1049 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1050         unregister_switch_driver(&mv88e6123_61_65_switch_driver);
1051 #endif
1052 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1053         unregister_switch_driver(&mv88e6131_switch_driver);
1054 #endif
1055 }
1056 module_exit(mv88e6xxx_cleanup);
1057
1058 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
1059 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
1060 MODULE_LICENSE("GPL");