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serial: sh-sci: Add support for GPIO-controlled modem lines
[linux-2.6/btrfs-unstable.git] / drivers / tty / serial / sh-sci.c
blobbf3780a7f700cad85d78f5a2bce0929b0297208e
1 /*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Copyright (C) 2015 Glider bvba
6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #define SUPPORT_SYSRQ
23 #endif
24
25 #undef DEBUG
26
27 #include <linux/clk.h>
28 #include <linux/console.h>
29 #include <linux/ctype.h>
30 #include <linux/cpufreq.h>
31 #include <linux/delay.h>
32 #include <linux/dmaengine.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/err.h>
35 #include <linux/errno.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/major.h>
40 #include <linux/module.h>
41 #include <linux/mm.h>
42 #include <linux/of.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55
56 #ifdef CONFIG_SUPERH
57 #include <asm/sh_bios.h>
58 #endif
59
60 #include "serial_mctrl_gpio.h"
61 #include "sh-sci.h"
62
63 /* Offsets into the sci_port->irqs array */
64 enum {
65 SCIx_ERI_IRQ,
66 SCIx_RXI_IRQ,
67 SCIx_TXI_IRQ,
68 SCIx_BRI_IRQ,
69 SCIx_NR_IRQS,
70
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72 };
73
74 #define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79
80 enum SCI_CLKS {
81 SCI_FCK, /* Functional Clock */
82 SCI_SCK, /* Optional External Clock */
83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
85 SCI_NUM_CLKS
86 };
87
88 /* Bit x set means sampling rate x + 1 is supported */
89 #define SCI_SR(x) BIT((x) - 1)
90 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
91
92 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
95
96 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
97 #define max_sr(_port) fls((_port)->sampling_rate_mask)
98
99 /* Iterate over all supported sampling rates, from high to low */
100 #define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
103
104 struct sci_port {
105 struct uart_port port;
106
107 /* Platform configuration */
108 struct plat_sci_port *cfg;
109 unsigned int overrun_reg;
110 unsigned int overrun_mask;
111 unsigned int error_mask;
112 unsigned int error_clear;
113 unsigned int sampling_rate_mask;
114 resource_size_t reg_size;
115 struct mctrl_gpios *gpios;
116
117 /* Break timer */
118 struct timer_list break_timer;
119 int break_flag;
120
121 /* Clocks */
122 struct clk *clks[SCI_NUM_CLKS];
123 unsigned long clk_rates[SCI_NUM_CLKS];
124
125 int irqs[SCIx_NR_IRQS];
126 char *irqstr[SCIx_NR_IRQS];
127
128 struct dma_chan *chan_tx;
129 struct dma_chan *chan_rx;
130
131 #ifdef CONFIG_SERIAL_SH_SCI_DMA
132 dma_cookie_t cookie_tx;
133 dma_cookie_t cookie_rx[2];
134 dma_cookie_t active_rx;
135 dma_addr_t tx_dma_addr;
136 unsigned int tx_dma_len;
137 struct scatterlist sg_rx[2];
138 void *rx_buf[2];
139 size_t buf_len_rx;
140 struct work_struct work_tx;
141 struct timer_list rx_timer;
142 unsigned int rx_timeout;
143 #endif
144 };
145
146 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
147
148 static struct sci_port sci_ports[SCI_NPORTS];
149 static struct uart_driver sci_uart_driver;
150
151 static inline struct sci_port *
152 to_sci_port(struct uart_port *uart)
153 {
154 return container_of(uart, struct sci_port, port);
155 }
156
157 struct plat_sci_reg {
158 u8 offset, size;
159 };
160
161 /* Helper for invalidating specific entries of an inherited map. */
162 #define sci_reg_invalid { .offset = 0, .size = 0 }
163
164 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
165 [SCIx_PROBE_REGTYPE] = {
166 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
167 },
168
169 /*
170 * Common SCI definitions, dependent on the port's regshift
171 * value.
172 */
173 [SCIx_SCI_REGTYPE] = {
174 [SCSMR] = { 0x00, 8 },
175 [SCBRR] = { 0x01, 8 },
176 [SCSCR] = { 0x02, 8 },
177 [SCxTDR] = { 0x03, 8 },
178 [SCxSR] = { 0x04, 8 },
179 [SCxRDR] = { 0x05, 8 },
180 [SCFCR] = sci_reg_invalid,
181 [SCFDR] = sci_reg_invalid,
182 [SCTFDR] = sci_reg_invalid,
183 [SCRFDR] = sci_reg_invalid,
184 [SCSPTR] = sci_reg_invalid,
185 [SCLSR] = sci_reg_invalid,
186 [HSSRR] = sci_reg_invalid,
187 [SCPCR] = sci_reg_invalid,
188 [SCPDR] = sci_reg_invalid,
189 [SCDL] = sci_reg_invalid,
190 [SCCKS] = sci_reg_invalid,
191 },
192
193 /*
194 * Common definitions for legacy IrDA ports, dependent on
195 * regshift value.
196 */
197 [SCIx_IRDA_REGTYPE] = {
198 [SCSMR] = { 0x00, 8 },
199 [SCBRR] = { 0x01, 8 },
200 [SCSCR] = { 0x02, 8 },
201 [SCxTDR] = { 0x03, 8 },
202 [SCxSR] = { 0x04, 8 },
203 [SCxRDR] = { 0x05, 8 },
204 [SCFCR] = { 0x06, 8 },
205 [SCFDR] = { 0x07, 16 },
206 [SCTFDR] = sci_reg_invalid,
207 [SCRFDR] = sci_reg_invalid,
208 [SCSPTR] = sci_reg_invalid,
209 [SCLSR] = sci_reg_invalid,
210 [HSSRR] = sci_reg_invalid,
211 [SCPCR] = sci_reg_invalid,
212 [SCPDR] = sci_reg_invalid,
213 [SCDL] = sci_reg_invalid,
214 [SCCKS] = sci_reg_invalid,
215 },
216
217 /*
218 * Common SCIFA definitions.
219 */
220 [SCIx_SCIFA_REGTYPE] = {
221 [SCSMR] = { 0x00, 16 },
222 [SCBRR] = { 0x04, 8 },
223 [SCSCR] = { 0x08, 16 },
224 [SCxTDR] = { 0x20, 8 },
225 [SCxSR] = { 0x14, 16 },
226 [SCxRDR] = { 0x24, 8 },
227 [SCFCR] = { 0x18, 16 },
228 [SCFDR] = { 0x1c, 16 },
229 [SCTFDR] = sci_reg_invalid,
230 [SCRFDR] = sci_reg_invalid,
231 [SCSPTR] = sci_reg_invalid,
232 [SCLSR] = sci_reg_invalid,
233 [HSSRR] = sci_reg_invalid,
234 [SCPCR] = { 0x30, 16 },
235 [SCPDR] = { 0x34, 16 },
236 [SCDL] = sci_reg_invalid,
237 [SCCKS] = sci_reg_invalid,
238 },
239
240 /*
241 * Common SCIFB definitions.
242 */
243 [SCIx_SCIFB_REGTYPE] = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x40, 8 },
248 [SCxSR] = { 0x14, 16 },
249 [SCxRDR] = { 0x60, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCFDR] = sci_reg_invalid,
252 [SCTFDR] = { 0x38, 16 },
253 [SCRFDR] = { 0x3c, 16 },
254 [SCSPTR] = sci_reg_invalid,
255 [SCLSR] = sci_reg_invalid,
256 [HSSRR] = sci_reg_invalid,
257 [SCPCR] = { 0x30, 16 },
258 [SCPDR] = { 0x34, 16 },
259 [SCDL] = sci_reg_invalid,
260 [SCCKS] = sci_reg_invalid,
261 },
262
263 /*
264 * Common SH-2(A) SCIF definitions for ports with FIFO data
265 * count registers.
266 */
267 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
268 [SCSMR] = { 0x00, 16 },
269 [SCBRR] = { 0x04, 8 },
270 [SCSCR] = { 0x08, 16 },
271 [SCxTDR] = { 0x0c, 8 },
272 [SCxSR] = { 0x10, 16 },
273 [SCxRDR] = { 0x14, 8 },
274 [SCFCR] = { 0x18, 16 },
275 [SCFDR] = { 0x1c, 16 },
276 [SCTFDR] = sci_reg_invalid,
277 [SCRFDR] = sci_reg_invalid,
278 [SCSPTR] = { 0x20, 16 },
279 [SCLSR] = { 0x24, 16 },
280 [HSSRR] = sci_reg_invalid,
281 [SCPCR] = sci_reg_invalid,
282 [SCPDR] = sci_reg_invalid,
283 [SCDL] = sci_reg_invalid,
284 [SCCKS] = sci_reg_invalid,
285 },
286
287 /*
288 * Common SH-3 SCIF definitions.
289 */
290 [SCIx_SH3_SCIF_REGTYPE] = {
291 [SCSMR] = { 0x00, 8 },
292 [SCBRR] = { 0x02, 8 },
293 [SCSCR] = { 0x04, 8 },
294 [SCxTDR] = { 0x06, 8 },
295 [SCxSR] = { 0x08, 16 },
296 [SCxRDR] = { 0x0a, 8 },
297 [SCFCR] = { 0x0c, 8 },
298 [SCFDR] = { 0x0e, 16 },
299 [SCTFDR] = sci_reg_invalid,
300 [SCRFDR] = sci_reg_invalid,
301 [SCSPTR] = sci_reg_invalid,
302 [SCLSR] = sci_reg_invalid,
303 [HSSRR] = sci_reg_invalid,
304 [SCPCR] = sci_reg_invalid,
305 [SCPDR] = sci_reg_invalid,
306 [SCDL] = sci_reg_invalid,
307 [SCCKS] = sci_reg_invalid,
308 },
309
310 /*
311 * Common SH-4(A) SCIF(B) definitions.
312 */
313 [SCIx_SH4_SCIF_REGTYPE] = {
314 [SCSMR] = { 0x00, 16 },
315 [SCBRR] = { 0x04, 8 },
316 [SCSCR] = { 0x08, 16 },
317 [SCxTDR] = { 0x0c, 8 },
318 [SCxSR] = { 0x10, 16 },
319 [SCxRDR] = { 0x14, 8 },
320 [SCFCR] = { 0x18, 16 },
321 [SCFDR] = { 0x1c, 16 },
322 [SCTFDR] = sci_reg_invalid,
323 [SCRFDR] = sci_reg_invalid,
324 [SCSPTR] = { 0x20, 16 },
325 [SCLSR] = { 0x24, 16 },
326 [HSSRR] = sci_reg_invalid,
327 [SCPCR] = sci_reg_invalid,
328 [SCPDR] = sci_reg_invalid,
329 [SCDL] = sci_reg_invalid,
330 [SCCKS] = sci_reg_invalid,
331 },
332
333 /*
334 * Common SCIF definitions for ports with a Baud Rate Generator for
335 * External Clock (BRG).
336 */
337 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
338 [SCSMR] = { 0x00, 16 },
339 [SCBRR] = { 0x04, 8 },
340 [SCSCR] = { 0x08, 16 },
341 [SCxTDR] = { 0x0c, 8 },
342 [SCxSR] = { 0x10, 16 },
343 [SCxRDR] = { 0x14, 8 },
344 [SCFCR] = { 0x18, 16 },
345 [SCFDR] = { 0x1c, 16 },
346 [SCTFDR] = sci_reg_invalid,
347 [SCRFDR] = sci_reg_invalid,
348 [SCSPTR] = { 0x20, 16 },
349 [SCLSR] = { 0x24, 16 },
350 [HSSRR] = sci_reg_invalid,
351 [SCPCR] = sci_reg_invalid,
352 [SCPDR] = sci_reg_invalid,
353 [SCDL] = { 0x30, 16 },
354 [SCCKS] = { 0x34, 16 },
355 },
356
357 /*
358 * Common HSCIF definitions.
359 */
360 [SCIx_HSCIF_REGTYPE] = {
361 [SCSMR] = { 0x00, 16 },
362 [SCBRR] = { 0x04, 8 },
363 [SCSCR] = { 0x08, 16 },
364 [SCxTDR] = { 0x0c, 8 },
365 [SCxSR] = { 0x10, 16 },
366 [SCxRDR] = { 0x14, 8 },
367 [SCFCR] = { 0x18, 16 },
368 [SCFDR] = { 0x1c, 16 },
369 [SCTFDR] = sci_reg_invalid,
370 [SCRFDR] = sci_reg_invalid,
371 [SCSPTR] = { 0x20, 16 },
372 [SCLSR] = { 0x24, 16 },
373 [HSSRR] = { 0x40, 16 },
374 [SCPCR] = sci_reg_invalid,
375 [SCPDR] = sci_reg_invalid,
376 [SCDL] = { 0x30, 16 },
377 [SCCKS] = { 0x34, 16 },
378 },
379
380 /*
381 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
382 * register.
383 */
384 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
385 [SCSMR] = { 0x00, 16 },
386 [SCBRR] = { 0x04, 8 },
387 [SCSCR] = { 0x08, 16 },
388 [SCxTDR] = { 0x0c, 8 },
389 [SCxSR] = { 0x10, 16 },
390 [SCxRDR] = { 0x14, 8 },
391 [SCFCR] = { 0x18, 16 },
392 [SCFDR] = { 0x1c, 16 },
393 [SCTFDR] = sci_reg_invalid,
394 [SCRFDR] = sci_reg_invalid,
395 [SCSPTR] = sci_reg_invalid,
396 [SCLSR] = { 0x24, 16 },
397 [HSSRR] = sci_reg_invalid,
398 [SCPCR] = sci_reg_invalid,
399 [SCPDR] = sci_reg_invalid,
400 [SCDL] = sci_reg_invalid,
401 [SCCKS] = sci_reg_invalid,
402 },
403
404 /*
405 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
406 * count registers.
407 */
408 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
409 [SCSMR] = { 0x00, 16 },
410 [SCBRR] = { 0x04, 8 },
411 [SCSCR] = { 0x08, 16 },
412 [SCxTDR] = { 0x0c, 8 },
413 [SCxSR] = { 0x10, 16 },
414 [SCxRDR] = { 0x14, 8 },
415 [SCFCR] = { 0x18, 16 },
416 [SCFDR] = { 0x1c, 16 },
417 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
418 [SCRFDR] = { 0x20, 16 },
419 [SCSPTR] = { 0x24, 16 },
420 [SCLSR] = { 0x28, 16 },
421 [HSSRR] = sci_reg_invalid,
422 [SCPCR] = sci_reg_invalid,
423 [SCPDR] = sci_reg_invalid,
424 [SCDL] = sci_reg_invalid,
425 [SCCKS] = sci_reg_invalid,
426 },
427
428 /*
429 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
430 * registers.
431 */
432 [SCIx_SH7705_SCIF_REGTYPE] = {
433 [SCSMR] = { 0x00, 16 },
434 [SCBRR] = { 0x04, 8 },
435 [SCSCR] = { 0x08, 16 },
436 [SCxTDR] = { 0x20, 8 },
437 [SCxSR] = { 0x14, 16 },
438 [SCxRDR] = { 0x24, 8 },
439 [SCFCR] = { 0x18, 16 },
440 [SCFDR] = { 0x1c, 16 },
441 [SCTFDR] = sci_reg_invalid,
442 [SCRFDR] = sci_reg_invalid,
443 [SCSPTR] = sci_reg_invalid,
444 [SCLSR] = sci_reg_invalid,
445 [HSSRR] = sci_reg_invalid,
446 [SCPCR] = sci_reg_invalid,
447 [SCPDR] = sci_reg_invalid,
448 [SCDL] = sci_reg_invalid,
449 [SCCKS] = sci_reg_invalid,
450 },
451 };
452
453 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
454
455 /*
456 * The "offset" here is rather misleading, in that it refers to an enum
457 * value relative to the port mapping rather than the fixed offset
458 * itself, which needs to be manually retrieved from the platform's
459 * register map for the given port.
460 */
461 static unsigned int sci_serial_in(struct uart_port *p, int offset)
462 {
463 const struct plat_sci_reg *reg = sci_getreg(p, offset);
464
465 if (reg->size == 8)
466 return ioread8(p->membase + (reg->offset << p->regshift));
467 else if (reg->size == 16)
468 return ioread16(p->membase + (reg->offset << p->regshift));
469 else
470 WARN(1, "Invalid register access\n");
471
472 return 0;
473 }
474
475 static void sci_serial_out(struct uart_port *p, int offset, int value)
476 {
477 const struct plat_sci_reg *reg = sci_getreg(p, offset);
478
479 if (reg->size == 8)
480 iowrite8(value, p->membase + (reg->offset << p->regshift));
481 else if (reg->size == 16)
482 iowrite16(value, p->membase + (reg->offset << p->regshift));
483 else
484 WARN(1, "Invalid register access\n");
485 }
486
487 static int sci_probe_regmap(struct plat_sci_port *cfg)
488 {
489 switch (cfg->type) {
490 case PORT_SCI:
491 cfg->regtype = SCIx_SCI_REGTYPE;
492 break;
493 case PORT_IRDA:
494 cfg->regtype = SCIx_IRDA_REGTYPE;
495 break;
496 case PORT_SCIFA:
497 cfg->regtype = SCIx_SCIFA_REGTYPE;
498 break;
499 case PORT_SCIFB:
500 cfg->regtype = SCIx_SCIFB_REGTYPE;
501 break;
502 case PORT_SCIF:
503 /*
504 * The SH-4 is a bit of a misnomer here, although that's
505 * where this particular port layout originated. This
506 * configuration (or some slight variation thereof)
507 * remains the dominant model for all SCIFs.
508 */
509 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
510 break;
511 case PORT_HSCIF:
512 cfg->regtype = SCIx_HSCIF_REGTYPE;
513 break;
514 default:
515 pr_err("Can't probe register map for given port\n");
516 return -EINVAL;
517 }
518
519 return 0;
520 }
521
522 static void sci_port_enable(struct sci_port *sci_port)
523 {
524 unsigned int i;
525
526 if (!sci_port->port.dev)
527 return;
528
529 pm_runtime_get_sync(sci_port->port.dev);
530
531 for (i = 0; i < SCI_NUM_CLKS; i++) {
532 clk_prepare_enable(sci_port->clks[i]);
533 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
534 }
535 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
536 }
537
538 static void sci_port_disable(struct sci_port *sci_port)
539 {
540 unsigned int i;
541
542 if (!sci_port->port.dev)
543 return;
544
545 /* Cancel the break timer to ensure that the timer handler will not try
546 * to access the hardware with clocks and power disabled. Reset the
547 * break flag to make the break debouncing state machine ready for the
548 * next break.
549 */
550 del_timer_sync(&sci_port->break_timer);
551 sci_port->break_flag = 0;
552
553 for (i = SCI_NUM_CLKS; i-- > 0; )
554 clk_disable_unprepare(sci_port->clks[i]);
555
556 pm_runtime_put_sync(sci_port->port.dev);
557 }
558
559 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
560 {
561 /*
562 * Not all ports (such as SCIFA) will support REIE. Rather than
563 * special-casing the port type, we check the port initialization
564 * IRQ enable mask to see whether the IRQ is desired at all. If
565 * it's unset, it's logically inferred that there's no point in
566 * testing for it.
567 */
568 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
569 }
570
571 static void sci_start_tx(struct uart_port *port)
572 {
573 struct sci_port *s = to_sci_port(port);
574 unsigned short ctrl;
575
576 #ifdef CONFIG_SERIAL_SH_SCI_DMA
577 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
578 u16 new, scr = serial_port_in(port, SCSCR);
579 if (s->chan_tx)
580 new = scr | SCSCR_TDRQE;
581 else
582 new = scr & ~SCSCR_TDRQE;
583 if (new != scr)
584 serial_port_out(port, SCSCR, new);
585 }
586
587 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
588 dma_submit_error(s->cookie_tx)) {
589 s->cookie_tx = 0;
590 schedule_work(&s->work_tx);
591 }
592 #endif
593
594 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
595 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
596 ctrl = serial_port_in(port, SCSCR);
597 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
598 }
599 }
600
601 static void sci_stop_tx(struct uart_port *port)
602 {
603 unsigned short ctrl;
604
605 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
606 ctrl = serial_port_in(port, SCSCR);
607
608 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
609 ctrl &= ~SCSCR_TDRQE;
610
611 ctrl &= ~SCSCR_TIE;
612
613 serial_port_out(port, SCSCR, ctrl);
614 }
615
616 static void sci_start_rx(struct uart_port *port)
617 {
618 unsigned short ctrl;
619
620 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
621
622 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
623 ctrl &= ~SCSCR_RDRQE;
624
625 serial_port_out(port, SCSCR, ctrl);
626 }
627
628 static void sci_stop_rx(struct uart_port *port)
629 {
630 unsigned short ctrl;
631
632 ctrl = serial_port_in(port, SCSCR);
633
634 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
635 ctrl &= ~SCSCR_RDRQE;
636
637 ctrl &= ~port_rx_irq_mask(port);
638
639 serial_port_out(port, SCSCR, ctrl);
640 }
641
642 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
643 {
644 if (port->type == PORT_SCI) {
645 /* Just store the mask */
646 serial_port_out(port, SCxSR, mask);
647 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
648 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
649 /* Only clear the status bits we want to clear */
650 serial_port_out(port, SCxSR,
651 serial_port_in(port, SCxSR) & mask);
652 } else {
653 /* Store the mask, clear parity/framing errors */
654 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
655 }
656 }
657
658 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
659 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
660
661 #ifdef CONFIG_CONSOLE_POLL
662 static int sci_poll_get_char(struct uart_port *port)
663 {
664 unsigned short status;
665 int c;
666
667 do {
668 status = serial_port_in(port, SCxSR);
669 if (status & SCxSR_ERRORS(port)) {
670 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
671 continue;
672 }
673 break;
674 } while (1);
675
676 if (!(status & SCxSR_RDxF(port)))
677 return NO_POLL_CHAR;
678
679 c = serial_port_in(port, SCxRDR);
680
681 /* Dummy read */
682 serial_port_in(port, SCxSR);
683 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
684
685 return c;
686 }
687 #endif
688
689 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
690 {
691 unsigned short status;
692
693 do {
694 status = serial_port_in(port, SCxSR);
695 } while (!(status & SCxSR_TDxE(port)));
696
697 serial_port_out(port, SCxTDR, c);
698 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
699 }
700 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
701 CONFIG_SERIAL_SH_SCI_EARLYCON */
702
703 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
704 {
705 struct sci_port *s = to_sci_port(port);
706 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
707
708 /*
709 * Use port-specific handler if provided.
710 */
711 if (s->cfg->ops && s->cfg->ops->init_pins) {
712 s->cfg->ops->init_pins(port, cflag);
713 return;
714 }
715
716 /*
717 * For the generic path SCSPTR is necessary. Bail out if that's
718 * unavailable, too.
719 */
720 if (!reg->size)
721 return;
722
723 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
724 ((!(cflag & CRTSCTS)))) {
725 unsigned short status;
726
727 status = serial_port_in(port, SCSPTR);
728 status &= ~SCSPTR_CTSIO;
729 status |= SCSPTR_RTSIO;
730 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
731 }
732 }
733
734 static int sci_txfill(struct uart_port *port)
735 {
736 const struct plat_sci_reg *reg;
737
738 reg = sci_getreg(port, SCTFDR);
739 if (reg->size)
740 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
741
742 reg = sci_getreg(port, SCFDR);
743 if (reg->size)
744 return serial_port_in(port, SCFDR) >> 8;
745
746 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
747 }
748
749 static int sci_txroom(struct uart_port *port)
750 {
751 return port->fifosize - sci_txfill(port);
752 }
753
754 static int sci_rxfill(struct uart_port *port)
755 {
756 const struct plat_sci_reg *reg;
757
758 reg = sci_getreg(port, SCRFDR);
759 if (reg->size)
760 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
761
762 reg = sci_getreg(port, SCFDR);
763 if (reg->size)
764 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
765
766 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
767 }
768
769 /*
770 * SCI helper for checking the state of the muxed port/RXD pins.
771 */
772 static inline int sci_rxd_in(struct uart_port *port)
773 {
774 struct sci_port *s = to_sci_port(port);
775
776 if (s->cfg->port_reg <= 0)
777 return 1;
778
779 /* Cast for ARM damage */
780 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
781 }
782
783 /* ********************************************************************** *
784 * the interrupt related routines *
785 * ********************************************************************** */
786
787 static void sci_transmit_chars(struct uart_port *port)
788 {
789 struct circ_buf *xmit = &port->state->xmit;
790 unsigned int stopped = uart_tx_stopped(port);
791 unsigned short status;
792 unsigned short ctrl;
793 int count;
794
795 status = serial_port_in(port, SCxSR);
796 if (!(status & SCxSR_TDxE(port))) {
797 ctrl = serial_port_in(port, SCSCR);
798 if (uart_circ_empty(xmit))
799 ctrl &= ~SCSCR_TIE;
800 else
801 ctrl |= SCSCR_TIE;
802 serial_port_out(port, SCSCR, ctrl);
803 return;
804 }
805
806 count = sci_txroom(port);
807
808 do {
809 unsigned char c;
810
811 if (port->x_char) {
812 c = port->x_char;
813 port->x_char = 0;
814 } else if (!uart_circ_empty(xmit) && !stopped) {
815 c = xmit->buf[xmit->tail];
816 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
817 } else {
818 break;
819 }
820
821 serial_port_out(port, SCxTDR, c);
822
823 port->icount.tx++;
824 } while (--count > 0);
825
826 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
827
828 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
829 uart_write_wakeup(port);
830 if (uart_circ_empty(xmit)) {
831 sci_stop_tx(port);
832 } else {
833 ctrl = serial_port_in(port, SCSCR);
834
835 if (port->type != PORT_SCI) {
836 serial_port_in(port, SCxSR); /* Dummy read */
837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
838 }
839
840 ctrl |= SCSCR_TIE;
841 serial_port_out(port, SCSCR, ctrl);
842 }
843 }
844
845 /* On SH3, SCIF may read end-of-break as a space->mark char */
846 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
847
848 static void sci_receive_chars(struct uart_port *port)
849 {
850 struct sci_port *sci_port = to_sci_port(port);
851 struct tty_port *tport = &port->state->port;
852 int i, count, copied = 0;
853 unsigned short status;
854 unsigned char flag;
855
856 status = serial_port_in(port, SCxSR);
857 if (!(status & SCxSR_RDxF(port)))
858 return;
859
860 while (1) {
861 /* Don't copy more bytes than there is room for in the buffer */
862 count = tty_buffer_request_room(tport, sci_rxfill(port));
863
864 /* If for any reason we can't copy more data, we're done! */
865 if (count == 0)
866 break;
867
868 if (port->type == PORT_SCI) {
869 char c = serial_port_in(port, SCxRDR);
870 if (uart_handle_sysrq_char(port, c) ||
871 sci_port->break_flag)
872 count = 0;
873 else
874 tty_insert_flip_char(tport, c, TTY_NORMAL);
875 } else {
876 for (i = 0; i < count; i++) {
877 char c = serial_port_in(port, SCxRDR);
878
879 status = serial_port_in(port, SCxSR);
880 #if defined(CONFIG_CPU_SH3)
881 /* Skip "chars" during break */
882 if (sci_port->break_flag) {
883 if ((c == 0) &&
884 (status & SCxSR_FER(port))) {
885 count--; i--;
886 continue;
887 }
888
889 /* Nonzero => end-of-break */
890 dev_dbg(port->dev, "debounce<%02x>\n", c);
891 sci_port->break_flag = 0;
892
893 if (STEPFN(c)) {
894 count--; i--;
895 continue;
896 }
897 }
898 #endif /* CONFIG_CPU_SH3 */
899 if (uart_handle_sysrq_char(port, c)) {
900 count--; i--;
901 continue;
902 }
903
904 /* Store data and status */
905 if (status & SCxSR_FER(port)) {
906 flag = TTY_FRAME;
907 port->icount.frame++;
908 dev_notice(port->dev, "frame error\n");
909 } else if (status & SCxSR_PER(port)) {
910 flag = TTY_PARITY;
911 port->icount.parity++;
912 dev_notice(port->dev, "parity error\n");
913 } else
914 flag = TTY_NORMAL;
915
916 tty_insert_flip_char(tport, c, flag);
917 }
918 }
919
920 serial_port_in(port, SCxSR); /* dummy read */
921 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
922
923 copied += count;
924 port->icount.rx += count;
925 }
926
927 if (copied) {
928 /* Tell the rest of the system the news. New characters! */
929 tty_flip_buffer_push(tport);
930 } else {
931 serial_port_in(port, SCxSR); /* dummy read */
932 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
933 }
934 }
935
936 #define SCI_BREAK_JIFFIES (HZ/20)
937
938 /*
939 * The sci generates interrupts during the break,
940 * 1 per millisecond or so during the break period, for 9600 baud.
941 * So dont bother disabling interrupts.
942 * But dont want more than 1 break event.
943 * Use a kernel timer to periodically poll the rx line until
944 * the break is finished.
945 */
946 static inline void sci_schedule_break_timer(struct sci_port *port)
947 {
948 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
949 }
950
951 /* Ensure that two consecutive samples find the break over. */
952 static void sci_break_timer(unsigned long data)
953 {
954 struct sci_port *port = (struct sci_port *)data;
955
956 if (sci_rxd_in(&port->port) == 0) {
957 port->break_flag = 1;
958 sci_schedule_break_timer(port);
959 } else if (port->break_flag == 1) {
960 /* break is over. */
961 port->break_flag = 2;
962 sci_schedule_break_timer(port);
963 } else
964 port->break_flag = 0;
965 }
966
967 static int sci_handle_errors(struct uart_port *port)
968 {
969 int copied = 0;
970 unsigned short status = serial_port_in(port, SCxSR);
971 struct tty_port *tport = &port->state->port;
972 struct sci_port *s = to_sci_port(port);
973
974 /* Handle overruns */
975 if (status & s->overrun_mask) {
976 port->icount.overrun++;
977
978 /* overrun error */
979 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
980 copied++;
981
982 dev_notice(port->dev, "overrun error\n");
983 }
984
985 if (status & SCxSR_FER(port)) {
986 if (sci_rxd_in(port) == 0) {
987 /* Notify of BREAK */
988 struct sci_port *sci_port = to_sci_port(port);
989
990 if (!sci_port->break_flag) {
991 port->icount.brk++;
992
993 sci_port->break_flag = 1;
994 sci_schedule_break_timer(sci_port);
995
996 /* Do sysrq handling. */
997 if (uart_handle_break(port))
998 return 0;
999
1000 dev_dbg(port->dev, "BREAK detected\n");
1001
1002 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1003 copied++;
1004 }
1005
1006 } else {
1007 /* frame error */
1008 port->icount.frame++;
1009
1010 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1011 copied++;
1012
1013 dev_notice(port->dev, "frame error\n");
1014 }
1015 }
1016
1017 if (status & SCxSR_PER(port)) {
1018 /* parity error */
1019 port->icount.parity++;
1020
1021 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1022 copied++;
1023
1024 dev_notice(port->dev, "parity error\n");
1025 }
1026
1027 if (copied)
1028 tty_flip_buffer_push(tport);
1029
1030 return copied;
1031 }
1032
1033 static int sci_handle_fifo_overrun(struct uart_port *port)
1034 {
1035 struct tty_port *tport = &port->state->port;
1036 struct sci_port *s = to_sci_port(port);
1037 const struct plat_sci_reg *reg;
1038 int copied = 0;
1039 u16 status;
1040
1041 reg = sci_getreg(port, s->overrun_reg);
1042 if (!reg->size)
1043 return 0;
1044
1045 status = serial_port_in(port, s->overrun_reg);
1046 if (status & s->overrun_mask) {
1047 status &= ~s->overrun_mask;
1048 serial_port_out(port, s->overrun_reg, status);
1049
1050 port->icount.overrun++;
1051
1052 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1053 tty_flip_buffer_push(tport);
1054
1055 dev_dbg(port->dev, "overrun error\n");
1056 copied++;
1057 }
1058
1059 return copied;
1060 }
1061
1062 static int sci_handle_breaks(struct uart_port *port)
1063 {
1064 int copied = 0;
1065 unsigned short status = serial_port_in(port, SCxSR);
1066 struct tty_port *tport = &port->state->port;
1067 struct sci_port *s = to_sci_port(port);
1068
1069 if (uart_handle_break(port))
1070 return 0;
1071
1072 if (!s->break_flag && status & SCxSR_BRK(port)) {
1073 #if defined(CONFIG_CPU_SH3)
1074 /* Debounce break */
1075 s->break_flag = 1;
1076 #endif
1077
1078 port->icount.brk++;
1079
1080 /* Notify of BREAK */
1081 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1082 copied++;
1083
1084 dev_dbg(port->dev, "BREAK detected\n");
1085 }
1086
1087 if (copied)
1088 tty_flip_buffer_push(tport);
1089
1090 copied += sci_handle_fifo_overrun(port);
1091
1092 return copied;
1093 }
1094
1095 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1096 static void sci_dma_tx_complete(void *arg)
1097 {
1098 struct sci_port *s = arg;
1099 struct uart_port *port = &s->port;
1100 struct circ_buf *xmit = &port->state->xmit;
1101 unsigned long flags;
1102
1103 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1104
1105 spin_lock_irqsave(&port->lock, flags);
1106
1107 xmit->tail += s->tx_dma_len;
1108 xmit->tail &= UART_XMIT_SIZE - 1;
1109
1110 port->icount.tx += s->tx_dma_len;
1111
1112 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1113 uart_write_wakeup(port);
1114
1115 if (!uart_circ_empty(xmit)) {
1116 s->cookie_tx = 0;
1117 schedule_work(&s->work_tx);
1118 } else {
1119 s->cookie_tx = -EINVAL;
1120 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1121 u16 ctrl = serial_port_in(port, SCSCR);
1122 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1123 }
1124 }
1125
1126 spin_unlock_irqrestore(&port->lock, flags);
1127 }
1128
1129 /* Locking: called with port lock held */
1130 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1131 {
1132 struct uart_port *port = &s->port;
1133 struct tty_port *tport = &port->state->port;
1134 int copied;
1135
1136 copied = tty_insert_flip_string(tport, buf, count);
1137 if (copied < count) {
1138 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1139 count - copied);
1140 port->icount.buf_overrun++;
1141 }
1142
1143 port->icount.rx += copied;
1144
1145 return copied;
1146 }
1147
1148 static int sci_dma_rx_find_active(struct sci_port *s)
1149 {
1150 unsigned int i;
1151
1152 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1153 if (s->active_rx == s->cookie_rx[i])
1154 return i;
1155
1156 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1157 s->active_rx);
1158 return -1;
1159 }
1160
1161 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1162 {
1163 struct dma_chan *chan = s->chan_rx;
1164 struct uart_port *port = &s->port;
1165 unsigned long flags;
1166
1167 spin_lock_irqsave(&port->lock, flags);
1168 s->chan_rx = NULL;
1169 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1170 spin_unlock_irqrestore(&port->lock, flags);
1171 dmaengine_terminate_all(chan);
1172 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1173 sg_dma_address(&s->sg_rx[0]));
1174 dma_release_channel(chan);
1175 if (enable_pio)
1176 sci_start_rx(port);
1177 }
1178
1179 static void sci_dma_rx_complete(void *arg)
1180 {
1181 struct sci_port *s = arg;
1182 struct dma_chan *chan = s->chan_rx;
1183 struct uart_port *port = &s->port;
1184 struct dma_async_tx_descriptor *desc;
1185 unsigned long flags;
1186 int active, count = 0;
1187
1188 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1189 s->active_rx);
1190
1191 spin_lock_irqsave(&port->lock, flags);
1192
1193 active = sci_dma_rx_find_active(s);
1194 if (active >= 0)
1195 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1196
1197 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1198
1199 if (count)
1200 tty_flip_buffer_push(&port->state->port);
1201
1202 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1203 DMA_DEV_TO_MEM,
1204 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1205 if (!desc)
1206 goto fail;
1207
1208 desc->callback = sci_dma_rx_complete;
1209 desc->callback_param = s;
1210 s->cookie_rx[active] = dmaengine_submit(desc);
1211 if (dma_submit_error(s->cookie_rx[active]))
1212 goto fail;
1213
1214 s->active_rx = s->cookie_rx[!active];
1215
1216 dma_async_issue_pending(chan);
1217
1218 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1219 __func__, s->cookie_rx[active], active, s->active_rx);
1220 spin_unlock_irqrestore(&port->lock, flags);
1221 return;
1222
1223 fail:
1224 spin_unlock_irqrestore(&port->lock, flags);
1225 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1226 sci_rx_dma_release(s, true);
1227 }
1228
1229 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1230 {
1231 struct dma_chan *chan = s->chan_tx;
1232 struct uart_port *port = &s->port;
1233 unsigned long flags;
1234
1235 spin_lock_irqsave(&port->lock, flags);
1236 s->chan_tx = NULL;
1237 s->cookie_tx = -EINVAL;
1238 spin_unlock_irqrestore(&port->lock, flags);
1239 dmaengine_terminate_all(chan);
1240 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1241 DMA_TO_DEVICE);
1242 dma_release_channel(chan);
1243 if (enable_pio)
1244 sci_start_tx(port);
1245 }
1246
1247 static void sci_submit_rx(struct sci_port *s)
1248 {
1249 struct dma_chan *chan = s->chan_rx;
1250 int i;
1251
1252 for (i = 0; i < 2; i++) {
1253 struct scatterlist *sg = &s->sg_rx[i];
1254 struct dma_async_tx_descriptor *desc;
1255
1256 desc = dmaengine_prep_slave_sg(chan,
1257 sg, 1, DMA_DEV_TO_MEM,
1258 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1259 if (!desc)
1260 goto fail;
1261
1262 desc->callback = sci_dma_rx_complete;
1263 desc->callback_param = s;
1264 s->cookie_rx[i] = dmaengine_submit(desc);
1265 if (dma_submit_error(s->cookie_rx[i]))
1266 goto fail;
1267
1268 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1269 s->cookie_rx[i], i);
1270 }
1271
1272 s->active_rx = s->cookie_rx[0];
1273
1274 dma_async_issue_pending(chan);
1275 return;
1276
1277 fail:
1278 if (i)
1279 dmaengine_terminate_all(chan);
1280 for (i = 0; i < 2; i++)
1281 s->cookie_rx[i] = -EINVAL;
1282 s->active_rx = -EINVAL;
1283 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1284 sci_rx_dma_release(s, true);
1285 }
1286
1287 static void work_fn_tx(struct work_struct *work)
1288 {
1289 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1290 struct dma_async_tx_descriptor *desc;
1291 struct dma_chan *chan = s->chan_tx;
1292 struct uart_port *port = &s->port;
1293 struct circ_buf *xmit = &port->state->xmit;
1294 dma_addr_t buf;
1295
1296 /*
1297 * DMA is idle now.
1298 * Port xmit buffer is already mapped, and it is one page... Just adjust
1299 * offsets and lengths. Since it is a circular buffer, we have to
1300 * transmit till the end, and then the rest. Take the port lock to get a
1301 * consistent xmit buffer state.
1302 */
1303 spin_lock_irq(&port->lock);
1304 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1305 s->tx_dma_len = min_t(unsigned int,
1306 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1307 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1308 spin_unlock_irq(&port->lock);
1309
1310 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1311 DMA_MEM_TO_DEV,
1312 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1313 if (!desc) {
1314 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1315 /* switch to PIO */
1316 sci_tx_dma_release(s, true);
1317 return;
1318 }
1319
1320 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1321 DMA_TO_DEVICE);
1322
1323 spin_lock_irq(&port->lock);
1324 desc->callback = sci_dma_tx_complete;
1325 desc->callback_param = s;
1326 spin_unlock_irq(&port->lock);
1327 s->cookie_tx = dmaengine_submit(desc);
1328 if (dma_submit_error(s->cookie_tx)) {
1329 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1330 /* switch to PIO */
1331 sci_tx_dma_release(s, true);
1332 return;
1333 }
1334
1335 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1336 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1337
1338 dma_async_issue_pending(chan);
1339 }
1340
1341 static void rx_timer_fn(unsigned long arg)
1342 {
1343 struct sci_port *s = (struct sci_port *)arg;
1344 struct dma_chan *chan = s->chan_rx;
1345 struct uart_port *port = &s->port;
1346 struct dma_tx_state state;
1347 enum dma_status status;
1348 unsigned long flags;
1349 unsigned int read;
1350 int active, count;
1351 u16 scr;
1352
1353 spin_lock_irqsave(&port->lock, flags);
1354
1355 dev_dbg(port->dev, "DMA Rx timed out\n");
1356
1357 active = sci_dma_rx_find_active(s);
1358 if (active < 0) {
1359 spin_unlock_irqrestore(&port->lock, flags);
1360 return;
1361 }
1362
1363 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1364 if (status == DMA_COMPLETE) {
1365 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1366 s->active_rx, active);
1367 spin_unlock_irqrestore(&port->lock, flags);
1368
1369 /* Let packet complete handler take care of the packet */
1370 return;
1371 }
1372
1373 dmaengine_pause(chan);
1374
1375 /*
1376 * sometimes DMA transfer doesn't stop even if it is stopped and
1377 * data keeps on coming until transaction is complete so check
1378 * for DMA_COMPLETE again
1379 * Let packet complete handler take care of the packet
1380 */
1381 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1382 if (status == DMA_COMPLETE) {
1383 spin_unlock_irqrestore(&port->lock, flags);
1384 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1385 return;
1386 }
1387
1388 /* Handle incomplete DMA receive */
1389 dmaengine_terminate_all(s->chan_rx);
1390 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1391 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1392 s->active_rx);
1393
1394 if (read) {
1395 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1396 if (count)
1397 tty_flip_buffer_push(&port->state->port);
1398 }
1399
1400 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1401 sci_submit_rx(s);
1402
1403 /* Direct new serial port interrupts back to CPU */
1404 scr = serial_port_in(port, SCSCR);
1405 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1406 scr &= ~SCSCR_RDRQE;
1407 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1408 }
1409 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1410
1411 spin_unlock_irqrestore(&port->lock, flags);
1412 }
1413
1414 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1415 enum dma_transfer_direction dir,
1416 unsigned int id)
1417 {
1418 dma_cap_mask_t mask;
1419 struct dma_chan *chan;
1420 struct dma_slave_config cfg;
1421 int ret;
1422
1423 dma_cap_zero(mask);
1424 dma_cap_set(DMA_SLAVE, mask);
1425
1426 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1427 (void *)(unsigned long)id, port->dev,
1428 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1429 if (!chan) {
1430 dev_warn(port->dev,
1431 "dma_request_slave_channel_compat failed\n");
1432 return NULL;
1433 }
1434
1435 memset(&cfg, 0, sizeof(cfg));
1436 cfg.direction = dir;
1437 if (dir == DMA_MEM_TO_DEV) {
1438 cfg.dst_addr = port->mapbase +
1439 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1440 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1441 } else {
1442 cfg.src_addr = port->mapbase +
1443 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1444 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1445 }
1446
1447 ret = dmaengine_slave_config(chan, &cfg);
1448 if (ret) {
1449 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1450 dma_release_channel(chan);
1451 return NULL;
1452 }
1453
1454 return chan;
1455 }
1456
1457 static void sci_request_dma(struct uart_port *port)
1458 {
1459 struct sci_port *s = to_sci_port(port);
1460 struct dma_chan *chan;
1461
1462 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1463
1464 if (!port->dev->of_node &&
1465 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1466 return;
1467
1468 s->cookie_tx = -EINVAL;
1469 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1470 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1471 if (chan) {
1472 s->chan_tx = chan;
1473 /* UART circular tx buffer is an aligned page. */
1474 s->tx_dma_addr = dma_map_single(chan->device->dev,
1475 port->state->xmit.buf,
1476 UART_XMIT_SIZE,
1477 DMA_TO_DEVICE);
1478 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1479 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1480 dma_release_channel(chan);
1481 s->chan_tx = NULL;
1482 } else {
1483 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1484 __func__, UART_XMIT_SIZE,
1485 port->state->xmit.buf, &s->tx_dma_addr);
1486 }
1487
1488 INIT_WORK(&s->work_tx, work_fn_tx);
1489 }
1490
1491 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1492 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1493 if (chan) {
1494 unsigned int i;
1495 dma_addr_t dma;
1496 void *buf;
1497
1498 s->chan_rx = chan;
1499
1500 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1501 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1502 &dma, GFP_KERNEL);
1503 if (!buf) {
1504 dev_warn(port->dev,
1505 "Failed to allocate Rx dma buffer, using PIO\n");
1506 dma_release_channel(chan);
1507 s->chan_rx = NULL;
1508 return;
1509 }
1510
1511 for (i = 0; i < 2; i++) {
1512 struct scatterlist *sg = &s->sg_rx[i];
1513
1514 sg_init_table(sg, 1);
1515 s->rx_buf[i] = buf;
1516 sg_dma_address(sg) = dma;
1517 sg_dma_len(sg) = s->buf_len_rx;
1518
1519 buf += s->buf_len_rx;
1520 dma += s->buf_len_rx;
1521 }
1522
1523 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1524
1525 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1526 sci_submit_rx(s);
1527 }
1528 }
1529
1530 static void sci_free_dma(struct uart_port *port)
1531 {
1532 struct sci_port *s = to_sci_port(port);
1533
1534 if (s->chan_tx)
1535 sci_tx_dma_release(s, false);
1536 if (s->chan_rx)
1537 sci_rx_dma_release(s, false);
1538 }
1539 #else
1540 static inline void sci_request_dma(struct uart_port *port)
1541 {
1542 }
1543
1544 static inline void sci_free_dma(struct uart_port *port)
1545 {
1546 }
1547 #endif
1548
1549 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1550 {
1551 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1552 struct uart_port *port = ptr;
1553 struct sci_port *s = to_sci_port(port);
1554
1555 if (s->chan_rx) {
1556 u16 scr = serial_port_in(port, SCSCR);
1557 u16 ssr = serial_port_in(port, SCxSR);
1558
1559 /* Disable future Rx interrupts */
1560 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1561 disable_irq_nosync(irq);
1562 scr |= SCSCR_RDRQE;
1563 } else {
1564 scr &= ~SCSCR_RIE;
1565 sci_submit_rx(s);
1566 }
1567 serial_port_out(port, SCSCR, scr);
1568 /* Clear current interrupt */
1569 serial_port_out(port, SCxSR,
1570 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1571 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1572 jiffies, s->rx_timeout);
1573 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1574
1575 return IRQ_HANDLED;
1576 }
1577 #endif
1578
1579 /* I think sci_receive_chars has to be called irrespective
1580 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1581 * to be disabled?
1582 */
1583 sci_receive_chars(ptr);
1584
1585 return IRQ_HANDLED;
1586 }
1587
1588 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1589 {
1590 struct uart_port *port = ptr;
1591 unsigned long flags;
1592
1593 spin_lock_irqsave(&port->lock, flags);
1594 sci_transmit_chars(port);
1595 spin_unlock_irqrestore(&port->lock, flags);
1596
1597 return IRQ_HANDLED;
1598 }
1599
1600 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1601 {
1602 struct uart_port *port = ptr;
1603 struct sci_port *s = to_sci_port(port);
1604
1605 /* Handle errors */
1606 if (port->type == PORT_SCI) {
1607 if (sci_handle_errors(port)) {
1608 /* discard character in rx buffer */
1609 serial_port_in(port, SCxSR);
1610 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1611 }
1612 } else {
1613 sci_handle_fifo_overrun(port);
1614 if (!s->chan_rx)
1615 sci_receive_chars(ptr);
1616 }
1617
1618 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1619
1620 /* Kick the transmission */
1621 if (!s->chan_tx)
1622 sci_tx_interrupt(irq, ptr);
1623
1624 return IRQ_HANDLED;
1625 }
1626
1627 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1628 {
1629 struct uart_port *port = ptr;
1630
1631 /* Handle BREAKs */
1632 sci_handle_breaks(port);
1633 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1634
1635 return IRQ_HANDLED;
1636 }
1637
1638 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1639 {
1640 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1641 struct uart_port *port = ptr;
1642 struct sci_port *s = to_sci_port(port);
1643 irqreturn_t ret = IRQ_NONE;
1644
1645 ssr_status = serial_port_in(port, SCxSR);
1646 scr_status = serial_port_in(port, SCSCR);
1647 if (s->overrun_reg == SCxSR)
1648 orer_status = ssr_status;
1649 else {
1650 if (sci_getreg(port, s->overrun_reg)->size)
1651 orer_status = serial_port_in(port, s->overrun_reg);
1652 }
1653
1654 err_enabled = scr_status & port_rx_irq_mask(port);
1655
1656 /* Tx Interrupt */
1657 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1658 !s->chan_tx)
1659 ret = sci_tx_interrupt(irq, ptr);
1660
1661 /*
1662 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1663 * DR flags
1664 */
1665 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1666 (scr_status & SCSCR_RIE))
1667 ret = sci_rx_interrupt(irq, ptr);
1668
1669 /* Error Interrupt */
1670 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1671 ret = sci_er_interrupt(irq, ptr);
1672
1673 /* Break Interrupt */
1674 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1675 ret = sci_br_interrupt(irq, ptr);
1676
1677 /* Overrun Interrupt */
1678 if (orer_status & s->overrun_mask) {
1679 sci_handle_fifo_overrun(port);
1680 ret = IRQ_HANDLED;
1681 }
1682
1683 return ret;
1684 }
1685
1686 static const struct sci_irq_desc {
1687 const char *desc;
1688 irq_handler_t handler;
1689 } sci_irq_desc[] = {
1690 /*
1691 * Split out handlers, the default case.
1692 */
1693 [SCIx_ERI_IRQ] = {
1694 .desc = "rx err",
1695 .handler = sci_er_interrupt,
1696 },
1697
1698 [SCIx_RXI_IRQ] = {
1699 .desc = "rx full",
1700 .handler = sci_rx_interrupt,
1701 },
1702
1703 [SCIx_TXI_IRQ] = {
1704 .desc = "tx empty",
1705 .handler = sci_tx_interrupt,
1706 },
1707
1708 [SCIx_BRI_IRQ] = {
1709 .desc = "break",
1710 .handler = sci_br_interrupt,
1711 },
1712
1713 /*
1714 * Special muxed handler.
1715 */
1716 [SCIx_MUX_IRQ] = {
1717 .desc = "mux",
1718 .handler = sci_mpxed_interrupt,
1719 },
1720 };
1721
1722 static int sci_request_irq(struct sci_port *port)
1723 {
1724 struct uart_port *up = &port->port;
1725 int i, j, ret = 0;
1726
1727 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1728 const struct sci_irq_desc *desc;
1729 int irq;
1730
1731 if (SCIx_IRQ_IS_MUXED(port)) {
1732 i = SCIx_MUX_IRQ;
1733 irq = up->irq;
1734 } else {
1735 irq = port->irqs[i];
1736
1737 /*
1738 * Certain port types won't support all of the
1739 * available interrupt sources.
1740 */
1741 if (unlikely(irq < 0))
1742 continue;
1743 }
1744
1745 desc = sci_irq_desc + i;
1746 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1747 dev_name(up->dev), desc->desc);
1748 if (!port->irqstr[j])
1749 goto out_nomem;
1750
1751 ret = request_irq(irq, desc->handler, up->irqflags,
1752 port->irqstr[j], port);
1753 if (unlikely(ret)) {
1754 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1755 goto out_noirq;
1756 }
1757 }
1758
1759 return 0;
1760
1761 out_noirq:
1762 while (--i >= 0)
1763 free_irq(port->irqs[i], port);
1764
1765 out_nomem:
1766 while (--j >= 0)
1767 kfree(port->irqstr[j]);
1768
1769 return ret;
1770 }
1771
1772 static void sci_free_irq(struct sci_port *port)
1773 {
1774 int i;
1775
1776 /*
1777 * Intentionally in reverse order so we iterate over the muxed
1778 * IRQ first.
1779 */
1780 for (i = 0; i < SCIx_NR_IRQS; i++) {
1781 int irq = port->irqs[i];
1782
1783 /*
1784 * Certain port types won't support all of the available
1785 * interrupt sources.
1786 */
1787 if (unlikely(irq < 0))
1788 continue;
1789
1790 free_irq(port->irqs[i], port);
1791 kfree(port->irqstr[i]);
1792
1793 if (SCIx_IRQ_IS_MUXED(port)) {
1794 /* If there's only one IRQ, we're done. */
1795 return;
1796 }
1797 }
1798 }
1799
1800 static unsigned int sci_tx_empty(struct uart_port *port)
1801 {
1802 unsigned short status = serial_port_in(port, SCxSR);
1803 unsigned short in_tx_fifo = sci_txfill(port);
1804
1805 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1806 }
1807
1808 /*
1809 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1810 * CTS/RTS is supported in hardware by at least one port and controlled
1811 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1812 * handled via the ->init_pins() op, which is a bit of a one-way street,
1813 * lacking any ability to defer pin control -- this will later be
1814 * converted over to the GPIO framework).
1815 *
1816 * Other modes (such as loopback) are supported generically on certain
1817 * port types, but not others. For these it's sufficient to test for the
1818 * existence of the support register and simply ignore the port type.
1819 */
1820 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1821 {
1822 struct sci_port *s = to_sci_port(port);
1823
1824 if (mctrl & TIOCM_LOOP) {
1825 const struct plat_sci_reg *reg;
1826
1827 /*
1828 * Standard loopback mode for SCFCR ports.
1829 */
1830 reg = sci_getreg(port, SCFCR);
1831 if (reg->size)
1832 serial_port_out(port, SCFCR,
1833 serial_port_in(port, SCFCR) |
1834 SCFCR_LOOP);
1835 }
1836
1837 mctrl_gpio_set(s->gpios, mctrl);
1838 }
1839
1840 static unsigned int sci_get_mctrl(struct uart_port *port)
1841 {
1842 struct sci_port *s = to_sci_port(port);
1843 struct mctrl_gpios *gpios = s->gpios;
1844 unsigned int mctrl = 0;
1845
1846 mctrl_gpio_get(gpios, &mctrl);
1847
1848 /*
1849 * CTS/RTS is handled in hardware when supported, while nothing
1850 * else is wired up. Keep it simple and simply assert CTS/DSR/CAR.
1851 */
1852 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)))
1853 mctrl |= TIOCM_CTS;
1854 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1855 mctrl |= TIOCM_DSR;
1856 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1857 mctrl |= TIOCM_CAR;
1858
1859 return mctrl;
1860 }
1861
1862 static void sci_enable_ms(struct uart_port *port)
1863 {
1864 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1865 }
1866
1867 static void sci_break_ctl(struct uart_port *port, int break_state)
1868 {
1869 struct sci_port *s = to_sci_port(port);
1870 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1871 unsigned short scscr, scsptr;
1872
1873 /* check wheter the port has SCSPTR */
1874 if (!reg->size) {
1875 /*
1876 * Not supported by hardware. Most parts couple break and rx
1877 * interrupts together, with break detection always enabled.
1878 */
1879 return;
1880 }
1881
1882 scsptr = serial_port_in(port, SCSPTR);
1883 scscr = serial_port_in(port, SCSCR);
1884
1885 if (break_state == -1) {
1886 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1887 scscr &= ~SCSCR_TE;
1888 } else {
1889 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1890 scscr |= SCSCR_TE;
1891 }
1892
1893 serial_port_out(port, SCSPTR, scsptr);
1894 serial_port_out(port, SCSCR, scscr);
1895 }
1896
1897 static int sci_startup(struct uart_port *port)
1898 {
1899 struct sci_port *s = to_sci_port(port);
1900 unsigned long flags;
1901 int ret;
1902
1903 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1904
1905 ret = sci_request_irq(s);
1906 if (unlikely(ret < 0))
1907 return ret;
1908
1909 sci_request_dma(port);
1910
1911 spin_lock_irqsave(&port->lock, flags);
1912 sci_start_tx(port);
1913 sci_start_rx(port);
1914 spin_unlock_irqrestore(&port->lock, flags);
1915
1916 return 0;
1917 }
1918
1919 static void sci_shutdown(struct uart_port *port)
1920 {
1921 struct sci_port *s = to_sci_port(port);
1922 unsigned long flags;
1923
1924 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1925
1926 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
1927
1928 spin_lock_irqsave(&port->lock, flags);
1929 sci_stop_rx(port);
1930 sci_stop_tx(port);
1931 spin_unlock_irqrestore(&port->lock, flags);
1932
1933 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1934 if (s->chan_rx) {
1935 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1936 port->line);
1937 del_timer_sync(&s->rx_timer);
1938 }
1939 #endif
1940
1941 sci_free_dma(port);
1942 sci_free_irq(s);
1943 }
1944
1945 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
1946 unsigned int *srr)
1947 {
1948 unsigned long freq = s->clk_rates[SCI_SCK];
1949 int err, min_err = INT_MAX;
1950 unsigned int sr;
1951
1952 if (s->port.type != PORT_HSCIF)
1953 freq *= 2;
1954
1955 for_each_sr(sr, s) {
1956 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
1957 if (abs(err) >= abs(min_err))
1958 continue;
1959
1960 min_err = err;
1961 *srr = sr - 1;
1962
1963 if (!err)
1964 break;
1965 }
1966
1967 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
1968 *srr + 1);
1969 return min_err;
1970 }
1971
1972 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
1973 unsigned long freq, unsigned int *dlr,
1974 unsigned int *srr)
1975 {
1976 int err, min_err = INT_MAX;
1977 unsigned int sr, dl;
1978
1979 if (s->port.type != PORT_HSCIF)
1980 freq *= 2;
1981
1982 for_each_sr(sr, s) {
1983 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
1984 dl = clamp(dl, 1U, 65535U);
1985
1986 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
1987 if (abs(err) >= abs(min_err))
1988 continue;
1989
1990 min_err = err;
1991 *dlr = dl;
1992 *srr = sr - 1;
1993
1994 if (!err)
1995 break;
1996 }
1997
1998 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
1999 min_err, *dlr, *srr + 1);
2000 return min_err;
2001 }
2002
2003 /* calculate sample rate, BRR, and clock select */
2004 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2005 unsigned int *brr, unsigned int *srr,
2006 unsigned int *cks)
2007 {
2008 unsigned long freq = s->clk_rates[SCI_FCK];
2009 unsigned int sr, br, prediv, scrate, c;
2010 int err, min_err = INT_MAX;
2011
2012 if (s->port.type != PORT_HSCIF)
2013 freq *= 2;
2014
2015 /*
2016 * Find the combination of sample rate and clock select with the
2017 * smallest deviation from the desired baud rate.
2018 * Prefer high sample rates to maximise the receive margin.
2019 *
2020 * M: Receive margin (%)
2021 * N: Ratio of bit rate to clock (N = sampling rate)
2022 * D: Clock duty (D = 0 to 1.0)
2023 * L: Frame length (L = 9 to 12)
2024 * F: Absolute value of clock frequency deviation
2025 *
2026 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2027 * (|D - 0.5| / N * (1 + F))|
2028 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2029 */
2030 for_each_sr(sr, s) {
2031 for (c = 0; c <= 3; c++) {
2032 /* integerized formulas from HSCIF documentation */
2033 prediv = sr * (1 << (2 * c + 1));
2034
2035 /*
2036 * We need to calculate:
2037 *
2038 * br = freq / (prediv * bps) clamped to [1..256]
2039 * err = freq / (br * prediv) - bps
2040 *
2041 * Watch out for overflow when calculating the desired
2042 * sampling clock rate!
2043 */
2044 if (bps > UINT_MAX / prediv)
2045 break;
2046
2047 scrate = prediv * bps;
2048 br = DIV_ROUND_CLOSEST(freq, scrate);
2049 br = clamp(br, 1U, 256U);
2050
2051 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2052 if (abs(err) >= abs(min_err))
2053 continue;
2054
2055 min_err = err;
2056 *brr = br - 1;
2057 *srr = sr - 1;
2058 *cks = c;
2059
2060 if (!err)
2061 goto found;
2062 }
2063 }
2064
2065 found:
2066 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2067 min_err, *brr, *srr + 1, *cks);
2068 return min_err;
2069 }
2070
2071 static void sci_reset(struct uart_port *port)
2072 {
2073 const struct plat_sci_reg *reg;
2074 unsigned int status;
2075
2076 do {
2077 status = serial_port_in(port, SCxSR);
2078 } while (!(status & SCxSR_TEND(port)));
2079
2080 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
2081
2082 reg = sci_getreg(port, SCFCR);
2083 if (reg->size)
2084 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2085 }
2086
2087 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2088 struct ktermios *old)
2089 {
2090 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
2091 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2092 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2093 struct sci_port *s = to_sci_port(port);
2094 const struct plat_sci_reg *reg;
2095 int min_err = INT_MAX, err;
2096 unsigned long max_freq = 0;
2097 int best_clk = -1;
2098
2099 if ((termios->c_cflag & CSIZE) == CS7)
2100 smr_val |= SCSMR_CHR;
2101 if (termios->c_cflag & PARENB)
2102 smr_val |= SCSMR_PE;
2103 if (termios->c_cflag & PARODD)
2104 smr_val |= SCSMR_PE | SCSMR_ODD;
2105 if (termios->c_cflag & CSTOPB)
2106 smr_val |= SCSMR_STOP;
2107
2108 /*
2109 * earlyprintk comes here early on with port->uartclk set to zero.
2110 * the clock framework is not up and running at this point so here
2111 * we assume that 115200 is the maximum baud rate. please note that
2112 * the baud rate is not programmed during earlyprintk - it is assumed
2113 * that the previous boot loader has enabled required clocks and
2114 * setup the baud rate generator hardware for us already.
2115 */
2116 if (!port->uartclk) {
2117 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2118 goto done;
2119 }
2120
2121 for (i = 0; i < SCI_NUM_CLKS; i++)
2122 max_freq = max(max_freq, s->clk_rates[i]);
2123
2124 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2125 if (!baud)
2126 goto done;
2127
2128 /*
2129 * There can be multiple sources for the sampling clock. Find the one
2130 * that gives us the smallest deviation from the desired baud rate.
2131 */
2132
2133 /* Optional Undivided External Clock */
2134 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2135 port->type != PORT_SCIFB) {
2136 err = sci_sck_calc(s, baud, &srr1);
2137 if (abs(err) < abs(min_err)) {
2138 best_clk = SCI_SCK;
2139 scr_val = SCSCR_CKE1;
2140 sccks = SCCKS_CKS;
2141 min_err = err;
2142 srr = srr1;
2143 if (!err)
2144 goto done;
2145 }
2146 }
2147
2148 /* Optional BRG Frequency Divided External Clock */
2149 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2150 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2151 &srr1);
2152 if (abs(err) < abs(min_err)) {
2153 best_clk = SCI_SCIF_CLK;
2154 scr_val = SCSCR_CKE1;
2155 sccks = 0;
2156 min_err = err;
2157 dl = dl1;
2158 srr = srr1;
2159 if (!err)
2160 goto done;
2161 }
2162 }
2163
2164 /* Optional BRG Frequency Divided Internal Clock */
2165 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2166 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2167 &srr1);
2168 if (abs(err) < abs(min_err)) {
2169 best_clk = SCI_BRG_INT;
2170 scr_val = SCSCR_CKE1;
2171 sccks = SCCKS_XIN;
2172 min_err = err;
2173 dl = dl1;
2174 srr = srr1;
2175 if (!min_err)
2176 goto done;
2177 }
2178 }
2179
2180 /* Divided Functional Clock using standard Bit Rate Register */
2181 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2182 if (abs(err) < abs(min_err)) {
2183 best_clk = SCI_FCK;
2184 scr_val = 0;
2185 min_err = err;
2186 brr = brr1;
2187 srr = srr1;
2188 cks = cks1;
2189 }
2190
2191 done:
2192 if (best_clk >= 0)
2193 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2194 s->clks[best_clk], baud, min_err);
2195
2196 sci_port_enable(s);
2197
2198 /*
2199 * Program the optional External Baud Rate Generator (BRG) first.
2200 * It controls the mux to select (H)SCK or frequency divided clock.
2201 */
2202 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2203 serial_port_out(port, SCDL, dl);
2204 serial_port_out(port, SCCKS, sccks);
2205 }
2206
2207 sci_reset(port);
2208
2209 uart_update_timeout(port, termios->c_cflag, baud);
2210
2211 if (best_clk >= 0) {
2212 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2213 switch (srr + 1) {
2214 case 5: smr_val |= SCSMR_SRC_5; break;
2215 case 7: smr_val |= SCSMR_SRC_7; break;
2216 case 11: smr_val |= SCSMR_SRC_11; break;
2217 case 13: smr_val |= SCSMR_SRC_13; break;
2218 case 16: smr_val |= SCSMR_SRC_16; break;
2219 case 17: smr_val |= SCSMR_SRC_17; break;
2220 case 19: smr_val |= SCSMR_SRC_19; break;
2221 case 27: smr_val |= SCSMR_SRC_27; break;
2222 }
2223 smr_val |= cks;
2224 dev_dbg(port->dev,
2225 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2226 scr_val, smr_val, brr, sccks, dl, srr);
2227 serial_port_out(port, SCSCR, scr_val);
2228 serial_port_out(port, SCSMR, smr_val);
2229 serial_port_out(port, SCBRR, brr);
2230 if (sci_getreg(port, HSSRR)->size)
2231 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2232
2233 /* Wait one bit interval */
2234 udelay((1000000 + (baud - 1)) / baud);
2235 } else {
2236 /* Don't touch the bit rate configuration */
2237 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2238 smr_val |= serial_port_in(port, SCSMR) &
2239 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2240 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2241 serial_port_out(port, SCSCR, scr_val);
2242 serial_port_out(port, SCSMR, smr_val);
2243 }
2244
2245 sci_init_pins(port, termios->c_cflag);
2246
2247 reg = sci_getreg(port, SCFCR);
2248 if (reg->size) {
2249 unsigned short ctrl = serial_port_in(port, SCFCR);
2250
2251 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2252 if (termios->c_cflag & CRTSCTS)
2253 ctrl |= SCFCR_MCE;
2254 else
2255 ctrl &= ~SCFCR_MCE;
2256 }
2257
2258 /*
2259 * As we've done a sci_reset() above, ensure we don't
2260 * interfere with the FIFOs while toggling MCE. As the
2261 * reset values could still be set, simply mask them out.
2262 */
2263 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2264
2265 serial_port_out(port, SCFCR, ctrl);
2266 }
2267
2268 scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2269 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2270 serial_port_out(port, SCSCR, scr_val);
2271 if ((srr + 1 == 5) &&
2272 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2273 /*
2274 * In asynchronous mode, when the sampling rate is 1/5, first
2275 * received data may become invalid on some SCIFA and SCIFB.
2276 * To avoid this problem wait more than 1 serial data time (1
2277 * bit time x serial data number) after setting SCSCR.RE = 1.
2278 */
2279 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2280 }
2281
2282 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2283 /*
2284 * Calculate delay for 2 DMA buffers (4 FIFO).
2285 * See serial_core.c::uart_update_timeout().
2286 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2287 * function calculates 1 jiffie for the data plus 5 jiffies for the
2288 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2289 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2290 * value obtained by this formula is too small. Therefore, if the value
2291 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2292 */
2293 if (s->chan_rx) {
2294 unsigned int bits;
2295
2296 /* byte size and parity */
2297 switch (termios->c_cflag & CSIZE) {
2298 case CS5:
2299 bits = 7;
2300 break;
2301 case CS6:
2302 bits = 8;
2303 break;
2304 case CS7:
2305 bits = 9;
2306 break;
2307 default:
2308 bits = 10;
2309 break;
2310 }
2311
2312 if (termios->c_cflag & CSTOPB)
2313 bits++;
2314 if (termios->c_cflag & PARENB)
2315 bits++;
2316 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2317 (baud / 10), 10);
2318 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2319 s->rx_timeout * 1000 / HZ, port->timeout);
2320 if (s->rx_timeout < msecs_to_jiffies(20))
2321 s->rx_timeout = msecs_to_jiffies(20);
2322 }
2323 #endif
2324
2325 if ((termios->c_cflag & CREAD) != 0)
2326 sci_start_rx(port);
2327
2328 sci_port_disable(s);
2329
2330 if (UART_ENABLE_MS(port, termios->c_cflag))
2331 sci_enable_ms(port);
2332 }
2333
2334 static void sci_pm(struct uart_port *port, unsigned int state,
2335 unsigned int oldstate)
2336 {
2337 struct sci_port *sci_port = to_sci_port(port);
2338
2339 switch (state) {
2340 case UART_PM_STATE_OFF:
2341 sci_port_disable(sci_port);
2342 break;
2343 default:
2344 sci_port_enable(sci_port);
2345 break;
2346 }
2347 }
2348
2349 static const char *sci_type(struct uart_port *port)
2350 {
2351 switch (port->type) {
2352 case PORT_IRDA:
2353 return "irda";
2354 case PORT_SCI:
2355 return "sci";
2356 case PORT_SCIF:
2357 return "scif";
2358 case PORT_SCIFA:
2359 return "scifa";
2360 case PORT_SCIFB:
2361 return "scifb";
2362 case PORT_HSCIF:
2363 return "hscif";
2364 }
2365
2366 return NULL;
2367 }
2368
2369 static int sci_remap_port(struct uart_port *port)
2370 {
2371 struct sci_port *sport = to_sci_port(port);
2372
2373 /*
2374 * Nothing to do if there's already an established membase.
2375 */
2376 if (port->membase)
2377 return 0;
2378
2379 if (port->flags & UPF_IOREMAP) {
2380 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2381 if (unlikely(!port->membase)) {
2382 dev_err(port->dev, "can't remap port#%d\n", port->line);
2383 return -ENXIO;
2384 }
2385 } else {
2386 /*
2387 * For the simple (and majority of) cases where we don't
2388 * need to do any remapping, just cast the cookie
2389 * directly.
2390 */
2391 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2392 }
2393
2394 return 0;
2395 }
2396
2397 static void sci_release_port(struct uart_port *port)
2398 {
2399 struct sci_port *sport = to_sci_port(port);
2400
2401 if (port->flags & UPF_IOREMAP) {
2402 iounmap(port->membase);
2403 port->membase = NULL;
2404 }
2405
2406 release_mem_region(port->mapbase, sport->reg_size);
2407 }
2408
2409 static int sci_request_port(struct uart_port *port)
2410 {
2411 struct resource *res;
2412 struct sci_port *sport = to_sci_port(port);
2413 int ret;
2414
2415 res = request_mem_region(port->mapbase, sport->reg_size,
2416 dev_name(port->dev));
2417 if (unlikely(res == NULL)) {
2418 dev_err(port->dev, "request_mem_region failed.");
2419 return -EBUSY;
2420 }
2421
2422 ret = sci_remap_port(port);
2423 if (unlikely(ret != 0)) {
2424 release_resource(res);
2425 return ret;
2426 }
2427
2428 return 0;
2429 }
2430
2431 static void sci_config_port(struct uart_port *port, int flags)
2432 {
2433 if (flags & UART_CONFIG_TYPE) {
2434 struct sci_port *sport = to_sci_port(port);
2435
2436 port->type = sport->cfg->type;
2437 sci_request_port(port);
2438 }
2439 }
2440
2441 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2442 {
2443 if (ser->baud_base < 2400)
2444 /* No paper tape reader for Mitch.. */
2445 return -EINVAL;
2446
2447 return 0;
2448 }
2449
2450 static struct uart_ops sci_uart_ops = {
2451 .tx_empty = sci_tx_empty,
2452 .set_mctrl = sci_set_mctrl,
2453 .get_mctrl = sci_get_mctrl,
2454 .start_tx = sci_start_tx,
2455 .stop_tx = sci_stop_tx,
2456 .stop_rx = sci_stop_rx,
2457 .enable_ms = sci_enable_ms,
2458 .break_ctl = sci_break_ctl,
2459 .startup = sci_startup,
2460 .shutdown = sci_shutdown,
2461 .set_termios = sci_set_termios,
2462 .pm = sci_pm,
2463 .type = sci_type,
2464 .release_port = sci_release_port,
2465 .request_port = sci_request_port,
2466 .config_port = sci_config_port,
2467 .verify_port = sci_verify_port,
2468 #ifdef CONFIG_CONSOLE_POLL
2469 .poll_get_char = sci_poll_get_char,
2470 .poll_put_char = sci_poll_put_char,
2471 #endif
2472 };
2473
2474 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2475 {
2476 const char *clk_names[] = {
2477 [SCI_FCK] = "fck",
2478 [SCI_SCK] = "sck",
2479 [SCI_BRG_INT] = "brg_int",
2480 [SCI_SCIF_CLK] = "scif_clk",
2481 };
2482 struct clk *clk;
2483 unsigned int i;
2484
2485 if (sci_port->cfg->type == PORT_HSCIF)
2486 clk_names[SCI_SCK] = "hsck";
2487
2488 for (i = 0; i < SCI_NUM_CLKS; i++) {
2489 clk = devm_clk_get(dev, clk_names[i]);
2490 if (PTR_ERR(clk) == -EPROBE_DEFER)
2491 return -EPROBE_DEFER;
2492
2493 if (IS_ERR(clk) && i == SCI_FCK) {
2494 /*
2495 * "fck" used to be called "sci_ick", and we need to
2496 * maintain DT backward compatibility.
2497 */
2498 clk = devm_clk_get(dev, "sci_ick");
2499 if (PTR_ERR(clk) == -EPROBE_DEFER)
2500 return -EPROBE_DEFER;
2501
2502 if (!IS_ERR(clk))
2503 goto found;
2504
2505 /*
2506 * Not all SH platforms declare a clock lookup entry
2507 * for SCI devices, in which case we need to get the
2508 * global "peripheral_clk" clock.
2509 */
2510 clk = devm_clk_get(dev, "peripheral_clk");
2511 if (!IS_ERR(clk))
2512 goto found;
2513
2514 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2515 PTR_ERR(clk));
2516 return PTR_ERR(clk);
2517 }
2518
2519 found:
2520 if (IS_ERR(clk))
2521 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2522 PTR_ERR(clk));
2523 else
2524 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2525 clk, clk);
2526 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2527 }
2528 return 0;
2529 }
2530
2531 static int sci_init_single(struct platform_device *dev,
2532 struct sci_port *sci_port, unsigned int index,
2533 struct plat_sci_port *p, bool early)
2534 {
2535 struct uart_port *port = &sci_port->port;
2536 const struct resource *res;
2537 unsigned int i;
2538 int ret;
2539
2540 sci_port->cfg = p;
2541
2542 port->ops = &sci_uart_ops;
2543 port->iotype = UPIO_MEM;
2544 port->line = index;
2545
2546 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2547 if (res == NULL)
2548 return -ENOMEM;
2549
2550 port->mapbase = res->start;
2551 sci_port->reg_size = resource_size(res);
2552
2553 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2554 sci_port->irqs[i] = platform_get_irq(dev, i);
2555
2556 /* The SCI generates several interrupts. They can be muxed together or
2557 * connected to different interrupt lines. In the muxed case only one
2558 * interrupt resource is specified. In the non-muxed case three or four
2559 * interrupt resources are specified, as the BRI interrupt is optional.
2560 */
2561 if (sci_port->irqs[0] < 0)
2562 return -ENXIO;
2563
2564 if (sci_port->irqs[1] < 0) {
2565 sci_port->irqs[1] = sci_port->irqs[0];
2566 sci_port->irqs[2] = sci_port->irqs[0];
2567 sci_port->irqs[3] = sci_port->irqs[0];
2568 }
2569
2570 if (p->regtype == SCIx_PROBE_REGTYPE) {
2571 ret = sci_probe_regmap(p);
2572 if (unlikely(ret))
2573 return ret;
2574 }
2575
2576 switch (p->type) {
2577 case PORT_SCIFB:
2578 port->fifosize = 256;
2579 sci_port->overrun_reg = SCxSR;
2580 sci_port->overrun_mask = SCIFA_ORER;
2581 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2582 break;
2583 case PORT_HSCIF:
2584 port->fifosize = 128;
2585 sci_port->overrun_reg = SCLSR;
2586 sci_port->overrun_mask = SCLSR_ORER;
2587 sci_port->sampling_rate_mask = SCI_SR_RANGE(8, 32);
2588 break;
2589 case PORT_SCIFA:
2590 port->fifosize = 64;
2591 sci_port->overrun_reg = SCxSR;
2592 sci_port->overrun_mask = SCIFA_ORER;
2593 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2594 break;
2595 case PORT_SCIF:
2596 port->fifosize = 16;
2597 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2598 sci_port->overrun_reg = SCxSR;
2599 sci_port->overrun_mask = SCIFA_ORER;
2600 sci_port->sampling_rate_mask = SCI_SR(16);
2601 } else {
2602 sci_port->overrun_reg = SCLSR;
2603 sci_port->overrun_mask = SCLSR_ORER;
2604 sci_port->sampling_rate_mask = SCI_SR(32);
2605 }
2606 break;
2607 default:
2608 port->fifosize = 1;
2609 sci_port->overrun_reg = SCxSR;
2610 sci_port->overrun_mask = SCI_ORER;
2611 sci_port->sampling_rate_mask = SCI_SR(32);
2612 break;
2613 }
2614
2615 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2616 * match the SoC datasheet, this should be investigated. Let platform
2617 * data override the sampling rate for now.
2618 */
2619 if (p->sampling_rate)
2620 sci_port->sampling_rate_mask = SCI_SR(p->sampling_rate);
2621
2622 if (!early) {
2623 ret = sci_init_clocks(sci_port, &dev->dev);
2624 if (ret < 0)
2625 return ret;
2626
2627 port->dev = &dev->dev;
2628
2629 pm_runtime_enable(&dev->dev);
2630 }
2631
2632 sci_port->break_timer.data = (unsigned long)sci_port;
2633 sci_port->break_timer.function = sci_break_timer;
2634 init_timer(&sci_port->break_timer);
2635
2636 /*
2637 * Establish some sensible defaults for the error detection.
2638 */
2639 if (p->type == PORT_SCI) {
2640 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2641 sci_port->error_clear = SCI_ERROR_CLEAR;
2642 } else {
2643 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2644 sci_port->error_clear = SCIF_ERROR_CLEAR;
2645 }
2646
2647 /*
2648 * Make the error mask inclusive of overrun detection, if
2649 * supported.
2650 */
2651 if (sci_port->overrun_reg == SCxSR) {
2652 sci_port->error_mask |= sci_port->overrun_mask;
2653 sci_port->error_clear &= ~sci_port->overrun_mask;
2654 }
2655
2656 port->type = p->type;
2657 port->flags = UPF_FIXED_PORT | p->flags;
2658 port->regshift = p->regshift;
2659
2660 /*
2661 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2662 * for the multi-IRQ ports, which is where we are primarily
2663 * concerned with the shutdown path synchronization.
2664 *
2665 * For the muxed case there's nothing more to do.
2666 */
2667 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2668 port->irqflags = 0;
2669
2670 port->serial_in = sci_serial_in;
2671 port->serial_out = sci_serial_out;
2672
2673 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2674 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2675 p->dma_slave_tx, p->dma_slave_rx);
2676
2677 return 0;
2678 }
2679
2680 static void sci_cleanup_single(struct sci_port *port)
2681 {
2682 pm_runtime_disable(port->port.dev);
2683 }
2684
2685 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2686 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2687 static void serial_console_putchar(struct uart_port *port, int ch)
2688 {
2689 sci_poll_put_char(port, ch);
2690 }
2691
2692 /*
2693 * Print a string to the serial port trying not to disturb
2694 * any possible real use of the port...
2695 */
2696 static void serial_console_write(struct console *co, const char *s,
2697 unsigned count)
2698 {
2699 struct sci_port *sci_port = &sci_ports[co->index];
2700 struct uart_port *port = &sci_port->port;
2701 unsigned short bits, ctrl, ctrl_temp;
2702 unsigned long flags;
2703 int locked = 1;
2704
2705 local_irq_save(flags);
2706 #if defined(SUPPORT_SYSRQ)
2707 if (port->sysrq)
2708 locked = 0;
2709 else
2710 #endif
2711 if (oops_in_progress)
2712 locked = spin_trylock(&port->lock);
2713 else
2714 spin_lock(&port->lock);
2715
2716 /* first save SCSCR then disable interrupts, keep clock source */
2717 ctrl = serial_port_in(port, SCSCR);
2718 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2719 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2720 serial_port_out(port, SCSCR, ctrl_temp);
2721
2722 uart_console_write(port, s, count, serial_console_putchar);
2723
2724 /* wait until fifo is empty and last bit has been transmitted */
2725 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2726 while ((serial_port_in(port, SCxSR) & bits) != bits)
2727 cpu_relax();
2728
2729 /* restore the SCSCR */
2730 serial_port_out(port, SCSCR, ctrl);
2731
2732 if (locked)
2733 spin_unlock(&port->lock);
2734 local_irq_restore(flags);
2735 }
2736
2737 static int serial_console_setup(struct console *co, char *options)
2738 {
2739 struct sci_port *sci_port;
2740 struct uart_port *port;
2741 int baud = 115200;
2742 int bits = 8;
2743 int parity = 'n';
2744 int flow = 'n';
2745 int ret;
2746
2747 /*
2748 * Refuse to handle any bogus ports.
2749 */
2750 if (co->index < 0 || co->index >= SCI_NPORTS)
2751 return -ENODEV;
2752
2753 sci_port = &sci_ports[co->index];
2754 port = &sci_port->port;
2755
2756 /*
2757 * Refuse to handle uninitialized ports.
2758 */
2759 if (!port->ops)
2760 return -ENODEV;
2761
2762 ret = sci_remap_port(port);
2763 if (unlikely(ret != 0))
2764 return ret;
2765
2766 if (options)
2767 uart_parse_options(options, &baud, &parity, &bits, &flow);
2768
2769 return uart_set_options(port, co, baud, parity, bits, flow);
2770 }
2771
2772 static struct console serial_console = {
2773 .name = "ttySC",
2774 .device = uart_console_device,
2775 .write = serial_console_write,
2776 .setup = serial_console_setup,
2777 .flags = CON_PRINTBUFFER,
2778 .index = -1,
2779 .data = &sci_uart_driver,
2780 };
2781
2782 static struct console early_serial_console = {
2783 .name = "early_ttySC",
2784 .write = serial_console_write,
2785 .flags = CON_PRINTBUFFER,
2786 .index = -1,
2787 };
2788
2789 static char early_serial_buf[32];
2790
2791 static int sci_probe_earlyprintk(struct platform_device *pdev)
2792 {
2793 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2794
2795 if (early_serial_console.data)
2796 return -EEXIST;
2797
2798 early_serial_console.index = pdev->id;
2799
2800 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2801
2802 serial_console_setup(&early_serial_console, early_serial_buf);
2803
2804 if (!strstr(early_serial_buf, "keep"))
2805 early_serial_console.flags |= CON_BOOT;
2806
2807 register_console(&early_serial_console);
2808 return 0;
2809 }
2810
2811 #define SCI_CONSOLE (&serial_console)
2812
2813 #else
2814 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2815 {
2816 return -EINVAL;
2817 }
2818
2819 #define SCI_CONSOLE NULL
2820
2821 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
2822
2823 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2824
2825 static struct uart_driver sci_uart_driver = {
2826 .owner = THIS_MODULE,
2827 .driver_name = "sci",
2828 .dev_name = "ttySC",
2829 .major = SCI_MAJOR,
2830 .minor = SCI_MINOR_START,
2831 .nr = SCI_NPORTS,
2832 .cons = SCI_CONSOLE,
2833 };
2834
2835 static int sci_remove(struct platform_device *dev)
2836 {
2837 struct sci_port *port = platform_get_drvdata(dev);
2838
2839 uart_remove_one_port(&sci_uart_driver, &port->port);
2840
2841 sci_cleanup_single(port);
2842
2843 return 0;
2844 }
2845
2846
2847 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2848 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2849 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
2850
2851 static const struct of_device_id of_sci_match[] = {
2852 /* SoC-specific types */
2853 {
2854 .compatible = "renesas,scif-r7s72100",
2855 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2856 },
2857 /* Family-specific types */
2858 {
2859 .compatible = "renesas,rcar-gen1-scif",
2860 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2861 }, {
2862 .compatible = "renesas,rcar-gen2-scif",
2863 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2864 }, {
2865 .compatible = "renesas,rcar-gen3-scif",
2866 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2867 },
2868 /* Generic types */
2869 {
2870 .compatible = "renesas,scif",
2871 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2872 }, {
2873 .compatible = "renesas,scifa",
2874 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2875 }, {
2876 .compatible = "renesas,scifb",
2877 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
2878 }, {
2879 .compatible = "renesas,hscif",
2880 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
2881 }, {
2882 .compatible = "renesas,sci",
2883 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
2884 }, {
2885 /* Terminator */
2886 },
2887 };
2888 MODULE_DEVICE_TABLE(of, of_sci_match);
2889
2890 static struct plat_sci_port *
2891 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2892 {
2893 struct device_node *np = pdev->dev.of_node;
2894 const struct of_device_id *match;
2895 struct plat_sci_port *p;
2896 int id;
2897
2898 if (!IS_ENABLED(CONFIG_OF) || !np)
2899 return NULL;
2900
2901 match = of_match_node(of_sci_match, np);
2902 if (!match)
2903 return NULL;
2904
2905 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2906 if (!p)
2907 return NULL;
2908
2909 /* Get the line number from the aliases node. */
2910 id = of_alias_get_id(np, "serial");
2911 if (id < 0) {
2912 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2913 return NULL;
2914 }
2915
2916 *dev_id = id;
2917
2918 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2919 p->type = SCI_OF_TYPE(match->data);
2920 p->regtype = SCI_OF_REGTYPE(match->data);
2921 p->scscr = SCSCR_RE | SCSCR_TE;
2922
2923 return p;
2924 }
2925
2926 static int sci_probe_single(struct platform_device *dev,
2927 unsigned int index,
2928 struct plat_sci_port *p,
2929 struct sci_port *sciport)
2930 {
2931 int ret;
2932
2933 /* Sanity check */
2934 if (unlikely(index >= SCI_NPORTS)) {
2935 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2936 index+1, SCI_NPORTS);
2937 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2938 return -EINVAL;
2939 }
2940
2941 ret = sci_init_single(dev, sciport, index, p, false);
2942 if (ret)
2943 return ret;
2944
2945 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
2946 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
2947 return PTR_ERR(sciport->gpios);
2948
2949 if (p->capabilities & SCIx_HAVE_RTSCTS) {
2950 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
2951 UART_GPIO_CTS)) ||
2952 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
2953 UART_GPIO_RTS))) {
2954 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
2955 return -EINVAL;
2956 }
2957 }
2958
2959 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2960 if (ret) {
2961 sci_cleanup_single(sciport);
2962 return ret;
2963 }
2964
2965 return 0;
2966 }
2967
2968 static int sci_probe(struct platform_device *dev)
2969 {
2970 struct plat_sci_port *p;
2971 struct sci_port *sp;
2972 unsigned int dev_id;
2973 int ret;
2974
2975 /*
2976 * If we've come here via earlyprintk initialization, head off to
2977 * the special early probe. We don't have sufficient device state
2978 * to make it beyond this yet.
2979 */
2980 if (is_early_platform_device(dev))
2981 return sci_probe_earlyprintk(dev);
2982
2983 if (dev->dev.of_node) {
2984 p = sci_parse_dt(dev, &dev_id);
2985 if (p == NULL)
2986 return -EINVAL;
2987 } else {
2988 p = dev->dev.platform_data;
2989 if (p == NULL) {
2990 dev_err(&dev->dev, "no platform data supplied\n");
2991 return -EINVAL;
2992 }
2993
2994 dev_id = dev->id;
2995 }
2996
2997 sp = &sci_ports[dev_id];
2998 platform_set_drvdata(dev, sp);
2999
3000 ret = sci_probe_single(dev, dev_id, p, sp);
3001 if (ret)
3002 return ret;
3003
3004 #ifdef CONFIG_SH_STANDARD_BIOS
3005 sh_bios_gdb_detach();
3006 #endif
3007
3008 return 0;
3009 }
3010
3011 static __maybe_unused int sci_suspend(struct device *dev)
3012 {
3013 struct sci_port *sport = dev_get_drvdata(dev);
3014
3015 if (sport)
3016 uart_suspend_port(&sci_uart_driver, &sport->port);
3017
3018 return 0;
3019 }
3020
3021 static __maybe_unused int sci_resume(struct device *dev)
3022 {
3023 struct sci_port *sport = dev_get_drvdata(dev);
3024
3025 if (sport)
3026 uart_resume_port(&sci_uart_driver, &sport->port);
3027
3028 return 0;
3029 }
3030
3031 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3032
3033 static struct platform_driver sci_driver = {
3034 .probe = sci_probe,
3035 .remove = sci_remove,
3036 .driver = {
3037 .name = "sh-sci",
3038 .pm = &sci_dev_pm_ops,
3039 .of_match_table = of_match_ptr(of_sci_match),
3040 },
3041 };
3042
3043 static int __init sci_init(void)
3044 {
3045 int ret;
3046
3047 pr_info("%s\n", banner);
3048
3049 ret = uart_register_driver(&sci_uart_driver);
3050 if (likely(ret == 0)) {
3051 ret = platform_driver_register(&sci_driver);
3052 if (unlikely(ret))
3053 uart_unregister_driver(&sci_uart_driver);
3054 }
3055
3056 return ret;
3057 }
3058
3059 static void __exit sci_exit(void)
3060 {
3061 platform_driver_unregister(&sci_driver);
3062 uart_unregister_driver(&sci_uart_driver);
3063 }
3064
3065 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3066 early_platform_init_buffer("earlyprintk", &sci_driver,
3067 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3068 #endif
3069 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3070 static struct __init plat_sci_port port_cfg;
3071
3072 static int __init early_console_setup(struct earlycon_device *device,
3073 int type)
3074 {
3075 if (!device->port.membase)
3076 return -ENODEV;
3077
3078 device->port.serial_in = sci_serial_in;
3079 device->port.serial_out = sci_serial_out;
3080 device->port.type = type;
3081 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3082 sci_ports[0].cfg = &port_cfg;
3083 sci_ports[0].cfg->type = type;
3084 sci_probe_regmap(sci_ports[0].cfg);
3085 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) |
3086 SCSCR_RE | SCSCR_TE;
3087 sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr);
3088
3089 device->con->write = serial_console_write;
3090 return 0;
3091 }
3092 static int __init sci_early_console_setup(struct earlycon_device *device,
3093 const char *opt)
3094 {
3095 return early_console_setup(device, PORT_SCI);
3096 }
3097 static int __init scif_early_console_setup(struct earlycon_device *device,
3098 const char *opt)
3099 {
3100 return early_console_setup(device, PORT_SCIF);
3101 }
3102 static int __init scifa_early_console_setup(struct earlycon_device *device,
3103 const char *opt)
3104 {
3105 return early_console_setup(device, PORT_SCIFA);
3106 }
3107 static int __init scifb_early_console_setup(struct earlycon_device *device,
3108 const char *opt)
3109 {
3110 return early_console_setup(device, PORT_SCIFB);
3111 }
3112 static int __init hscif_early_console_setup(struct earlycon_device *device,
3113 const char *opt)
3114 {
3115 return early_console_setup(device, PORT_HSCIF);
3116 }
3117
3118 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3119 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3120 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3121 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3122 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3123 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3124
3125 module_init(sci_init);
3126 module_exit(sci_exit);
3127
3128 MODULE_LICENSE("GPL");
3129 MODULE_ALIAS("platform:sh-sci");
3130 MODULE_AUTHOR("Paul Mundt");
3131 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
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