3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/clocksource.h>
18 #include <linux/clockchips.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
24 #include <asm/mach/time.h>
25 #include <asm/hardware/gic.h>
26 #include <asm/localtimer.h>
27 #include <asm/sched_clock.h>
29 #include <mach/msm_iomap.h>
31 #include <mach/board.h>
33 #define TIMER_MATCH_VAL 0x0000
34 #define TIMER_COUNT_VAL 0x0004
35 #define TIMER_ENABLE 0x0008
36 #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
37 #define TIMER_ENABLE_EN BIT(0)
38 #define TIMER_CLEAR 0x000C
39 #define DGT_CLK_CTL 0x0034
40 #define DGT_CLK_CTL_DIV_4 0x3
44 #define MSM_DGT_SHIFT 5
46 static void __iomem
*event_base
;
48 static irqreturn_t
msm_timer_interrupt(int irq
, void *dev_id
)
50 struct clock_event_device
*evt
= *(struct clock_event_device
**)dev_id
;
51 /* Stop the timer tick */
52 if (evt
->mode
== CLOCK_EVT_MODE_ONESHOT
) {
53 u32 ctrl
= readl_relaxed(event_base
+ TIMER_ENABLE
);
54 ctrl
&= ~TIMER_ENABLE_EN
;
55 writel_relaxed(ctrl
, event_base
+ TIMER_ENABLE
);
57 evt
->event_handler(evt
);
61 static int msm_timer_set_next_event(unsigned long cycles
,
62 struct clock_event_device
*evt
)
64 u32 ctrl
= readl_relaxed(event_base
+ TIMER_ENABLE
);
66 writel_relaxed(0, event_base
+ TIMER_CLEAR
);
67 writel_relaxed(cycles
, event_base
+ TIMER_MATCH_VAL
);
68 writel_relaxed(ctrl
| TIMER_ENABLE_EN
, event_base
+ TIMER_ENABLE
);
72 static void msm_timer_set_mode(enum clock_event_mode mode
,
73 struct clock_event_device
*evt
)
77 ctrl
= readl_relaxed(event_base
+ TIMER_ENABLE
);
78 ctrl
&= ~(TIMER_ENABLE_EN
| TIMER_ENABLE_CLR_ON_MATCH_EN
);
81 case CLOCK_EVT_MODE_RESUME
:
82 case CLOCK_EVT_MODE_PERIODIC
:
84 case CLOCK_EVT_MODE_ONESHOT
:
85 /* Timer is enabled in set_next_event */
87 case CLOCK_EVT_MODE_UNUSED
:
88 case CLOCK_EVT_MODE_SHUTDOWN
:
91 writel_relaxed(ctrl
, event_base
+ TIMER_ENABLE
);
94 static struct clock_event_device msm_clockevent
= {
96 .features
= CLOCK_EVT_FEAT_ONESHOT
,
98 .set_next_event
= msm_timer_set_next_event
,
99 .set_mode
= msm_timer_set_mode
,
103 struct clock_event_device
*evt
;
104 struct clock_event_device __percpu
**percpu_evt
;
107 static void __iomem
*source_base
;
109 static notrace cycle_t
msm_read_timer_count(struct clocksource
*cs
)
111 return readl_relaxed(source_base
+ TIMER_COUNT_VAL
);
114 static notrace cycle_t
msm_read_timer_count_shift(struct clocksource
*cs
)
117 * Shift timer count down by a constant due to unreliable lower bits
120 return msm_read_timer_count(cs
) >> MSM_DGT_SHIFT
;
123 static struct clocksource msm_clocksource
= {
126 .read
= msm_read_timer_count
,
127 .mask
= CLOCKSOURCE_MASK(32),
128 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
131 static notrace u32
msm_sched_clock_read(void)
133 return msm_clocksource
.read(&msm_clocksource
);
136 static void __init
msm_timer_init(void)
138 struct clock_event_device
*ce
= &msm_clockevent
;
139 struct clocksource
*cs
= &msm_clocksource
;
143 if (cpu_is_msm7x01()) {
144 event_base
= MSM_CSR_BASE
;
145 source_base
= MSM_CSR_BASE
+ 0x10;
146 dgt_hz
= 19200000 >> MSM_DGT_SHIFT
; /* 600 KHz */
147 cs
->read
= msm_read_timer_count_shift
;
148 cs
->mask
= CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT
));
149 } else if (cpu_is_msm7x30()) {
150 event_base
= MSM_CSR_BASE
+ 0x04;
151 source_base
= MSM_CSR_BASE
+ 0x24;
152 dgt_hz
= 24576000 / 4;
153 } else if (cpu_is_qsd8x50()) {
154 event_base
= MSM_CSR_BASE
;
155 source_base
= MSM_CSR_BASE
+ 0x10;
156 dgt_hz
= 19200000 / 4;
157 } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
158 event_base
= MSM_TMR_BASE
+ 0x04;
159 /* Use CPU0's timer as the global clock source. */
160 source_base
= MSM_TMR0_BASE
+ 0x24;
161 dgt_hz
= 27000000 / 4;
162 writel_relaxed(DGT_CLK_CTL_DIV_4
, MSM_TMR_BASE
+ DGT_CLK_CTL
);
166 writel_relaxed(0, event_base
+ TIMER_ENABLE
);
167 writel_relaxed(0, event_base
+ TIMER_CLEAR
);
168 writel_relaxed(~0, event_base
+ TIMER_MATCH_VAL
);
169 ce
->cpumask
= cpumask_of(0);
171 ce
->irq
= INT_GP_TIMER_EXP
;
172 clockevents_config_and_register(ce
, GPT_HZ
, 4, 0xffffffff);
173 if (cpu_is_msm8x60() || cpu_is_msm8960()) {
174 msm_evt
.percpu_evt
= alloc_percpu(struct clock_event_device
*);
175 if (!msm_evt
.percpu_evt
) {
176 pr_err("memory allocation failed for %s\n", ce
->name
);
179 *__this_cpu_ptr(msm_evt
.percpu_evt
) = ce
;
180 res
= request_percpu_irq(ce
->irq
, msm_timer_interrupt
,
181 ce
->name
, msm_evt
.percpu_evt
);
183 enable_percpu_irq(ce
->irq
, 0);
186 res
= request_irq(ce
->irq
, msm_timer_interrupt
,
187 IRQF_TIMER
| IRQF_NOBALANCING
|
188 IRQF_TRIGGER_RISING
, ce
->name
, &msm_evt
.evt
);
192 pr_err("request_irq failed for %s\n", ce
->name
);
194 writel_relaxed(TIMER_ENABLE_EN
, source_base
+ TIMER_ENABLE
);
195 res
= clocksource_register_hz(cs
, dgt_hz
);
197 pr_err("clocksource_register failed\n");
198 setup_sched_clock(msm_sched_clock_read
,
199 cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT
: 32, dgt_hz
);
202 #ifdef CONFIG_LOCAL_TIMERS
203 int __cpuinit
local_timer_setup(struct clock_event_device
*evt
)
205 /* Use existing clock_event for cpu 0 */
206 if (!smp_processor_id())
209 writel_relaxed(0, event_base
+ TIMER_ENABLE
);
210 writel_relaxed(0, event_base
+ TIMER_CLEAR
);
211 writel_relaxed(~0, event_base
+ TIMER_MATCH_VAL
);
212 evt
->irq
= msm_clockevent
.irq
;
213 evt
->name
= "local_timer";
214 evt
->features
= msm_clockevent
.features
;
215 evt
->rating
= msm_clockevent
.rating
;
216 evt
->set_mode
= msm_timer_set_mode
;
217 evt
->set_next_event
= msm_timer_set_next_event
;
218 evt
->shift
= msm_clockevent
.shift
;
219 evt
->mult
= div_sc(GPT_HZ
, NSEC_PER_SEC
, evt
->shift
);
220 evt
->max_delta_ns
= clockevent_delta2ns(0xf0000000, evt
);
221 evt
->min_delta_ns
= clockevent_delta2ns(4, evt
);
223 *__this_cpu_ptr(msm_evt
.percpu_evt
) = evt
;
224 clockevents_register_device(evt
);
225 enable_percpu_irq(evt
->irq
, 0);
229 void local_timer_stop(struct clock_event_device
*evt
)
231 evt
->set_mode(CLOCK_EVT_MODE_UNUSED
, evt
);
232 disable_percpu_irq(evt
->irq
);
234 #endif /* CONFIG_LOCAL_TIMERS */
236 struct sys_timer msm_timer
= {
237 .init
= msm_timer_init