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Staging: et131x: kill TXTEST and TXFILL, clean up CF_PARAM
[linux-2.6/btrfs-unstable.git] / drivers / staging / et131x / et1310_address_map.h
blob9fa8628f81f5c653016410512e64a0abf4bb2e6a
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright © 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et1310_address_map.h - Contains the register mapping for the ET1310
12 *
13 *------------------------------------------------------------------------------
14 *
15 * SOFTWARE LICENSE
16 *
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
21 *
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
24 *
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
27 *
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
31 * distribution.
32 *
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
36 *
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * Disclaimer
42 *
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 * DAMAGE.
55 *
56 */
57
58 #ifndef _ET1310_ADDRESS_MAP_H_
59 #define _ET1310_ADDRESS_MAP_H_
60
61
62 /* START OF GLOBAL REGISTER ADDRESS MAP */
63
64 /*
65 * 10bit registers
66 *
67 * Tx queue start address reg in global address map at address 0x0000
68 * tx queue end address reg in global address map at address 0x0004
69 * rx queue start address reg in global address map at address 0x0008
70 * rx queue end address reg in global address map at address 0x000C
71 */
72
73 /*
74 * structure for power management control status reg in global address map
75 * located at address 0x0010
76 * jagcore_rx_rdy bit 9
77 * jagcore_tx_rdy bit 8
78 * phy_lped_en bit 7
79 * phy_sw_coma bit 6
80 * rxclk_gate bit 5
81 * txclk_gate bit 4
82 * sysclk_gate bit 3
83 * jagcore_rx_en bit 2
84 * jagcore_tx_en bit 1
85 * gigephy_en bit 0
86 */
87
88 #define ET_PM_PHY_SW_COMA 0x40
89 #define ET_PMCSR_INIT 0x38
90
91 /*
92 * Interrupt status reg at address 0x0018
93 */
94
95 #define ET_INTR_TXDMA_ISR 0x00000008
96 #define ET_INTR_TXDMA_ERR 0x00000010
97 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
98 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
99 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
100 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
101 #define ET_INTR_RXDMA_ERR 0x00000200
102 #define ET_INTR_WATCHDOG 0x00004000
103 #define ET_INTR_WOL 0x00008000
104 #define ET_INTR_PHY 0x00010000
105 #define ET_INTR_TXMAC 0x00020000
106 #define ET_INTR_RXMAC 0x00040000
107 #define ET_INTR_MAC_STAT 0x00080000
108 #define ET_INTR_SLV_TIMEOUT 0x00100000
109
110 /*
111 * Interrupt mask register at address 0x001C
112 * Interrupt alias clear mask reg at address 0x0020
113 * Interrupt status alias reg at address 0x0024
114 *
115 * Same masks as above
116 */
117
118 /*
119 * Software reset reg at address 0x0028
120 * 0: txdma_sw_reset
121 * 1: rxdma_sw_reset
122 * 2: txmac_sw_reset
123 * 3: rxmac_sw_reset
124 * 4: mac_sw_reset
125 * 5: mac_stat_sw_reset
126 * 6: mmc_sw_reset
127 *31: selfclr_disable
128 */
129
130 /*
131 * SLV Timer reg at address 0x002C (low 24 bits)
132 */
133
134 /*
135 * MSI Configuration reg at address 0x0030
136 */
137
138 #define ET_MSI_VECTOR 0x0000001F
139 #define ET_MSI_TC 0x00070000
140
141 /*
142 * Loopback reg located at address 0x0034
143 */
144
145 #define ET_LOOP_MAC 0x00000001
146 #define ET_LOOP_DMA 0x00000002
147
148 /*
149 * GLOBAL Module of JAGCore Address Mapping
150 * Located at address 0x0000
151 */
152 typedef struct _GLOBAL_t { /* Location: */
153 u32 txq_start_addr; /* 0x0000 */
154 u32 txq_end_addr; /* 0x0004 */
155 u32 rxq_start_addr; /* 0x0008 */
156 u32 rxq_end_addr; /* 0x000C */
157 u32 pm_csr; /* 0x0010 */
158 u32 unused; /* 0x0014 */
159 u32 int_status; /* 0x0018 */
160 u32 int_mask; /* 0x001C */
161 u32 int_alias_clr_en; /* 0x0020 */
162 u32 int_status_alias; /* 0x0024 */
163 u32 sw_reset; /* 0x0028 */
164 u32 slv_timer; /* 0x002C */
165 u32 msi_config; /* 0x0030 */
166 u32 loopback; /* 0x0034 */
167 u32 watchdog_timer; /* 0x0038 */
168 } GLOBAL_t, *PGLOBAL_t;
169
170 /* END OF GLOBAL REGISTER ADDRESS MAP */
171
172
173 /* START OF TXDMA REGISTER ADDRESS MAP */
174
175 /*
176 * txdma control status reg at address 0x1000
177 */
178
179 #define ET_TXDMA_CSR_HALT 0x00000001
180 #define ET_TXDMA_DROP_TLP 0x00000002
181 #define ET_TXDMA_CACHE_THRS 0x000000F0
182 #define ET_TXDMA_CACHE_SHIFT 4
183 #define ET_TXDMA_SNGL_EPKT 0x00000100
184 #define ET_TXDMA_CLASS 0x00001E00
185
186 /*
187 * structure for txdma packet ring base address hi reg in txdma address map
188 * located at address 0x1004
189 * Defined earlier (u32)
190 */
191
192 /*
193 * structure for txdma packet ring base address low reg in txdma address map
194 * located at address 0x1008
195 * Defined earlier (u32)
196 */
197
198 /*
199 * structure for txdma packet ring number of descriptor reg in txdma address
200 * map. Located at address 0x100C
201 */
202 typedef union _TXDMA_PR_NUM_DES_t {
203 u32 value;
204 struct {
205 #ifdef _BIT_FIELDS_HTOL
206 u32 unused:22; /* bits 10-31 */
207 u32 pr_ndes:10; /* bits 0-9 */
208 #else
209 u32 pr_ndes:10; /* bits 0-9 */
210 u32 unused:22; /* bits 10-31 */
211 #endif
212 } bits;
213 } TXDMA_PR_NUM_DES_t, *PTXDMA_PR_NUM_DES_t;
214
215
216 #define ET_DMA10_MASK 0x3FF /* 10 bit mask for DMA10W types */
217 #define ET_DMA10_WRAP 0x400
218 #define ET_DMA4_MASK 0x00F /* 4 bit mask for DMA4W types */
219 #define ET_DMA4_WRAP 0x010
220
221 #define INDEX10(x) ((x) & ET_DMA10_MASK)
222 #define INDEX4(x) ((x) & ET_DMA4_MASK)
223
224 extern inline void add_10bit(u32 *v, int n)
225 {
226 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
227 }
228
229 /*
230 * 10bit DMA with wrap
231 * txdma tx queue write address reg in txdma address map at 0x1010
232 * txdma tx queue write address external reg in txdma address map at 0x1014
233 * txdma tx queue read address reg in txdma address map at 0x1018
234 *
235 * u32
236 * txdma status writeback address hi reg in txdma address map at0x101C
237 * txdma status writeback address lo reg in txdma address map at 0x1020
238 *
239 * 10bit DMA with wrap
240 * txdma service request reg in txdma address map at 0x1024
241 * structure for txdma service complete reg in txdma address map at 0x1028
242 *
243 * 4bit DMA with wrap
244 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
245 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
246 *
247 * txdma error reg in txdma address map at address 0x1034
248 * 0: PyldResend
249 * 1: PyldRewind
250 * 4: DescrResend
251 * 5: DescrRewind
252 * 8: WrbkResend
253 * 9: WrbkRewind
254 */
255
256 /*
257 * Tx DMA Module of JAGCore Address Mapping
258 * Located at address 0x1000
259 */
260 typedef struct _TXDMA_t { /* Location: */
261 u32 csr; /* 0x1000 */
262 u32 pr_base_hi; /* 0x1004 */
263 u32 pr_base_lo; /* 0x1008 */
264 TXDMA_PR_NUM_DES_t pr_num_des; /* 0x100C */
265 u32 txq_wr_addr; /* 0x1010 */
266 u32 txq_wr_addr_ext; /* 0x1014 */
267 u32 txq_rd_addr; /* 0x1018 */
268 u32 dma_wb_base_hi; /* 0x101C */
269 u32 dma_wb_base_lo; /* 0x1020 */
270 u32 service_request; /* 0x1024 */
271 u32 service_complete; /* 0x1028 */
272 u32 cache_rd_index; /* 0x102C */
273 u32 cache_wr_index; /* 0x1030 */
274 u32 TxDmaError; /* 0x1034 */
275 u32 DescAbortCount; /* 0x1038 */
276 u32 PayloadAbortCnt; /* 0x103c */
277 u32 WriteBackAbortCnt; /* 0x1040 */
278 u32 DescTimeoutCnt; /* 0x1044 */
279 u32 PayloadTimeoutCnt; /* 0x1048 */
280 u32 WriteBackTimeoutCnt; /* 0x104c */
281 u32 DescErrorCount; /* 0x1050 */
282 u32 PayloadErrorCnt; /* 0x1054 */
283 u32 WriteBackErrorCnt; /* 0x1058 */
284 u32 DroppedTLPCount; /* 0x105c */
285 u32 NewServiceComplete; /* 0x1060 */
286 u32 EthernetPacketCount; /* 0x1064 */
287 } TXDMA_t, *PTXDMA_t;
288
289 /* END OF TXDMA REGISTER ADDRESS MAP */
290
291
292 /* START OF RXDMA REGISTER ADDRESS MAP */
293
294 /*
295 * structure for control status reg in rxdma address map
296 * Located at address 0x2000
297 */
298 typedef union _RXDMA_CSR_t {
299 u32 value;
300 struct {
301 #ifdef _BIT_FIELDS_HTOL
302 u32 unused2:14; /* bits 18-31 */
303 u32 halt_status:1; /* bit 17 */
304 u32 pkt_done_flush:1; /* bit 16 */
305 u32 pkt_drop_disable:1; /* bit 15 */
306 u32 unused1:1; /* bit 14 */
307 u32 fbr1_enable:1; /* bit 13 */
308 u32 fbr1_size:2; /* bits 11-12 */
309 u32 fbr0_enable:1; /* bit 10 */
310 u32 fbr0_size:2; /* bits 8-9 */
311 u32 dma_big_endian:1; /* bit 7 */
312 u32 pkt_big_endian:1; /* bit 6 */
313 u32 psr_big_endian:1; /* bit 5 */
314 u32 fbr_big_endian:1; /* bit 4 */
315 u32 tc:3; /* bits 1-3 */
316 u32 halt:1; /* bit 0 */
317 #else
318 u32 halt:1; /* bit 0 */
319 u32 tc:3; /* bits 1-3 */
320 u32 fbr_big_endian:1; /* bit 4 */
321 u32 psr_big_endian:1; /* bit 5 */
322 u32 pkt_big_endian:1; /* bit 6 */
323 u32 dma_big_endian:1; /* bit 7 */
324 u32 fbr0_size:2; /* bits 8-9 */
325 u32 fbr0_enable:1; /* bit 10 */
326 u32 fbr1_size:2; /* bits 11-12 */
327 u32 fbr1_enable:1; /* bit 13 */
328 u32 unused1:1; /* bit 14 */
329 u32 pkt_drop_disable:1; /* bit 15 */
330 u32 pkt_done_flush:1; /* bit 16 */
331 u32 halt_status:1; /* bit 17 */
332 u32 unused2:14; /* bits 18-31 */
333 #endif
334 } bits;
335 } RXDMA_CSR_t, *PRXDMA_CSR_t;
336
337 /*
338 * structure for dma writeback lo reg in rxdma address map
339 * located at address 0x2004
340 * Defined earlier (u32)
341 */
342
343 /*
344 * structure for dma writeback hi reg in rxdma address map
345 * located at address 0x2008
346 * Defined earlier (u32)
347 */
348
349 /*
350 * structure for number of packets done reg in rxdma address map
351 * located at address 0x200C
352 */
353 typedef union _RXDMA_NUM_PKT_DONE_t {
354 u32 value;
355 struct {
356 #ifdef _BIT_FIELDS_HTOL
357 u32 unused:24; /* bits 8-31 */
358 u32 num_done:8; /* bits 0-7 */
359 #else
360 u32 num_done:8; /* bits 0-7 */
361 u32 unused:24; /* bits 8-31 */
362 #endif
363 } bits;
364 } RXDMA_NUM_PKT_DONE_t, *PRXDMA_NUM_PKT_DONE_t;
365
366 /*
367 * structure for max packet time reg in rxdma address map
368 * located at address 0x2010
369 */
370 typedef union _RXDMA_MAX_PKT_TIME_t {
371 u32 value;
372 struct {
373 #ifdef _BIT_FIELDS_HTOL
374 u32 unused:14; /* bits 18-31 */
375 u32 time_done:18; /* bits 0-17 */
376 #else
377 u32 time_done:18; /* bits 0-17 */
378 u32 unused:14; /* bits 18-31 */
379 #endif
380 } bits;
381 } RXDMA_MAX_PKT_TIME_t, *PRXDMA_MAX_PKT_TIME_t;
382
383 /*
384 * structure for rx queue read address reg in rxdma address map
385 * located at address 0x2014
386 * Defined earlier (u32)
387 */
388
389 /*
390 * structure for rx queue read address external reg in rxdma address map
391 * located at address 0x2018
392 * Defined earlier (u32)
393 */
394
395 /*
396 * structure for rx queue write address reg in rxdma address map
397 * located at address 0x201C
398 * Defined earlier (u32)
399 */
400
401 /*
402 * structure for packet status ring base address lo reg in rxdma address map
403 * located at address 0x2020
404 * Defined earlier (u32)
405 */
406
407 /*
408 * structure for packet status ring base address hi reg in rxdma address map
409 * located at address 0x2024
410 * Defined earlier (u32)
411 */
412
413 /*
414 * structure for packet status ring number of descriptors reg in rxdma address
415 * map. Located at address 0x2028
416 */
417 typedef union _RXDMA_PSR_NUM_DES_t {
418 u32 value;
419 struct {
420 #ifdef _BIT_FIELDS_HTOL
421 u32 unused:20; /* bits 12-31 */
422 u32 psr_ndes:12; /* bit 0-11 */
423 #else
424 u32 psr_ndes:12; /* bit 0-11 */
425 u32 unused:20; /* bits 12-31 */
426 #endif
427 } bits;
428 } RXDMA_PSR_NUM_DES_t, *PRXDMA_PSR_NUM_DES_t;
429
430 /*
431 * structure for packet status ring available offset reg in rxdma address map
432 * located at address 0x202C
433 */
434 typedef union _RXDMA_PSR_AVAIL_OFFSET_t {
435 u32 value;
436 struct {
437 #ifdef _BIT_FIELDS_HTOL
438 u32 unused:19; /* bits 13-31 */
439 u32 psr_avail_wrap:1; /* bit 12 */
440 u32 psr_avail:12; /* bit 0-11 */
441 #else
442 u32 psr_avail:12; /* bit 0-11 */
443 u32 psr_avail_wrap:1; /* bit 12 */
444 u32 unused:19; /* bits 13-31 */
445 #endif
446 } bits;
447 } RXDMA_PSR_AVAIL_OFFSET_t, *PRXDMA_PSR_AVAIL_OFFSET_t;
448
449 /*
450 * structure for packet status ring full offset reg in rxdma address map
451 * located at address 0x2030
452 */
453 typedef union _RXDMA_PSR_FULL_OFFSET_t {
454 u32 value;
455 struct {
456 #ifdef _BIT_FIELDS_HTOL
457 u32 unused:19; /* bits 13-31 */
458 u32 psr_full_wrap:1; /* bit 12 */
459 u32 psr_full:12; /* bit 0-11 */
460 #else
461 u32 psr_full:12; /* bit 0-11 */
462 u32 psr_full_wrap:1; /* bit 12 */
463 u32 unused:19; /* bits 13-31 */
464 #endif
465 } bits;
466 } RXDMA_PSR_FULL_OFFSET_t, *PRXDMA_PSR_FULL_OFFSET_t;
467
468 /*
469 * structure for packet status ring access index reg in rxdma address map
470 * located at address 0x2034
471 */
472 typedef union _RXDMA_PSR_ACCESS_INDEX_t {
473 u32 value;
474 struct {
475 #ifdef _BIT_FIELDS_HTOL
476 u32 unused:27; /* bits 5-31 */
477 u32 psr_ai:5; /* bits 0-4 */
478 #else
479 u32 psr_ai:5; /* bits 0-4 */
480 u32 unused:27; /* bits 5-31 */
481 #endif
482 } bits;
483 } RXDMA_PSR_ACCESS_INDEX_t, *PRXDMA_PSR_ACCESS_INDEX_t;
484
485 /*
486 * structure for packet status ring minimum descriptors reg in rxdma address
487 * map. Located at address 0x2038
488 */
489 typedef union _RXDMA_PSR_MIN_DES_t {
490 u32 value;
491 struct {
492 #ifdef _BIT_FIELDS_HTOL
493 u32 unused:20; /* bits 12-31 */
494 u32 psr_min:12; /* bits 0-11 */
495 #else
496 u32 psr_min:12; /* bits 0-11 */
497 u32 unused:20; /* bits 12-31 */
498 #endif
499 } bits;
500 } RXDMA_PSR_MIN_DES_t, *PRXDMA_PSR_MIN_DES_t;
501
502 /*
503 * structure for free buffer ring base lo address reg in rxdma address map
504 * located at address 0x203C
505 * Defined earlier (u32)
506 */
507
508 /*
509 * structure for free buffer ring base hi address reg in rxdma address map
510 * located at address 0x2040
511 * Defined earlier (u32)
512 */
513
514 /*
515 * structure for free buffer ring number of descriptors reg in rxdma address
516 * map. Located at address 0x2044
517 */
518 typedef union _RXDMA_FBR_NUM_DES_t {
519 u32 value;
520 struct {
521 #ifdef _BIT_FIELDS_HTOL
522 u32 unused:22; /* bits 10-31 */
523 u32 fbr_ndesc:10; /* bits 0-9 */
524 #else
525 u32 fbr_ndesc:10; /* bits 0-9 */
526 u32 unused:22; /* bits 10-31 */
527 #endif
528 } bits;
529 } RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t;
530
531 /*
532 * structure for free buffer ring 0 available offset reg in rxdma address map
533 * located at address 0x2048
534 * Defined earlier (u32)
535 */
536
537 /*
538 * structure for free buffer ring 0 full offset reg in rxdma address map
539 * located at address 0x204C
540 * Defined earlier (u32)
541 */
542
543 /*
544 * structure for free buffer cache 0 full offset reg in rxdma address map
545 * located at address 0x2050
546 */
547 typedef union _RXDMA_FBC_RD_INDEX_t {
548 u32 value;
549 struct {
550 #ifdef _BIT_FIELDS_HTOL
551 u32 unused:27; /* bits 5-31 */
552 u32 fbc_rdi:5; /* bit 0-4 */
553 #else
554 u32 fbc_rdi:5; /* bit 0-4 */
555 u32 unused:27; /* bits 5-31 */
556 #endif
557 } bits;
558 } RXDMA_FBC_RD_INDEX_t, *PRXDMA_FBC_RD_INDEX_t;
559
560 /*
561 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
562 * located at address 0x2054
563 */
564 typedef union _RXDMA_FBR_MIN_DES_t {
565 u32 value;
566 struct {
567 #ifdef _BIT_FIELDS_HTOL
568 u32 unused:22; /* bits 10-31 */
569 u32 fbr_min:10; /* bits 0-9 */
570 #else
571 u32 fbr_min:10; /* bits 0-9 */
572 u32 unused:22; /* bits 10-31 */
573 #endif
574 } bits;
575 } RXDMA_FBR_MIN_DES_t, *PRXDMA_FBR_MIN_DES_t;
576
577 /*
578 * structure for free buffer ring 1 base address lo reg in rxdma address map
579 * located at address 0x2058 - 0x205C
580 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
581 */
582
583 /*
584 * structure for free buffer ring 1 number of descriptors reg in rxdma address
585 * map. Located at address 0x2060
586 * Defined earlier (RXDMA_FBR_NUM_DES_t)
587 */
588
589 /*
590 * structure for free buffer ring 1 available offset reg in rxdma address map
591 * located at address 0x2064
592 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
593 */
594
595 /*
596 * structure for free buffer ring 1 full offset reg in rxdma address map
597 * located at address 0x2068
598 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
599 */
600
601 /*
602 * structure for free buffer cache 1 read index reg in rxdma address map
603 * located at address 0x206C
604 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
605 */
606
607 /*
608 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
609 * located at address 0x2070
610 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
611 */
612
613 /*
614 * Rx DMA Module of JAGCore Address Mapping
615 * Located at address 0x2000
616 */
617 typedef struct _RXDMA_t { /* Location: */
618 RXDMA_CSR_t csr; /* 0x2000 */
619 u32 dma_wb_base_lo; /* 0x2004 */
620 u32 dma_wb_base_hi; /* 0x2008 */
621 RXDMA_NUM_PKT_DONE_t num_pkt_done; /* 0x200C */
622 RXDMA_MAX_PKT_TIME_t max_pkt_time; /* 0x2010 */
623 u32 rxq_rd_addr; /* 0x2014 */
624 u32 rxq_rd_addr_ext; /* 0x2018 */
625 u32 rxq_wr_addr; /* 0x201C */
626 u32 psr_base_lo; /* 0x2020 */
627 u32 psr_base_hi; /* 0x2024 */
628 RXDMA_PSR_NUM_DES_t psr_num_des; /* 0x2028 */
629 RXDMA_PSR_AVAIL_OFFSET_t psr_avail_offset; /* 0x202C */
630 RXDMA_PSR_FULL_OFFSET_t psr_full_offset; /* 0x2030 */
631 RXDMA_PSR_ACCESS_INDEX_t psr_access_index; /* 0x2034 */
632 RXDMA_PSR_MIN_DES_t psr_min_des; /* 0x2038 */
633 u32 fbr0_base_lo; /* 0x203C */
634 u32 fbr0_base_hi; /* 0x2040 */
635 RXDMA_FBR_NUM_DES_t fbr0_num_des; /* 0x2044 */
636 u32 fbr0_avail_offset; /* 0x2048 */
637 u32 fbr0_full_offset; /* 0x204C */
638 RXDMA_FBC_RD_INDEX_t fbr0_rd_index; /* 0x2050 */
639 RXDMA_FBR_MIN_DES_t fbr0_min_des; /* 0x2054 */
640 u32 fbr1_base_lo; /* 0x2058 */
641 u32 fbr1_base_hi; /* 0x205C */
642 RXDMA_FBR_NUM_DES_t fbr1_num_des; /* 0x2060 */
643 u32 fbr1_avail_offset; /* 0x2064 */
644 u32 fbr1_full_offset; /* 0x2068 */
645 RXDMA_FBC_RD_INDEX_t fbr1_rd_index; /* 0x206C */
646 RXDMA_FBR_MIN_DES_t fbr1_min_des; /* 0x2070 */
647 } RXDMA_t, *PRXDMA_t;
648
649 /* END OF RXDMA REGISTER ADDRESS MAP */
650
651
652 /* START OF TXMAC REGISTER ADDRESS MAP */
653
654 /*
655 * structure for control reg in txmac address map
656 * located at address 0x3000
657 */
658 typedef union _TXMAC_CTL_t {
659 u32 value;
660 struct {
661 #ifdef _BIT_FIELDS_HTOL
662 u32 unused:24; /* bits 8-31 */
663 u32 cklseg_diable:1; /* bit 7 */
664 u32 ckbcnt_disable:1; /* bit 6 */
665 u32 cksegnum:1; /* bit 5 */
666 u32 async_disable:1; /* bit 4 */
667 u32 fc_disable:1; /* bit 3 */
668 u32 mcif_disable:1; /* bit 2 */
669 u32 mif_disable:1; /* bit 1 */
670 u32 txmac_en:1; /* bit 0 */
671 #else
672 u32 txmac_en:1; /* bit 0 */
673 u32 mif_disable:1; /* bit 1 mac interface */
674 u32 mcif_disable:1; /* bit 2 mem. contr. interface */
675 u32 fc_disable:1; /* bit 3 */
676 u32 async_disable:1; /* bit 4 */
677 u32 cksegnum:1; /* bit 5 */
678 u32 ckbcnt_disable:1; /* bit 6 */
679 u32 cklseg_diable:1; /* bit 7 */
680 u32 unused:24; /* bits 8-31 */
681 #endif
682 } bits;
683 } TXMAC_CTL_t, *PTXMAC_CTL_t;
684
685 /*
686 * structure for shadow pointer reg in txmac address map
687 * located at address 0x3004
688 */
689 typedef union _TXMAC_SHADOW_PTR_t {
690 u32 value;
691 struct {
692 #ifdef _BIT_FIELDS_HTOL
693 u32 reserved2:5; /* bits 27-31 */
694 u32 txq_rd_ptr:11; /* bits 16-26 */
695 u32 reserved:5; /* bits 11-15 */
696 u32 txq_wr_ptr:11; /* bits 0-10 */
697 #else
698 u32 txq_wr_ptr:11; /* bits 0-10 */
699 u32 reserved:5; /* bits 11-15 */
700 u32 txq_rd_ptr:11; /* bits 16-26 */
701 u32 reserved2:5; /* bits 27-31 */
702 #endif
703 } bits;
704 } TXMAC_SHADOW_PTR_t, *PTXMAC_SHADOW_PTR_t;
705
706 /*
707 * structure for error count reg in txmac address map
708 * located at address 0x3008
709 */
710 typedef union _TXMAC_ERR_CNT_t {
711 u32 value;
712 struct {
713 #ifdef _BIT_FIELDS_HTOL
714 u32 unused:20; /* bits 12-31 */
715 u32 reserved:4; /* bits 8-11 */
716 u32 txq_underrun:4; /* bits 4-7 */
717 u32 fifo_underrun:4; /* bits 0-3 */
718 #else
719 u32 fifo_underrun:4; /* bits 0-3 */
720 u32 txq_underrun:4; /* bits 4-7 */
721 u32 reserved:4; /* bits 8-11 */
722 u32 unused:20; /* bits 12-31 */
723 #endif
724 } bits;
725 } TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t;
726
727 /*
728 * structure for max fill reg in txmac address map
729 * located at address 0x300C
730 * 31-12: unused
731 * 11-0: max fill
732 */
733
734 /*
735 * structure for cf parameter reg in txmac address map
736 * located at address 0x3010
737 * 31-16: cfep
738 * 15-0: cfpt
739 */
740
741 /*
742 * structure for tx test reg in txmac address map
743 * located at address 0x3014
744 * 31-17: unused
745 * 16: reserved1
746 * 15: txtest_en
747 * 14-11: unused
748 * 10-0: txq test pointer
749 */
750
751 /*
752 * structure for error reg in txmac address map
753 * located at address 0x3018
754 */
755 typedef union _TXMAC_ERR_t {
756 u32 value;
757 struct {
758 #ifdef _BIT_FIELDS_HTOL
759 u32 unused2:23; /* bits 9-31 */
760 u32 fifo_underrun:1; /* bit 8 */
761 u32 unused1:2; /* bits 6-7 */
762 u32 ctrl2_err:1; /* bit 5 */
763 u32 txq_underrun:1; /* bit 4 */
764 u32 bcnt_err:1; /* bit 3 */
765 u32 lseg_err:1; /* bit 2 */
766 u32 segnum_err:1; /* bit 1 */
767 u32 seg0_err:1; /* bit 0 */
768 #else
769 u32 seg0_err:1; /* bit 0 */
770 u32 segnum_err:1; /* bit 1 */
771 u32 lseg_err:1; /* bit 2 */
772 u32 bcnt_err:1; /* bit 3 */
773 u32 txq_underrun:1; /* bit 4 */
774 u32 ctrl2_err:1; /* bit 5 */
775 u32 unused1:2; /* bits 6-7 */
776 u32 fifo_underrun:1; /* bit 8 */
777 u32 unused2:23; /* bits 9-31 */
778 #endif
779 } bits;
780 } TXMAC_ERR_t, *PTXMAC_ERR_t;
781
782 /*
783 * structure for error interrupt reg in txmac address map
784 * located at address 0x301C
785 */
786 typedef union _TXMAC_ERR_INT_t {
787 u32 value;
788 struct {
789 #ifdef _BIT_FIELDS_HTOL
790 u32 unused2:23; /* bits 9-31 */
791 u32 fifo_underrun:1; /* bit 8 */
792 u32 unused1:2; /* bits 6-7 */
793 u32 ctrl2_err:1; /* bit 5 */
794 u32 txq_underrun:1; /* bit 4 */
795 u32 bcnt_err:1; /* bit 3 */
796 u32 lseg_err:1; /* bit 2 */
797 u32 segnum_err:1; /* bit 1 */
798 u32 seg0_err:1; /* bit 0 */
799 #else
800 u32 seg0_err:1; /* bit 0 */
801 u32 segnum_err:1; /* bit 1 */
802 u32 lseg_err:1; /* bit 2 */
803 u32 bcnt_err:1; /* bit 3 */
804 u32 txq_underrun:1; /* bit 4 */
805 u32 ctrl2_err:1; /* bit 5 */
806 u32 unused1:2; /* bits 6-7 */
807 u32 fifo_underrun:1; /* bit 8 */
808 u32 unused2:23; /* bits 9-31 */
809 #endif
810 } bits;
811 } TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
812
813 /*
814 * structure for error interrupt reg in txmac address map
815 * located at address 0x3020
816 */
817 typedef union _TXMAC_CP_CTRL_t {
818 u32 value;
819 struct {
820 #ifdef _BIT_FIELDS_HTOL
821 u32 unused:30; /* bits 2-31 */
822 u32 bp_req:1; /* bit 1 */
823 u32 bp_xonxoff:1; /* bit 0 */
824 #else
825 u32 bp_xonxoff:1; /* bit 0 */
826 u32 bp_req:1; /* bit 1 */
827 u32 unused:30; /* bits 2-31 */
828 #endif
829 } bits;
830 } TXMAC_BP_CTRL_t, *PTXMAC_BP_CTRL_t;
831
832 /*
833 * Tx MAC Module of JAGCore Address Mapping
834 */
835 typedef struct _TXMAC_t { /* Location: */
836 TXMAC_CTL_t ctl; /* 0x3000 */
837 TXMAC_SHADOW_PTR_t shadow_ptr; /* 0x3004 */
838 TXMAC_ERR_CNT_t err_cnt; /* 0x3008 */
839 u32 max_fill; /* 0x300C */
840 u32 cf_param; /* 0x3010 */
841 u32 tx_test; /* 0x3014 */
842 TXMAC_ERR_t err; /* 0x3018 */
843 TXMAC_ERR_INT_t err_int; /* 0x301C */
844 TXMAC_BP_CTRL_t bp_ctrl; /* 0x3020 */
845 } TXMAC_t, *PTXMAC_t;
846
847 /* END OF TXMAC REGISTER ADDRESS MAP */
848
849 /* START OF RXMAC REGISTER ADDRESS MAP */
850
851 /*
852 * structure for rxmac control reg in rxmac address map
853 * located at address 0x4000
854 */
855 typedef union _RXMAC_CTRL_t {
856 u32 value;
857 struct {
858 #ifdef _BIT_FIELDS_HTOL
859 u32 reserved:25; /* bits 7-31 */
860 u32 rxmac_int_disable:1; /* bit 6 */
861 u32 async_disable:1; /* bit 5 */
862 u32 mif_disable:1; /* bit 4 */
863 u32 wol_disable:1; /* bit 3 */
864 u32 pkt_filter_disable:1; /* bit 2 */
865 u32 mcif_disable:1; /* bit 1 */
866 u32 rxmac_en:1; /* bit 0 */
867 #else
868 u32 rxmac_en:1; /* bit 0 */
869 u32 mcif_disable:1; /* bit 1 */
870 u32 pkt_filter_disable:1; /* bit 2 */
871 u32 wol_disable:1; /* bit 3 */
872 u32 mif_disable:1; /* bit 4 */
873 u32 async_disable:1; /* bit 5 */
874 u32 rxmac_int_disable:1; /* bit 6 */
875 u32 reserved:25; /* bits 7-31 */
876 #endif
877 } bits;
878 } RXMAC_CTRL_t, *PRXMAC_CTRL_t;
879
880 /*
881 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
882 * located at address 0x4004
883 */
884 typedef union _RXMAC_WOL_CTL_CRC0_t {
885 u32 value;
886 struct {
887 #ifdef _BIT_FIELDS_HTOL
888 u32 crc0:16; /* bits 16-31 */
889 u32 reserve:4; /* bits 12-15 */
890 u32 ignore_pp:1; /* bit 11 */
891 u32 ignore_mp:1; /* bit 10 */
892 u32 clr_intr:1; /* bit 9 */
893 u32 ignore_link_chg:1; /* bit 8 */
894 u32 ignore_uni:1; /* bit 7 */
895 u32 ignore_multi:1; /* bit 6 */
896 u32 ignore_broad:1; /* bit 5 */
897 u32 valid_crc4:1; /* bit 4 */
898 u32 valid_crc3:1; /* bit 3 */
899 u32 valid_crc2:1; /* bit 2 */
900 u32 valid_crc1:1; /* bit 1 */
901 u32 valid_crc0:1; /* bit 0 */
902 #else
903 u32 valid_crc0:1; /* bit 0 */
904 u32 valid_crc1:1; /* bit 1 */
905 u32 valid_crc2:1; /* bit 2 */
906 u32 valid_crc3:1; /* bit 3 */
907 u32 valid_crc4:1; /* bit 4 */
908 u32 ignore_broad:1; /* bit 5 */
909 u32 ignore_multi:1; /* bit 6 */
910 u32 ignore_uni:1; /* bit 7 */
911 u32 ignore_link_chg:1; /* bit 8 */
912 u32 clr_intr:1; /* bit 9 */
913 u32 ignore_mp:1; /* bit 10 */
914 u32 ignore_pp:1; /* bit 11 */
915 u32 reserve:4; /* bits 12-15 */
916 u32 crc0:16; /* bits 16-31 */
917 #endif
918 } bits;
919 } RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
920
921 /*
922 * structure for CRC 1 and CRC 2 reg in rxmac address map
923 * located at address 0x4008
924 */
925 typedef union _RXMAC_WOL_CRC12_t {
926 u32 value;
927 struct {
928 #ifdef _BIT_FIELDS_HTOL
929 u32 crc2:16; /* bits 16-31 */
930 u32 crc1:16; /* bits 0-15 */
931 #else
932 u32 crc1:16; /* bits 0-15 */
933 u32 crc2:16; /* bits 16-31 */
934 #endif
935 } bits;
936 } RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
937
938 /*
939 * structure for CRC 3 and CRC 4 reg in rxmac address map
940 * located at address 0x400C
941 */
942 typedef union _RXMAC_WOL_CRC34_t {
943 u32 value;
944 struct {
945 #ifdef _BIT_FIELDS_HTOL
946 u32 crc4:16; /* bits 16-31 */
947 u32 crc3:16; /* bits 0-15 */
948 #else
949 u32 crc3:16; /* bits 0-15 */
950 u32 crc4:16; /* bits 16-31 */
951 #endif
952 } bits;
953 } RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
954
955 /*
956 * structure for Wake On Lan Source Address Lo reg in rxmac address map
957 * located at address 0x4010
958 */
959 typedef union _RXMAC_WOL_SA_LO_t {
960 u32 value;
961 struct {
962 #ifdef _BIT_FIELDS_HTOL
963 u32 sa3:8; /* bits 24-31 */
964 u32 sa4:8; /* bits 16-23 */
965 u32 sa5:8; /* bits 8-15 */
966 u32 sa6:8; /* bits 0-7 */
967 #else
968 u32 sa6:8; /* bits 0-7 */
969 u32 sa5:8; /* bits 8-15 */
970 u32 sa4:8; /* bits 16-23 */
971 u32 sa3:8; /* bits 24-31 */
972 #endif
973 } bits;
974 } RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
975
976 /*
977 * structure for Wake On Lan Source Address Hi reg in rxmac address map
978 * located at address 0x4014
979 */
980 typedef union _RXMAC_WOL_SA_HI_t {
981 u32 value;
982 struct {
983 #ifdef _BIT_FIELDS_HTOL
984 u32 reserved:16; /* bits 16-31 */
985 u32 sa1:8; /* bits 8-15 */
986 u32 sa2:8; /* bits 0-7 */
987 #else
988 u32 sa2:8; /* bits 0-7 */
989 u32 sa1:8; /* bits 8-15 */
990 u32 reserved:16; /* bits 16-31 */
991 #endif
992 } bits;
993 } RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
994
995 /*
996 * structure for Wake On Lan mask reg in rxmac address map
997 * located at address 0x4018 - 0x4064
998 * Defined earlier (u32)
999 */
1000
1001 /*
1002 * structure for Unicast Paket Filter Address 1 reg in rxmac address map
1003 * located at address 0x4068
1004 */
1005 typedef union _RXMAC_UNI_PF_ADDR1_t {
1006 u32 value;
1007 struct {
1008 #ifdef _BIT_FIELDS_HTOL
1009 u32 addr1_3:8; /* bits 24-31 */
1010 u32 addr1_4:8; /* bits 16-23 */
1011 u32 addr1_5:8; /* bits 8-15 */
1012 u32 addr1_6:8; /* bits 0-7 */
1013 #else
1014 u32 addr1_6:8; /* bits 0-7 */
1015 u32 addr1_5:8; /* bits 8-15 */
1016 u32 addr1_4:8; /* bits 16-23 */
1017 u32 addr1_3:8; /* bits 24-31 */
1018 #endif
1019 } bits;
1020 } RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
1021
1022 /*
1023 * structure for Unicast Paket Filter Address 2 reg in rxmac address map
1024 * located at address 0x406C
1025 */
1026 typedef union _RXMAC_UNI_PF_ADDR2_t {
1027 u32 value;
1028 struct {
1029 #ifdef _BIT_FIELDS_HTOL
1030 u32 addr2_3:8; /* bits 24-31 */
1031 u32 addr2_4:8; /* bits 16-23 */
1032 u32 addr2_5:8; /* bits 8-15 */
1033 u32 addr2_6:8; /* bits 0-7 */
1034 #else
1035 u32 addr2_6:8; /* bits 0-7 */
1036 u32 addr2_5:8; /* bits 8-15 */
1037 u32 addr2_4:8; /* bits 16-23 */
1038 u32 addr2_3:8; /* bits 24-31 */
1039 #endif
1040 } bits;
1041 } RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
1042
1043 /*
1044 * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
1045 * located at address 0x4070
1046 */
1047 typedef union _RXMAC_UNI_PF_ADDR3_t {
1048 u32 value;
1049 struct {
1050 #ifdef _BIT_FIELDS_HTOL
1051 u32 addr2_1:8; /* bits 24-31 */
1052 u32 addr2_2:8; /* bits 16-23 */
1053 u32 addr1_1:8; /* bits 8-15 */
1054 u32 addr1_2:8; /* bits 0-7 */
1055 #else
1056 u32 addr1_2:8; /* bits 0-7 */
1057 u32 addr1_1:8; /* bits 8-15 */
1058 u32 addr2_2:8; /* bits 16-23 */
1059 u32 addr2_1:8; /* bits 24-31 */
1060 #endif
1061 } bits;
1062 } RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
1063
1064 /*
1065 * structure for Multicast Hash reg in rxmac address map
1066 * located at address 0x4074 - 0x4080
1067 * Defined earlier (u32)
1068 */
1069
1070 /*
1071 * structure for Packet Filter Control reg in rxmac address map
1072 * located at address 0x4084
1073 */
1074 typedef union _RXMAC_PF_CTRL_t {
1075 u32 value;
1076 struct {
1077 #ifdef _BIT_FIELDS_HTOL
1078 u32 unused2:9; /* bits 23-31 */
1079 u32 min_pkt_size:7; /* bits 16-22 */
1080 u32 unused1:12; /* bits 4-15 */
1081 u32 filter_frag_en:1; /* bit 3 */
1082 u32 filter_uni_en:1; /* bit 2 */
1083 u32 filter_multi_en:1; /* bit 1 */
1084 u32 filter_broad_en:1; /* bit 0 */
1085 #else
1086 u32 filter_broad_en:1; /* bit 0 */
1087 u32 filter_multi_en:1; /* bit 1 */
1088 u32 filter_uni_en:1; /* bit 2 */
1089 u32 filter_frag_en:1; /* bit 3 */
1090 u32 unused1:12; /* bits 4-15 */
1091 u32 min_pkt_size:7; /* bits 16-22 */
1092 u32 unused2:9; /* bits 23-31 */
1093 #endif
1094 } bits;
1095 } RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
1096
1097 /*
1098 * structure for Memory Controller Interface Control Max Segment reg in rxmac
1099 * address map. Located at address 0x4088
1100 */
1101 typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
1102 u32 value;
1103 struct {
1104 #ifdef _BIT_FIELDS_HTOL
1105 u32 reserved:22; /* bits 10-31 */
1106 u32 max_size:8; /* bits 2-9 */
1107 u32 fc_en:1; /* bit 1 */
1108 u32 seg_en:1; /* bit 0 */
1109 #else
1110 u32 seg_en:1; /* bit 0 */
1111 u32 fc_en:1; /* bit 1 */
1112 u32 max_size:8; /* bits 2-9 */
1113 u32 reserved:22; /* bits 10-31 */
1114 #endif
1115 } bits;
1116 } RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
1117
1118 /*
1119 * structure for Memory Controller Interface Water Mark reg in rxmac address
1120 * map. Located at address 0x408C
1121 */
1122 typedef union _RXMAC_MCIF_WATER_MARK_t {
1123 u32 value;
1124 struct {
1125 #ifdef _BIT_FIELDS_HTOL
1126 u32 reserved2:6; /* bits 26-31 */
1127 u32 mark_hi:10; /* bits 16-25 */
1128 u32 reserved1:6; /* bits 10-15 */
1129 u32 mark_lo:10; /* bits 0-9 */
1130 #else
1131 u32 mark_lo:10; /* bits 0-9 */
1132 u32 reserved1:6; /* bits 10-15 */
1133 u32 mark_hi:10; /* bits 16-25 */
1134 u32 reserved2:6; /* bits 26-31 */
1135 #endif
1136 } bits;
1137 } RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
1138
1139 /*
1140 * structure for Rx Queue Dialog reg in rxmac address map.
1141 * located at address 0x4090
1142 */
1143 typedef union _RXMAC_RXQ_DIAG_t {
1144 u32 value;
1145 struct {
1146 #ifdef _BIT_FIELDS_HTOL
1147 u32 reserved2:6; /* bits 26-31 */
1148 u32 rd_ptr:10; /* bits 16-25 */
1149 u32 reserved1:6; /* bits 10-15 */
1150 u32 wr_ptr:10; /* bits 0-9 */
1151 #else
1152 u32 wr_ptr:10; /* bits 0-9 */
1153 u32 reserved1:6; /* bits 10-15 */
1154 u32 rd_ptr:10; /* bits 16-25 */
1155 u32 reserved2:6; /* bits 26-31 */
1156 #endif
1157 } bits;
1158 } RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
1159
1160 /*
1161 * structure for space availiable reg in rxmac address map.
1162 * located at address 0x4094
1163 */
1164 typedef union _RXMAC_SPACE_AVAIL_t {
1165 u32 value;
1166 struct {
1167 #ifdef _BIT_FIELDS_HTOL
1168 u32 reserved2:15; /* bits 17-31 */
1169 u32 space_avail_en:1; /* bit 16 */
1170 u32 reserved1:6; /* bits 10-15 */
1171 u32 space_avail:10; /* bits 0-9 */
1172 #else
1173 u32 space_avail:10; /* bits 0-9 */
1174 u32 reserved1:6; /* bits 10-15 */
1175 u32 space_avail_en:1; /* bit 16 */
1176 u32 reserved2:15; /* bits 17-31 */
1177 #endif
1178 } bits;
1179 } RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
1180
1181 /*
1182 * structure for management interface reg in rxmac address map.
1183 * located at address 0x4098
1184 */
1185 typedef union _RXMAC_MIF_CTL_t {
1186 u32 value;
1187 struct {
1188 #ifdef _BIT_FIELDS_HTOL
1189 u32 reserve:14; /* bits 18-31 */
1190 u32 drop_pkt_en:1; /* bit 17 */
1191 u32 drop_pkt_mask:17; /* bits 0-16 */
1192 #else
1193 u32 drop_pkt_mask:17; /* bits 0-16 */
1194 u32 drop_pkt_en:1; /* bit 17 */
1195 u32 reserve:14; /* bits 18-31 */
1196 #endif
1197 } bits;
1198 } RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
1199
1200 /*
1201 * structure for Error reg in rxmac address map.
1202 * located at address 0x409C
1203 */
1204 typedef union _RXMAC_ERROR_REG_t {
1205 u32 value;
1206 struct {
1207 #ifdef _BIT_FIELDS_HTOL
1208 u32 reserve:28; /* bits 4-31 */
1209 u32 mif:1; /* bit 3 */
1210 u32 async:1; /* bit 2 */
1211 u32 pkt_filter:1; /* bit 1 */
1212 u32 mcif:1; /* bit 0 */
1213 #else
1214 u32 mcif:1; /* bit 0 */
1215 u32 pkt_filter:1; /* bit 1 */
1216 u32 async:1; /* bit 2 */
1217 u32 mif:1; /* bit 3 */
1218 u32 reserve:28; /* bits 4-31 */
1219 #endif
1220 } bits;
1221 } RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
1222
1223 /*
1224 * Rx MAC Module of JAGCore Address Mapping
1225 */
1226 typedef struct _RXMAC_t { /* Location: */
1227 RXMAC_CTRL_t ctrl; /* 0x4000 */
1228 RXMAC_WOL_CTL_CRC0_t crc0; /* 0x4004 */
1229 RXMAC_WOL_CRC12_t crc12; /* 0x4008 */
1230 RXMAC_WOL_CRC34_t crc34; /* 0x400C */
1231 RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */
1232 RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */
1233 u32 mask0_word0; /* 0x4018 */
1234 u32 mask0_word1; /* 0x401C */
1235 u32 mask0_word2; /* 0x4020 */
1236 u32 mask0_word3; /* 0x4024 */
1237 u32 mask1_word0; /* 0x4028 */
1238 u32 mask1_word1; /* 0x402C */
1239 u32 mask1_word2; /* 0x4030 */
1240 u32 mask1_word3; /* 0x4034 */
1241 u32 mask2_word0; /* 0x4038 */
1242 u32 mask2_word1; /* 0x403C */
1243 u32 mask2_word2; /* 0x4040 */
1244 u32 mask2_word3; /* 0x4044 */
1245 u32 mask3_word0; /* 0x4048 */
1246 u32 mask3_word1; /* 0x404C */
1247 u32 mask3_word2; /* 0x4050 */
1248 u32 mask3_word3; /* 0x4054 */
1249 u32 mask4_word0; /* 0x4058 */
1250 u32 mask4_word1; /* 0x405C */
1251 u32 mask4_word2; /* 0x4060 */
1252 u32 mask4_word3; /* 0x4064 */
1253 RXMAC_UNI_PF_ADDR1_t uni_pf_addr1; /* 0x4068 */
1254 RXMAC_UNI_PF_ADDR2_t uni_pf_addr2; /* 0x406C */
1255 RXMAC_UNI_PF_ADDR3_t uni_pf_addr3; /* 0x4070 */
1256 u32 multi_hash1; /* 0x4074 */
1257 u32 multi_hash2; /* 0x4078 */
1258 u32 multi_hash3; /* 0x407C */
1259 u32 multi_hash4; /* 0x4080 */
1260 RXMAC_PF_CTRL_t pf_ctrl; /* 0x4084 */
1261 RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; /* 0x4088 */
1262 RXMAC_MCIF_WATER_MARK_t mcif_water_mark; /* 0x408C */
1263 RXMAC_RXQ_DIAG_t rxq_diag; /* 0x4090 */
1264 RXMAC_SPACE_AVAIL_t space_avail; /* 0x4094 */
1265
1266 RXMAC_MIF_CTL_t mif_ctrl; /* 0x4098 */
1267 RXMAC_ERROR_REG_t err_reg; /* 0x409C */
1268 } RXMAC_t, *PRXMAC_t;
1269
1270 /* END OF TXMAC REGISTER ADDRESS MAP */
1271
1272
1273 /* START OF MAC REGISTER ADDRESS MAP */
1274
1275 /*
1276 * structure for configuration #1 reg in mac address map.
1277 * located at address 0x5000
1278 *
1279 * 31: soft reset
1280 * 30: sim reset
1281 * 29-20: reserved
1282 * 19: reset rx mc
1283 * 18: reset tx mc
1284 * 17: reset rx func
1285 * 16: reset tx fnc
1286 * 15-9: reserved
1287 * 8: loopback
1288 * 7-6: reserved
1289 * 5: rx flow
1290 * 4: tx flow
1291 * 3: syncd rx en
1292 * 2: rx enable
1293 * 1: syncd tx en
1294 * 0: tx enable
1295 */
1296
1297 #define CFG1_LOOPBACK 0x00000100
1298 #define CFG1_RX_FLOW 0x00000020
1299 #define CFG1_TX_FLOW 0x00000010
1300 #define CFG1_RX_ENABLE 0x00000004
1301 #define CFG1_TX_ENABLE 0x00000001
1302 #define CFG1_WAIT 0x0000000A /* RX & TX syncd */
1303
1304 /*
1305 * structure for configuration #2 reg in mac address map.
1306 * located at address 0x5004
1307 * 31-16: reserved
1308 * 15-12: preamble
1309 * 11-10: reserved
1310 * 9-8: if mode
1311 * 7-6: reserved
1312 * 5: huge frame
1313 * 4: length check
1314 * 3: undefined
1315 * 2: pad crc
1316 * 1: crc enable
1317 * 0: full duplex
1318 */
1319
1320
1321 /*
1322 * structure for Interpacket gap reg in mac address map.
1323 * located at address 0x5008
1324 *
1325 * 31: reserved
1326 * 30-24: non B2B ipg 1
1327 * 23: undefined
1328 * 22-16: non B2B ipg 2
1329 * 15-8: Min ifg enforce
1330 * 7-0: B2B ipg
1331 *
1332 * structure for half duplex reg in mac address map.
1333 * located at address 0x500C
1334 * 31-24: reserved
1335 * 23-20: Alt BEB trunc
1336 * 19: Alt BEB enable
1337 * 18: BP no backoff
1338 * 17: no backoff
1339 * 16: excess defer
1340 * 15-12: re-xmit max
1341 * 11-10: reserved
1342 * 9-0: collision window
1343 */
1344
1345 /*
1346 * structure for Maximum Frame Length reg in mac address map.
1347 * located at address 0x5010: bits 0-15 hold the length.
1348 */
1349
1350 /*
1351 * structure for Reserve 1 reg in mac address map.
1352 * located at address 0x5014 - 0x5018
1353 * Defined earlier (u32)
1354 */
1355
1356 /*
1357 * structure for Test reg in mac address map.
1358 * located at address 0x501C
1359 * test: bits 0-2, rest unused
1360 */
1361
1362 /*
1363 * structure for MII Management Configuration reg in mac address map.
1364 * located at address 0x5020
1365 *
1366 * 31: reset MII mgmt
1367 * 30-6: unused
1368 * 5: scan auto increment
1369 * 4: preamble supress
1370 * 3: undefined
1371 * 2-0: mgmt clock reset
1372 */
1373
1374 /*
1375 * structure for MII Management Command reg in mac address map.
1376 * located at address 0x5024
1377 * bit 1: scan cycle
1378 * bit 0: read cycle
1379 */
1380
1381 /*
1382 * structure for MII Management Address reg in mac address map.
1383 * located at address 0x5028
1384 * 31-13: reserved
1385 * 12-8: phy addr
1386 * 7-5: reserved
1387 * 4-0: register
1388 */
1389
1390 #define MII_ADDR(phy,reg) ((phy) << 8 | (reg))
1391
1392 /*
1393 * structure for MII Management Control reg in mac address map.
1394 * located at address 0x502C
1395 * 31-16: reserved
1396 * 15-0: phy control
1397 */
1398
1399 /*
1400 * structure for MII Management Status reg in mac address map.
1401 * located at address 0x5030
1402 * 31-16: reserved
1403 * 15-0: phy control
1404 */
1405
1406 /*
1407 * structure for MII Management Indicators reg in mac address map.
1408 * located at address 0x5034
1409 * 31-3: reserved
1410 * 2: not valid
1411 * 1: scanning
1412 * 0: busy
1413 */
1414
1415 #define MGMT_BUSY 0x00000001 /* busy */
1416 #define MGMT_WAIT 0x00000005 /* busy | not valid */
1417
1418 /*
1419 * structure for Interface Control reg in mac address map.
1420 * located at address 0x5038
1421 *
1422 * 31: reset if module
1423 * 30-28: reserved
1424 * 27: tbi mode
1425 * 26: ghd mode
1426 * 25: lhd mode
1427 * 24: phy mode
1428 * 23: reset per mii
1429 * 22-17: reserved
1430 * 16: speed
1431 * 15: reset pe100x
1432 * 14-11: reserved
1433 * 10: force quiet
1434 * 9: no cipher
1435 * 8: disable link fail
1436 * 7: reset gpsi
1437 * 6-1: reserved
1438 * 0: enable jabber protection
1439 */
1440
1441 /*
1442 * structure for Interface Status reg in mac address map.
1443 * located at address 0x503C
1444 */
1445 typedef union _MAC_IF_STAT_t {
1446 u32 value;
1447 struct {
1448 #ifdef _BIT_FIELDS_HTOL
1449 u32 reserved:22; /* bits 10-31 */
1450 u32 excess_defer:1; /* bit 9 */
1451 u32 clash:1; /* bit 8 */
1452 u32 phy_jabber:1; /* bit 7 */
1453 u32 phy_link_ok:1; /* bit 6 */
1454 u32 phy_full_duplex:1; /* bit 5 */
1455 u32 phy_speed:1; /* bit 4 */
1456 u32 pe100x_link_fail:1; /* bit 3 */
1457 u32 pe10t_loss_carrie:1; /* bit 2 */
1458 u32 pe10t_sqe_error:1; /* bit 1 */
1459 u32 pe10t_jabber:1; /* bit 0 */
1460 #else
1461 u32 pe10t_jabber:1; /* bit 0 */
1462 u32 pe10t_sqe_error:1; /* bit 1 */
1463 u32 pe10t_loss_carrie:1; /* bit 2 */
1464 u32 pe100x_link_fail:1; /* bit 3 */
1465 u32 phy_speed:1; /* bit 4 */
1466 u32 phy_full_duplex:1; /* bit 5 */
1467 u32 phy_link_ok:1; /* bit 6 */
1468 u32 phy_jabber:1; /* bit 7 */
1469 u32 clash:1; /* bit 8 */
1470 u32 excess_defer:1; /* bit 9 */
1471 u32 reserved:22; /* bits 10-31 */
1472 #endif
1473 } bits;
1474 } MAC_IF_STAT_t, *PMAC_IF_STAT_t;
1475
1476 /*
1477 * structure for Mac Station Address, Part 1 reg in mac address map.
1478 * located at address 0x5040
1479 */
1480 typedef union _MAC_STATION_ADDR1_t {
1481 u32 value;
1482 struct {
1483 #ifdef _BIT_FIELDS_HTOL
1484 u32 Octet6:8; /* bits 24-31 */
1485 u32 Octet5:8; /* bits 16-23 */
1486 u32 Octet4:8; /* bits 8-15 */
1487 u32 Octet3:8; /* bits 0-7 */
1488 #else
1489 u32 Octet3:8; /* bits 0-7 */
1490 u32 Octet4:8; /* bits 8-15 */
1491 u32 Octet5:8; /* bits 16-23 */
1492 u32 Octet6:8; /* bits 24-31 */
1493 #endif
1494 } bits;
1495 } MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
1496
1497 /*
1498 * structure for Mac Station Address, Part 2 reg in mac address map.
1499 * located at address 0x5044
1500 */
1501 typedef union _MAC_STATION_ADDR2_t {
1502 u32 value;
1503 struct {
1504 #ifdef _BIT_FIELDS_HTOL
1505 u32 Octet2:8; /* bits 24-31 */
1506 u32 Octet1:8; /* bits 16-23 */
1507 u32 reserved:16; /* bits 0-15 */
1508 #else
1509 u32 reserved:16; /* bit 0-15 */
1510 u32 Octet1:8; /* bits 16-23 */
1511 u32 Octet2:8; /* bits 24-31 */
1512 #endif
1513 } bits;
1514 } MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
1515
1516 /*
1517 * MAC Module of JAGCore Address Mapping
1518 */
1519 typedef struct _MAC_t { /* Location: */
1520 u32 cfg1; /* 0x5000 */
1521 u32 cfg2; /* 0x5004 */
1522 u32 ipg; /* 0x5008 */
1523 u32 hfdp; /* 0x500C */
1524 u32 max_fm_len; /* 0x5010 */
1525 u32 rsv1; /* 0x5014 */
1526 u32 rsv2; /* 0x5018 */
1527 u32 mac_test; /* 0x501C */
1528 u32 mii_mgmt_cfg; /* 0x5020 */
1529 u32 mii_mgmt_cmd; /* 0x5024 */
1530 u32 mii_mgmt_addr; /* 0x5028 */
1531 u32 mii_mgmt_ctrl; /* 0x502C */
1532 u32 mii_mgmt_stat; /* 0x5030 */
1533 u32 mii_mgmt_indicator; /* 0x5034 */
1534 u32 if_ctrl; /* 0x5038 */
1535 MAC_IF_STAT_t if_stat; /* 0x503C */
1536 MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */
1537 MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */
1538 } MAC_t, *PMAC_t;
1539
1540 /* END OF MAC REGISTER ADDRESS MAP */
1541
1542 /* START OF MAC STAT REGISTER ADDRESS MAP */
1543
1544 /*
1545 * structure for Carry Register One and it's Mask Register reg located in mac
1546 * stat address map address 0x6130 and 0x6138.
1547 *
1548 * 31: tr64
1549 * 30: tr127
1550 * 29: tr255
1551 * 28: tr511
1552 * 27: tr1k
1553 * 26: trmax
1554 * 25: trmgv
1555 * 24-17: unused
1556 * 16: rbyt
1557 * 15: rpkt
1558 * 14: rfcs
1559 * 13: rmca
1560 * 12: rbca
1561 * 11: rxcf
1562 * 10: rxpf
1563 * 9: rxuo
1564 * 8: raln
1565 * 7: rflr
1566 * 6: rcde
1567 * 5: rcse
1568 * 4: rund
1569 * 3: rovr
1570 * 2: rfrg
1571 * 1: rjbr
1572 * 0: rdrp
1573 */
1574
1575 /*
1576 * structure for Carry Register Two Mask Register reg in mac stat address map.
1577 * located at address 0x613C
1578 *
1579 * 31-20: unused
1580 * 19: tjbr
1581 * 18: tfcs
1582 * 17: txcf
1583 * 16: tovr
1584 * 15: tund
1585 * 14: trfg
1586 * 13: tbyt
1587 * 12: tpkt
1588 * 11: tmca
1589 * 10: tbca
1590 * 9: txpf
1591 * 8: tdfr
1592 * 7: tedf
1593 * 6: tscl
1594 * 5: tmcl
1595 * 4: tlcl
1596 * 3: txcl
1597 * 2: tncl
1598 * 1: tpfh
1599 * 0: tdrp
1600 */
1601
1602 /*
1603 * MAC STATS Module of JAGCore Address Mapping
1604 */
1605 typedef struct _MAC_STAT_t { /* Location: */
1606 u32 pad[32]; /* 0x6000 - 607C */
1607
1608 /* Tx/Rx 0-64 Byte Frame Counter */
1609 u32 TR64; /* 0x6080 */
1610
1611 /* Tx/Rx 65-127 Byte Frame Counter */
1612 u32 TR127; /* 0x6084 */
1613
1614 /* Tx/Rx 128-255 Byte Frame Counter */
1615 u32 TR255; /* 0x6088 */
1616
1617 /* Tx/Rx 256-511 Byte Frame Counter */
1618 u32 TR511; /* 0x608C */
1619
1620 /* Tx/Rx 512-1023 Byte Frame Counter */
1621 u32 TR1K; /* 0x6090 */
1622
1623 /* Tx/Rx 1024-1518 Byte Frame Counter */
1624 u32 TRMax; /* 0x6094 */
1625
1626 /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1627 u32 TRMgv; /* 0x6098 */
1628
1629 /* Rx Byte Counter */
1630 u32 RByt; /* 0x609C */
1631
1632 /* Rx Packet Counter */
1633 u32 RPkt; /* 0x60A0 */
1634
1635 /* Rx FCS Error Counter */
1636 u32 RFcs; /* 0x60A4 */
1637
1638 /* Rx Multicast Packet Counter */
1639 u32 RMca; /* 0x60A8 */
1640
1641 /* Rx Broadcast Packet Counter */
1642 u32 RBca; /* 0x60AC */
1643
1644 /* Rx Control Frame Packet Counter */
1645 u32 RxCf; /* 0x60B0 */
1646
1647 /* Rx Pause Frame Packet Counter */
1648 u32 RxPf; /* 0x60B4 */
1649
1650 /* Rx Unknown OP Code Counter */
1651 u32 RxUo; /* 0x60B8 */
1652
1653 /* Rx Alignment Error Counter */
1654 u32 RAln; /* 0x60BC */
1655
1656 /* Rx Frame Length Error Counter */
1657 u32 RFlr; /* 0x60C0 */
1658
1659 /* Rx Code Error Counter */
1660 u32 RCde; /* 0x60C4 */
1661
1662 /* Rx Carrier Sense Error Counter */
1663 u32 RCse; /* 0x60C8 */
1664
1665 /* Rx Undersize Packet Counter */
1666 u32 RUnd; /* 0x60CC */
1667
1668 /* Rx Oversize Packet Counter */
1669 u32 ROvr; /* 0x60D0 */
1670
1671 /* Rx Fragment Counter */
1672 u32 RFrg; /* 0x60D4 */
1673
1674 /* Rx Jabber Counter */
1675 u32 RJbr; /* 0x60D8 */
1676
1677 /* Rx Drop */
1678 u32 RDrp; /* 0x60DC */
1679
1680 /* Tx Byte Counter */
1681 u32 TByt; /* 0x60E0 */
1682
1683 /* Tx Packet Counter */
1684 u32 TPkt; /* 0x60E4 */
1685
1686 /* Tx Multicast Packet Counter */
1687 u32 TMca; /* 0x60E8 */
1688
1689 /* Tx Broadcast Packet Counter */
1690 u32 TBca; /* 0x60EC */
1691
1692 /* Tx Pause Control Frame Counter */
1693 u32 TxPf; /* 0x60F0 */
1694
1695 /* Tx Deferral Packet Counter */
1696 u32 TDfr; /* 0x60F4 */
1697
1698 /* Tx Excessive Deferral Packet Counter */
1699 u32 TEdf; /* 0x60F8 */
1700
1701 /* Tx Single Collision Packet Counter */
1702 u32 TScl; /* 0x60FC */
1703
1704 /* Tx Multiple Collision Packet Counter */
1705 u32 TMcl; /* 0x6100 */
1706
1707 /* Tx Late Collision Packet Counter */
1708 u32 TLcl; /* 0x6104 */
1709
1710 /* Tx Excessive Collision Packet Counter */
1711 u32 TXcl; /* 0x6108 */
1712
1713 /* Tx Total Collision Packet Counter */
1714 u32 TNcl; /* 0x610C */
1715
1716 /* Tx Pause Frame Honored Counter */
1717 u32 TPfh; /* 0x6110 */
1718
1719 /* Tx Drop Frame Counter */
1720 u32 TDrp; /* 0x6114 */
1721
1722 /* Tx Jabber Frame Counter */
1723 u32 TJbr; /* 0x6118 */
1724
1725 /* Tx FCS Error Counter */
1726 u32 TFcs; /* 0x611C */
1727
1728 /* Tx Control Frame Counter */
1729 u32 TxCf; /* 0x6120 */
1730
1731 /* Tx Oversize Frame Counter */
1732 u32 TOvr; /* 0x6124 */
1733
1734 /* Tx Undersize Frame Counter */
1735 u32 TUnd; /* 0x6128 */
1736
1737 /* Tx Fragments Frame Counter */
1738 u32 TFrg; /* 0x612C */
1739
1740 /* Carry Register One Register */
1741 u32 Carry1; /* 0x6130 */
1742
1743 /* Carry Register Two Register */
1744 u32 Carry2; /* 0x6134 */
1745
1746 /* Carry Register One Mask Register */
1747 u32 Carry1M; /* 0x6138 */
1748
1749 /* Carry Register Two Mask Register */
1750 u32 Carry2M; /* 0x613C */
1751 } MAC_STAT_t, *PMAC_STAT_t;
1752
1753 /* END OF MAC STAT REGISTER ADDRESS MAP */
1754
1755
1756 /* START OF MMC REGISTER ADDRESS MAP */
1757
1758 /*
1759 * Main Memory Controller Control reg in mmc address map.
1760 * located at address 0x7000
1761 */
1762
1763 #define ET_MMC_ENABLE 1
1764 #define ET_MMC_ARB_DISABLE 2
1765 #define ET_MMC_RXMAC_DISABLE 4
1766 #define ET_MMC_TXMAC_DISABLE 8
1767 #define ET_MMC_TXDMA_DISABLE 16
1768 #define ET_MMC_RXDMA_DISABLE 32
1769 #define ET_MMC_FORCE_CE 64
1770
1771 /*
1772 * Main Memory Controller Host Memory Access Address reg in mmc
1773 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1774 */
1775
1776 #define ET_SRAM_REQ_ACCESS 1
1777 #define ET_SRAM_WR_ACCESS 2
1778 #define ET_SRAM_IS_CTRL 4
1779
1780 /*
1781 * structure for Main Memory Controller Host Memory Access Data reg in mmc
1782 * address map. Located at address 0x7008 - 0x7014
1783 * Defined earlier (u32)
1784 */
1785
1786 /*
1787 * Memory Control Module of JAGCore Address Mapping
1788 */
1789 typedef struct _MMC_t { /* Location: */
1790 u32 mmc_ctrl; /* 0x7000 */
1791 u32 sram_access; /* 0x7004 */
1792 u32 sram_word1; /* 0x7008 */
1793 u32 sram_word2; /* 0x700C */
1794 u32 sram_word3; /* 0x7010 */
1795 u32 sram_word4; /* 0x7014 */
1796 } MMC_t, *PMMC_t;
1797
1798 /* END OF MMC REGISTER ADDRESS MAP */
1799
1800
1801 /* START OF EXP ROM REGISTER ADDRESS MAP */
1802
1803 /*
1804 * Expansion ROM Module of JAGCore Address Mapping
1805 */
1806
1807 /* Take this out until it is not empty */
1808 #if 0
1809 typedef struct _EXP_ROM_t {
1810
1811 } EXP_ROM_t, *PEXP_ROM_t;
1812 #endif
1813
1814 /* END OF EXP ROM REGISTER ADDRESS MAP */
1815
1816
1817 /*
1818 * JAGCore Address Mapping
1819 */
1820 typedef struct _ADDRESS_MAP_t {
1821 GLOBAL_t global;
1822 /* unused section of global address map */
1823 u8 unused_global[4096 - sizeof(GLOBAL_t)];
1824 TXDMA_t txdma;
1825 /* unused section of txdma address map */
1826 u8 unused_txdma[4096 - sizeof(TXDMA_t)];
1827 RXDMA_t rxdma;
1828 /* unused section of rxdma address map */
1829 u8 unused_rxdma[4096 - sizeof(RXDMA_t)];
1830 TXMAC_t txmac;
1831 /* unused section of txmac address map */
1832 u8 unused_txmac[4096 - sizeof(TXMAC_t)];
1833 RXMAC_t rxmac;
1834 /* unused section of rxmac address map */
1835 u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
1836 MAC_t mac;
1837 /* unused section of mac address map */
1838 u8 unused_mac[4096 - sizeof(MAC_t)];
1839 MAC_STAT_t macStat;
1840 /* unused section of mac stat address map */
1841 u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)];
1842 MMC_t mmc;
1843 /* unused section of mmc address map */
1844 u8 unused_mmc[4096 - sizeof(MMC_t)];
1845 /* unused section of address map */
1846 u8 unused_[1015808];
1847
1848 /* Take this out until it is not empty */
1849 #if 0
1850 EXP_ROM_t exp_rom;
1851 #endif
1852
1853 u8 unused_exp_rom[4096]; /* MGS-size TBD */
1854 u8 unused__[524288]; /* unused section of address map */
1855 } ADDRESS_MAP_t, *PADDRESS_MAP_t;
1856
1857 #endif /* _ET1310_ADDRESS_MAP_H_ */
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