drivers/net/wireless/iwlwifi/pcie/internal.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
   5  *
   6  * Portions of this file are derived from the ipw3945 project, as well
   7  * as portions of the ieee80211 subsystem header files.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program; if not, write to the Free Software Foundation, Inc.,
  20  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  21  *
  22  * The full GNU General Public License is included in this distribution in the
  23  * file called LICENSE.
  24  *
  25  * Contact Information:
  26  *  Intel Linux Wireless <ilw@linux.intel.com>
  27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  28  *
  29  *****************************************************************************/
  30 #ifndef __iwl_trans_int_pcie_h__
  31 #define __iwl_trans_int_pcie_h__
  32
  33 #include <linux/spinlock.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/skbuff.h>
  36 #include <linux/wait.h>
  37 #include <linux/pci.h>
  38 #include <linux/timer.h>
  39
  40 #include "iwl-fh.h"
  41 #include "iwl-csr.h"
  42 #include "iwl-trans.h"
  43 #include "iwl-debug.h"
  44 #include "iwl-io.h"
  45 #include "iwl-op-mode.h"
  46
  47 /*
  48  * RX related structures and functions
  49  */
  50 #define RX_NUM_QUEUES 1
  51 #define RX_POST_REQ_ALLOC 2
  52 #define RX_CLAIM_REQ_ALLOC 8
  53 #define RX_POOL_SIZE ((RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC) * RX_NUM_QUEUES)
  54 #define RX_LOW_WATERMARK 8
  55
  56 struct iwl_host_cmd;
  57
  58 /*This file includes the declaration that are internal to the
  59  * trans_pcie layer */
  60
  61 struct iwl_rx_mem_buffer {
  62         dma_addr_t page_dma;
  63         struct page *page;
  64         struct list_head list;
  65 };
  66
  67 /**
  68  * struct isr_statistics - interrupt statistics
  69  *
  70  */
  71 struct isr_statistics {
  72         u32 hw;
  73         u32 sw;
  74         u32 err_code;
  75         u32 sch;
  76         u32 alive;
  77         u32 rfkill;
  78         u32 ctkill;
  79         u32 wakeup;
  80         u32 rx;
  81         u32 tx;
  82         u32 unhandled;
  83 };
  84
  85 /**
  86  * struct iwl_rxq - Rx queue
  87  * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
  88  * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
  89  * @read: Shared index to newest available Rx buffer
  90  * @write: Shared index to oldest written Rx packet
  91  * @free_count: Number of pre-allocated buffers in rx_free
  92  * @used_count: Number of RBDs handled to allocator to use for allocation
  93  * @write_actual:
  94  * @rx_free: list of RBDs with allocated RB ready for use
  95  * @rx_used: list of RBDs with no RB attached
  96  * @need_update: flag to indicate we need to update read/write index
  97  * @rb_stts: driver's pointer to receive buffer status
  98  * @rb_stts_dma: bus address of receive buffer status
  99  * @lock:
 100  * @pool: initial pool of iwl_rx_mem_buffer for the queue
 101  * @queue: actual rx queue
 102  *
 103  * NOTE:  rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
 104  */
 105 struct iwl_rxq {
 106         __le32 *bd;
 107         dma_addr_t bd_dma;
 108         u32 read;
 109         u32 write;
 110         u32 free_count;
 111         u32 used_count;
 112         u32 write_actual;
 113         struct list_head rx_free;
 114         struct list_head rx_used;
 115         bool need_update;
 116         struct iwl_rb_status *rb_stts;
 117         dma_addr_t rb_stts_dma;
 118         spinlock_t lock;
 119         struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE];
 120         struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
 121 };
 122
 123 /**
 124  * struct iwl_rb_allocator - Rx allocator
 125  * @pool: initial pool of allocator
 126  * @req_pending: number of requests the allcator had not processed yet
 127  * @req_ready: number of requests honored and ready for claiming
 128  * @rbd_allocated: RBDs with pages allocated and ready to be handled to
 129  *      the queue. This is a list of &struct iwl_rx_mem_buffer
 130  * @rbd_empty: RBDs with no page attached for allocator use. This is a list
 131  *      of &struct iwl_rx_mem_buffer
 132  * @lock: protects the rbd_allocated and rbd_empty lists
 133  * @alloc_wq: work queue for background calls
 134  * @rx_alloc: work struct for background calls
 135  */
 136 struct iwl_rb_allocator {
 137         struct iwl_rx_mem_buffer pool[RX_POOL_SIZE];
 138         atomic_t req_pending;
 139         atomic_t req_ready;
 140         struct list_head rbd_allocated;
 141         struct list_head rbd_empty;
 142         spinlock_t lock;
 143         struct workqueue_struct *alloc_wq;
 144         struct work_struct rx_alloc;
 145 };
 146
 147 struct iwl_dma_ptr {
 148         dma_addr_t dma;
 149         void *addr;
 150         size_t size;
 151 };
 152
 153 /**
 154  * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
 155  * @index -- current index
 156  */
 157 static inline int iwl_queue_inc_wrap(int index)
 158 {
 159         return ++index & (TFD_QUEUE_SIZE_MAX - 1);
 160 }
 161
 162 /**
 163  * iwl_queue_dec_wrap - decrement queue index, wrap back to end
 164  * @index -- current index
 165  */
 166 static inline int iwl_queue_dec_wrap(int index)
 167 {
 168         return --index & (TFD_QUEUE_SIZE_MAX - 1);
 169 }
 170
 171 struct iwl_cmd_meta {
 172         /* only for SYNC commands, iff the reply skb is wanted */
 173         struct iwl_host_cmd *source;
 174         u32 flags;
 175 };
 176
 177 /*
 178  * Generic queue structure
 179  *
 180  * Contains common data for Rx and Tx queues.
 181  *
 182  * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
 183  * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
 184  * there might be HW changes in the future). For the normal TX
 185  * queues, n_window, which is the size of the software queue data
 186  * is also 256; however, for the command queue, n_window is only
 187  * 32 since we don't need so many commands pending. Since the HW
 188  * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. As a result,
 189  * the software buffers (in the variables @meta, @txb in struct
 190  * iwl_txq) only have 32 entries, while the HW buffers (@tfds in
 191  * the same struct) have 256.
 192  * This means that we end up with the following:
 193  *  HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
 194  *  SW entries:           | 0      | ... | 31          |
 195  * where N is a number between 0 and 7. This means that the SW
 196  * data is a window overlayed over the HW queue.
 197  */
 198 struct iwl_queue {
 199         int write_ptr;       /* 1-st empty entry (index) host_w*/
 200         int read_ptr;         /* last used entry (index) host_r*/
 201         /* use for monitoring and recovering the stuck queue */
 202         dma_addr_t dma_addr;   /* physical addr for BD's */
 203         int n_window;          /* safe queue window */
 204         u32 id;
 205         int low_mark;          /* low watermark, resume queue if free
 206                                 * space more than this */
 207         int high_mark;         /* high watermark, stop queue if free
 208                                 * space less than this */
 209 };
 210
 211 #define TFD_TX_CMD_SLOTS 256
 212 #define TFD_CMD_SLOTS 32
 213
 214 /*
 215  * The FH will write back to the first TB only, so we need
 216  * to copy some data into the buffer regardless of whether
 217  * it should be mapped or not. This indicates how big the
 218  * first TB must be to include the scratch buffer. Since
 219  * the scratch is 4 bytes at offset 12, it's 16 now. If we
 220  * make it bigger then allocations will be bigger and copy
 221  * slower, so that's probably not useful.
 222  */
 223 #define IWL_HCMD_SCRATCHBUF_SIZE        16
 224
 225 struct iwl_pcie_txq_entry {
 226         struct iwl_device_cmd *cmd;
 227         struct sk_buff *skb;
 228         /* buffer to free after command completes */
 229         const void *free_buf;
 230         struct iwl_cmd_meta meta;
 231 };
 232
 233 struct iwl_pcie_txq_scratch_buf {
 234         struct iwl_cmd_header hdr;
 235         u8 buf[8];
 236         __le32 scratch;
 237 };
 238
 239 /**
 240  * struct iwl_txq - Tx Queue for DMA
 241  * @q: generic Rx/Tx queue descriptor
 242  * @tfds: transmit frame descriptors (DMA memory)
 243  * @scratchbufs: start of command headers, including scratch buffers, for
 244  *      the writeback -- this is DMA memory and an array holding one buffer
 245  *      for each command on the queue
 246  * @scratchbufs_dma: DMA address for the scratchbufs start
 247  * @entries: transmit entries (driver state)
 248  * @lock: queue lock
 249  * @stuck_timer: timer that fires if queue gets stuck
 250  * @trans_pcie: pointer back to transport (for timer)
 251  * @need_update: indicates need to update read/write index
 252  * @active: stores if queue is active
 253  * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
 254  * @wd_timeout: queue watchdog timeout (jiffies) - per queue
 255  * @frozen: tx stuck queue timer is frozen
 256  * @frozen_expiry_remainder: remember how long until the timer fires
 257  *
 258  * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
 259  * descriptors) and required locking structures.
 260  */
 261 struct iwl_txq {
 262         struct iwl_queue q;
 263         struct iwl_tfd *tfds;
 264         struct iwl_pcie_txq_scratch_buf *scratchbufs;
 265         dma_addr_t scratchbufs_dma;
 266         struct iwl_pcie_txq_entry *entries;
 267         spinlock_t lock;
 268         unsigned long frozen_expiry_remainder;
 269         struct timer_list stuck_timer;
 270         struct iwl_trans_pcie *trans_pcie;
 271         bool need_update;
 272         bool frozen;
 273         u8 active;
 274         bool ampdu;
 275         unsigned long wd_timeout;
 276 };
 277
 278 static inline dma_addr_t
 279 iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx)
 280 {
 281         return txq->scratchbufs_dma +
 282                sizeof(struct iwl_pcie_txq_scratch_buf) * idx;
 283 }
 284
 285 /**
 286  * struct iwl_trans_pcie - PCIe transport specific data
 287  * @rxq: all the RX queue data
 288  * @rba: allocator for RX replenishing
 289  * @drv - pointer to iwl_drv
 290  * @trans: pointer to the generic transport area
 291  * @scd_base_addr: scheduler sram base address in SRAM
 292  * @scd_bc_tbls: pointer to the byte count table of the scheduler
 293  * @kw: keep warm address
 294  * @pci_dev: basic pci-network driver stuff
 295  * @hw_base: pci hardware address support
 296  * @ucode_write_complete: indicates that the ucode has been copied.
 297  * @ucode_write_waitq: wait queue for uCode load
 298  * @cmd_queue - command queue number
 299  * @rx_buf_size_8k: 8 kB RX buffer size
 300  * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
 301  * @scd_set_active: should the transport configure the SCD for HCMD queue
 302  * @rx_page_order: page order for receive buffer size
 303  * @reg_lock: protect hw register access
 304  * @mutex: to protect stop_device / start_fw / start_hw
 305  * @cmd_in_flight: true when we have a host command in flight
 306  * @fw_mon_phys: physical address of the buffer for the firmware monitor
 307  * @fw_mon_page: points to the first page of the buffer for the firmware monitor
 308  * @fw_mon_size: size of the buffer for the firmware monitor
 309  */
 310 struct iwl_trans_pcie {
 311         struct iwl_rxq rxq;
 312         struct iwl_rb_allocator rba;
 313         struct iwl_trans *trans;
 314         struct iwl_drv *drv;
 315
 316         struct net_device napi_dev;
 317         struct napi_struct napi;
 318
 319         /* INT ICT Table */
 320         __le32 *ict_tbl;
 321         dma_addr_t ict_tbl_dma;
 322         int ict_index;
 323         bool use_ict;
 324         bool is_down;
 325         struct isr_statistics isr_stats;
 326
 327         spinlock_t irq_lock;
 328         struct mutex mutex;
 329         u32 inta_mask;
 330         u32 scd_base_addr;
 331         struct iwl_dma_ptr scd_bc_tbls;
 332         struct iwl_dma_ptr kw;
 333
 334         struct iwl_txq *txq;
 335         unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
 336         unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
 337
 338         /* PCI bus related data */
 339         struct pci_dev *pci_dev;
 340         void __iomem *hw_base;
 341
 342         bool ucode_write_complete;
 343         wait_queue_head_t ucode_write_waitq;
 344         wait_queue_head_t wait_command_queue;
 345
 346         u8 cmd_queue;
 347         u8 cmd_fifo;
 348         unsigned int cmd_q_wdg_timeout;
 349         u8 n_no_reclaim_cmds;
 350         u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
 351
 352         bool rx_buf_size_8k;
 353         bool bc_table_dword;
 354         bool scd_set_active;
 355         u32 rx_page_order;
 356
 357         const char *const *command_names;
 358
 359         /*protect hw register */
 360         spinlock_t reg_lock;
 361         bool cmd_hold_nic_awake;
 362         bool ref_cmd_in_flight;
 363
 364         /* protect ref counter */
 365         spinlock_t ref_lock;
 366         u32 ref_count;
 367
 368         dma_addr_t fw_mon_phys;
 369         struct page *fw_mon_page;
 370         u32 fw_mon_size;
 371 };
 372
 373 #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
 374         ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
 375
 376 static inline struct iwl_trans *
 377 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
 378 {
 379         return container_of((void *)trans_pcie, struct iwl_trans,
 380                             trans_specific);
 381 }
 382
 383 /*
 384  * Convention: trans API functions: iwl_trans_pcie_XXX
 385  *      Other functions: iwl_pcie_XXX
 386  */
 387 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
 388                                        const struct pci_device_id *ent,
 389                                        const struct iwl_cfg *cfg);
 390 void iwl_trans_pcie_free(struct iwl_trans *trans);
 391
 392 /*****************************************************
 393 * RX
 394 ******************************************************/
 395 int iwl_pcie_rx_init(struct iwl_trans *trans);
 396 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
 397 int iwl_pcie_rx_stop(struct iwl_trans *trans);
 398 void iwl_pcie_rx_free(struct iwl_trans *trans);
 399
 400 /*****************************************************
 401 * ICT - interrupt handling
 402 ******************************************************/
 403 irqreturn_t iwl_pcie_isr(int irq, void *data);
 404 int iwl_pcie_alloc_ict(struct iwl_trans *trans);
 405 void iwl_pcie_free_ict(struct iwl_trans *trans);
 406 void iwl_pcie_reset_ict(struct iwl_trans *trans);
 407 void iwl_pcie_disable_ict(struct iwl_trans *trans);
 408
 409 /*****************************************************
 410 * TX / HCMD
 411 ******************************************************/
 412 int iwl_pcie_tx_init(struct iwl_trans *trans);
 413 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
 414 int iwl_pcie_tx_stop(struct iwl_trans *trans);
 415 void iwl_pcie_tx_free(struct iwl_trans *trans);
 416 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
 417                                const struct iwl_trans_txq_scd_cfg *cfg,
 418                                unsigned int wdg_timeout);
 419 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
 420                                 bool configure_scd);
 421 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
 422                       struct iwl_device_cmd *dev_cmd, int txq_id);
 423 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
 424 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
 425 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
 426                             struct iwl_rx_cmd_buffer *rxb);
 427 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
 428                             struct sk_buff_head *skbs);
 429 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
 430
 431 void iwl_trans_pcie_ref(struct iwl_trans *trans);
 432 void iwl_trans_pcie_unref(struct iwl_trans *trans);
 433
 434 static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 435 {
 436         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 437
 438         return le16_to_cpu(tb->hi_n_len) >> 4;
 439 }
 440
 441 /*****************************************************
 442 * Error handling
 443 ******************************************************/
 444 void iwl_pcie_dump_csr(struct iwl_trans *trans);
 445
 446 /*****************************************************
 447 * Helpers
 448 ******************************************************/
 449 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
 450 {
 451         clear_bit(STATUS_INT_ENABLED, &trans->status);
 452
 453         /* disable interrupts from uCode/NIC to host */
 454         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
 455
 456         /* acknowledge/clear/reset any interrupts still pending
 457          * from uCode or flow handler (Rx/Tx DMA) */
 458         iwl_write32(trans, CSR_INT, 0xffffffff);
 459         iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
 460         IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
 461 }
 462
 463 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
 464 {
 465         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 466
 467         IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
 468         set_bit(STATUS_INT_ENABLED, &trans->status);
 469         trans_pcie->inta_mask = CSR_INI_SET_MASK;
 470         iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
 471 }
 472
 473 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
 474 {
 475         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 476
 477         IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
 478         trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
 479         iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
 480 }
 481
 482 static inline void iwl_wake_queue(struct iwl_trans *trans,
 483                                   struct iwl_txq *txq)
 484 {
 485         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 486
 487         if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) {
 488                 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id);
 489                 iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id);
 490         }
 491 }
 492
 493 static inline void iwl_stop_queue(struct iwl_trans *trans,
 494                                   struct iwl_txq *txq)
 495 {
 496         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 497
 498         if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) {
 499                 iwl_op_mode_queue_full(trans->op_mode, txq->q.id);
 500                 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id);
 501         } else
 502                 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
 503                                     txq->q.id);
 504 }
 505
 506 static inline bool iwl_queue_used(const struct iwl_queue *q, int i)
 507 {
 508         return q->write_ptr >= q->read_ptr ?
 509                 (i >= q->read_ptr && i < q->write_ptr) :
 510                 !(i < q->read_ptr && i >= q->write_ptr);
 511 }
 512
 513 static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
 514 {
 515         return index & (q->n_window - 1);
 516 }
 517
 518 static inline const char *get_cmd_string(struct iwl_trans_pcie *trans_pcie,
 519                                          u8 cmd)
 520 {
 521         if (!trans_pcie->command_names || !trans_pcie->command_names[cmd])
 522                 return "UNKNOWN";
 523         return trans_pcie->command_names[cmd];
 524 }
 525
 526 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
 527 {
 528         return !(iwl_read32(trans, CSR_GP_CNTRL) &
 529                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
 530 }
 531
 532 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
 533                                                   u32 reg, u32 mask, u32 value)
 534 {
 535         u32 v;
 536
 537 #ifdef CONFIG_IWLWIFI_DEBUG
 538         WARN_ON_ONCE(value & ~mask);
 539 #endif
 540
 541         v = iwl_read32(trans, reg);
 542         v &= ~mask;
 543         v |= value;
 544         iwl_write32(trans, reg, v);
 545 }
 546
 547 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
 548                                               u32 reg, u32 mask)
 549 {
 550         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
 551 }
 552
 553 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
 554                                             u32 reg, u32 mask)
 555 {
 556         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
 557 }
 558
 559 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
 560
 561 #endif /* __iwl_trans_int_pcie_h__ */