2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
30 #include <mach/hardware.h>
32 #include <mach/regs-clock.h>
33 #include <mach/regs-gpio.h>
36 #include <plat/gpio-core.h>
37 #include <plat/gpio-cfg.h>
38 #include <plat/gpio-cfg-helpers.h>
39 #include <plat/gpio-fns.h>
43 #define gpio_dbg(x...) do { } while (0)
45 #define gpio_dbg(x...) printk(KERN_DEBUG x)
48 int samsung_gpio_setpull_updown(struct samsung_gpio_chip
*chip
,
49 unsigned int off
, samsung_gpio_pull_t pull
)
51 void __iomem
*reg
= chip
->base
+ 0x08;
55 pup
= __raw_readl(reg
);
58 __raw_writel(pup
, reg
);
63 samsung_gpio_pull_t
samsung_gpio_getpull_updown(struct samsung_gpio_chip
*chip
,
66 void __iomem
*reg
= chip
->base
+ 0x08;
68 u32 pup
= __raw_readl(reg
);
73 return (__force samsung_gpio_pull_t
)pup
;
76 int s3c2443_gpio_setpull(struct samsung_gpio_chip
*chip
,
77 unsigned int off
, samsung_gpio_pull_t pull
)
80 case S3C_GPIO_PULL_NONE
:
83 case S3C_GPIO_PULL_UP
:
86 case S3C_GPIO_PULL_DOWN
:
90 return samsung_gpio_setpull_updown(chip
, off
, pull
);
93 samsung_gpio_pull_t
s3c2443_gpio_getpull(struct samsung_gpio_chip
*chip
,
96 samsung_gpio_pull_t pull
;
98 pull
= samsung_gpio_getpull_updown(chip
, off
);
102 pull
= S3C_GPIO_PULL_UP
;
106 pull
= S3C_GPIO_PULL_NONE
;
109 pull
= S3C_GPIO_PULL_DOWN
;
116 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip
*chip
,
117 unsigned int off
, samsung_gpio_pull_t pull
,
118 samsung_gpio_pull_t updown
)
120 void __iomem
*reg
= chip
->base
+ 0x08;
121 u32 pup
= __raw_readl(reg
);
125 else if (pull
== S3C_GPIO_PULL_NONE
)
130 __raw_writel(pup
, reg
);
134 static samsung_gpio_pull_t
s3c24xx_gpio_getpull_1(struct samsung_gpio_chip
*chip
,
136 samsung_gpio_pull_t updown
)
138 void __iomem
*reg
= chip
->base
+ 0x08;
139 u32 pup
= __raw_readl(reg
);
142 return pup
? S3C_GPIO_PULL_NONE
: updown
;
145 samsung_gpio_pull_t
s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip
*chip
,
148 return s3c24xx_gpio_getpull_1(chip
, off
, S3C_GPIO_PULL_UP
);
151 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip
*chip
,
152 unsigned int off
, samsung_gpio_pull_t pull
)
154 return s3c24xx_gpio_setpull_1(chip
, off
, pull
, S3C_GPIO_PULL_UP
);
157 samsung_gpio_pull_t
s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip
*chip
,
160 return s3c24xx_gpio_getpull_1(chip
, off
, S3C_GPIO_PULL_DOWN
);
163 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip
*chip
,
164 unsigned int off
, samsung_gpio_pull_t pull
)
166 return s3c24xx_gpio_setpull_1(chip
, off
, pull
, S3C_GPIO_PULL_DOWN
);
169 static int exynos4_gpio_setpull(struct samsung_gpio_chip
*chip
,
170 unsigned int off
, samsung_gpio_pull_t pull
)
172 if (pull
== S3C_GPIO_PULL_UP
)
175 return samsung_gpio_setpull_updown(chip
, off
, pull
);
178 static samsung_gpio_pull_t
exynos4_gpio_getpull(struct samsung_gpio_chip
*chip
,
181 samsung_gpio_pull_t pull
;
183 pull
= samsung_gpio_getpull_updown(chip
, off
);
186 pull
= S3C_GPIO_PULL_UP
;
192 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
193 * @chip: The gpio chip that is being configured.
194 * @off: The offset for the GPIO being configured.
195 * @cfg: The configuration value to set.
197 * This helper deal with the GPIO cases where the control register
198 * has two bits of configuration per gpio, which have the following
202 * 1x = special function
205 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip
*chip
,
206 unsigned int off
, unsigned int cfg
)
208 void __iomem
*reg
= chip
->base
;
209 unsigned int shift
= off
* 2;
212 if (samsung_gpio_is_cfg_special(cfg
)) {
220 con
= __raw_readl(reg
);
221 con
&= ~(0x3 << shift
);
223 __raw_writel(con
, reg
);
229 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
230 * @chip: The gpio chip that is being configured.
231 * @off: The offset for the GPIO being configured.
233 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value whicg
234 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
235 * S3C_GPIO_SPECIAL() macro.
238 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip
*chip
,
243 con
= __raw_readl(chip
->base
);
247 /* this conversion works for IN and OUT as well as special mode */
248 return S3C_GPIO_SPECIAL(con
);
252 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
253 * @chip: The gpio chip that is being configured.
254 * @off: The offset for the GPIO being configured.
255 * @cfg: The configuration value to set.
257 * This helper deal with the GPIO cases where the control register has 4 bits
258 * of control per GPIO, generally in the form of:
261 * others = Special functions (dependent on bank)
263 * Note, since the code to deal with the case where there are two control
264 * registers instead of one, we do not have a separate set of functions for
268 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip
*chip
,
269 unsigned int off
, unsigned int cfg
)
271 void __iomem
*reg
= chip
->base
;
272 unsigned int shift
= (off
& 7) * 4;
275 if (off
< 8 && chip
->chip
.ngpio
> 8)
278 if (samsung_gpio_is_cfg_special(cfg
)) {
283 con
= __raw_readl(reg
);
284 con
&= ~(0xf << shift
);
286 __raw_writel(con
, reg
);
292 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
293 * @chip: The gpio chip that is being configured.
294 * @off: The offset for the GPIO being configured.
296 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
297 * register setting into a value the software can use, such as could be passed
298 * to samsung_gpio_setcfg_4bit().
300 * @sa samsung_gpio_getcfg_2bit
303 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip
*chip
,
306 void __iomem
*reg
= chip
->base
;
307 unsigned int shift
= (off
& 7) * 4;
310 if (off
< 8 && chip
->chip
.ngpio
> 8)
313 con
= __raw_readl(reg
);
317 /* this conversion works for IN and OUT as well as special mode */
318 return S3C_GPIO_SPECIAL(con
);
322 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
323 * @chip: The gpio chip that is being configured.
324 * @off: The offset for the GPIO being configured.
325 * @cfg: The configuration value to set.
327 * This helper deal with the GPIO cases where the control register
328 * has one bit of configuration for the gpio, where setting the bit
329 * means the pin is in special function mode and unset means output.
332 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip
*chip
,
333 unsigned int off
, unsigned int cfg
)
335 void __iomem
*reg
= chip
->base
;
336 unsigned int shift
= off
;
339 if (samsung_gpio_is_cfg_special(cfg
)) {
342 /* Map output to 0, and SFN2 to 1 */
350 con
= __raw_readl(reg
);
351 con
&= ~(0x1 << shift
);
353 __raw_writel(con
, reg
);
359 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
360 * @chip: The gpio chip that is being configured.
361 * @off: The offset for the GPIO being configured.
363 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
364 * GPIO configuration value.
366 * @sa samsung_gpio_getcfg_2bit
367 * @sa samsung_gpio_getcfg_4bit
370 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip
*chip
,
375 con
= __raw_readl(chip
->base
);
380 return S3C_GPIO_SFN(con
);
383 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip
*chip
,
384 unsigned int off
, unsigned int cfg
)
386 void __iomem
*reg
= chip
->base
;
397 shift
= (off
& 7) * 4;
401 shift
= ((off
+ 1) & 7) * 4;
404 shift
= ((off
+ 1) & 7) * 4;
408 if (samsung_gpio_is_cfg_special(cfg
)) {
413 con
= __raw_readl(reg
);
414 con
&= ~(0xf << shift
);
416 __raw_writel(con
, reg
);
421 static void __init
samsung_gpiolib_set_cfg(struct samsung_gpio_cfg
*chipcfg
,
424 for (; nr_chips
> 0; nr_chips
--, chipcfg
++) {
425 if (!chipcfg
->set_config
)
426 chipcfg
->set_config
= samsung_gpio_setcfg_4bit
;
427 if (!chipcfg
->get_config
)
428 chipcfg
->get_config
= samsung_gpio_getcfg_4bit
;
429 if (!chipcfg
->set_pull
)
430 chipcfg
->set_pull
= samsung_gpio_setpull_updown
;
431 if (!chipcfg
->get_pull
)
432 chipcfg
->get_pull
= samsung_gpio_getpull_updown
;
436 struct samsung_gpio_cfg s3c24xx_gpiocfg_default
= {
437 .set_config
= samsung_gpio_setcfg_2bit
,
438 .get_config
= samsung_gpio_getcfg_2bit
,
441 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka
= {
442 .set_config
= s3c24xx_gpio_setcfg_abank
,
443 .get_config
= s3c24xx_gpio_getcfg_abank
,
446 static struct samsung_gpio_cfg exynos4_gpio_cfg
= {
447 .set_pull
= exynos4_gpio_setpull
,
448 .get_pull
= exynos4_gpio_getpull
,
449 .set_config
= samsung_gpio_setcfg_4bit
,
450 .get_config
= samsung_gpio_getcfg_4bit
,
453 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank
= {
455 .set_config
= s5p64x0_gpio_setcfg_rbank
,
456 .get_config
= samsung_gpio_getcfg_4bit
,
457 .set_pull
= samsung_gpio_setpull_updown
,
458 .get_pull
= samsung_gpio_getpull_updown
,
461 static struct samsung_gpio_cfg samsung_gpio_cfgs
[] = {
472 .set_config
= samsung_gpio_setcfg_2bit
,
473 .get_config
= samsung_gpio_getcfg_2bit
,
476 .set_config
= samsung_gpio_setcfg_2bit
,
477 .get_config
= samsung_gpio_getcfg_2bit
,
480 .set_config
= samsung_gpio_setcfg_2bit
,
481 .get_config
= samsung_gpio_getcfg_2bit
,
483 .set_config
= samsung_gpio_setcfg_2bit
,
484 .get_config
= samsung_gpio_getcfg_2bit
,
489 * Default routines for controlling GPIO, based on the original S3C24XX
490 * GPIO functions which deal with the case where each gpio bank of the
491 * chip is as following:
493 * base + 0x00: Control register, 2 bits per gpio
494 * gpio n: 2 bits starting at (2*n)
495 * 00 = input, 01 = output, others mean special-function
496 * base + 0x04: Data register, 1 bit per gpio
500 static int samsung_gpiolib_2bit_input(struct gpio_chip
*chip
, unsigned offset
)
502 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
503 void __iomem
*base
= ourchip
->base
;
507 samsung_gpio_lock(ourchip
, flags
);
509 con
= __raw_readl(base
+ 0x00);
510 con
&= ~(3 << (offset
* 2));
512 __raw_writel(con
, base
+ 0x00);
514 samsung_gpio_unlock(ourchip
, flags
);
518 static int samsung_gpiolib_2bit_output(struct gpio_chip
*chip
,
519 unsigned offset
, int value
)
521 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
522 void __iomem
*base
= ourchip
->base
;
527 samsung_gpio_lock(ourchip
, flags
);
529 dat
= __raw_readl(base
+ 0x04);
530 dat
&= ~(1 << offset
);
533 __raw_writel(dat
, base
+ 0x04);
535 con
= __raw_readl(base
+ 0x00);
536 con
&= ~(3 << (offset
* 2));
537 con
|= 1 << (offset
* 2);
539 __raw_writel(con
, base
+ 0x00);
540 __raw_writel(dat
, base
+ 0x04);
542 samsung_gpio_unlock(ourchip
, flags
);
547 * The samsung_gpiolib_4bit routines are to control the gpio banks where
548 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
551 * base + 0x00: Control register, 4 bits per gpio
552 * gpio n: 4 bits starting at (4*n)
553 * 0000 = input, 0001 = output, others mean special-function
554 * base + 0x04: Data register, 1 bit per gpio
557 * Note, since the data register is one bit per gpio and is at base + 0x4
558 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
559 * state of the output.
562 static int samsung_gpiolib_4bit_input(struct gpio_chip
*chip
,
565 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
566 void __iomem
*base
= ourchip
->base
;
569 con
= __raw_readl(base
+ GPIOCON_OFF
);
570 con
&= ~(0xf << con_4bit_shift(offset
));
571 __raw_writel(con
, base
+ GPIOCON_OFF
);
573 gpio_dbg("%s: %p: CON now %08lx\n", __func__
, base
, con
);
578 static int samsung_gpiolib_4bit_output(struct gpio_chip
*chip
,
579 unsigned int offset
, int value
)
581 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
582 void __iomem
*base
= ourchip
->base
;
586 con
= __raw_readl(base
+ GPIOCON_OFF
);
587 con
&= ~(0xf << con_4bit_shift(offset
));
588 con
|= 0x1 << con_4bit_shift(offset
);
590 dat
= __raw_readl(base
+ GPIODAT_OFF
);
595 dat
&= ~(1 << offset
);
597 __raw_writel(dat
, base
+ GPIODAT_OFF
);
598 __raw_writel(con
, base
+ GPIOCON_OFF
);
599 __raw_writel(dat
, base
+ GPIODAT_OFF
);
601 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__
, base
, con
, dat
);
607 * The next set of routines are for the case where the GPIO configuration
608 * registers are 4 bits per GPIO but there is more than one register (the
609 * bank has more than 8 GPIOs.
611 * This case is the similar to the 4 bit case, but the registers are as
614 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
615 * gpio n: 4 bits starting at (4*n)
616 * 0000 = input, 0001 = output, others mean special-function
617 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
618 * gpio n: 4 bits starting at (4*n)
619 * 0000 = input, 0001 = output, others mean special-function
620 * base + 0x08: Data register, 1 bit per gpio
623 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
624 * routines we store the 'base + 0x4' address so that these routines see
625 * the data register at ourchip->base + 0x04.
628 static int samsung_gpiolib_4bit2_input(struct gpio_chip
*chip
,
631 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
632 void __iomem
*base
= ourchip
->base
;
633 void __iomem
*regcon
= base
;
641 con
= __raw_readl(regcon
);
642 con
&= ~(0xf << con_4bit_shift(offset
));
643 __raw_writel(con
, regcon
);
645 gpio_dbg("%s: %p: CON %08lx\n", __func__
, base
, con
);
650 static int samsung_gpiolib_4bit2_output(struct gpio_chip
*chip
,
651 unsigned int offset
, int value
)
653 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
654 void __iomem
*base
= ourchip
->base
;
655 void __iomem
*regcon
= base
;
658 unsigned con_offset
= offset
;
665 con
= __raw_readl(regcon
);
666 con
&= ~(0xf << con_4bit_shift(con_offset
));
667 con
|= 0x1 << con_4bit_shift(con_offset
);
669 dat
= __raw_readl(base
+ GPIODAT_OFF
);
674 dat
&= ~(1 << offset
);
676 __raw_writel(dat
, base
+ GPIODAT_OFF
);
677 __raw_writel(con
, regcon
);
678 __raw_writel(dat
, base
+ GPIODAT_OFF
);
680 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__
, base
, con
, dat
);
685 /* The next set of routines are for the case of s3c24xx bank a */
687 static int s3c24xx_gpiolib_banka_input(struct gpio_chip
*chip
, unsigned offset
)
692 static int s3c24xx_gpiolib_banka_output(struct gpio_chip
*chip
,
693 unsigned offset
, int value
)
695 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
696 void __iomem
*base
= ourchip
->base
;
701 local_irq_save(flags
);
703 con
= __raw_readl(base
+ 0x00);
704 dat
= __raw_readl(base
+ 0x04);
706 dat
&= ~(1 << offset
);
710 __raw_writel(dat
, base
+ 0x04);
712 con
&= ~(1 << offset
);
714 __raw_writel(con
, base
+ 0x00);
715 __raw_writel(dat
, base
+ 0x04);
717 local_irq_restore(flags
);
721 /* The next set of routines are for the case of s5p64x0 bank r */
723 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip
*chip
,
726 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
727 void __iomem
*base
= ourchip
->base
;
728 void __iomem
*regcon
= base
;
748 samsung_gpio_lock(ourchip
, flags
);
750 con
= __raw_readl(regcon
);
751 con
&= ~(0xf << con_4bit_shift(offset
));
752 __raw_writel(con
, regcon
);
754 samsung_gpio_unlock(ourchip
, flags
);
759 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip
*chip
,
760 unsigned int offset
, int value
)
762 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
763 void __iomem
*base
= ourchip
->base
;
764 void __iomem
*regcon
= base
;
768 unsigned con_offset
= offset
;
770 switch (con_offset
) {
786 samsung_gpio_lock(ourchip
, flags
);
788 con
= __raw_readl(regcon
);
789 con
&= ~(0xf << con_4bit_shift(con_offset
));
790 con
|= 0x1 << con_4bit_shift(con_offset
);
792 dat
= __raw_readl(base
+ GPIODAT_OFF
);
796 dat
&= ~(1 << offset
);
798 __raw_writel(con
, regcon
);
799 __raw_writel(dat
, base
+ GPIODAT_OFF
);
801 samsung_gpio_unlock(ourchip
, flags
);
806 static void samsung_gpiolib_set(struct gpio_chip
*chip
,
807 unsigned offset
, int value
)
809 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
810 void __iomem
*base
= ourchip
->base
;
814 samsung_gpio_lock(ourchip
, flags
);
816 dat
= __raw_readl(base
+ 0x04);
817 dat
&= ~(1 << offset
);
820 __raw_writel(dat
, base
+ 0x04);
822 samsung_gpio_unlock(ourchip
, flags
);
825 static int samsung_gpiolib_get(struct gpio_chip
*chip
, unsigned offset
)
827 struct samsung_gpio_chip
*ourchip
= to_samsung_gpio(chip
);
830 val
= __raw_readl(ourchip
->base
+ 0x04);
838 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
839 * for use with the configuration calls, and other parts of the s3c gpiolib
842 * Not all s3c support code will need this, as some configurations of cpu
843 * may only support one or two different configuration options and have an
844 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
845 * the machine support file should provide its own samsung_gpiolib_getchip()
846 * and any other necessary functions.
849 #ifdef CONFIG_S3C_GPIO_TRACK
850 struct samsung_gpio_chip
*s3c_gpios
[S3C_GPIO_END
];
852 static __init
void s3c_gpiolib_track(struct samsung_gpio_chip
*chip
)
857 gpn
= chip
->chip
.base
;
858 for (i
= 0; i
< chip
->chip
.ngpio
; i
++, gpn
++) {
859 BUG_ON(gpn
>= ARRAY_SIZE(s3c_gpios
));
860 s3c_gpios
[gpn
] = chip
;
863 #endif /* CONFIG_S3C_GPIO_TRACK */
866 * samsung_gpiolib_add() - add the Samsung gpio_chip.
867 * @chip: The chip to register
869 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
870 * information and makes the necessary alterations for the platform and
871 * notes the information for use with the configuration systems and any
872 * other parts of the system.
875 static void __init
samsung_gpiolib_add(struct samsung_gpio_chip
*chip
)
877 struct gpio_chip
*gc
= &chip
->chip
;
884 spin_lock_init(&chip
->lock
);
886 if (!gc
->direction_input
)
887 gc
->direction_input
= samsung_gpiolib_2bit_input
;
888 if (!gc
->direction_output
)
889 gc
->direction_output
= samsung_gpiolib_2bit_output
;
891 gc
->set
= samsung_gpiolib_set
;
893 gc
->get
= samsung_gpiolib_get
;
896 if (chip
->pm
!= NULL
) {
897 if (!chip
->pm
->save
|| !chip
->pm
->resume
)
898 printk(KERN_ERR
"gpio: %s has missing PM functions\n",
901 printk(KERN_ERR
"gpio: %s has no PM function\n", gc
->label
);
904 /* gpiochip_add() prints own failure message on error. */
905 ret
= gpiochip_add(gc
);
907 s3c_gpiolib_track(chip
);
910 static void __init
s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip
*chip
,
911 int nr_chips
, void __iomem
*base
)
914 struct gpio_chip
*gc
= &chip
->chip
;
916 for (i
= 0 ; i
< nr_chips
; i
++, chip
++) {
918 chip
->config
= &s3c24xx_gpiocfg_default
;
920 chip
->pm
= __gpio_pm(&samsung_gpio_pm_2bit
);
921 if ((base
!= NULL
) && (chip
->base
== NULL
))
922 chip
->base
= base
+ ((i
) * 0x10);
924 if (!gc
->direction_input
)
925 gc
->direction_input
= samsung_gpiolib_2bit_input
;
926 if (!gc
->direction_output
)
927 gc
->direction_output
= samsung_gpiolib_2bit_output
;
929 samsung_gpiolib_add(chip
);
933 static void __init
samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip
*chip
,
934 int nr_chips
, void __iomem
*base
,
939 for (i
= 0 ; i
< nr_chips
; i
++, chip
++) {
940 chip
->chip
.direction_input
= samsung_gpiolib_2bit_input
;
941 chip
->chip
.direction_output
= samsung_gpiolib_2bit_output
;
944 chip
->config
= &samsung_gpio_cfgs
[7];
946 chip
->pm
= __gpio_pm(&samsung_gpio_pm_2bit
);
947 if ((base
!= NULL
) && (chip
->base
== NULL
))
948 chip
->base
= base
+ ((i
) * offset
);
950 samsung_gpiolib_add(chip
);
955 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
956 * @chip: The gpio chip that is being configured.
957 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
959 * This helper deal with the GPIO cases where the control register has 4 bits
960 * of control per GPIO, generally in the form of:
963 * others = Special functions (dependent on bank)
965 * Note, since the code to deal with the case where there are two control
966 * registers instead of one, we do not have a separate set of function
967 * (samsung_gpiolib_add_4bit2_chips)for each case.
970 static void __init
samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip
*chip
,
971 int nr_chips
, void __iomem
*base
)
975 for (i
= 0 ; i
< nr_chips
; i
++, chip
++) {
976 chip
->chip
.direction_input
= samsung_gpiolib_4bit_input
;
977 chip
->chip
.direction_output
= samsung_gpiolib_4bit_output
;
980 chip
->config
= &samsung_gpio_cfgs
[2];
982 chip
->pm
= __gpio_pm(&samsung_gpio_pm_4bit
);
983 if ((base
!= NULL
) && (chip
->base
== NULL
))
984 chip
->base
= base
+ ((i
) * 0x20);
986 samsung_gpiolib_add(chip
);
990 static void __init
samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip
*chip
,
993 for (; nr_chips
> 0; nr_chips
--, chip
++) {
994 chip
->chip
.direction_input
= samsung_gpiolib_4bit2_input
;
995 chip
->chip
.direction_output
= samsung_gpiolib_4bit2_output
;
998 chip
->config
= &samsung_gpio_cfgs
[2];
1000 chip
->pm
= __gpio_pm(&samsung_gpio_pm_4bit
);
1002 samsung_gpiolib_add(chip
);
1006 static void __init
s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip
*chip
,
1009 for (; nr_chips
> 0; nr_chips
--, chip
++) {
1010 chip
->chip
.direction_input
= s5p64x0_gpiolib_rbank_input
;
1011 chip
->chip
.direction_output
= s5p64x0_gpiolib_rbank_output
;
1014 chip
->pm
= __gpio_pm(&samsung_gpio_pm_4bit
);
1016 samsung_gpiolib_add(chip
);
1020 int samsung_gpiolib_to_irq(struct gpio_chip
*chip
, unsigned int offset
)
1022 struct samsung_gpio_chip
*samsung_chip
= container_of(chip
, struct samsung_gpio_chip
, chip
);
1024 return samsung_chip
->irq_base
+ offset
;
1027 #ifdef CONFIG_PLAT_S3C24XX
1028 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip
*chip
, unsigned offset
)
1031 return IRQ_EINT0
+ offset
;
1034 return IRQ_EINT4
+ offset
- 4;
1040 #ifdef CONFIG_PLAT_S3C64XX
1041 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip
*chip
, unsigned pin
)
1043 return pin
< 5 ? IRQ_EINT(23) + pin
: -ENXIO
;
1046 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip
*chip
, unsigned pin
)
1048 return pin
>= 8 ? IRQ_EINT(16) + pin
- 8 : -ENXIO
;
1052 struct samsung_gpio_chip s3c24xx_gpios
[] = {
1053 #ifdef CONFIG_PLAT_S3C24XX
1055 .config
= &s3c24xx_gpiocfg_banka
,
1057 .base
= S3C2410_GPA(0),
1058 .owner
= THIS_MODULE
,
1061 .direction_input
= s3c24xx_gpiolib_banka_input
,
1062 .direction_output
= s3c24xx_gpiolib_banka_output
,
1066 .base
= S3C2410_GPB(0),
1067 .owner
= THIS_MODULE
,
1073 .base
= S3C2410_GPC(0),
1074 .owner
= THIS_MODULE
,
1080 .base
= S3C2410_GPD(0),
1081 .owner
= THIS_MODULE
,
1087 .base
= S3C2410_GPE(0),
1089 .owner
= THIS_MODULE
,
1094 .base
= S3C2410_GPF(0),
1095 .owner
= THIS_MODULE
,
1098 .to_irq
= s3c24xx_gpiolib_fbank_to_irq
,
1101 .irq_base
= IRQ_EINT8
,
1103 .base
= S3C2410_GPG(0),
1104 .owner
= THIS_MODULE
,
1107 .to_irq
= samsung_gpiolib_to_irq
,
1111 .base
= S3C2410_GPH(0),
1112 .owner
= THIS_MODULE
,
1117 /* GPIOS for the S3C2443 and later devices. */
1119 .base
= S3C2440_GPJCON
,
1121 .base
= S3C2410_GPJ(0),
1122 .owner
= THIS_MODULE
,
1127 .base
= S3C2443_GPKCON
,
1129 .base
= S3C2410_GPK(0),
1130 .owner
= THIS_MODULE
,
1135 .base
= S3C2443_GPLCON
,
1137 .base
= S3C2410_GPL(0),
1138 .owner
= THIS_MODULE
,
1143 .base
= S3C2443_GPMCON
,
1145 .base
= S3C2410_GPM(0),
1146 .owner
= THIS_MODULE
,
1155 * GPIO bank summary:
1157 * Bank GPIOs Style SlpCon ExtInt Group
1163 * F 16 2Bit Yes 4 [1]
1165 * H 10 4Bit[2] Yes 6
1166 * I 16 2Bit Yes None
1167 * J 12 2Bit Yes None
1168 * K 16 4Bit[2] No None
1169 * L 15 4Bit[2] No None
1170 * M 6 4Bit No IRQ_EINT
1171 * N 16 2Bit No IRQ_EINT
1176 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1177 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1180 static struct samsung_gpio_chip s3c64xx_gpios_4bit
[] = {
1181 #ifdef CONFIG_PLAT_S3C64XX
1184 .base
= S3C64XX_GPA(0),
1185 .ngpio
= S3C64XX_GPIO_A_NR
,
1190 .base
= S3C64XX_GPB(0),
1191 .ngpio
= S3C64XX_GPIO_B_NR
,
1196 .base
= S3C64XX_GPC(0),
1197 .ngpio
= S3C64XX_GPIO_C_NR
,
1202 .base
= S3C64XX_GPD(0),
1203 .ngpio
= S3C64XX_GPIO_D_NR
,
1207 .config
= &samsung_gpio_cfgs
[0],
1209 .base
= S3C64XX_GPE(0),
1210 .ngpio
= S3C64XX_GPIO_E_NR
,
1214 .base
= S3C64XX_GPG_BASE
,
1216 .base
= S3C64XX_GPG(0),
1217 .ngpio
= S3C64XX_GPIO_G_NR
,
1221 .base
= S3C64XX_GPM_BASE
,
1222 .config
= &samsung_gpio_cfgs
[1],
1224 .base
= S3C64XX_GPM(0),
1225 .ngpio
= S3C64XX_GPIO_M_NR
,
1227 .to_irq
= s3c64xx_gpiolib_mbank_to_irq
,
1233 static struct samsung_gpio_chip s3c64xx_gpios_4bit2
[] = {
1234 #ifdef CONFIG_PLAT_S3C64XX
1236 .base
= S3C64XX_GPH_BASE
+ 0x4,
1238 .base
= S3C64XX_GPH(0),
1239 .ngpio
= S3C64XX_GPIO_H_NR
,
1243 .base
= S3C64XX_GPK_BASE
+ 0x4,
1244 .config
= &samsung_gpio_cfgs
[0],
1246 .base
= S3C64XX_GPK(0),
1247 .ngpio
= S3C64XX_GPIO_K_NR
,
1251 .base
= S3C64XX_GPL_BASE
+ 0x4,
1252 .config
= &samsung_gpio_cfgs
[1],
1254 .base
= S3C64XX_GPL(0),
1255 .ngpio
= S3C64XX_GPIO_L_NR
,
1257 .to_irq
= s3c64xx_gpiolib_lbank_to_irq
,
1263 static struct samsung_gpio_chip s3c64xx_gpios_2bit
[] = {
1264 #ifdef CONFIG_PLAT_S3C64XX
1266 .base
= S3C64XX_GPF_BASE
,
1267 .config
= &samsung_gpio_cfgs
[6],
1269 .base
= S3C64XX_GPF(0),
1270 .ngpio
= S3C64XX_GPIO_F_NR
,
1274 .config
= &samsung_gpio_cfgs
[7],
1276 .base
= S3C64XX_GPI(0),
1277 .ngpio
= S3C64XX_GPIO_I_NR
,
1281 .config
= &samsung_gpio_cfgs
[7],
1283 .base
= S3C64XX_GPJ(0),
1284 .ngpio
= S3C64XX_GPIO_J_NR
,
1288 .config
= &samsung_gpio_cfgs
[6],
1290 .base
= S3C64XX_GPO(0),
1291 .ngpio
= S3C64XX_GPIO_O_NR
,
1295 .config
= &samsung_gpio_cfgs
[6],
1297 .base
= S3C64XX_GPP(0),
1298 .ngpio
= S3C64XX_GPIO_P_NR
,
1302 .config
= &samsung_gpio_cfgs
[6],
1304 .base
= S3C64XX_GPQ(0),
1305 .ngpio
= S3C64XX_GPIO_Q_NR
,
1309 .base
= S3C64XX_GPN_BASE
,
1310 .irq_base
= IRQ_EINT(0),
1311 .config
= &samsung_gpio_cfgs
[5],
1313 .base
= S3C64XX_GPN(0),
1314 .ngpio
= S3C64XX_GPIO_N_NR
,
1316 .to_irq
= samsung_gpiolib_to_irq
,
1323 * S5P6440 GPIO bank summary:
1325 * Bank GPIOs Style SlpCon ExtInt Group
1329 * F 2 2Bit Yes 4 [1]
1331 * H 10 4Bit[2] Yes 6
1332 * I 16 2Bit Yes None
1333 * J 12 2Bit Yes None
1334 * N 16 2Bit No IRQ_EINT
1336 * R 15 4Bit[2] Yes 8
1339 static struct samsung_gpio_chip s5p6440_gpios_4bit
[] = {
1340 #ifdef CONFIG_CPU_S5P6440
1343 .base
= S5P6440_GPA(0),
1344 .ngpio
= S5P6440_GPIO_A_NR
,
1349 .base
= S5P6440_GPB(0),
1350 .ngpio
= S5P6440_GPIO_B_NR
,
1355 .base
= S5P6440_GPC(0),
1356 .ngpio
= S5P6440_GPIO_C_NR
,
1360 .base
= S5P64X0_GPG_BASE
,
1362 .base
= S5P6440_GPG(0),
1363 .ngpio
= S5P6440_GPIO_G_NR
,
1370 static struct samsung_gpio_chip s5p6440_gpios_4bit2
[] = {
1371 #ifdef CONFIG_CPU_S5P6440
1373 .base
= S5P64X0_GPH_BASE
+ 0x4,
1375 .base
= S5P6440_GPH(0),
1376 .ngpio
= S5P6440_GPIO_H_NR
,
1383 static struct samsung_gpio_chip s5p6440_gpios_rbank
[] = {
1384 #ifdef CONFIG_CPU_S5P6440
1386 .base
= S5P64X0_GPR_BASE
+ 0x4,
1387 .config
= &s5p64x0_gpio_cfg_rbank
,
1389 .base
= S5P6440_GPR(0),
1390 .ngpio
= S5P6440_GPIO_R_NR
,
1397 static struct samsung_gpio_chip s5p6440_gpios_2bit
[] = {
1398 #ifdef CONFIG_CPU_S5P6440
1400 .base
= S5P64X0_GPF_BASE
,
1401 .config
= &samsung_gpio_cfgs
[6],
1403 .base
= S5P6440_GPF(0),
1404 .ngpio
= S5P6440_GPIO_F_NR
,
1408 .base
= S5P64X0_GPI_BASE
,
1409 .config
= &samsung_gpio_cfgs
[4],
1411 .base
= S5P6440_GPI(0),
1412 .ngpio
= S5P6440_GPIO_I_NR
,
1416 .base
= S5P64X0_GPJ_BASE
,
1417 .config
= &samsung_gpio_cfgs
[4],
1419 .base
= S5P6440_GPJ(0),
1420 .ngpio
= S5P6440_GPIO_J_NR
,
1424 .base
= S5P64X0_GPN_BASE
,
1425 .config
= &samsung_gpio_cfgs
[5],
1427 .base
= S5P6440_GPN(0),
1428 .ngpio
= S5P6440_GPIO_N_NR
,
1432 .base
= S5P64X0_GPP_BASE
,
1433 .config
= &samsung_gpio_cfgs
[6],
1435 .base
= S5P6440_GPP(0),
1436 .ngpio
= S5P6440_GPIO_P_NR
,
1444 * S5P6450 GPIO bank summary:
1446 * Bank GPIOs Style SlpCon ExtInt Group
1452 * G 14 4Bit[2] Yes 5
1453 * H 10 4Bit[2] Yes 6
1454 * I 16 2Bit Yes None
1455 * J 12 2Bit Yes None
1457 * N 16 2Bit No IRQ_EINT
1459 * Q 14 2Bit Yes None
1460 * R 15 4Bit[2] Yes None
1463 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1464 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1467 static struct samsung_gpio_chip s5p6450_gpios_4bit
[] = {
1468 #ifdef CONFIG_CPU_S5P6450
1471 .base
= S5P6450_GPA(0),
1472 .ngpio
= S5P6450_GPIO_A_NR
,
1477 .base
= S5P6450_GPB(0),
1478 .ngpio
= S5P6450_GPIO_B_NR
,
1483 .base
= S5P6450_GPC(0),
1484 .ngpio
= S5P6450_GPIO_C_NR
,
1489 .base
= S5P6450_GPD(0),
1490 .ngpio
= S5P6450_GPIO_D_NR
,
1494 .base
= S5P6450_GPK_BASE
,
1496 .base
= S5P6450_GPK(0),
1497 .ngpio
= S5P6450_GPIO_K_NR
,
1504 static struct samsung_gpio_chip s5p6450_gpios_4bit2
[] = {
1505 #ifdef CONFIG_CPU_S5P6450
1507 .base
= S5P64X0_GPG_BASE
+ 0x4,
1509 .base
= S5P6450_GPG(0),
1510 .ngpio
= S5P6450_GPIO_G_NR
,
1514 .base
= S5P64X0_GPH_BASE
+ 0x4,
1516 .base
= S5P6450_GPH(0),
1517 .ngpio
= S5P6450_GPIO_H_NR
,
1524 static struct samsung_gpio_chip s5p6450_gpios_rbank
[] = {
1525 #ifdef CONFIG_CPU_S5P6450
1527 .base
= S5P64X0_GPR_BASE
+ 0x4,
1528 .config
= &s5p64x0_gpio_cfg_rbank
,
1530 .base
= S5P6450_GPR(0),
1531 .ngpio
= S5P6450_GPIO_R_NR
,
1538 static struct samsung_gpio_chip s5p6450_gpios_2bit
[] = {
1539 #ifdef CONFIG_CPU_S5P6450
1541 .base
= S5P64X0_GPF_BASE
,
1542 .config
= &samsung_gpio_cfgs
[6],
1544 .base
= S5P6450_GPF(0),
1545 .ngpio
= S5P6450_GPIO_F_NR
,
1549 .base
= S5P64X0_GPI_BASE
,
1550 .config
= &samsung_gpio_cfgs
[4],
1552 .base
= S5P6450_GPI(0),
1553 .ngpio
= S5P6450_GPIO_I_NR
,
1557 .base
= S5P64X0_GPJ_BASE
,
1558 .config
= &samsung_gpio_cfgs
[4],
1560 .base
= S5P6450_GPJ(0),
1561 .ngpio
= S5P6450_GPIO_J_NR
,
1565 .base
= S5P64X0_GPN_BASE
,
1566 .config
= &samsung_gpio_cfgs
[5],
1568 .base
= S5P6450_GPN(0),
1569 .ngpio
= S5P6450_GPIO_N_NR
,
1573 .base
= S5P64X0_GPP_BASE
,
1574 .config
= &samsung_gpio_cfgs
[6],
1576 .base
= S5P6450_GPP(0),
1577 .ngpio
= S5P6450_GPIO_P_NR
,
1581 .base
= S5P6450_GPQ_BASE
,
1582 .config
= &samsung_gpio_cfgs
[5],
1584 .base
= S5P6450_GPQ(0),
1585 .ngpio
= S5P6450_GPIO_Q_NR
,
1589 .base
= S5P6450_GPS_BASE
,
1590 .config
= &samsung_gpio_cfgs
[6],
1592 .base
= S5P6450_GPS(0),
1593 .ngpio
= S5P6450_GPIO_S_NR
,
1601 * S5PC100 GPIO bank summary:
1603 * Bank GPIOs Style INT Type
1604 * A0 8 4Bit GPIO_INT0
1605 * A1 5 4Bit GPIO_INT1
1606 * B 8 4Bit GPIO_INT2
1607 * C 5 4Bit GPIO_INT3
1608 * D 7 4Bit GPIO_INT4
1609 * E0 8 4Bit GPIO_INT5
1610 * E1 6 4Bit GPIO_INT6
1611 * F0 8 4Bit GPIO_INT7
1612 * F1 8 4Bit GPIO_INT8
1613 * F2 8 4Bit GPIO_INT9
1614 * F3 4 4Bit GPIO_INT10
1615 * G0 8 4Bit GPIO_INT11
1616 * G1 3 4Bit GPIO_INT12
1617 * G2 7 4Bit GPIO_INT13
1618 * G3 7 4Bit GPIO_INT14
1619 * H0 8 4Bit WKUP_INT
1620 * H1 8 4Bit WKUP_INT
1621 * H2 8 4Bit WKUP_INT
1622 * H3 8 4Bit WKUP_INT
1623 * I 8 4Bit GPIO_INT15
1624 * J0 8 4Bit GPIO_INT16
1625 * J1 5 4Bit GPIO_INT17
1626 * J2 8 4Bit GPIO_INT18
1627 * J3 8 4Bit GPIO_INT19
1628 * J4 4 4Bit GPIO_INT20
1639 static struct samsung_gpio_chip s5pc100_gpios_4bit
[] = {
1640 #ifdef CONFIG_CPU_S5PC100
1643 .base
= S5PC100_GPA0(0),
1644 .ngpio
= S5PC100_GPIO_A0_NR
,
1649 .base
= S5PC100_GPA1(0),
1650 .ngpio
= S5PC100_GPIO_A1_NR
,
1655 .base
= S5PC100_GPB(0),
1656 .ngpio
= S5PC100_GPIO_B_NR
,
1661 .base
= S5PC100_GPC(0),
1662 .ngpio
= S5PC100_GPIO_C_NR
,
1667 .base
= S5PC100_GPD(0),
1668 .ngpio
= S5PC100_GPIO_D_NR
,
1673 .base
= S5PC100_GPE0(0),
1674 .ngpio
= S5PC100_GPIO_E0_NR
,
1679 .base
= S5PC100_GPE1(0),
1680 .ngpio
= S5PC100_GPIO_E1_NR
,
1685 .base
= S5PC100_GPF0(0),
1686 .ngpio
= S5PC100_GPIO_F0_NR
,
1691 .base
= S5PC100_GPF1(0),
1692 .ngpio
= S5PC100_GPIO_F1_NR
,
1697 .base
= S5PC100_GPF2(0),
1698 .ngpio
= S5PC100_GPIO_F2_NR
,
1703 .base
= S5PC100_GPF3(0),
1704 .ngpio
= S5PC100_GPIO_F3_NR
,
1709 .base
= S5PC100_GPG0(0),
1710 .ngpio
= S5PC100_GPIO_G0_NR
,
1715 .base
= S5PC100_GPG1(0),
1716 .ngpio
= S5PC100_GPIO_G1_NR
,
1721 .base
= S5PC100_GPG2(0),
1722 .ngpio
= S5PC100_GPIO_G2_NR
,
1727 .base
= S5PC100_GPG3(0),
1728 .ngpio
= S5PC100_GPIO_G3_NR
,
1733 .base
= S5PC100_GPI(0),
1734 .ngpio
= S5PC100_GPIO_I_NR
,
1739 .base
= S5PC100_GPJ0(0),
1740 .ngpio
= S5PC100_GPIO_J0_NR
,
1745 .base
= S5PC100_GPJ1(0),
1746 .ngpio
= S5PC100_GPIO_J1_NR
,
1751 .base
= S5PC100_GPJ2(0),
1752 .ngpio
= S5PC100_GPIO_J2_NR
,
1757 .base
= S5PC100_GPJ3(0),
1758 .ngpio
= S5PC100_GPIO_J3_NR
,
1763 .base
= S5PC100_GPJ4(0),
1764 .ngpio
= S5PC100_GPIO_J4_NR
,
1769 .base
= S5PC100_GPK0(0),
1770 .ngpio
= S5PC100_GPIO_K0_NR
,
1775 .base
= S5PC100_GPK1(0),
1776 .ngpio
= S5PC100_GPIO_K1_NR
,
1781 .base
= S5PC100_GPK2(0),
1782 .ngpio
= S5PC100_GPIO_K2_NR
,
1787 .base
= S5PC100_GPK3(0),
1788 .ngpio
= S5PC100_GPIO_K3_NR
,
1793 .base
= S5PC100_GPL0(0),
1794 .ngpio
= S5PC100_GPIO_L0_NR
,
1799 .base
= S5PC100_GPL1(0),
1800 .ngpio
= S5PC100_GPIO_L1_NR
,
1805 .base
= S5PC100_GPL2(0),
1806 .ngpio
= S5PC100_GPIO_L2_NR
,
1811 .base
= S5PC100_GPL3(0),
1812 .ngpio
= S5PC100_GPIO_L3_NR
,
1817 .base
= S5PC100_GPL4(0),
1818 .ngpio
= S5PC100_GPIO_L4_NR
,
1822 .base
= (S5P_VA_GPIO
+ 0xC00),
1823 .irq_base
= IRQ_EINT(0),
1825 .base
= S5PC100_GPH0(0),
1826 .ngpio
= S5PC100_GPIO_H0_NR
,
1828 .to_irq
= samsung_gpiolib_to_irq
,
1831 .base
= (S5P_VA_GPIO
+ 0xC20),
1832 .irq_base
= IRQ_EINT(8),
1834 .base
= S5PC100_GPH1(0),
1835 .ngpio
= S5PC100_GPIO_H1_NR
,
1837 .to_irq
= samsung_gpiolib_to_irq
,
1840 .base
= (S5P_VA_GPIO
+ 0xC40),
1841 .irq_base
= IRQ_EINT(16),
1843 .base
= S5PC100_GPH2(0),
1844 .ngpio
= S5PC100_GPIO_H2_NR
,
1846 .to_irq
= samsung_gpiolib_to_irq
,
1849 .base
= (S5P_VA_GPIO
+ 0xC60),
1850 .irq_base
= IRQ_EINT(24),
1852 .base
= S5PC100_GPH3(0),
1853 .ngpio
= S5PC100_GPIO_H3_NR
,
1855 .to_irq
= samsung_gpiolib_to_irq
,
1862 * Followings are the gpio banks in S5PV210/S5PC110
1864 * The 'config' member when left to NULL, is initialized to the default
1865 * structure samsung_gpio_cfgs[4] in the init function below.
1867 * The 'base' member is also initialized in the init function below.
1868 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1869 * uses the above macro and depends on the banks being listed in order here.
1872 static struct samsung_gpio_chip s5pv210_gpios_4bit
[] = {
1873 #ifdef CONFIG_CPU_S5PV210
1876 .base
= S5PV210_GPA0(0),
1877 .ngpio
= S5PV210_GPIO_A0_NR
,
1882 .base
= S5PV210_GPA1(0),
1883 .ngpio
= S5PV210_GPIO_A1_NR
,
1888 .base
= S5PV210_GPB(0),
1889 .ngpio
= S5PV210_GPIO_B_NR
,
1894 .base
= S5PV210_GPC0(0),
1895 .ngpio
= S5PV210_GPIO_C0_NR
,
1900 .base
= S5PV210_GPC1(0),
1901 .ngpio
= S5PV210_GPIO_C1_NR
,
1906 .base
= S5PV210_GPD0(0),
1907 .ngpio
= S5PV210_GPIO_D0_NR
,
1912 .base
= S5PV210_GPD1(0),
1913 .ngpio
= S5PV210_GPIO_D1_NR
,
1918 .base
= S5PV210_GPE0(0),
1919 .ngpio
= S5PV210_GPIO_E0_NR
,
1924 .base
= S5PV210_GPE1(0),
1925 .ngpio
= S5PV210_GPIO_E1_NR
,
1930 .base
= S5PV210_GPF0(0),
1931 .ngpio
= S5PV210_GPIO_F0_NR
,
1936 .base
= S5PV210_GPF1(0),
1937 .ngpio
= S5PV210_GPIO_F1_NR
,
1942 .base
= S5PV210_GPF2(0),
1943 .ngpio
= S5PV210_GPIO_F2_NR
,
1948 .base
= S5PV210_GPF3(0),
1949 .ngpio
= S5PV210_GPIO_F3_NR
,
1954 .base
= S5PV210_GPG0(0),
1955 .ngpio
= S5PV210_GPIO_G0_NR
,
1960 .base
= S5PV210_GPG1(0),
1961 .ngpio
= S5PV210_GPIO_G1_NR
,
1966 .base
= S5PV210_GPG2(0),
1967 .ngpio
= S5PV210_GPIO_G2_NR
,
1972 .base
= S5PV210_GPG3(0),
1973 .ngpio
= S5PV210_GPIO_G3_NR
,
1978 .base
= S5PV210_GPI(0),
1979 .ngpio
= S5PV210_GPIO_I_NR
,
1984 .base
= S5PV210_GPJ0(0),
1985 .ngpio
= S5PV210_GPIO_J0_NR
,
1990 .base
= S5PV210_GPJ1(0),
1991 .ngpio
= S5PV210_GPIO_J1_NR
,
1996 .base
= S5PV210_GPJ2(0),
1997 .ngpio
= S5PV210_GPIO_J2_NR
,
2002 .base
= S5PV210_GPJ3(0),
2003 .ngpio
= S5PV210_GPIO_J3_NR
,
2008 .base
= S5PV210_GPJ4(0),
2009 .ngpio
= S5PV210_GPIO_J4_NR
,
2014 .base
= S5PV210_MP01(0),
2015 .ngpio
= S5PV210_GPIO_MP01_NR
,
2020 .base
= S5PV210_MP02(0),
2021 .ngpio
= S5PV210_GPIO_MP02_NR
,
2026 .base
= S5PV210_MP03(0),
2027 .ngpio
= S5PV210_GPIO_MP03_NR
,
2032 .base
= S5PV210_MP04(0),
2033 .ngpio
= S5PV210_GPIO_MP04_NR
,
2038 .base
= S5PV210_MP05(0),
2039 .ngpio
= S5PV210_GPIO_MP05_NR
,
2043 .base
= (S5P_VA_GPIO
+ 0xC00),
2044 .irq_base
= IRQ_EINT(0),
2046 .base
= S5PV210_GPH0(0),
2047 .ngpio
= S5PV210_GPIO_H0_NR
,
2049 .to_irq
= samsung_gpiolib_to_irq
,
2052 .base
= (S5P_VA_GPIO
+ 0xC20),
2053 .irq_base
= IRQ_EINT(8),
2055 .base
= S5PV210_GPH1(0),
2056 .ngpio
= S5PV210_GPIO_H1_NR
,
2058 .to_irq
= samsung_gpiolib_to_irq
,
2061 .base
= (S5P_VA_GPIO
+ 0xC40),
2062 .irq_base
= IRQ_EINT(16),
2064 .base
= S5PV210_GPH2(0),
2065 .ngpio
= S5PV210_GPIO_H2_NR
,
2067 .to_irq
= samsung_gpiolib_to_irq
,
2070 .base
= (S5P_VA_GPIO
+ 0xC60),
2071 .irq_base
= IRQ_EINT(24),
2073 .base
= S5PV210_GPH3(0),
2074 .ngpio
= S5PV210_GPIO_H3_NR
,
2076 .to_irq
= samsung_gpiolib_to_irq
,
2083 * Followings are the gpio banks in EXYNOS4210
2085 * The 'config' member when left to NULL, is initialized to the default
2086 * structure samsung_gpio_cfgs[4] in the init function below.
2088 * The 'base' member is also initialized in the init function below.
2089 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2090 * uses the above macro and depends on the banks being listed in order here.
2093 static struct samsung_gpio_chip exynos4_gpios_1
[] = {
2094 #ifdef CONFIG_ARCH_EXYNOS4
2097 .base
= EXYNOS4_GPA0(0),
2098 .ngpio
= EXYNOS4_GPIO_A0_NR
,
2103 .base
= EXYNOS4_GPA1(0),
2104 .ngpio
= EXYNOS4_GPIO_A1_NR
,
2109 .base
= EXYNOS4_GPB(0),
2110 .ngpio
= EXYNOS4_GPIO_B_NR
,
2115 .base
= EXYNOS4_GPC0(0),
2116 .ngpio
= EXYNOS4_GPIO_C0_NR
,
2121 .base
= EXYNOS4_GPC1(0),
2122 .ngpio
= EXYNOS4_GPIO_C1_NR
,
2127 .base
= EXYNOS4_GPD0(0),
2128 .ngpio
= EXYNOS4_GPIO_D0_NR
,
2133 .base
= EXYNOS4_GPD1(0),
2134 .ngpio
= EXYNOS4_GPIO_D1_NR
,
2139 .base
= EXYNOS4_GPE0(0),
2140 .ngpio
= EXYNOS4_GPIO_E0_NR
,
2145 .base
= EXYNOS4_GPE1(0),
2146 .ngpio
= EXYNOS4_GPIO_E1_NR
,
2151 .base
= EXYNOS4_GPE2(0),
2152 .ngpio
= EXYNOS4_GPIO_E2_NR
,
2157 .base
= EXYNOS4_GPE3(0),
2158 .ngpio
= EXYNOS4_GPIO_E3_NR
,
2163 .base
= EXYNOS4_GPE4(0),
2164 .ngpio
= EXYNOS4_GPIO_E4_NR
,
2169 .base
= EXYNOS4_GPF0(0),
2170 .ngpio
= EXYNOS4_GPIO_F0_NR
,
2175 .base
= EXYNOS4_GPF1(0),
2176 .ngpio
= EXYNOS4_GPIO_F1_NR
,
2181 .base
= EXYNOS4_GPF2(0),
2182 .ngpio
= EXYNOS4_GPIO_F2_NR
,
2187 .base
= EXYNOS4_GPF3(0),
2188 .ngpio
= EXYNOS4_GPIO_F3_NR
,
2195 static struct samsung_gpio_chip exynos4_gpios_2
[] = {
2196 #ifdef CONFIG_ARCH_EXYNOS4
2199 .base
= EXYNOS4_GPJ0(0),
2200 .ngpio
= EXYNOS4_GPIO_J0_NR
,
2205 .base
= EXYNOS4_GPJ1(0),
2206 .ngpio
= EXYNOS4_GPIO_J1_NR
,
2211 .base
= EXYNOS4_GPK0(0),
2212 .ngpio
= EXYNOS4_GPIO_K0_NR
,
2217 .base
= EXYNOS4_GPK1(0),
2218 .ngpio
= EXYNOS4_GPIO_K1_NR
,
2223 .base
= EXYNOS4_GPK2(0),
2224 .ngpio
= EXYNOS4_GPIO_K2_NR
,
2229 .base
= EXYNOS4_GPK3(0),
2230 .ngpio
= EXYNOS4_GPIO_K3_NR
,
2235 .base
= EXYNOS4_GPL0(0),
2236 .ngpio
= EXYNOS4_GPIO_L0_NR
,
2241 .base
= EXYNOS4_GPL1(0),
2242 .ngpio
= EXYNOS4_GPIO_L1_NR
,
2247 .base
= EXYNOS4_GPL2(0),
2248 .ngpio
= EXYNOS4_GPIO_L2_NR
,
2252 .config
= &samsung_gpio_cfgs
[4],
2254 .base
= EXYNOS4_GPY0(0),
2255 .ngpio
= EXYNOS4_GPIO_Y0_NR
,
2259 .config
= &samsung_gpio_cfgs
[4],
2261 .base
= EXYNOS4_GPY1(0),
2262 .ngpio
= EXYNOS4_GPIO_Y1_NR
,
2266 .config
= &samsung_gpio_cfgs
[4],
2268 .base
= EXYNOS4_GPY2(0),
2269 .ngpio
= EXYNOS4_GPIO_Y2_NR
,
2273 .config
= &samsung_gpio_cfgs
[4],
2275 .base
= EXYNOS4_GPY3(0),
2276 .ngpio
= EXYNOS4_GPIO_Y3_NR
,
2280 .config
= &samsung_gpio_cfgs
[4],
2282 .base
= EXYNOS4_GPY4(0),
2283 .ngpio
= EXYNOS4_GPIO_Y4_NR
,
2287 .config
= &samsung_gpio_cfgs
[4],
2289 .base
= EXYNOS4_GPY5(0),
2290 .ngpio
= EXYNOS4_GPIO_Y5_NR
,
2294 .config
= &samsung_gpio_cfgs
[4],
2296 .base
= EXYNOS4_GPY6(0),
2297 .ngpio
= EXYNOS4_GPIO_Y6_NR
,
2301 .base
= (S5P_VA_GPIO2
+ 0xC00),
2302 .config
= &samsung_gpio_cfgs
[4],
2303 .irq_base
= IRQ_EINT(0),
2305 .base
= EXYNOS4_GPX0(0),
2306 .ngpio
= EXYNOS4_GPIO_X0_NR
,
2308 .to_irq
= samsung_gpiolib_to_irq
,
2311 .base
= (S5P_VA_GPIO2
+ 0xC20),
2312 .config
= &samsung_gpio_cfgs
[4],
2313 .irq_base
= IRQ_EINT(8),
2315 .base
= EXYNOS4_GPX1(0),
2316 .ngpio
= EXYNOS4_GPIO_X1_NR
,
2318 .to_irq
= samsung_gpiolib_to_irq
,
2321 .base
= (S5P_VA_GPIO2
+ 0xC40),
2322 .config
= &samsung_gpio_cfgs
[4],
2323 .irq_base
= IRQ_EINT(16),
2325 .base
= EXYNOS4_GPX2(0),
2326 .ngpio
= EXYNOS4_GPIO_X2_NR
,
2328 .to_irq
= samsung_gpiolib_to_irq
,
2331 .base
= (S5P_VA_GPIO2
+ 0xC60),
2332 .config
= &samsung_gpio_cfgs
[4],
2333 .irq_base
= IRQ_EINT(24),
2335 .base
= EXYNOS4_GPX3(0),
2336 .ngpio
= EXYNOS4_GPIO_X3_NR
,
2338 .to_irq
= samsung_gpiolib_to_irq
,
2344 static struct samsung_gpio_chip exynos4_gpios_3
[] = {
2345 #ifdef CONFIG_ARCH_EXYNOS4
2348 .base
= EXYNOS4_GPZ(0),
2349 .ngpio
= EXYNOS4_GPIO_Z_NR
,
2356 /* TODO: cleanup soc_is_* */
2357 static __init
int samsung_gpiolib_init(void)
2359 struct samsung_gpio_chip
*chip
;
2363 samsung_gpiolib_set_cfg(samsung_gpio_cfgs
, ARRAY_SIZE(samsung_gpio_cfgs
));
2365 if (soc_is_s3c24xx()) {
2366 s3c24xx_gpiolib_add_chips(s3c24xx_gpios
,
2367 ARRAY_SIZE(s3c24xx_gpios
), S3C24XX_VA_GPIO
);
2368 } else if (soc_is_s3c64xx()) {
2369 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit
,
2370 ARRAY_SIZE(s3c64xx_gpios_2bit
),
2371 S3C64XX_VA_GPIO
+ 0xE0, 0x20);
2372 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit
,
2373 ARRAY_SIZE(s3c64xx_gpios_4bit
),
2375 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2
,
2376 ARRAY_SIZE(s3c64xx_gpios_4bit2
));
2377 } else if (soc_is_s5p6440()) {
2378 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit
,
2379 ARRAY_SIZE(s5p6440_gpios_2bit
), NULL
, 0x0);
2380 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit
,
2381 ARRAY_SIZE(s5p6440_gpios_4bit
), S5P_VA_GPIO
);
2382 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2
,
2383 ARRAY_SIZE(s5p6440_gpios_4bit2
));
2384 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank
,
2385 ARRAY_SIZE(s5p6440_gpios_rbank
));
2386 } else if (soc_is_s5p6450()) {
2387 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit
,
2388 ARRAY_SIZE(s5p6450_gpios_2bit
), NULL
, 0x0);
2389 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit
,
2390 ARRAY_SIZE(s5p6450_gpios_4bit
), S5P_VA_GPIO
);
2391 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2
,
2392 ARRAY_SIZE(s5p6450_gpios_4bit2
));
2393 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank
,
2394 ARRAY_SIZE(s5p6450_gpios_rbank
));
2395 } else if (soc_is_s5pc100()) {
2397 chip
= s5pc100_gpios_4bit
;
2398 nr_chips
= ARRAY_SIZE(s5pc100_gpios_4bit
);
2400 for (i
= 0; i
< nr_chips
; i
++, chip
++) {
2401 if (!chip
->config
) {
2402 chip
->config
= &samsung_gpio_cfgs
[4];
2403 chip
->group
= group
++;
2406 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit
, nr_chips
, S5P_VA_GPIO
);
2407 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
2408 s5p_register_gpioint_bank(IRQ_GPIOINT
, 0, S5P_GPIOINT_GROUP_MAXNR
);
2410 } else if (soc_is_s5pv210()) {
2412 chip
= s5pv210_gpios_4bit
;
2413 nr_chips
= ARRAY_SIZE(s5pv210_gpios_4bit
);
2415 for (i
= 0; i
< nr_chips
; i
++, chip
++) {
2416 if (!chip
->config
) {
2417 chip
->config
= &samsung_gpio_cfgs
[4];
2418 chip
->group
= group
++;
2421 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit
, nr_chips
, S5P_VA_GPIO
);
2422 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
2423 s5p_register_gpioint_bank(IRQ_GPIOINT
, 0, S5P_GPIOINT_GROUP_MAXNR
);
2425 } else if (soc_is_exynos4210()) {
2429 chip
= exynos4_gpios_1
;
2430 nr_chips
= ARRAY_SIZE(exynos4_gpios_1
);
2432 for (i
= 0; i
< nr_chips
; i
++, chip
++) {
2433 if (!chip
->config
) {
2434 chip
->config
= &exynos4_gpio_cfg
;
2435 chip
->group
= group
++;
2438 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1
, nr_chips
, S5P_VA_GPIO1
);
2441 chip
= exynos4_gpios_2
;
2442 nr_chips
= ARRAY_SIZE(exynos4_gpios_2
);
2444 for (i
= 0; i
< nr_chips
; i
++, chip
++) {
2445 if (!chip
->config
) {
2446 chip
->config
= &exynos4_gpio_cfg
;
2447 chip
->group
= group
++;
2450 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2
, nr_chips
, S5P_VA_GPIO2
);
2453 chip
= exynos4_gpios_3
;
2454 nr_chips
= ARRAY_SIZE(exynos4_gpios_3
);
2456 for (i
= 0; i
< nr_chips
; i
++, chip
++) {
2457 if (!chip
->config
) {
2458 chip
->config
= &exynos4_gpio_cfg
;
2459 chip
->group
= group
++;
2462 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3
, nr_chips
, S5P_VA_GPIO3
);
2464 #if defined(CONFIG_SOC_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2465 s5p_register_gpioint_bank(IRQ_GPIO_XA
, 0, IRQ_GPIO1_NR_GROUPS
);
2466 s5p_register_gpioint_bank(IRQ_GPIO_XB
, IRQ_GPIO1_NR_GROUPS
, IRQ_GPIO2_NR_GROUPS
);
2472 core_initcall(samsung_gpiolib_init
);
2474 int s3c_gpio_cfgpin(unsigned int pin
, unsigned int config
)
2476 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2477 unsigned long flags
;
2484 offset
= pin
- chip
->chip
.base
;
2486 samsung_gpio_lock(chip
, flags
);
2487 ret
= samsung_gpio_do_setcfg(chip
, offset
, config
);
2488 samsung_gpio_unlock(chip
, flags
);
2492 EXPORT_SYMBOL(s3c_gpio_cfgpin
);
2494 int s3c_gpio_cfgpin_range(unsigned int start
, unsigned int nr
,
2499 for (; nr
> 0; nr
--, start
++) {
2500 ret
= s3c_gpio_cfgpin(start
, cfg
);
2507 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range
);
2509 int s3c_gpio_cfgall_range(unsigned int start
, unsigned int nr
,
2510 unsigned int cfg
, samsung_gpio_pull_t pull
)
2514 for (; nr
> 0; nr
--, start
++) {
2515 s3c_gpio_setpull(start
, pull
);
2516 ret
= s3c_gpio_cfgpin(start
, cfg
);
2523 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range
);
2525 unsigned s3c_gpio_getcfg(unsigned int pin
)
2527 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2528 unsigned long flags
;
2533 offset
= pin
- chip
->chip
.base
;
2535 samsung_gpio_lock(chip
, flags
);
2536 ret
= samsung_gpio_do_getcfg(chip
, offset
);
2537 samsung_gpio_unlock(chip
, flags
);
2542 EXPORT_SYMBOL(s3c_gpio_getcfg
);
2544 int s3c_gpio_setpull(unsigned int pin
, samsung_gpio_pull_t pull
)
2546 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2547 unsigned long flags
;
2553 offset
= pin
- chip
->chip
.base
;
2555 samsung_gpio_lock(chip
, flags
);
2556 ret
= samsung_gpio_do_setpull(chip
, offset
, pull
);
2557 samsung_gpio_unlock(chip
, flags
);
2561 EXPORT_SYMBOL(s3c_gpio_setpull
);
2563 samsung_gpio_pull_t
s3c_gpio_getpull(unsigned int pin
)
2565 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2566 unsigned long flags
;
2571 offset
= pin
- chip
->chip
.base
;
2573 samsung_gpio_lock(chip
, flags
);
2574 pup
= samsung_gpio_do_getpull(chip
, offset
);
2575 samsung_gpio_unlock(chip
, flags
);
2578 return (__force samsung_gpio_pull_t
)pup
;
2580 EXPORT_SYMBOL(s3c_gpio_getpull
);
2582 /* gpiolib wrappers until these are totally eliminated */
2584 void s3c2410_gpio_pullup(unsigned int pin
, unsigned int to
)
2588 WARN_ON(to
); /* should be none of these left */
2591 /* if pull is enabled, try first with up, and if that
2592 * fails, try using down */
2594 ret
= s3c_gpio_setpull(pin
, S3C_GPIO_PULL_UP
);
2596 s3c_gpio_setpull(pin
, S3C_GPIO_PULL_DOWN
);
2598 s3c_gpio_setpull(pin
, S3C_GPIO_PULL_NONE
);
2601 EXPORT_SYMBOL(s3c2410_gpio_pullup
);
2603 void s3c2410_gpio_setpin(unsigned int pin
, unsigned int to
)
2605 /* do this via gpiolib until all users removed */
2607 gpio_request(pin
, "temporary");
2608 gpio_set_value(pin
, to
);
2611 EXPORT_SYMBOL(s3c2410_gpio_setpin
);
2613 unsigned int s3c2410_gpio_getpin(unsigned int pin
)
2615 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2616 unsigned long offs
= pin
- chip
->chip
.base
;
2618 return __raw_readl(chip
->base
+ 0x04) & (1 << offs
);
2620 EXPORT_SYMBOL(s3c2410_gpio_getpin
);
2622 #ifdef CONFIG_S5P_GPIO_DRVSTR
2623 s5p_gpio_drvstr_t
s5p_gpio_get_drvstr(unsigned int pin
)
2625 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2634 off
= pin
- chip
->chip
.base
;
2636 reg
= chip
->base
+ 0x0C;
2638 drvstr
= __raw_readl(reg
);
2639 drvstr
= drvstr
>> shift
;
2642 return (__force s5p_gpio_drvstr_t
)drvstr
;
2644 EXPORT_SYMBOL(s5p_gpio_get_drvstr
);
2646 int s5p_gpio_set_drvstr(unsigned int pin
, s5p_gpio_drvstr_t drvstr
)
2648 struct samsung_gpio_chip
*chip
= samsung_gpiolib_getchip(pin
);
2657 off
= pin
- chip
->chip
.base
;
2659 reg
= chip
->base
+ 0x0C;
2661 tmp
= __raw_readl(reg
);
2662 tmp
&= ~(0x3 << shift
);
2663 tmp
|= drvstr
<< shift
;
2665 __raw_writel(tmp
, reg
);
2669 EXPORT_SYMBOL(s5p_gpio_set_drvstr
);
2670 #endif /* CONFIG_S5P_GPIO_DRVSTR */
2672 #ifdef CONFIG_PLAT_S3C24XX
2673 unsigned int s3c2410_modify_misccr(unsigned int clear
, unsigned int change
)
2675 unsigned long flags
;
2676 unsigned long misccr
;
2678 local_irq_save(flags
);
2679 misccr
= __raw_readl(S3C24XX_MISCCR
);
2682 __raw_writel(misccr
, S3C24XX_MISCCR
);
2683 local_irq_restore(flags
);
2687 EXPORT_SYMBOL(s3c2410_modify_misccr
);