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ASoC: Intel: Skylake: Removed unused skl_get_format()
[linux-2.6/btrfs-unstable.git] / sound / soc / intel / skylake / skl-pcm.c
blob10fa10df4e5716db7e780d003797f55b3988bca6
1 /*
2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
19 *
20 */
21
22 #include <linux/pci.h>
23 #include <linux/pm_runtime.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include "skl.h"
27 #include "skl-topology.h"
28 #include "skl-sst-dsp.h"
29 #include "skl-sst-ipc.h"
30
31 #define HDA_MONO 1
32 #define HDA_STEREO 2
33 #define HDA_QUAD 4
34
35 static struct snd_pcm_hardware azx_pcm_hw = {
36 .info = (SNDRV_PCM_INFO_MMAP |
37 SNDRV_PCM_INFO_INTERLEAVED |
38 SNDRV_PCM_INFO_BLOCK_TRANSFER |
39 SNDRV_PCM_INFO_MMAP_VALID |
40 SNDRV_PCM_INFO_PAUSE |
41 SNDRV_PCM_INFO_RESUME |
42 SNDRV_PCM_INFO_SYNC_START |
43 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
44 SNDRV_PCM_INFO_HAS_LINK_ATIME |
45 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
46 .formats = SNDRV_PCM_FMTBIT_S16_LE |
47 SNDRV_PCM_FMTBIT_S32_LE |
48 SNDRV_PCM_FMTBIT_S24_LE,
49 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
50 SNDRV_PCM_RATE_8000,
51 .rate_min = 8000,
52 .rate_max = 48000,
53 .channels_min = 1,
54 .channels_max = 8,
55 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
56 .period_bytes_min = 128,
57 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
58 .periods_min = 2,
59 .periods_max = AZX_MAX_FRAG,
60 .fifo_size = 0,
61 };
62
63 static inline
64 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
65 {
66 return substream->runtime->private_data;
67 }
68
69 static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
70 {
71 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
72 struct hdac_stream *hstream = hdac_stream(stream);
73 struct hdac_bus *bus = hstream->bus;
74
75 return hbus_to_ebus(bus);
76 }
77
78 static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
79 struct snd_pcm_substream *substream,
80 size_t size)
81 {
82 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
83
84 hdac_stream(stream)->bufsize = 0;
85 hdac_stream(stream)->period_bytes = 0;
86 hdac_stream(stream)->format_val = 0;
87
88 return snd_pcm_lib_malloc_pages(substream, size);
89 }
90
91 static int skl_substream_free_pages(struct hdac_bus *bus,
92 struct snd_pcm_substream *substream)
93 {
94 return snd_pcm_lib_free_pages(substream);
95 }
96
97 static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
98 struct snd_pcm_runtime *runtime)
99 {
100 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
101
102 /* avoid wrap-around with wall-clock */
103 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
104 20, 178000000);
105 }
106
107 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
108 {
109 if ((ebus_to_hbus(ebus))->ppcap)
110 return HDAC_EXT_STREAM_TYPE_HOST;
111 else
112 return HDAC_EXT_STREAM_TYPE_COUPLED;
113 }
114
115 /*
116 * check if the stream opened is marked as ignore_suspend by machine, if so
117 * then enable suspend_active refcount
118 *
119 * The count supend_active does not need lock as it is used in open/close
120 * and suspend context
121 */
122 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
123 struct snd_soc_dai *dai, bool enable)
124 {
125 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
126 struct snd_soc_dapm_widget *w;
127 struct skl *skl = ebus_to_skl(ebus);
128
129 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
130 w = dai->playback_widget;
131 else
132 w = dai->capture_widget;
133
134 if (w->ignore_suspend && enable)
135 skl->supend_active++;
136 else if (w->ignore_suspend && !enable)
137 skl->supend_active--;
138 }
139
140 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
141 {
142 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
143 struct hdac_bus *bus = ebus_to_hbus(ebus);
144 unsigned int format_val;
145 struct hdac_stream *hstream;
146 struct hdac_ext_stream *stream;
147 int err;
148
149 hstream = snd_hdac_get_stream(bus, params->stream,
150 params->host_dma_id + 1);
151 if (!hstream)
152 return -EINVAL;
153
154 stream = stream_to_hdac_ext_stream(hstream);
155 snd_hdac_ext_stream_decouple(ebus, stream, true);
156
157 format_val = snd_hdac_calc_stream_format(params->s_freq,
158 params->ch, params->format, 32, 0);
159
160 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
161 format_val, params->s_freq, params->ch, params->format);
162
163 snd_hdac_stream_reset(hdac_stream(stream));
164 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
165 if (err < 0)
166 return err;
167
168 err = snd_hdac_stream_setup(hdac_stream(stream));
169 if (err < 0)
170 return err;
171
172 hdac_stream(stream)->prepared = 1;
173
174 return 0;
175 }
176
177 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
178 {
179 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
180 struct hdac_bus *bus = ebus_to_hbus(ebus);
181 unsigned int format_val;
182 struct hdac_stream *hstream;
183 struct hdac_ext_stream *stream;
184 struct hdac_ext_link *link;
185
186 hstream = snd_hdac_get_stream(bus, params->stream,
187 params->link_dma_id + 1);
188 if (!hstream)
189 return -EINVAL;
190
191 stream = stream_to_hdac_ext_stream(hstream);
192 snd_hdac_ext_stream_decouple(ebus, stream, true);
193 format_val = snd_hdac_calc_stream_format(params->s_freq,
194 params->ch, params->format, 24, 0);
195
196 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
197 format_val, params->s_freq, params->ch, params->format);
198
199 snd_hdac_ext_link_stream_reset(stream);
200
201 snd_hdac_ext_link_stream_setup(stream, format_val);
202
203 list_for_each_entry(link, &ebus->hlink_list, list) {
204 if (link->index == params->link_index)
205 snd_hdac_ext_link_set_stream_id(link,
206 hstream->stream_tag);
207 }
208
209 stream->link_prepared = 1;
210
211 return 0;
212 }
213
214 static int skl_pcm_open(struct snd_pcm_substream *substream,
215 struct snd_soc_dai *dai)
216 {
217 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
218 struct hdac_ext_stream *stream;
219 struct snd_pcm_runtime *runtime = substream->runtime;
220 struct skl_dma_params *dma_params;
221 struct skl *skl = get_skl_ctx(dai->dev);
222 struct skl_module_cfg *mconfig;
223
224 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
225
226 stream = snd_hdac_ext_stream_assign(ebus, substream,
227 skl_get_host_stream_type(ebus));
228 if (stream == NULL)
229 return -EBUSY;
230
231 skl_set_pcm_constrains(ebus, runtime);
232
233 /*
234 * disable WALLCLOCK timestamps for capture streams
235 * until we figure out how to handle digital inputs
236 */
237 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
238 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
239 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
240 }
241
242 runtime->private_data = stream;
243
244 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
245 if (!dma_params)
246 return -ENOMEM;
247
248 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
249 snd_soc_dai_set_dma_data(dai, substream, dma_params);
250
251 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
252 dma_params->stream_tag);
253 skl_set_suspend_active(substream, dai, true);
254 snd_pcm_set_sync(substream);
255
256 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
257 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
258
259 return 0;
260 }
261
262 static int skl_be_prepare(struct snd_pcm_substream *substream,
263 struct snd_soc_dai *dai)
264 {
265 struct skl *skl = get_skl_ctx(dai->dev);
266 struct skl_sst *ctx = skl->skl_sst;
267 struct skl_module_cfg *mconfig;
268
269 if (dai->playback_widget->power || dai->capture_widget->power)
270 return 0;
271
272 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
273 if (mconfig == NULL)
274 return -EINVAL;
275
276 return skl_dsp_set_dma_control(ctx, mconfig);
277 }
278
279 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
280 struct snd_soc_dai *dai)
281 {
282 struct skl *skl = get_skl_ctx(dai->dev);
283 struct skl_module_cfg *mconfig;
284
285 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
286
287 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
288
289 /* In case of XRUN recovery, reset the FW pipe to clean state */
290 if (mconfig && (substream->runtime->status->state ==
291 SNDRV_PCM_STATE_XRUN))
292 skl_reset_pipe(skl->skl_sst, mconfig->pipe);
293
294 return 0;
295 }
296
297 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
298 struct snd_pcm_hw_params *params,
299 struct snd_soc_dai *dai)
300 {
301 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
302 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
303 struct snd_pcm_runtime *runtime = substream->runtime;
304 struct skl_pipe_params p_params = {0};
305 struct skl_module_cfg *m_cfg;
306 int ret, dma_id;
307
308 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
309 ret = skl_substream_alloc_pages(ebus, substream,
310 params_buffer_bytes(params));
311 if (ret < 0)
312 return ret;
313
314 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
315 runtime->rate, runtime->channels, runtime->format);
316
317 dma_id = hdac_stream(stream)->stream_tag - 1;
318 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
319
320 p_params.s_fmt = snd_pcm_format_width(params_format(params));
321 p_params.ch = params_channels(params);
322 p_params.s_freq = params_rate(params);
323 p_params.host_dma_id = dma_id;
324 p_params.stream = substream->stream;
325 p_params.format = params_format(params);
326
327 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
328 if (m_cfg)
329 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
330
331 return 0;
332 }
333
334 static void skl_pcm_close(struct snd_pcm_substream *substream,
335 struct snd_soc_dai *dai)
336 {
337 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
338 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
339 struct skl_dma_params *dma_params = NULL;
340 struct skl *skl = ebus_to_skl(ebus);
341 struct skl_module_cfg *mconfig;
342
343 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
344
345 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
346
347 dma_params = snd_soc_dai_get_dma_data(dai, substream);
348 /*
349 * now we should set this to NULL as we are freeing by the
350 * dma_params
351 */
352 snd_soc_dai_set_dma_data(dai, substream, NULL);
353 skl_set_suspend_active(substream, dai, false);
354
355 /*
356 * check if close is for "Reference Pin" and set back the
357 * CGCTL.MISCBDCGE if disabled by driver
358 */
359 if (!strncmp(dai->name, "Reference Pin", 13) &&
360 skl->skl_sst->miscbdcg_disabled) {
361 skl->skl_sst->enable_miscbdcge(dai->dev, true);
362 skl->skl_sst->miscbdcg_disabled = false;
363 }
364
365 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
366 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
367
368 kfree(dma_params);
369 }
370
371 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
372 struct snd_soc_dai *dai)
373 {
374 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
375 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
376
377 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
378
379 snd_hdac_stream_cleanup(hdac_stream(stream));
380 hdac_stream(stream)->prepared = 0;
381
382 return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
383 }
384
385 static int skl_be_hw_params(struct snd_pcm_substream *substream,
386 struct snd_pcm_hw_params *params,
387 struct snd_soc_dai *dai)
388 {
389 struct skl_pipe_params p_params = {0};
390
391 p_params.s_fmt = snd_pcm_format_width(params_format(params));
392 p_params.ch = params_channels(params);
393 p_params.s_freq = params_rate(params);
394 p_params.stream = substream->stream;
395
396 return skl_tplg_be_update_params(dai, &p_params);
397 }
398
399 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
400 int cmd)
401 {
402 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
403 struct hdac_bus *bus = ebus_to_hbus(ebus);
404 struct hdac_ext_stream *stream;
405 int start;
406 unsigned long cookie;
407 struct hdac_stream *hstr;
408
409 stream = get_hdac_ext_stream(substream);
410 hstr = hdac_stream(stream);
411
412 if (!hstr->prepared)
413 return -EPIPE;
414
415 switch (cmd) {
416 case SNDRV_PCM_TRIGGER_START:
417 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
418 case SNDRV_PCM_TRIGGER_RESUME:
419 start = 1;
420 break;
421
422 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
423 case SNDRV_PCM_TRIGGER_SUSPEND:
424 case SNDRV_PCM_TRIGGER_STOP:
425 start = 0;
426 break;
427
428 default:
429 return -EINVAL;
430 }
431
432 spin_lock_irqsave(&bus->reg_lock, cookie);
433
434 if (start) {
435 snd_hdac_stream_start(hdac_stream(stream), true);
436 snd_hdac_stream_timecounter_init(hstr, 0);
437 } else {
438 snd_hdac_stream_stop(hdac_stream(stream));
439 }
440
441 spin_unlock_irqrestore(&bus->reg_lock, cookie);
442
443 return 0;
444 }
445
446 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
447 struct snd_soc_dai *dai)
448 {
449 struct skl *skl = get_skl_ctx(dai->dev);
450 struct skl_sst *ctx = skl->skl_sst;
451 struct skl_module_cfg *mconfig;
452 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
453 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
454 struct snd_soc_dapm_widget *w;
455 int ret;
456
457 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
458 if (!mconfig)
459 return -EIO;
460
461 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
462 w = dai->playback_widget;
463 else
464 w = dai->capture_widget;
465
466 switch (cmd) {
467 case SNDRV_PCM_TRIGGER_RESUME:
468 if (!w->ignore_suspend) {
469 /*
470 * enable DMA Resume enable bit for the stream, set the
471 * dpib & lpib position to resume before starting the
472 * DMA
473 */
474 snd_hdac_ext_stream_drsm_enable(ebus, true,
475 hdac_stream(stream)->index);
476 snd_hdac_ext_stream_set_dpibr(ebus, stream,
477 stream->dpib);
478 snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
479 }
480
481 case SNDRV_PCM_TRIGGER_START:
482 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
483 /*
484 * Start HOST DMA and Start FE Pipe.This is to make sure that
485 * there are no underrun/overrun in the case when the FE
486 * pipeline is started but there is a delay in starting the
487 * DMA channel on the host.
488 */
489 ret = skl_decoupled_trigger(substream, cmd);
490 if (ret < 0)
491 return ret;
492 return skl_run_pipe(ctx, mconfig->pipe);
493 break;
494
495 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
496 case SNDRV_PCM_TRIGGER_SUSPEND:
497 case SNDRV_PCM_TRIGGER_STOP:
498 /*
499 * Stop FE Pipe first and stop DMA. This is to make sure that
500 * there are no underrun/overrun in the case if there is a delay
501 * between the two operations.
502 */
503 ret = skl_stop_pipe(ctx, mconfig->pipe);
504 if (ret < 0)
505 return ret;
506
507 ret = skl_decoupled_trigger(substream, cmd);
508 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
509 /* save the dpib and lpib positions */
510 stream->dpib = readl(ebus->bus.remap_addr +
511 AZX_REG_VS_SDXDPIB_XBASE +
512 (AZX_REG_VS_SDXDPIB_XINTERVAL *
513 hdac_stream(stream)->index));
514
515 stream->lpib = snd_hdac_stream_get_pos_lpib(
516 hdac_stream(stream));
517 snd_hdac_ext_stream_decouple(ebus, stream, false);
518 }
519 break;
520
521 default:
522 return -EINVAL;
523 }
524
525 return 0;
526 }
527
528 static int skl_link_hw_params(struct snd_pcm_substream *substream,
529 struct snd_pcm_hw_params *params,
530 struct snd_soc_dai *dai)
531 {
532 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
533 struct hdac_ext_stream *link_dev;
534 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
535 struct hdac_ext_dma_params *dma_params;
536 struct snd_soc_dai *codec_dai = rtd->codec_dai;
537 struct skl_pipe_params p_params = {0};
538 struct hdac_ext_link *link;
539
540 link_dev = snd_hdac_ext_stream_assign(ebus, substream,
541 HDAC_EXT_STREAM_TYPE_LINK);
542 if (!link_dev)
543 return -EBUSY;
544
545 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
546
547 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
548 if (!link)
549 return -EINVAL;
550
551 /* set the stream tag in the codec dai dma params */
552 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
553 if (dma_params)
554 dma_params->stream_tag = hdac_stream(link_dev)->stream_tag;
555
556 p_params.s_fmt = snd_pcm_format_width(params_format(params));
557 p_params.ch = params_channels(params);
558 p_params.s_freq = params_rate(params);
559 p_params.stream = substream->stream;
560 p_params.link_dma_id = hdac_stream(link_dev)->stream_tag - 1;
561 p_params.link_index = link->index;
562 p_params.format = params_format(params);
563
564 return skl_tplg_be_update_params(dai, &p_params);
565 }
566
567 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
568 struct snd_soc_dai *dai)
569 {
570 struct skl *skl = get_skl_ctx(dai->dev);
571 struct skl_module_cfg *mconfig = NULL;
572
573 /* In case of XRUN recovery, reset the FW pipe to clean state */
574 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
575 if (mconfig && (substream->runtime->status->state ==
576 SNDRV_PCM_STATE_XRUN))
577 skl_reset_pipe(skl->skl_sst, mconfig->pipe);
578
579 return 0;
580 }
581
582 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
583 int cmd, struct snd_soc_dai *dai)
584 {
585 struct hdac_ext_stream *link_dev =
586 snd_soc_dai_get_dma_data(dai, substream);
587 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
588 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
589
590 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
591 switch (cmd) {
592 case SNDRV_PCM_TRIGGER_RESUME:
593 case SNDRV_PCM_TRIGGER_START:
594 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
595 snd_hdac_ext_link_stream_start(link_dev);
596 break;
597
598 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
599 case SNDRV_PCM_TRIGGER_SUSPEND:
600 case SNDRV_PCM_TRIGGER_STOP:
601 snd_hdac_ext_link_stream_clear(link_dev);
602 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
603 snd_hdac_ext_stream_decouple(ebus, stream, false);
604 break;
605
606 default:
607 return -EINVAL;
608 }
609 return 0;
610 }
611
612 static int skl_link_hw_free(struct snd_pcm_substream *substream,
613 struct snd_soc_dai *dai)
614 {
615 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
616 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
617 struct hdac_ext_stream *link_dev =
618 snd_soc_dai_get_dma_data(dai, substream);
619 struct hdac_ext_link *link;
620
621 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
622
623 link_dev->link_prepared = 0;
624
625 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
626 if (!link)
627 return -EINVAL;
628
629 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
630 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
631 return 0;
632 }
633
634 static struct snd_soc_dai_ops skl_pcm_dai_ops = {
635 .startup = skl_pcm_open,
636 .shutdown = skl_pcm_close,
637 .prepare = skl_pcm_prepare,
638 .hw_params = skl_pcm_hw_params,
639 .hw_free = skl_pcm_hw_free,
640 .trigger = skl_pcm_trigger,
641 };
642
643 static struct snd_soc_dai_ops skl_dmic_dai_ops = {
644 .hw_params = skl_be_hw_params,
645 };
646
647 static struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
648 .hw_params = skl_be_hw_params,
649 .prepare = skl_be_prepare,
650 };
651
652 static struct snd_soc_dai_ops skl_link_dai_ops = {
653 .prepare = skl_link_pcm_prepare,
654 .hw_params = skl_link_hw_params,
655 .hw_free = skl_link_hw_free,
656 .trigger = skl_link_pcm_trigger,
657 };
658
659 static struct snd_soc_dai_driver skl_platform_dai[] = {
660 {
661 .name = "System Pin",
662 .ops = &skl_pcm_dai_ops,
663 .playback = {
664 .stream_name = "System Playback",
665 .channels_min = HDA_MONO,
666 .channels_max = HDA_STEREO,
667 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
668 .formats = SNDRV_PCM_FMTBIT_S16_LE |
669 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
670 },
671 .capture = {
672 .stream_name = "System Capture",
673 .channels_min = HDA_MONO,
674 .channels_max = HDA_STEREO,
675 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
676 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
677 },
678 },
679 {
680 .name = "Reference Pin",
681 .ops = &skl_pcm_dai_ops,
682 .capture = {
683 .stream_name = "Reference Capture",
684 .channels_min = HDA_MONO,
685 .channels_max = HDA_QUAD,
686 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
687 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
688 },
689 },
690 {
691 .name = "Deepbuffer Pin",
692 .ops = &skl_pcm_dai_ops,
693 .playback = {
694 .stream_name = "Deepbuffer Playback",
695 .channels_min = HDA_STEREO,
696 .channels_max = HDA_STEREO,
697 .rates = SNDRV_PCM_RATE_48000,
698 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
699 },
700 },
701 {
702 .name = "LowLatency Pin",
703 .ops = &skl_pcm_dai_ops,
704 .playback = {
705 .stream_name = "Low Latency Playback",
706 .channels_min = HDA_STEREO,
707 .channels_max = HDA_STEREO,
708 .rates = SNDRV_PCM_RATE_48000,
709 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
710 },
711 },
712 {
713 .name = "DMIC Pin",
714 .ops = &skl_pcm_dai_ops,
715 .capture = {
716 .stream_name = "DMIC Capture",
717 .channels_min = HDA_MONO,
718 .channels_max = HDA_QUAD,
719 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
720 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
721 },
722 },
723 {
724 .name = "HDMI1 Pin",
725 .ops = &skl_pcm_dai_ops,
726 .playback = {
727 .stream_name = "HDMI1 Playback",
728 .channels_min = HDA_STEREO,
729 .channels_max = 8,
730 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
731 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
732 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
733 SNDRV_PCM_RATE_192000,
734 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
735 SNDRV_PCM_FMTBIT_S32_LE,
736 },
737 },
738 {
739 .name = "HDMI2 Pin",
740 .ops = &skl_pcm_dai_ops,
741 .playback = {
742 .stream_name = "HDMI2 Playback",
743 .channels_min = HDA_STEREO,
744 .channels_max = 8,
745 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
746 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
747 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
748 SNDRV_PCM_RATE_192000,
749 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
750 SNDRV_PCM_FMTBIT_S32_LE,
751 },
752 },
753 {
754 .name = "HDMI3 Pin",
755 .ops = &skl_pcm_dai_ops,
756 .playback = {
757 .stream_name = "HDMI3 Playback",
758 .channels_min = HDA_STEREO,
759 .channels_max = 8,
760 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
761 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
762 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
763 SNDRV_PCM_RATE_192000,
764 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
765 SNDRV_PCM_FMTBIT_S32_LE,
766 },
767 },
768
769 /* BE CPU Dais */
770 {
771 .name = "SSP0 Pin",
772 .ops = &skl_be_ssp_dai_ops,
773 .playback = {
774 .stream_name = "ssp0 Tx",
775 .channels_min = HDA_STEREO,
776 .channels_max = HDA_STEREO,
777 .rates = SNDRV_PCM_RATE_48000,
778 .formats = SNDRV_PCM_FMTBIT_S16_LE,
779 },
780 .capture = {
781 .stream_name = "ssp0 Rx",
782 .channels_min = HDA_STEREO,
783 .channels_max = HDA_STEREO,
784 .rates = SNDRV_PCM_RATE_48000,
785 .formats = SNDRV_PCM_FMTBIT_S16_LE,
786 },
787 },
788 {
789 .name = "SSP1 Pin",
790 .ops = &skl_be_ssp_dai_ops,
791 .playback = {
792 .stream_name = "ssp1 Tx",
793 .channels_min = HDA_STEREO,
794 .channels_max = HDA_STEREO,
795 .rates = SNDRV_PCM_RATE_48000,
796 .formats = SNDRV_PCM_FMTBIT_S16_LE,
797 },
798 .capture = {
799 .stream_name = "ssp1 Rx",
800 .channels_min = HDA_STEREO,
801 .channels_max = HDA_STEREO,
802 .rates = SNDRV_PCM_RATE_48000,
803 .formats = SNDRV_PCM_FMTBIT_S16_LE,
804 },
805 },
806 {
807 .name = "SSP2 Pin",
808 .ops = &skl_be_ssp_dai_ops,
809 .playback = {
810 .stream_name = "ssp2 Tx",
811 .channels_min = HDA_STEREO,
812 .channels_max = HDA_STEREO,
813 .rates = SNDRV_PCM_RATE_48000,
814 .formats = SNDRV_PCM_FMTBIT_S16_LE,
815 },
816 .capture = {
817 .stream_name = "ssp2 Rx",
818 .channels_min = HDA_STEREO,
819 .channels_max = HDA_STEREO,
820 .rates = SNDRV_PCM_RATE_48000,
821 .formats = SNDRV_PCM_FMTBIT_S16_LE,
822 },
823 },
824 {
825 .name = "SSP3 Pin",
826 .ops = &skl_be_ssp_dai_ops,
827 .playback = {
828 .stream_name = "ssp3 Tx",
829 .channels_min = HDA_STEREO,
830 .channels_max = HDA_STEREO,
831 .rates = SNDRV_PCM_RATE_48000,
832 .formats = SNDRV_PCM_FMTBIT_S16_LE,
833 },
834 .capture = {
835 .stream_name = "ssp3 Rx",
836 .channels_min = HDA_STEREO,
837 .channels_max = HDA_STEREO,
838 .rates = SNDRV_PCM_RATE_48000,
839 .formats = SNDRV_PCM_FMTBIT_S16_LE,
840 },
841 },
842 {
843 .name = "SSP4 Pin",
844 .ops = &skl_be_ssp_dai_ops,
845 .playback = {
846 .stream_name = "ssp4 Tx",
847 .channels_min = HDA_STEREO,
848 .channels_max = HDA_STEREO,
849 .rates = SNDRV_PCM_RATE_48000,
850 .formats = SNDRV_PCM_FMTBIT_S16_LE,
851 },
852 .capture = {
853 .stream_name = "ssp4 Rx",
854 .channels_min = HDA_STEREO,
855 .channels_max = HDA_STEREO,
856 .rates = SNDRV_PCM_RATE_48000,
857 .formats = SNDRV_PCM_FMTBIT_S16_LE,
858 },
859 },
860 {
861 .name = "SSP5 Pin",
862 .ops = &skl_be_ssp_dai_ops,
863 .playback = {
864 .stream_name = "ssp5 Tx",
865 .channels_min = HDA_STEREO,
866 .channels_max = HDA_STEREO,
867 .rates = SNDRV_PCM_RATE_48000,
868 .formats = SNDRV_PCM_FMTBIT_S16_LE,
869 },
870 .capture = {
871 .stream_name = "ssp5 Rx",
872 .channels_min = HDA_STEREO,
873 .channels_max = HDA_STEREO,
874 .rates = SNDRV_PCM_RATE_48000,
875 .formats = SNDRV_PCM_FMTBIT_S16_LE,
876 },
877 },
878 {
879 .name = "iDisp1 Pin",
880 .ops = &skl_link_dai_ops,
881 .playback = {
882 .stream_name = "iDisp1 Tx",
883 .channels_min = HDA_STEREO,
884 .channels_max = 8,
885 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
886 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
887 SNDRV_PCM_FMTBIT_S24_LE,
888 },
889 },
890 {
891 .name = "iDisp2 Pin",
892 .ops = &skl_link_dai_ops,
893 .playback = {
894 .stream_name = "iDisp2 Tx",
895 .channels_min = HDA_STEREO,
896 .channels_max = 8,
897 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
898 SNDRV_PCM_RATE_48000,
899 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
900 SNDRV_PCM_FMTBIT_S24_LE,
901 },
902 },
903 {
904 .name = "iDisp3 Pin",
905 .ops = &skl_link_dai_ops,
906 .playback = {
907 .stream_name = "iDisp3 Tx",
908 .channels_min = HDA_STEREO,
909 .channels_max = 8,
910 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
911 SNDRV_PCM_RATE_48000,
912 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
913 SNDRV_PCM_FMTBIT_S24_LE,
914 },
915 },
916 {
917 .name = "DMIC01 Pin",
918 .ops = &skl_dmic_dai_ops,
919 .capture = {
920 .stream_name = "DMIC01 Rx",
921 .channels_min = HDA_MONO,
922 .channels_max = HDA_QUAD,
923 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
924 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
925 },
926 },
927 {
928 .name = "HD-Codec Pin",
929 .ops = &skl_link_dai_ops,
930 .playback = {
931 .stream_name = "HD-Codec Tx",
932 .channels_min = HDA_STEREO,
933 .channels_max = HDA_STEREO,
934 .rates = SNDRV_PCM_RATE_48000,
935 .formats = SNDRV_PCM_FMTBIT_S16_LE,
936 },
937 .capture = {
938 .stream_name = "HD-Codec Rx",
939 .channels_min = HDA_STEREO,
940 .channels_max = HDA_STEREO,
941 .rates = SNDRV_PCM_RATE_48000,
942 .formats = SNDRV_PCM_FMTBIT_S16_LE,
943 },
944 },
945 };
946
947 static int skl_platform_open(struct snd_pcm_substream *substream)
948 {
949 struct snd_pcm_runtime *runtime;
950 struct snd_soc_pcm_runtime *rtd = substream->private_data;
951 struct snd_soc_dai_link *dai_link = rtd->dai_link;
952
953 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
954 dai_link->cpu_dai_name);
955
956 runtime = substream->runtime;
957 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
958
959 return 0;
960 }
961
962 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
963 int cmd)
964 {
965 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
966 struct hdac_bus *bus = ebus_to_hbus(ebus);
967 struct hdac_ext_stream *stream;
968 struct snd_pcm_substream *s;
969 bool start;
970 int sbits = 0;
971 unsigned long cookie;
972 struct hdac_stream *hstr;
973
974 stream = get_hdac_ext_stream(substream);
975 hstr = hdac_stream(stream);
976
977 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
978
979 if (!hstr->prepared)
980 return -EPIPE;
981
982 switch (cmd) {
983 case SNDRV_PCM_TRIGGER_START:
984 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
985 case SNDRV_PCM_TRIGGER_RESUME:
986 start = true;
987 break;
988
989 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
990 case SNDRV_PCM_TRIGGER_SUSPEND:
991 case SNDRV_PCM_TRIGGER_STOP:
992 start = false;
993 break;
994
995 default:
996 return -EINVAL;
997 }
998
999 snd_pcm_group_for_each_entry(s, substream) {
1000 if (s->pcm->card != substream->pcm->card)
1001 continue;
1002 stream = get_hdac_ext_stream(s);
1003 sbits |= 1 << hdac_stream(stream)->index;
1004 snd_pcm_trigger_done(s, substream);
1005 }
1006
1007 spin_lock_irqsave(&bus->reg_lock, cookie);
1008
1009 /* first, set SYNC bits of corresponding streams */
1010 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1011
1012 snd_pcm_group_for_each_entry(s, substream) {
1013 if (s->pcm->card != substream->pcm->card)
1014 continue;
1015 stream = get_hdac_ext_stream(s);
1016 if (start)
1017 snd_hdac_stream_start(hdac_stream(stream), true);
1018 else
1019 snd_hdac_stream_stop(hdac_stream(stream));
1020 }
1021 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1022
1023 snd_hdac_stream_sync(hstr, start, sbits);
1024
1025 spin_lock_irqsave(&bus->reg_lock, cookie);
1026
1027 /* reset SYNC bits */
1028 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1029 if (start)
1030 snd_hdac_stream_timecounter_init(hstr, sbits);
1031 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1032
1033 return 0;
1034 }
1035
1036 static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
1037 int cmd)
1038 {
1039 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1040
1041 if (!(ebus_to_hbus(ebus))->ppcap)
1042 return skl_coupled_trigger(substream, cmd);
1043
1044 return 0;
1045 }
1046
1047 static snd_pcm_uframes_t skl_platform_pcm_pointer
1048 (struct snd_pcm_substream *substream)
1049 {
1050 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1051 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1052 unsigned int pos;
1053
1054 /*
1055 * Use DPIB for Playback stream as the periodic DMA Position-in-
1056 * Buffer Writes may be scheduled at the same time or later than
1057 * the MSI and does not guarantee to reflect the Position of the
1058 * last buffer that was transferred. Whereas DPIB register in
1059 * HAD space reflects the actual data that is transferred.
1060 * Use the position buffer for capture, as DPIB write gets
1061 * completed earlier than the actual data written to the DDR.
1062 */
1063 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1064 pos = readl(ebus->bus.remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1065 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1066 hdac_stream(hstream)->index));
1067 else
1068 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1069
1070 if (pos >= hdac_stream(hstream)->bufsize)
1071 pos = 0;
1072
1073 return bytes_to_frames(substream->runtime, pos);
1074 }
1075
1076 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1077 u64 nsec)
1078 {
1079 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
1080 struct snd_soc_dai *codec_dai = rtd->codec_dai;
1081 u64 codec_frames, codec_nsecs;
1082
1083 if (!codec_dai->driver->ops->delay)
1084 return nsec;
1085
1086 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1087 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1088 substream->runtime->rate);
1089
1090 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1091 return nsec + codec_nsecs;
1092
1093 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1094 }
1095
1096 static int skl_get_time_info(struct snd_pcm_substream *substream,
1097 struct timespec *system_ts, struct timespec *audio_ts,
1098 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1099 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1100 {
1101 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1102 struct hdac_stream *hstr = hdac_stream(sstream);
1103 u64 nsec;
1104
1105 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1106 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1107
1108 snd_pcm_gettime(substream->runtime, system_ts);
1109
1110 nsec = timecounter_read(&hstr->tc);
1111 nsec = div_u64(nsec, 3); /* can be optimized */
1112 if (audio_tstamp_config->report_delay)
1113 nsec = skl_adjust_codec_delay(substream, nsec);
1114
1115 *audio_ts = ns_to_timespec(nsec);
1116
1117 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1118 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1119 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1120
1121 } else {
1122 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1123 }
1124
1125 return 0;
1126 }
1127
1128 static const struct snd_pcm_ops skl_platform_ops = {
1129 .open = skl_platform_open,
1130 .ioctl = snd_pcm_lib_ioctl,
1131 .trigger = skl_platform_pcm_trigger,
1132 .pointer = skl_platform_pcm_pointer,
1133 .get_time_info = skl_get_time_info,
1134 .mmap = snd_pcm_lib_default_mmap,
1135 .page = snd_pcm_sgbuf_ops_page,
1136 };
1137
1138 static void skl_pcm_free(struct snd_pcm *pcm)
1139 {
1140 snd_pcm_lib_preallocate_free_for_all(pcm);
1141 }
1142
1143 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
1144
1145 static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
1146 {
1147 struct snd_soc_dai *dai = rtd->cpu_dai;
1148 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
1149 struct snd_pcm *pcm = rtd->pcm;
1150 unsigned int size;
1151 int retval = 0;
1152 struct skl *skl = ebus_to_skl(ebus);
1153
1154 if (dai->driver->playback.channels_min ||
1155 dai->driver->capture.channels_min) {
1156 /* buffer pre-allocation */
1157 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1158 if (size > MAX_PREALLOC_SIZE)
1159 size = MAX_PREALLOC_SIZE;
1160 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
1161 SNDRV_DMA_TYPE_DEV_SG,
1162 snd_dma_pci_data(skl->pci),
1163 size, MAX_PREALLOC_SIZE);
1164 if (retval) {
1165 dev_err(dai->dev, "dma buffer allocationf fail\n");
1166 return retval;
1167 }
1168 }
1169
1170 return retval;
1171 }
1172
1173 static int skl_populate_modules(struct skl *skl)
1174 {
1175 struct skl_pipeline *p;
1176 struct skl_pipe_module *m;
1177 struct snd_soc_dapm_widget *w;
1178 struct skl_module_cfg *mconfig;
1179 int ret;
1180
1181 list_for_each_entry(p, &skl->ppl_list, node) {
1182 list_for_each_entry(m, &p->pipe->w_list, node) {
1183
1184 w = m->w;
1185 mconfig = w->priv;
1186
1187 ret = snd_skl_get_module_info(skl->skl_sst, mconfig);
1188 if (ret < 0) {
1189 dev_err(skl->skl_sst->dev,
1190 "query module info failed:%d\n", ret);
1191 goto err;
1192 }
1193 }
1194 }
1195 err:
1196 return ret;
1197 }
1198
1199 static int skl_platform_soc_probe(struct snd_soc_platform *platform)
1200 {
1201 struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev);
1202 struct skl *skl = ebus_to_skl(ebus);
1203 const struct skl_dsp_ops *ops;
1204 int ret;
1205
1206 pm_runtime_get_sync(platform->dev);
1207 if ((ebus_to_hbus(ebus))->ppcap) {
1208 ret = skl_tplg_init(platform, ebus);
1209 if (ret < 0) {
1210 dev_err(platform->dev, "Failed to init topology!\n");
1211 return ret;
1212 }
1213 skl->platform = platform;
1214
1215 /* load the firmwares, since all is set */
1216 ops = skl_get_dsp_ops(skl->pci->device);
1217 if (!ops)
1218 return -EIO;
1219
1220 if (skl->skl_sst->is_first_boot == false) {
1221 dev_err(platform->dev, "DSP reports first boot done!!!\n");
1222 return -EIO;
1223 }
1224
1225 ret = ops->init_fw(platform->dev, skl->skl_sst);
1226 if (ret < 0) {
1227 dev_err(platform->dev, "Failed to boot first fw: %d\n", ret);
1228 return ret;
1229 }
1230 skl_populate_modules(skl);
1231 skl->skl_sst->update_d0i3c = skl_update_d0i3c;
1232 }
1233 pm_runtime_mark_last_busy(platform->dev);
1234 pm_runtime_put_autosuspend(platform->dev);
1235
1236 return 0;
1237 }
1238 static struct snd_soc_platform_driver skl_platform_drv = {
1239 .probe = skl_platform_soc_probe,
1240 .ops = &skl_platform_ops,
1241 .pcm_new = skl_pcm_new,
1242 .pcm_free = skl_pcm_free,
1243 };
1244
1245 static const struct snd_soc_component_driver skl_component = {
1246 .name = "pcm",
1247 };
1248
1249 int skl_platform_register(struct device *dev)
1250 {
1251 int ret;
1252 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
1253 struct skl *skl = ebus_to_skl(ebus);
1254
1255 INIT_LIST_HEAD(&skl->ppl_list);
1256
1257 ret = snd_soc_register_platform(dev, &skl_platform_drv);
1258 if (ret) {
1259 dev_err(dev, "soc platform registration failed %d\n", ret);
1260 return ret;
1261 }
1262 ret = snd_soc_register_component(dev, &skl_component,
1263 skl_platform_dai,
1264 ARRAY_SIZE(skl_platform_dai));
1265 if (ret) {
1266 dev_err(dev, "soc component registration failed %d\n", ret);
1267 snd_soc_unregister_platform(dev);
1268 }
1269
1270 return ret;
1271
1272 }
1273
1274 int skl_platform_unregister(struct device *dev)
1275 {
1276 snd_soc_unregister_component(dev);
1277 snd_soc_unregister_platform(dev);
1278 return 0;
1279 }
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