?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm/i915: set "ret" correctly on error paths
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / i915 / intel_overlay.c
blob2e0c56ed22bb2551e88d34b6ec1641ac5377c383
1 /*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
28 #include <drm/drmP.h>
29 #include <drm/i915_drm.h>
30 #include "i915_drv.h"
31 #include "i915_reg.h"
32 #include "intel_drv.h"
33 #include "intel_frontbuffer.h"
34
35 /* Limits for overlay size. According to intel doc, the real limits are:
36 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
37 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
38 * the mininum of both. */
39 #define IMAGE_MAX_WIDTH 2048
40 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
41 /* on 830 and 845 these large limits result in the card hanging */
42 #define IMAGE_MAX_WIDTH_LEGACY 1024
43 #define IMAGE_MAX_HEIGHT_LEGACY 1088
44
45 /* overlay register definitions */
46 /* OCMD register */
47 #define OCMD_TILED_SURFACE (0x1<<19)
48 #define OCMD_MIRROR_MASK (0x3<<17)
49 #define OCMD_MIRROR_MODE (0x3<<17)
50 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
51 #define OCMD_MIRROR_VERTICAL (0x2<<17)
52 #define OCMD_MIRROR_BOTH (0x3<<17)
53 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
54 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
55 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
56 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
58 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
59 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
60 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
61 #define OCMD_YUV_422_PACKED (0x8<<10)
62 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_420_PLANAR (0xc<<10)
64 #define OCMD_YUV_422_PLANAR (0xd<<10)
65 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
66 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
67 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
68 #define OCMD_BUF_TYPE_MASK (0x1<<5)
69 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
70 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
71 #define OCMD_TEST_MODE (0x1<<4)
72 #define OCMD_BUFFER_SELECT (0x3<<2)
73 #define OCMD_BUFFER0 (0x0<<2)
74 #define OCMD_BUFFER1 (0x1<<2)
75 #define OCMD_FIELD_SELECT (0x1<<2)
76 #define OCMD_FIELD0 (0x0<<1)
77 #define OCMD_FIELD1 (0x1<<1)
78 #define OCMD_ENABLE (0x1<<0)
79
80 /* OCONFIG register */
81 #define OCONF_PIPE_MASK (0x1<<18)
82 #define OCONF_PIPE_A (0x0<<18)
83 #define OCONF_PIPE_B (0x1<<18)
84 #define OCONF_GAMMA2_ENABLE (0x1<<16)
85 #define OCONF_CSC_MODE_BT601 (0x0<<5)
86 #define OCONF_CSC_MODE_BT709 (0x1<<5)
87 #define OCONF_CSC_BYPASS (0x1<<4)
88 #define OCONF_CC_OUT_8BIT (0x1<<3)
89 #define OCONF_TEST_MODE (0x1<<2)
90 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
91 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
92
93 /* DCLRKM (dst-key) register */
94 #define DST_KEY_ENABLE (0x1<<31)
95 #define CLK_RGB24_MASK 0x0
96 #define CLK_RGB16_MASK 0x070307
97 #define CLK_RGB15_MASK 0x070707
98 #define CLK_RGB8I_MASK 0xffffff
99
100 #define RGB16_TO_COLORKEY(c) \
101 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
102 #define RGB15_TO_COLORKEY(c) \
103 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
104
105 /* overlay flip addr flag */
106 #define OFC_UPDATE 0x1
107
108 /* polyphase filter coefficients */
109 #define N_HORIZ_Y_TAPS 5
110 #define N_VERT_Y_TAPS 3
111 #define N_HORIZ_UV_TAPS 3
112 #define N_VERT_UV_TAPS 3
113 #define N_PHASES 17
114 #define MAX_TAPS 5
115
116 /* memory bufferd overlay registers */
117 struct overlay_registers {
118 u32 OBUF_0Y;
119 u32 OBUF_1Y;
120 u32 OBUF_0U;
121 u32 OBUF_0V;
122 u32 OBUF_1U;
123 u32 OBUF_1V;
124 u32 OSTRIDE;
125 u32 YRGB_VPH;
126 u32 UV_VPH;
127 u32 HORZ_PH;
128 u32 INIT_PHS;
129 u32 DWINPOS;
130 u32 DWINSZ;
131 u32 SWIDTH;
132 u32 SWIDTHSW;
133 u32 SHEIGHT;
134 u32 YRGBSCALE;
135 u32 UVSCALE;
136 u32 OCLRC0;
137 u32 OCLRC1;
138 u32 DCLRKV;
139 u32 DCLRKM;
140 u32 SCLRKVH;
141 u32 SCLRKVL;
142 u32 SCLRKEN;
143 u32 OCONFIG;
144 u32 OCMD;
145 u32 RESERVED1; /* 0x6C */
146 u32 OSTART_0Y;
147 u32 OSTART_1Y;
148 u32 OSTART_0U;
149 u32 OSTART_0V;
150 u32 OSTART_1U;
151 u32 OSTART_1V;
152 u32 OTILEOFF_0Y;
153 u32 OTILEOFF_1Y;
154 u32 OTILEOFF_0U;
155 u32 OTILEOFF_0V;
156 u32 OTILEOFF_1U;
157 u32 OTILEOFF_1V;
158 u32 FASTHSCALE; /* 0xA0 */
159 u32 UVSCALEV; /* 0xA4 */
160 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
161 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
162 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
163 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
164 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
165 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
166 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
167 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
168 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
169 };
170
171 struct intel_overlay {
172 struct drm_i915_private *i915;
173 struct intel_crtc *crtc;
174 struct i915_vma *vma;
175 struct i915_vma *old_vma;
176 bool active;
177 bool pfit_active;
178 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
179 u32 color_key:24;
180 u32 color_key_enabled:1;
181 u32 brightness, contrast, saturation;
182 u32 old_xscale, old_yscale;
183 /* register access */
184 u32 flip_addr;
185 struct drm_i915_gem_object *reg_bo;
186 /* flip handling */
187 struct i915_gem_active last_flip;
188 };
189
190 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
191 bool enable)
192 {
193 struct pci_dev *pdev = dev_priv->drm.pdev;
194 u8 val;
195
196 /* WA_OVERLAY_CLKGATE:alm */
197 if (enable)
198 I915_WRITE(DSPCLK_GATE_D, 0);
199 else
200 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
201
202 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
203 pci_bus_read_config_byte(pdev->bus,
204 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
205 if (enable)
206 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
207 else
208 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
209 pci_bus_write_config_byte(pdev->bus,
210 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
211 }
212
213 static struct overlay_registers __iomem *
214 intel_overlay_map_regs(struct intel_overlay *overlay)
215 {
216 struct drm_i915_private *dev_priv = overlay->i915;
217 struct overlay_registers __iomem *regs;
218
219 if (OVERLAY_NEEDS_PHYSICAL(dev_priv))
220 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr;
221 else
222 regs = io_mapping_map_wc(&dev_priv->ggtt.mappable,
223 overlay->flip_addr,
224 PAGE_SIZE);
225
226 return regs;
227 }
228
229 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
230 struct overlay_registers __iomem *regs)
231 {
232 if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915))
233 io_mapping_unmap(regs);
234 }
235
236 static void intel_overlay_submit_request(struct intel_overlay *overlay,
237 struct drm_i915_gem_request *req,
238 i915_gem_retire_fn retire)
239 {
240 GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip,
241 &overlay->i915->drm.struct_mutex));
242 i915_gem_active_set_retire_fn(&overlay->last_flip, retire,
243 &overlay->i915->drm.struct_mutex);
244 i915_gem_active_set(&overlay->last_flip, req);
245 i915_add_request(req);
246 }
247
248 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
249 struct drm_i915_gem_request *req,
250 i915_gem_retire_fn retire)
251 {
252 intel_overlay_submit_request(overlay, req, retire);
253 return i915_gem_active_retire(&overlay->last_flip,
254 &overlay->i915->drm.struct_mutex);
255 }
256
257 static struct drm_i915_gem_request *alloc_request(struct intel_overlay *overlay)
258 {
259 struct drm_i915_private *dev_priv = overlay->i915;
260 struct intel_engine_cs *engine = dev_priv->engine[RCS];
261
262 return i915_gem_request_alloc(engine, dev_priv->kernel_context);
263 }
264
265 /* overlay needs to be disable in OCMD reg */
266 static int intel_overlay_on(struct intel_overlay *overlay)
267 {
268 struct drm_i915_private *dev_priv = overlay->i915;
269 struct drm_i915_gem_request *req;
270 u32 *cs;
271
272 WARN_ON(overlay->active);
273 WARN_ON(IS_I830(dev_priv) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
274
275 req = alloc_request(overlay);
276 if (IS_ERR(req))
277 return PTR_ERR(req);
278
279 cs = intel_ring_begin(req, 4);
280 if (IS_ERR(cs)) {
281 i915_add_request(req);
282 return PTR_ERR(cs);
283 }
284
285 overlay->active = true;
286
287 if (IS_I830(dev_priv))
288 i830_overlay_clock_gating(dev_priv, false);
289
290 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
291 *cs++ = overlay->flip_addr | OFC_UPDATE;
292 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
293 *cs++ = MI_NOOP;
294 intel_ring_advance(req, cs);
295
296 return intel_overlay_do_wait_request(overlay, req, NULL);
297 }
298
299 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
300 struct i915_vma *vma)
301 {
302 enum pipe pipe = overlay->crtc->pipe;
303
304 WARN_ON(overlay->old_vma);
305
306 i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL,
307 vma ? vma->obj : NULL,
308 INTEL_FRONTBUFFER_OVERLAY(pipe));
309
310 intel_frontbuffer_flip_prepare(overlay->i915,
311 INTEL_FRONTBUFFER_OVERLAY(pipe));
312
313 overlay->old_vma = overlay->vma;
314 if (vma)
315 overlay->vma = i915_vma_get(vma);
316 else
317 overlay->vma = NULL;
318 }
319
320 /* overlay needs to be enabled in OCMD reg */
321 static int intel_overlay_continue(struct intel_overlay *overlay,
322 struct i915_vma *vma,
323 bool load_polyphase_filter)
324 {
325 struct drm_i915_private *dev_priv = overlay->i915;
326 struct drm_i915_gem_request *req;
327 u32 flip_addr = overlay->flip_addr;
328 u32 tmp, *cs;
329
330 WARN_ON(!overlay->active);
331
332 if (load_polyphase_filter)
333 flip_addr |= OFC_UPDATE;
334
335 /* check for underruns */
336 tmp = I915_READ(DOVSTA);
337 if (tmp & (1 << 17))
338 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
339
340 req = alloc_request(overlay);
341 if (IS_ERR(req))
342 return PTR_ERR(req);
343
344 cs = intel_ring_begin(req, 2);
345 if (IS_ERR(cs)) {
346 i915_add_request(req);
347 return PTR_ERR(cs);
348 }
349
350 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
351 *cs++ = flip_addr;
352 intel_ring_advance(req, cs);
353
354 intel_overlay_flip_prepare(overlay, vma);
355
356 intel_overlay_submit_request(overlay, req, NULL);
357
358 return 0;
359 }
360
361 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
362 {
363 struct i915_vma *vma;
364
365 vma = fetch_and_zero(&overlay->old_vma);
366 if (WARN_ON(!vma))
367 return;
368
369 intel_frontbuffer_flip_complete(overlay->i915,
370 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
371
372 i915_gem_object_unpin_from_display_plane(vma);
373 i915_vma_put(vma);
374 }
375
376 static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
377 struct drm_i915_gem_request *req)
378 {
379 struct intel_overlay *overlay =
380 container_of(active, typeof(*overlay), last_flip);
381
382 intel_overlay_release_old_vma(overlay);
383 }
384
385 static void intel_overlay_off_tail(struct i915_gem_active *active,
386 struct drm_i915_gem_request *req)
387 {
388 struct intel_overlay *overlay =
389 container_of(active, typeof(*overlay), last_flip);
390 struct drm_i915_private *dev_priv = overlay->i915;
391
392 intel_overlay_release_old_vma(overlay);
393
394 overlay->crtc->overlay = NULL;
395 overlay->crtc = NULL;
396 overlay->active = false;
397
398 if (IS_I830(dev_priv))
399 i830_overlay_clock_gating(dev_priv, true);
400 }
401
402 /* overlay needs to be disabled in OCMD reg */
403 static int intel_overlay_off(struct intel_overlay *overlay)
404 {
405 struct drm_i915_gem_request *req;
406 u32 *cs, flip_addr = overlay->flip_addr;
407
408 WARN_ON(!overlay->active);
409
410 /* According to intel docs the overlay hw may hang (when switching
411 * off) without loading the filter coeffs. It is however unclear whether
412 * this applies to the disabling of the overlay or to the switching off
413 * of the hw. Do it in both cases */
414 flip_addr |= OFC_UPDATE;
415
416 req = alloc_request(overlay);
417 if (IS_ERR(req))
418 return PTR_ERR(req);
419
420 cs = intel_ring_begin(req, 6);
421 if (IS_ERR(cs)) {
422 i915_add_request(req);
423 return PTR_ERR(cs);
424 }
425
426 /* wait for overlay to go idle */
427 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
428 *cs++ = flip_addr;
429 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
430
431 /* turn overlay off */
432 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
433 *cs++ = flip_addr;
434 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
435
436 intel_ring_advance(req, cs);
437
438 intel_overlay_flip_prepare(overlay, NULL);
439
440 return intel_overlay_do_wait_request(overlay, req,
441 intel_overlay_off_tail);
442 }
443
444 /* recover from an interruption due to a signal
445 * We have to be careful not to repeat work forever an make forward progess. */
446 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
447 {
448 return i915_gem_active_retire(&overlay->last_flip,
449 &overlay->i915->drm.struct_mutex);
450 }
451
452 /* Wait for pending overlay flip and release old frame.
453 * Needs to be called before the overlay register are changed
454 * via intel_overlay_(un)map_regs
455 */
456 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
457 {
458 struct drm_i915_private *dev_priv = overlay->i915;
459 u32 *cs;
460 int ret;
461
462 lockdep_assert_held(&dev_priv->drm.struct_mutex);
463
464 /* Only wait if there is actually an old frame to release to
465 * guarantee forward progress.
466 */
467 if (!overlay->old_vma)
468 return 0;
469
470 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
471 /* synchronous slowpath */
472 struct drm_i915_gem_request *req;
473
474 req = alloc_request(overlay);
475 if (IS_ERR(req))
476 return PTR_ERR(req);
477
478 cs = intel_ring_begin(req, 2);
479 if (IS_ERR(cs)) {
480 i915_add_request(req);
481 return PTR_ERR(cs);
482 }
483
484 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
485 *cs++ = MI_NOOP;
486 intel_ring_advance(req, cs);
487
488 ret = intel_overlay_do_wait_request(overlay, req,
489 intel_overlay_release_old_vid_tail);
490 if (ret)
491 return ret;
492 } else
493 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
494
495 return 0;
496 }
497
498 void intel_overlay_reset(struct drm_i915_private *dev_priv)
499 {
500 struct intel_overlay *overlay = dev_priv->overlay;
501
502 if (!overlay)
503 return;
504
505 intel_overlay_release_old_vid(overlay);
506
507 overlay->old_xscale = 0;
508 overlay->old_yscale = 0;
509 overlay->crtc = NULL;
510 overlay->active = false;
511 }
512
513 struct put_image_params {
514 int format;
515 short dst_x;
516 short dst_y;
517 short dst_w;
518 short dst_h;
519 short src_w;
520 short src_scan_h;
521 short src_scan_w;
522 short src_h;
523 short stride_Y;
524 short stride_UV;
525 int offset_Y;
526 int offset_U;
527 int offset_V;
528 };
529
530 static int packed_depth_bytes(u32 format)
531 {
532 switch (format & I915_OVERLAY_DEPTH_MASK) {
533 case I915_OVERLAY_YUV422:
534 return 4;
535 case I915_OVERLAY_YUV411:
536 /* return 6; not implemented */
537 default:
538 return -EINVAL;
539 }
540 }
541
542 static int packed_width_bytes(u32 format, short width)
543 {
544 switch (format & I915_OVERLAY_DEPTH_MASK) {
545 case I915_OVERLAY_YUV422:
546 return width << 1;
547 default:
548 return -EINVAL;
549 }
550 }
551
552 static int uv_hsubsampling(u32 format)
553 {
554 switch (format & I915_OVERLAY_DEPTH_MASK) {
555 case I915_OVERLAY_YUV422:
556 case I915_OVERLAY_YUV420:
557 return 2;
558 case I915_OVERLAY_YUV411:
559 case I915_OVERLAY_YUV410:
560 return 4;
561 default:
562 return -EINVAL;
563 }
564 }
565
566 static int uv_vsubsampling(u32 format)
567 {
568 switch (format & I915_OVERLAY_DEPTH_MASK) {
569 case I915_OVERLAY_YUV420:
570 case I915_OVERLAY_YUV410:
571 return 2;
572 case I915_OVERLAY_YUV422:
573 case I915_OVERLAY_YUV411:
574 return 1;
575 default:
576 return -EINVAL;
577 }
578 }
579
580 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
581 {
582 u32 sw;
583
584 if (IS_GEN2(dev_priv))
585 sw = ALIGN((offset & 31) + width, 32);
586 else
587 sw = ALIGN((offset & 63) + width, 64);
588
589 if (sw == 0)
590 return 0;
591
592 return (sw - 32) >> 3;
593 }
594
595 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
596 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
597 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
598 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
599 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
600 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
601 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
602 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
603 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
604 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
605 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
606 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
607 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
608 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
609 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
610 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
611 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
612 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
613 };
614
615 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
616 [ 0] = { 0x3000, 0x1800, 0x1800, },
617 [ 1] = { 0xb000, 0x18d0, 0x2e60, },
618 [ 2] = { 0xb000, 0x1990, 0x2ce0, },
619 [ 3] = { 0xb020, 0x1a68, 0x2b40, },
620 [ 4] = { 0xb040, 0x1b20, 0x29e0, },
621 [ 5] = { 0xb060, 0x1bd8, 0x2880, },
622 [ 6] = { 0xb080, 0x1c88, 0x3e60, },
623 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
624 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
625 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
626 [10] = { 0xb100, 0x1eb8, 0x3620, },
627 [11] = { 0xb100, 0x1f18, 0x34a0, },
628 [12] = { 0xb100, 0x1f68, 0x3360, },
629 [13] = { 0xb0e0, 0x1fa8, 0x3240, },
630 [14] = { 0xb0c0, 0x1fe0, 0x3140, },
631 [15] = { 0xb060, 0x1ff0, 0x30a0, },
632 [16] = { 0x3000, 0x0800, 0x3000, },
633 };
634
635 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
636 {
637 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
638 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
639 sizeof(uv_static_hcoeffs));
640 }
641
642 static bool update_scaling_factors(struct intel_overlay *overlay,
643 struct overlay_registers __iomem *regs,
644 struct put_image_params *params)
645 {
646 /* fixed point with a 12 bit shift */
647 u32 xscale, yscale, xscale_UV, yscale_UV;
648 #define FP_SHIFT 12
649 #define FRACT_MASK 0xfff
650 bool scale_changed = false;
651 int uv_hscale = uv_hsubsampling(params->format);
652 int uv_vscale = uv_vsubsampling(params->format);
653
654 if (params->dst_w > 1)
655 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
656 /(params->dst_w);
657 else
658 xscale = 1 << FP_SHIFT;
659
660 if (params->dst_h > 1)
661 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
662 /(params->dst_h);
663 else
664 yscale = 1 << FP_SHIFT;
665
666 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
667 xscale_UV = xscale/uv_hscale;
668 yscale_UV = yscale/uv_vscale;
669 /* make the Y scale to UV scale ratio an exact multiply */
670 xscale = xscale_UV * uv_hscale;
671 yscale = yscale_UV * uv_vscale;
672 /*} else {
673 xscale_UV = 0;
674 yscale_UV = 0;
675 }*/
676
677 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
678 scale_changed = true;
679 overlay->old_xscale = xscale;
680 overlay->old_yscale = yscale;
681
682 iowrite32(((yscale & FRACT_MASK) << 20) |
683 ((xscale >> FP_SHIFT) << 16) |
684 ((xscale & FRACT_MASK) << 3),
685 &regs->YRGBSCALE);
686
687 iowrite32(((yscale_UV & FRACT_MASK) << 20) |
688 ((xscale_UV >> FP_SHIFT) << 16) |
689 ((xscale_UV & FRACT_MASK) << 3),
690 &regs->UVSCALE);
691
692 iowrite32((((yscale >> FP_SHIFT) << 16) |
693 ((yscale_UV >> FP_SHIFT) << 0)),
694 &regs->UVSCALEV);
695
696 if (scale_changed)
697 update_polyphase_filter(regs);
698
699 return scale_changed;
700 }
701
702 static void update_colorkey(struct intel_overlay *overlay,
703 struct overlay_registers __iomem *regs)
704 {
705 const struct intel_plane_state *state =
706 to_intel_plane_state(overlay->crtc->base.primary->state);
707 u32 key = overlay->color_key;
708 u32 format = 0;
709 u32 flags = 0;
710
711 if (overlay->color_key_enabled)
712 flags |= DST_KEY_ENABLE;
713
714 if (state->base.visible)
715 format = state->base.fb->format->format;
716
717 switch (format) {
718 case DRM_FORMAT_C8:
719 key = 0;
720 flags |= CLK_RGB8I_MASK;
721 break;
722 case DRM_FORMAT_XRGB1555:
723 key = RGB15_TO_COLORKEY(key);
724 flags |= CLK_RGB15_MASK;
725 break;
726 case DRM_FORMAT_RGB565:
727 key = RGB16_TO_COLORKEY(key);
728 flags |= CLK_RGB16_MASK;
729 break;
730 default:
731 flags |= CLK_RGB24_MASK;
732 break;
733 }
734
735 iowrite32(key, &regs->DCLRKV);
736 iowrite32(flags, &regs->DCLRKM);
737 }
738
739 static u32 overlay_cmd_reg(struct put_image_params *params)
740 {
741 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
742
743 if (params->format & I915_OVERLAY_YUV_PLANAR) {
744 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
745 case I915_OVERLAY_YUV422:
746 cmd |= OCMD_YUV_422_PLANAR;
747 break;
748 case I915_OVERLAY_YUV420:
749 cmd |= OCMD_YUV_420_PLANAR;
750 break;
751 case I915_OVERLAY_YUV411:
752 case I915_OVERLAY_YUV410:
753 cmd |= OCMD_YUV_410_PLANAR;
754 break;
755 }
756 } else { /* YUV packed */
757 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
758 case I915_OVERLAY_YUV422:
759 cmd |= OCMD_YUV_422_PACKED;
760 break;
761 case I915_OVERLAY_YUV411:
762 cmd |= OCMD_YUV_411_PACKED;
763 break;
764 }
765
766 switch (params->format & I915_OVERLAY_SWAP_MASK) {
767 case I915_OVERLAY_NO_SWAP:
768 break;
769 case I915_OVERLAY_UV_SWAP:
770 cmd |= OCMD_UV_SWAP;
771 break;
772 case I915_OVERLAY_Y_SWAP:
773 cmd |= OCMD_Y_SWAP;
774 break;
775 case I915_OVERLAY_Y_AND_UV_SWAP:
776 cmd |= OCMD_Y_AND_UV_SWAP;
777 break;
778 }
779 }
780
781 return cmd;
782 }
783
784 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
785 struct drm_i915_gem_object *new_bo,
786 struct put_image_params *params)
787 {
788 int ret, tmp_width;
789 struct overlay_registers __iomem *regs;
790 bool scale_changed = false;
791 struct drm_i915_private *dev_priv = overlay->i915;
792 u32 swidth, swidthsw, sheight, ostride;
793 enum pipe pipe = overlay->crtc->pipe;
794 struct i915_vma *vma;
795
796 lockdep_assert_held(&dev_priv->drm.struct_mutex);
797 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
798
799 ret = intel_overlay_release_old_vid(overlay);
800 if (ret != 0)
801 return ret;
802
803 vma = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
804 if (IS_ERR(vma))
805 return PTR_ERR(vma);
806
807 ret = i915_vma_put_fence(vma);
808 if (ret)
809 goto out_unpin;
810
811 if (!overlay->active) {
812 u32 oconfig;
813 regs = intel_overlay_map_regs(overlay);
814 if (!regs) {
815 ret = -ENOMEM;
816 goto out_unpin;
817 }
818 oconfig = OCONF_CC_OUT_8BIT;
819 if (IS_GEN4(dev_priv))
820 oconfig |= OCONF_CSC_MODE_BT709;
821 oconfig |= pipe == 0 ?
822 OCONF_PIPE_A : OCONF_PIPE_B;
823 iowrite32(oconfig, &regs->OCONFIG);
824 intel_overlay_unmap_regs(overlay, regs);
825
826 ret = intel_overlay_on(overlay);
827 if (ret != 0)
828 goto out_unpin;
829 }
830
831 regs = intel_overlay_map_regs(overlay);
832 if (!regs) {
833 ret = -ENOMEM;
834 goto out_unpin;
835 }
836
837 iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
838 iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
839
840 if (params->format & I915_OVERLAY_YUV_PACKED)
841 tmp_width = packed_width_bytes(params->format, params->src_w);
842 else
843 tmp_width = params->src_w;
844
845 swidth = params->src_w;
846 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
847 sheight = params->src_h;
848 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
849 ostride = params->stride_Y;
850
851 if (params->format & I915_OVERLAY_YUV_PLANAR) {
852 int uv_hscale = uv_hsubsampling(params->format);
853 int uv_vscale = uv_vsubsampling(params->format);
854 u32 tmp_U, tmp_V;
855 swidth |= (params->src_w/uv_hscale) << 16;
856 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
857 params->src_w/uv_hscale);
858 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
859 params->src_w/uv_hscale);
860 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
861 sheight |= (params->src_h/uv_vscale) << 16;
862 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
863 &regs->OBUF_0U);
864 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
865 &regs->OBUF_0V);
866 ostride |= params->stride_UV << 16;
867 }
868
869 iowrite32(swidth, &regs->SWIDTH);
870 iowrite32(swidthsw, &regs->SWIDTHSW);
871 iowrite32(sheight, &regs->SHEIGHT);
872 iowrite32(ostride, &regs->OSTRIDE);
873
874 scale_changed = update_scaling_factors(overlay, regs, params);
875
876 update_colorkey(overlay, regs);
877
878 iowrite32(overlay_cmd_reg(params), &regs->OCMD);
879
880 intel_overlay_unmap_regs(overlay, regs);
881
882 ret = intel_overlay_continue(overlay, vma, scale_changed);
883 if (ret)
884 goto out_unpin;
885
886 return 0;
887
888 out_unpin:
889 i915_gem_object_unpin_from_display_plane(vma);
890 return ret;
891 }
892
893 int intel_overlay_switch_off(struct intel_overlay *overlay)
894 {
895 struct drm_i915_private *dev_priv = overlay->i915;
896 struct overlay_registers __iomem *regs;
897 int ret;
898
899 lockdep_assert_held(&dev_priv->drm.struct_mutex);
900 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
901
902 ret = intel_overlay_recover_from_interrupt(overlay);
903 if (ret != 0)
904 return ret;
905
906 if (!overlay->active)
907 return 0;
908
909 ret = intel_overlay_release_old_vid(overlay);
910 if (ret != 0)
911 return ret;
912
913 regs = intel_overlay_map_regs(overlay);
914 iowrite32(0, &regs->OCMD);
915 intel_overlay_unmap_regs(overlay, regs);
916
917 return intel_overlay_off(overlay);
918 }
919
920 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
921 struct intel_crtc *crtc)
922 {
923 if (!crtc->active)
924 return -EINVAL;
925
926 /* can't use the overlay with double wide pipe */
927 if (crtc->config->double_wide)
928 return -EINVAL;
929
930 return 0;
931 }
932
933 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
934 {
935 struct drm_i915_private *dev_priv = overlay->i915;
936 u32 pfit_control = I915_READ(PFIT_CONTROL);
937 u32 ratio;
938
939 /* XXX: This is not the same logic as in the xorg driver, but more in
940 * line with the intel documentation for the i965
941 */
942 if (INTEL_GEN(dev_priv) >= 4) {
943 /* on i965 use the PGM reg to read out the autoscaler values */
944 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
945 } else {
946 if (pfit_control & VERT_AUTO_SCALE)
947 ratio = I915_READ(PFIT_AUTO_RATIOS);
948 else
949 ratio = I915_READ(PFIT_PGM_RATIOS);
950 ratio >>= PFIT_VERT_SCALE_SHIFT;
951 }
952
953 overlay->pfit_vscale_ratio = ratio;
954 }
955
956 static int check_overlay_dst(struct intel_overlay *overlay,
957 struct drm_intel_overlay_put_image *rec)
958 {
959 const struct intel_crtc_state *pipe_config =
960 overlay->crtc->config;
961
962 if (rec->dst_x < pipe_config->pipe_src_w &&
963 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
964 rec->dst_y < pipe_config->pipe_src_h &&
965 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
966 return 0;
967 else
968 return -EINVAL;
969 }
970
971 static int check_overlay_scaling(struct put_image_params *rec)
972 {
973 u32 tmp;
974
975 /* downscaling limit is 8.0 */
976 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
977 if (tmp > 7)
978 return -EINVAL;
979 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
980 if (tmp > 7)
981 return -EINVAL;
982
983 return 0;
984 }
985
986 static int check_overlay_src(struct drm_i915_private *dev_priv,
987 struct drm_intel_overlay_put_image *rec,
988 struct drm_i915_gem_object *new_bo)
989 {
990 int uv_hscale = uv_hsubsampling(rec->flags);
991 int uv_vscale = uv_vsubsampling(rec->flags);
992 u32 stride_mask;
993 int depth;
994 u32 tmp;
995
996 /* check src dimensions */
997 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
998 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
999 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
1000 return -EINVAL;
1001 } else {
1002 if (rec->src_height > IMAGE_MAX_HEIGHT ||
1003 rec->src_width > IMAGE_MAX_WIDTH)
1004 return -EINVAL;
1005 }
1006
1007 /* better safe than sorry, use 4 as the maximal subsampling ratio */
1008 if (rec->src_height < N_VERT_Y_TAPS*4 ||
1009 rec->src_width < N_HORIZ_Y_TAPS*4)
1010 return -EINVAL;
1011
1012 /* check alignment constraints */
1013 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1014 case I915_OVERLAY_RGB:
1015 /* not implemented */
1016 return -EINVAL;
1017
1018 case I915_OVERLAY_YUV_PACKED:
1019 if (uv_vscale != 1)
1020 return -EINVAL;
1021
1022 depth = packed_depth_bytes(rec->flags);
1023 if (depth < 0)
1024 return depth;
1025
1026 /* ignore UV planes */
1027 rec->stride_UV = 0;
1028 rec->offset_U = 0;
1029 rec->offset_V = 0;
1030 /* check pixel alignment */
1031 if (rec->offset_Y % depth)
1032 return -EINVAL;
1033 break;
1034
1035 case I915_OVERLAY_YUV_PLANAR:
1036 if (uv_vscale < 0 || uv_hscale < 0)
1037 return -EINVAL;
1038 /* no offset restrictions for planar formats */
1039 break;
1040
1041 default:
1042 return -EINVAL;
1043 }
1044
1045 if (rec->src_width % uv_hscale)
1046 return -EINVAL;
1047
1048 /* stride checking */
1049 if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1050 stride_mask = 255;
1051 else
1052 stride_mask = 63;
1053
1054 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1055 return -EINVAL;
1056 if (IS_GEN4(dev_priv) && rec->stride_Y < 512)
1057 return -EINVAL;
1058
1059 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1060 4096 : 8192;
1061 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1062 return -EINVAL;
1063
1064 /* check buffer dimensions */
1065 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1066 case I915_OVERLAY_RGB:
1067 case I915_OVERLAY_YUV_PACKED:
1068 /* always 4 Y values per depth pixels */
1069 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1070 return -EINVAL;
1071
1072 tmp = rec->stride_Y*rec->src_height;
1073 if (rec->offset_Y + tmp > new_bo->base.size)
1074 return -EINVAL;
1075 break;
1076
1077 case I915_OVERLAY_YUV_PLANAR:
1078 if (rec->src_width > rec->stride_Y)
1079 return -EINVAL;
1080 if (rec->src_width/uv_hscale > rec->stride_UV)
1081 return -EINVAL;
1082
1083 tmp = rec->stride_Y * rec->src_height;
1084 if (rec->offset_Y + tmp > new_bo->base.size)
1085 return -EINVAL;
1086
1087 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1088 if (rec->offset_U + tmp > new_bo->base.size ||
1089 rec->offset_V + tmp > new_bo->base.size)
1090 return -EINVAL;
1091 break;
1092 }
1093
1094 return 0;
1095 }
1096
1097 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1098 struct drm_file *file_priv)
1099 {
1100 struct drm_intel_overlay_put_image *put_image_rec = data;
1101 struct drm_i915_private *dev_priv = to_i915(dev);
1102 struct intel_overlay *overlay;
1103 struct drm_crtc *drmmode_crtc;
1104 struct intel_crtc *crtc;
1105 struct drm_i915_gem_object *new_bo;
1106 struct put_image_params *params;
1107 int ret;
1108
1109 overlay = dev_priv->overlay;
1110 if (!overlay) {
1111 DRM_DEBUG("userspace bug: no overlay\n");
1112 return -ENODEV;
1113 }
1114
1115 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1116 drm_modeset_lock_all(dev);
1117 mutex_lock(&dev->struct_mutex);
1118
1119 ret = intel_overlay_switch_off(overlay);
1120
1121 mutex_unlock(&dev->struct_mutex);
1122 drm_modeset_unlock_all(dev);
1123
1124 return ret;
1125 }
1126
1127 params = kmalloc(sizeof(*params), GFP_KERNEL);
1128 if (!params)
1129 return -ENOMEM;
1130
1131 drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
1132 if (!drmmode_crtc) {
1133 ret = -ENOENT;
1134 goto out_free;
1135 }
1136 crtc = to_intel_crtc(drmmode_crtc);
1137
1138 new_bo = i915_gem_object_lookup(file_priv, put_image_rec->bo_handle);
1139 if (!new_bo) {
1140 ret = -ENOENT;
1141 goto out_free;
1142 }
1143
1144 drm_modeset_lock_all(dev);
1145 mutex_lock(&dev->struct_mutex);
1146
1147 if (i915_gem_object_is_tiled(new_bo)) {
1148 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1149 ret = -EINVAL;
1150 goto out_unlock;
1151 }
1152
1153 ret = intel_overlay_recover_from_interrupt(overlay);
1154 if (ret != 0)
1155 goto out_unlock;
1156
1157 if (overlay->crtc != crtc) {
1158 ret = intel_overlay_switch_off(overlay);
1159 if (ret != 0)
1160 goto out_unlock;
1161
1162 ret = check_overlay_possible_on_crtc(overlay, crtc);
1163 if (ret != 0)
1164 goto out_unlock;
1165
1166 overlay->crtc = crtc;
1167 crtc->overlay = overlay;
1168
1169 /* line too wide, i.e. one-line-mode */
1170 if (crtc->config->pipe_src_w > 1024 &&
1171 crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1172 overlay->pfit_active = true;
1173 update_pfit_vscale_ratio(overlay);
1174 } else
1175 overlay->pfit_active = false;
1176 }
1177
1178 ret = check_overlay_dst(overlay, put_image_rec);
1179 if (ret != 0)
1180 goto out_unlock;
1181
1182 if (overlay->pfit_active) {
1183 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1184 overlay->pfit_vscale_ratio);
1185 /* shifting right rounds downwards, so add 1 */
1186 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1187 overlay->pfit_vscale_ratio) + 1;
1188 } else {
1189 params->dst_y = put_image_rec->dst_y;
1190 params->dst_h = put_image_rec->dst_height;
1191 }
1192 params->dst_x = put_image_rec->dst_x;
1193 params->dst_w = put_image_rec->dst_width;
1194
1195 params->src_w = put_image_rec->src_width;
1196 params->src_h = put_image_rec->src_height;
1197 params->src_scan_w = put_image_rec->src_scan_width;
1198 params->src_scan_h = put_image_rec->src_scan_height;
1199 if (params->src_scan_h > params->src_h ||
1200 params->src_scan_w > params->src_w) {
1201 ret = -EINVAL;
1202 goto out_unlock;
1203 }
1204
1205 ret = check_overlay_src(dev_priv, put_image_rec, new_bo);
1206 if (ret != 0)
1207 goto out_unlock;
1208 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1209 params->stride_Y = put_image_rec->stride_Y;
1210 params->stride_UV = put_image_rec->stride_UV;
1211 params->offset_Y = put_image_rec->offset_Y;
1212 params->offset_U = put_image_rec->offset_U;
1213 params->offset_V = put_image_rec->offset_V;
1214
1215 /* Check scaling after src size to prevent a divide-by-zero. */
1216 ret = check_overlay_scaling(params);
1217 if (ret != 0)
1218 goto out_unlock;
1219
1220 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1221 if (ret != 0)
1222 goto out_unlock;
1223
1224 mutex_unlock(&dev->struct_mutex);
1225 drm_modeset_unlock_all(dev);
1226 i915_gem_object_put(new_bo);
1227
1228 kfree(params);
1229
1230 return 0;
1231
1232 out_unlock:
1233 mutex_unlock(&dev->struct_mutex);
1234 drm_modeset_unlock_all(dev);
1235 i915_gem_object_put(new_bo);
1236 out_free:
1237 kfree(params);
1238
1239 return ret;
1240 }
1241
1242 static void update_reg_attrs(struct intel_overlay *overlay,
1243 struct overlay_registers __iomem *regs)
1244 {
1245 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1246 &regs->OCLRC0);
1247 iowrite32(overlay->saturation, &regs->OCLRC1);
1248 }
1249
1250 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1251 {
1252 int i;
1253
1254 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1255 return false;
1256
1257 for (i = 0; i < 3; i++) {
1258 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1259 return false;
1260 }
1261
1262 return true;
1263 }
1264
1265 static bool check_gamma5_errata(u32 gamma5)
1266 {
1267 int i;
1268
1269 for (i = 0; i < 3; i++) {
1270 if (((gamma5 >> i*8) & 0xff) == 0x80)
1271 return false;
1272 }
1273
1274 return true;
1275 }
1276
1277 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1278 {
1279 if (!check_gamma_bounds(0, attrs->gamma0) ||
1280 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1281 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1282 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1283 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1284 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1285 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1286 return -EINVAL;
1287
1288 if (!check_gamma5_errata(attrs->gamma5))
1289 return -EINVAL;
1290
1291 return 0;
1292 }
1293
1294 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1295 struct drm_file *file_priv)
1296 {
1297 struct drm_intel_overlay_attrs *attrs = data;
1298 struct drm_i915_private *dev_priv = to_i915(dev);
1299 struct intel_overlay *overlay;
1300 struct overlay_registers __iomem *regs;
1301 int ret;
1302
1303 overlay = dev_priv->overlay;
1304 if (!overlay) {
1305 DRM_DEBUG("userspace bug: no overlay\n");
1306 return -ENODEV;
1307 }
1308
1309 drm_modeset_lock_all(dev);
1310 mutex_lock(&dev->struct_mutex);
1311
1312 ret = -EINVAL;
1313 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1314 attrs->color_key = overlay->color_key;
1315 attrs->brightness = overlay->brightness;
1316 attrs->contrast = overlay->contrast;
1317 attrs->saturation = overlay->saturation;
1318
1319 if (!IS_GEN2(dev_priv)) {
1320 attrs->gamma0 = I915_READ(OGAMC0);
1321 attrs->gamma1 = I915_READ(OGAMC1);
1322 attrs->gamma2 = I915_READ(OGAMC2);
1323 attrs->gamma3 = I915_READ(OGAMC3);
1324 attrs->gamma4 = I915_READ(OGAMC4);
1325 attrs->gamma5 = I915_READ(OGAMC5);
1326 }
1327 } else {
1328 if (attrs->brightness < -128 || attrs->brightness > 127)
1329 goto out_unlock;
1330 if (attrs->contrast > 255)
1331 goto out_unlock;
1332 if (attrs->saturation > 1023)
1333 goto out_unlock;
1334
1335 overlay->color_key = attrs->color_key;
1336 overlay->brightness = attrs->brightness;
1337 overlay->contrast = attrs->contrast;
1338 overlay->saturation = attrs->saturation;
1339
1340 regs = intel_overlay_map_regs(overlay);
1341 if (!regs) {
1342 ret = -ENOMEM;
1343 goto out_unlock;
1344 }
1345
1346 update_reg_attrs(overlay, regs);
1347
1348 intel_overlay_unmap_regs(overlay, regs);
1349
1350 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1351 if (IS_GEN2(dev_priv))
1352 goto out_unlock;
1353
1354 if (overlay->active) {
1355 ret = -EBUSY;
1356 goto out_unlock;
1357 }
1358
1359 ret = check_gamma(attrs);
1360 if (ret)
1361 goto out_unlock;
1362
1363 I915_WRITE(OGAMC0, attrs->gamma0);
1364 I915_WRITE(OGAMC1, attrs->gamma1);
1365 I915_WRITE(OGAMC2, attrs->gamma2);
1366 I915_WRITE(OGAMC3, attrs->gamma3);
1367 I915_WRITE(OGAMC4, attrs->gamma4);
1368 I915_WRITE(OGAMC5, attrs->gamma5);
1369 }
1370 }
1371 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1372
1373 ret = 0;
1374 out_unlock:
1375 mutex_unlock(&dev->struct_mutex);
1376 drm_modeset_unlock_all(dev);
1377
1378 return ret;
1379 }
1380
1381 void intel_setup_overlay(struct drm_i915_private *dev_priv)
1382 {
1383 struct intel_overlay *overlay;
1384 struct drm_i915_gem_object *reg_bo;
1385 struct overlay_registers __iomem *regs;
1386 struct i915_vma *vma = NULL;
1387 int ret;
1388
1389 if (!HAS_OVERLAY(dev_priv))
1390 return;
1391
1392 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1393 if (!overlay)
1394 return;
1395
1396 mutex_lock(&dev_priv->drm.struct_mutex);
1397 if (WARN_ON(dev_priv->overlay))
1398 goto out_free;
1399
1400 overlay->i915 = dev_priv;
1401
1402 reg_bo = NULL;
1403 if (!OVERLAY_NEEDS_PHYSICAL(dev_priv))
1404 reg_bo = i915_gem_object_create_stolen(dev_priv, PAGE_SIZE);
1405 if (reg_bo == NULL)
1406 reg_bo = i915_gem_object_create(dev_priv, PAGE_SIZE);
1407 if (IS_ERR(reg_bo))
1408 goto out_free;
1409 overlay->reg_bo = reg_bo;
1410
1411 if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) {
1412 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE);
1413 if (ret) {
1414 DRM_ERROR("failed to attach phys overlay regs\n");
1415 goto out_free_bo;
1416 }
1417 overlay->flip_addr = reg_bo->phys_handle->busaddr;
1418 } else {
1419 vma = i915_gem_object_ggtt_pin(reg_bo, NULL,
1420 0, PAGE_SIZE, PIN_MAPPABLE);
1421 if (IS_ERR(vma)) {
1422 DRM_ERROR("failed to pin overlay register bo\n");
1423 ret = PTR_ERR(vma);
1424 goto out_free_bo;
1425 }
1426 overlay->flip_addr = i915_ggtt_offset(vma);
1427
1428 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1429 if (ret) {
1430 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1431 goto out_unpin_bo;
1432 }
1433 }
1434
1435 /* init all values */
1436 overlay->color_key = 0x0101fe;
1437 overlay->color_key_enabled = true;
1438 overlay->brightness = -19;
1439 overlay->contrast = 75;
1440 overlay->saturation = 146;
1441
1442 init_request_active(&overlay->last_flip, NULL);
1443
1444 regs = intel_overlay_map_regs(overlay);
1445 if (!regs)
1446 goto out_unpin_bo;
1447
1448 memset_io(regs, 0, sizeof(struct overlay_registers));
1449 update_polyphase_filter(regs);
1450 update_reg_attrs(overlay, regs);
1451
1452 intel_overlay_unmap_regs(overlay, regs);
1453
1454 dev_priv->overlay = overlay;
1455 mutex_unlock(&dev_priv->drm.struct_mutex);
1456 DRM_INFO("initialized overlay support\n");
1457 return;
1458
1459 out_unpin_bo:
1460 if (vma)
1461 i915_vma_unpin(vma);
1462 out_free_bo:
1463 i915_gem_object_put(reg_bo);
1464 out_free:
1465 mutex_unlock(&dev_priv->drm.struct_mutex);
1466 kfree(overlay);
1467 return;
1468 }
1469
1470 void intel_cleanup_overlay(struct drm_i915_private *dev_priv)
1471 {
1472 if (!dev_priv->overlay)
1473 return;
1474
1475 /* The bo's should be free'd by the generic code already.
1476 * Furthermore modesetting teardown happens beforehand so the
1477 * hardware should be off already */
1478 WARN_ON(dev_priv->overlay->active);
1479
1480 i915_gem_object_put(dev_priv->overlay->reg_bo);
1481 kfree(dev_priv->overlay);
1482 }
1483
1484 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1485
1486 struct intel_overlay_error_state {
1487 struct overlay_registers regs;
1488 unsigned long base;
1489 u32 dovsta;
1490 u32 isr;
1491 };
1492
1493 static struct overlay_registers __iomem *
1494 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1495 {
1496 struct drm_i915_private *dev_priv = overlay->i915;
1497 struct overlay_registers __iomem *regs;
1498
1499 if (OVERLAY_NEEDS_PHYSICAL(dev_priv))
1500 /* Cast to make sparse happy, but it's wc memory anyway, so
1501 * equivalent to the wc io mapping on X86. */
1502 regs = (struct overlay_registers __iomem *)
1503 overlay->reg_bo->phys_handle->vaddr;
1504 else
1505 regs = io_mapping_map_atomic_wc(&dev_priv->ggtt.mappable,
1506 overlay->flip_addr);
1507
1508 return regs;
1509 }
1510
1511 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1512 struct overlay_registers __iomem *regs)
1513 {
1514 if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915))
1515 io_mapping_unmap_atomic(regs);
1516 }
1517
1518 struct intel_overlay_error_state *
1519 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1520 {
1521 struct intel_overlay *overlay = dev_priv->overlay;
1522 struct intel_overlay_error_state *error;
1523 struct overlay_registers __iomem *regs;
1524
1525 if (!overlay || !overlay->active)
1526 return NULL;
1527
1528 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1529 if (error == NULL)
1530 return NULL;
1531
1532 error->dovsta = I915_READ(DOVSTA);
1533 error->isr = I915_READ(ISR);
1534 error->base = overlay->flip_addr;
1535
1536 regs = intel_overlay_map_regs_atomic(overlay);
1537 if (!regs)
1538 goto err;
1539
1540 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1541 intel_overlay_unmap_regs_atomic(overlay, regs);
1542
1543 return error;
1544
1545 err:
1546 kfree(error);
1547 return NULL;
1548 }
1549
1550 void
1551 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1552 struct intel_overlay_error_state *error)
1553 {
1554 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1555 error->dovsta, error->isr);
1556 i915_error_printf(m, " Register file at 0x%08lx:\n",
1557 error->base);
1558
1559 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1560 P(OBUF_0Y);
1561 P(OBUF_1Y);
1562 P(OBUF_0U);
1563 P(OBUF_0V);
1564 P(OBUF_1U);
1565 P(OBUF_1V);
1566 P(OSTRIDE);
1567 P(YRGB_VPH);
1568 P(UV_VPH);
1569 P(HORZ_PH);
1570 P(INIT_PHS);
1571 P(DWINPOS);
1572 P(DWINSZ);
1573 P(SWIDTH);
1574 P(SWIDTHSW);
1575 P(SHEIGHT);
1576 P(YRGBSCALE);
1577 P(UVSCALE);
1578 P(OCLRC0);
1579 P(OCLRC1);
1580 P(DCLRKV);
1581 P(DCLRKM);
1582 P(SCLRKVH);
1583 P(SCLRKVL);
1584 P(SCLRKEN);
1585 P(OCONFIG);
1586 P(OCMD);
1587 P(OSTART_0Y);
1588 P(OSTART_1Y);
1589 P(OSTART_0U);
1590 P(OSTART_0V);
1591 P(OSTART_1U);
1592 P(OSTART_1V);
1593 P(OTILEOFF_0Y);
1594 P(OTILEOFF_1Y);
1595 P(OTILEOFF_0U);
1596 P(OTILEOFF_0V);
1597 P(OTILEOFF_1U);
1598 P(OTILEOFF_1V);
1599 P(FASTHSCALE);
1600 P(UVSCALEV);
1601 #undef P
1602 }
1603
1604 #endif
(deprecated) Btrfs devel tree