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drm/i915: set "ret" correctly on error paths
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / i915 / intel_dsi.c
blob3ffe8b1f1d486f5e7352f50a62091cbb60831c83
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26 #include <drm/drmP.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_mipi_dsi.h>
32 #include <linux/slab.h>
33 #include <linux/gpio/consumer.h>
34 #include "i915_drv.h"
35 #include "intel_drv.h"
36 #include "intel_dsi.h"
37
38 /* return pixels in terms of txbyteclkhs */
39 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
40 u16 burst_mode_ratio)
41 {
42 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
43 8 * 100), lane_count);
44 }
45
46 /* return pixels equvalent to txbyteclkhs */
47 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
48 u16 burst_mode_ratio)
49 {
50 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
51 (bpp * burst_mode_ratio));
52 }
53
54 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
55 {
56 /* It just so happens the VBT matches register contents. */
57 switch (fmt) {
58 case VID_MODE_FORMAT_RGB888:
59 return MIPI_DSI_FMT_RGB888;
60 case VID_MODE_FORMAT_RGB666:
61 return MIPI_DSI_FMT_RGB666;
62 case VID_MODE_FORMAT_RGB666_PACKED:
63 return MIPI_DSI_FMT_RGB666_PACKED;
64 case VID_MODE_FORMAT_RGB565:
65 return MIPI_DSI_FMT_RGB565;
66 default:
67 MISSING_CASE(fmt);
68 return MIPI_DSI_FMT_RGB666;
69 }
70 }
71
72 void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
73 {
74 struct drm_encoder *encoder = &intel_dsi->base.base;
75 struct drm_device *dev = encoder->dev;
76 struct drm_i915_private *dev_priv = to_i915(dev);
77 u32 mask;
78
79 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
80 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
81
82 if (intel_wait_for_register(dev_priv,
83 MIPI_GEN_FIFO_STAT(port), mask, mask,
84 100))
85 DRM_ERROR("DPI FIFOs are not empty\n");
86 }
87
88 static void write_data(struct drm_i915_private *dev_priv,
89 i915_reg_t reg,
90 const u8 *data, u32 len)
91 {
92 u32 i, j;
93
94 for (i = 0; i < len; i += 4) {
95 u32 val = 0;
96
97 for (j = 0; j < min_t(u32, len - i, 4); j++)
98 val |= *data++ << 8 * j;
99
100 I915_WRITE(reg, val);
101 }
102 }
103
104 static void read_data(struct drm_i915_private *dev_priv,
105 i915_reg_t reg,
106 u8 *data, u32 len)
107 {
108 u32 i, j;
109
110 for (i = 0; i < len; i += 4) {
111 u32 val = I915_READ(reg);
112
113 for (j = 0; j < min_t(u32, len - i, 4); j++)
114 *data++ = val >> 8 * j;
115 }
116 }
117
118 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
119 const struct mipi_dsi_msg *msg)
120 {
121 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
122 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
123 struct drm_i915_private *dev_priv = to_i915(dev);
124 enum port port = intel_dsi_host->port;
125 struct mipi_dsi_packet packet;
126 ssize_t ret;
127 const u8 *header, *data;
128 i915_reg_t data_reg, ctrl_reg;
129 u32 data_mask, ctrl_mask;
130
131 ret = mipi_dsi_create_packet(&packet, msg);
132 if (ret < 0)
133 return ret;
134
135 header = packet.header;
136 data = packet.payload;
137
138 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
139 data_reg = MIPI_LP_GEN_DATA(port);
140 data_mask = LP_DATA_FIFO_FULL;
141 ctrl_reg = MIPI_LP_GEN_CTRL(port);
142 ctrl_mask = LP_CTRL_FIFO_FULL;
143 } else {
144 data_reg = MIPI_HS_GEN_DATA(port);
145 data_mask = HS_DATA_FIFO_FULL;
146 ctrl_reg = MIPI_HS_GEN_CTRL(port);
147 ctrl_mask = HS_CTRL_FIFO_FULL;
148 }
149
150 /* note: this is never true for reads */
151 if (packet.payload_length) {
152 if (intel_wait_for_register(dev_priv,
153 MIPI_GEN_FIFO_STAT(port),
154 data_mask, 0,
155 50))
156 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
157
158 write_data(dev_priv, data_reg, packet.payload,
159 packet.payload_length);
160 }
161
162 if (msg->rx_len) {
163 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
164 }
165
166 if (intel_wait_for_register(dev_priv,
167 MIPI_GEN_FIFO_STAT(port),
168 ctrl_mask, 0,
169 50)) {
170 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
171 }
172
173 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
174
175 /* ->rx_len is set only for reads */
176 if (msg->rx_len) {
177 data_mask = GEN_READ_DATA_AVAIL;
178 if (intel_wait_for_register(dev_priv,
179 MIPI_INTR_STAT(port),
180 data_mask, data_mask,
181 50))
182 DRM_ERROR("Timeout waiting for read data.\n");
183
184 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
185 }
186
187 /* XXX: fix for reads and writes */
188 return 4 + packet.payload_length;
189 }
190
191 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
192 struct mipi_dsi_device *dsi)
193 {
194 return 0;
195 }
196
197 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
198 struct mipi_dsi_device *dsi)
199 {
200 return 0;
201 }
202
203 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
204 .attach = intel_dsi_host_attach,
205 .detach = intel_dsi_host_detach,
206 .transfer = intel_dsi_host_transfer,
207 };
208
209 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
210 enum port port)
211 {
212 struct intel_dsi_host *host;
213 struct mipi_dsi_device *device;
214
215 host = kzalloc(sizeof(*host), GFP_KERNEL);
216 if (!host)
217 return NULL;
218
219 host->base.ops = &intel_dsi_host_ops;
220 host->intel_dsi = intel_dsi;
221 host->port = port;
222
223 /*
224 * We should call mipi_dsi_host_register(&host->base) here, but we don't
225 * have a host->dev, and we don't have OF stuff either. So just use the
226 * dsi framework as a library and hope for the best. Create the dsi
227 * devices by ourselves here too. Need to be careful though, because we
228 * don't initialize any of the driver model devices here.
229 */
230 device = kzalloc(sizeof(*device), GFP_KERNEL);
231 if (!device) {
232 kfree(host);
233 return NULL;
234 }
235
236 device->host = &host->base;
237 host->device = device;
238
239 return host;
240 }
241
242 /*
243 * send a video mode command
244 *
245 * XXX: commands with data in MIPI_DPI_DATA?
246 */
247 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
248 enum port port)
249 {
250 struct drm_encoder *encoder = &intel_dsi->base.base;
251 struct drm_device *dev = encoder->dev;
252 struct drm_i915_private *dev_priv = to_i915(dev);
253 u32 mask;
254
255 /* XXX: pipe, hs */
256 if (hs)
257 cmd &= ~DPI_LP_MODE;
258 else
259 cmd |= DPI_LP_MODE;
260
261 /* clear bit */
262 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
263
264 /* XXX: old code skips write if control unchanged */
265 if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
266 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
267
268 I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
269
270 mask = SPL_PKT_SENT_INTERRUPT;
271 if (intel_wait_for_register(dev_priv,
272 MIPI_INTR_STAT(port), mask, mask,
273 100))
274 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
275
276 return 0;
277 }
278
279 static void band_gap_reset(struct drm_i915_private *dev_priv)
280 {
281 mutex_lock(&dev_priv->sb_lock);
282
283 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
284 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
285 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
286 udelay(150);
287 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
288 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
289
290 mutex_unlock(&dev_priv->sb_lock);
291 }
292
293 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
294 {
295 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
296 }
297
298 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
299 {
300 return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
301 }
302
303 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
304 struct intel_crtc_state *pipe_config,
305 struct drm_connector_state *conn_state)
306 {
307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
308 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
309 base);
310 struct intel_connector *intel_connector = intel_dsi->attached_connector;
311 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
312 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
313 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
314 int ret;
315
316 DRM_DEBUG_KMS("\n");
317
318 if (fixed_mode) {
319 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
320
321 if (HAS_GMCH_DISPLAY(dev_priv))
322 intel_gmch_panel_fitting(crtc, pipe_config,
323 intel_connector->panel.fitting_mode);
324 else
325 intel_pch_panel_fitting(crtc, pipe_config,
326 intel_connector->panel.fitting_mode);
327 }
328
329 /* DSI uses short packets for sync events, so clear mode flags for DSI */
330 adjusted_mode->flags = 0;
331
332 if (IS_GEN9_LP(dev_priv)) {
333 /* Dual link goes to DSI transcoder A. */
334 if (intel_dsi->ports == BIT(PORT_C))
335 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
336 else
337 pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
338 }
339
340 ret = intel_compute_dsi_pll(encoder, pipe_config);
341 if (ret)
342 return false;
343
344 pipe_config->clock_set = true;
345
346 return true;
347 }
348
349 static void glk_dsi_device_ready(struct intel_encoder *encoder)
350 {
351 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
352 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
353 enum port port;
354 u32 tmp, val;
355
356 /* Set the MIPI mode
357 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
358 * Power ON MIPI IO first and then write into IO reset and LP wake bits
359 */
360 for_each_dsi_port(port, intel_dsi->ports) {
361 tmp = I915_READ(MIPI_CTRL(port));
362 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
363 }
364
365 /* Put the IO into reset */
366 tmp = I915_READ(MIPI_CTRL(PORT_A));
367 tmp &= ~GLK_MIPIIO_RESET_RELEASED;
368 I915_WRITE(MIPI_CTRL(PORT_A), tmp);
369
370 /* Program LP Wake */
371 for_each_dsi_port(port, intel_dsi->ports) {
372 tmp = I915_READ(MIPI_CTRL(port));
373 tmp |= GLK_LP_WAKE;
374 I915_WRITE(MIPI_CTRL(port), tmp);
375 }
376
377 /* Wait for Pwr ACK */
378 for_each_dsi_port(port, intel_dsi->ports) {
379 if (intel_wait_for_register(dev_priv,
380 MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
381 GLK_MIPIIO_PORT_POWERED, 20))
382 DRM_ERROR("MIPIO port is powergated\n");
383 }
384
385 /* Wait for MIPI PHY status bit to set */
386 for_each_dsi_port(port, intel_dsi->ports) {
387 if (intel_wait_for_register(dev_priv,
388 MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
389 GLK_PHY_STATUS_PORT_READY, 20))
390 DRM_ERROR("PHY is not ON\n");
391 }
392
393 /* Get IO out of reset */
394 tmp = I915_READ(MIPI_CTRL(PORT_A));
395 I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
396
397 /* Get IO out of Low power state*/
398 for_each_dsi_port(port, intel_dsi->ports) {
399 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
400 val = I915_READ(MIPI_DEVICE_READY(port));
401 val &= ~ULPS_STATE_MASK;
402 val |= DEVICE_READY;
403 I915_WRITE(MIPI_DEVICE_READY(port), val);
404 usleep_range(10, 15);
405 }
406
407 /* Enter ULPS */
408 val = I915_READ(MIPI_DEVICE_READY(port));
409 val &= ~ULPS_STATE_MASK;
410 val |= (ULPS_STATE_ENTER | DEVICE_READY);
411 I915_WRITE(MIPI_DEVICE_READY(port), val);
412
413 /* Wait for ULPS Not active */
414 if (intel_wait_for_register(dev_priv,
415 MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
416 GLK_ULPS_NOT_ACTIVE, 20))
417 DRM_ERROR("ULPS is still active\n");
418
419 /* Exit ULPS */
420 val = I915_READ(MIPI_DEVICE_READY(port));
421 val &= ~ULPS_STATE_MASK;
422 val |= (ULPS_STATE_EXIT | DEVICE_READY);
423 I915_WRITE(MIPI_DEVICE_READY(port), val);
424
425 /* Enter Normal Mode */
426 val = I915_READ(MIPI_DEVICE_READY(port));
427 val &= ~ULPS_STATE_MASK;
428 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
429 I915_WRITE(MIPI_DEVICE_READY(port), val);
430
431 tmp = I915_READ(MIPI_CTRL(port));
432 tmp &= ~GLK_LP_WAKE;
433 I915_WRITE(MIPI_CTRL(port), tmp);
434 }
435
436 /* Wait for Stop state */
437 for_each_dsi_port(port, intel_dsi->ports) {
438 if (intel_wait_for_register(dev_priv,
439 MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
440 GLK_DATA_LANE_STOP_STATE, 20))
441 DRM_ERROR("Date lane not in STOP state\n");
442 }
443
444 /* Wait for AFE LATCH */
445 for_each_dsi_port(port, intel_dsi->ports) {
446 if (intel_wait_for_register(dev_priv,
447 BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
448 AFE_LATCHOUT, 20))
449 DRM_ERROR("D-PHY not entering LP-11 state\n");
450 }
451 }
452
453 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
454 {
455 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
456 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
457 enum port port;
458 u32 val;
459
460 DRM_DEBUG_KMS("\n");
461
462 /* Enable MIPI PHY transparent latch */
463 for_each_dsi_port(port, intel_dsi->ports) {
464 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
465 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
466 usleep_range(2000, 2500);
467 }
468
469 /* Clear ULPS and set device ready */
470 for_each_dsi_port(port, intel_dsi->ports) {
471 val = I915_READ(MIPI_DEVICE_READY(port));
472 val &= ~ULPS_STATE_MASK;
473 I915_WRITE(MIPI_DEVICE_READY(port), val);
474 usleep_range(2000, 2500);
475 val |= DEVICE_READY;
476 I915_WRITE(MIPI_DEVICE_READY(port), val);
477 }
478 }
479
480 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
481 {
482 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
483 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
484 enum port port;
485 u32 val;
486
487 DRM_DEBUG_KMS("\n");
488
489 mutex_lock(&dev_priv->sb_lock);
490 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
491 * needed everytime after power gate */
492 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
493 mutex_unlock(&dev_priv->sb_lock);
494
495 /* bandgap reset is needed after everytime we do power gate */
496 band_gap_reset(dev_priv);
497
498 for_each_dsi_port(port, intel_dsi->ports) {
499
500 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
501 usleep_range(2500, 3000);
502
503 /* Enable MIPI PHY transparent latch
504 * Common bit for both MIPI Port A & MIPI Port C
505 * No similar bit in MIPI Port C reg
506 */
507 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
508 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
509 usleep_range(1000, 1500);
510
511 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
512 usleep_range(2500, 3000);
513
514 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
515 usleep_range(2500, 3000);
516 }
517 }
518
519 static void intel_dsi_device_ready(struct intel_encoder *encoder)
520 {
521 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
522
523 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
524 vlv_dsi_device_ready(encoder);
525 else if (IS_BROXTON(dev_priv))
526 bxt_dsi_device_ready(encoder);
527 else if (IS_GEMINILAKE(dev_priv))
528 glk_dsi_device_ready(encoder);
529 }
530
531 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
532 {
533 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
534 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
535 enum port port;
536 u32 val;
537
538 /* Enter ULPS */
539 for_each_dsi_port(port, intel_dsi->ports) {
540 val = I915_READ(MIPI_DEVICE_READY(port));
541 val &= ~ULPS_STATE_MASK;
542 val |= (ULPS_STATE_ENTER | DEVICE_READY);
543 I915_WRITE(MIPI_DEVICE_READY(port), val);
544 }
545
546 /* Wait for MIPI PHY status bit to unset */
547 for_each_dsi_port(port, intel_dsi->ports) {
548 if (intel_wait_for_register(dev_priv,
549 MIPI_CTRL(port),
550 GLK_PHY_STATUS_PORT_READY, 0, 20))
551 DRM_ERROR("PHY is not turning OFF\n");
552 }
553
554 /* Wait for Pwr ACK bit to unset */
555 for_each_dsi_port(port, intel_dsi->ports) {
556 if (intel_wait_for_register(dev_priv,
557 MIPI_CTRL(port),
558 GLK_MIPIIO_PORT_POWERED, 0, 20))
559 DRM_ERROR("MIPI IO Port is not powergated\n");
560 }
561 }
562
563 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
564 {
565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
566 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
567 enum port port;
568 u32 tmp;
569
570 /* Put the IO into reset */
571 tmp = I915_READ(MIPI_CTRL(PORT_A));
572 tmp &= ~GLK_MIPIIO_RESET_RELEASED;
573 I915_WRITE(MIPI_CTRL(PORT_A), tmp);
574
575 /* Wait for MIPI PHY status bit to unset */
576 for_each_dsi_port(port, intel_dsi->ports) {
577 if (intel_wait_for_register(dev_priv,
578 MIPI_CTRL(port),
579 GLK_PHY_STATUS_PORT_READY, 0, 20))
580 DRM_ERROR("PHY is not turning OFF\n");
581 }
582
583 /* Clear MIPI mode */
584 for_each_dsi_port(port, intel_dsi->ports) {
585 tmp = I915_READ(MIPI_CTRL(port));
586 tmp &= ~GLK_MIPIIO_ENABLE;
587 I915_WRITE(MIPI_CTRL(port), tmp);
588 }
589 }
590
591 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
592 {
593 glk_dsi_enter_low_power_mode(encoder);
594 glk_dsi_disable_mipi_io(encoder);
595 }
596
597 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
598 {
599 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
600 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
601 enum port port;
602
603 DRM_DEBUG_KMS("\n");
604 for_each_dsi_port(port, intel_dsi->ports) {
605 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
606 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
607 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
608 u32 val;
609
610 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
611 ULPS_STATE_ENTER);
612 usleep_range(2000, 2500);
613
614 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
615 ULPS_STATE_EXIT);
616 usleep_range(2000, 2500);
617
618 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
619 ULPS_STATE_ENTER);
620 usleep_range(2000, 2500);
621
622 /*
623 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
624 * Port A only. MIPI Port C has no similar bit for checking.
625 */
626 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
627 intel_wait_for_register(dev_priv,
628 port_ctrl, AFE_LATCHOUT, 0,
629 30))
630 DRM_ERROR("DSI LP not going Low\n");
631
632 /* Disable MIPI PHY transparent latch */
633 val = I915_READ(port_ctrl);
634 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
635 usleep_range(1000, 1500);
636
637 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
638 usleep_range(2000, 2500);
639 }
640 }
641
642 static void intel_dsi_port_enable(struct intel_encoder *encoder)
643 {
644 struct drm_device *dev = encoder->base.dev;
645 struct drm_i915_private *dev_priv = to_i915(dev);
646 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
647 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
648 enum port port;
649
650 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
651 u32 temp;
652 if (IS_GEN9_LP(dev_priv)) {
653 for_each_dsi_port(port, intel_dsi->ports) {
654 temp = I915_READ(MIPI_CTRL(port));
655 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
656 intel_dsi->pixel_overlap <<
657 BXT_PIXEL_OVERLAP_CNT_SHIFT;
658 I915_WRITE(MIPI_CTRL(port), temp);
659 }
660 } else {
661 temp = I915_READ(VLV_CHICKEN_3);
662 temp &= ~PIXEL_OVERLAP_CNT_MASK |
663 intel_dsi->pixel_overlap <<
664 PIXEL_OVERLAP_CNT_SHIFT;
665 I915_WRITE(VLV_CHICKEN_3, temp);
666 }
667 }
668
669 for_each_dsi_port(port, intel_dsi->ports) {
670 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
671 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
672 u32 temp;
673
674 temp = I915_READ(port_ctrl);
675
676 temp &= ~LANE_CONFIGURATION_MASK;
677 temp &= ~DUAL_LINK_MODE_MASK;
678
679 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
680 temp |= (intel_dsi->dual_link - 1)
681 << DUAL_LINK_MODE_SHIFT;
682 if (IS_BROXTON(dev_priv))
683 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
684 else
685 temp |= intel_crtc->pipe ?
686 LANE_CONFIGURATION_DUAL_LINK_B :
687 LANE_CONFIGURATION_DUAL_LINK_A;
688 }
689 /* assert ip_tg_enable signal */
690 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
691 POSTING_READ(port_ctrl);
692 }
693 }
694
695 static void intel_dsi_port_disable(struct intel_encoder *encoder)
696 {
697 struct drm_device *dev = encoder->base.dev;
698 struct drm_i915_private *dev_priv = to_i915(dev);
699 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
700 enum port port;
701
702 for_each_dsi_port(port, intel_dsi->ports) {
703 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
704 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
705 u32 temp;
706
707 /* de-assert ip_tg_enable signal */
708 temp = I915_READ(port_ctrl);
709 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
710 POSTING_READ(port_ctrl);
711 }
712 }
713
714 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
715 struct intel_crtc_state *pipe_config);
716 static void intel_dsi_unprepare(struct intel_encoder *encoder);
717
718 static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
719 {
720 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
721
722 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
723 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
724 return;
725
726 msleep(msec);
727 }
728
729 /*
730 * Panel enable/disable sequences from the VBT spec.
731 *
732 * Note the spec has AssertReset / DeassertReset swapped from their
733 * usual naming. We use the normal names to avoid confusion (so below
734 * they are swapped compared to the spec).
735 *
736 * Steps starting with MIPI refer to VBT sequences, note that for v2
737 * VBTs several steps which have a VBT in v2 are expected to be handled
738 * directly by the driver, by directly driving gpios for example.
739 *
740 * v2 video mode seq v3 video mode seq command mode seq
741 * - power on - MIPIPanelPowerOn - power on
742 * - wait t1+t2 - wait t1+t2
743 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
744 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
745 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
746 * - MIPITearOn
747 * - MIPIDisplayOn
748 * - turn on DPI - turn on DPI - set pipe to dsr mode
749 * - MIPIDisplayOn - MIPIDisplayOn
750 * - wait t5 - wait t5
751 * - backlight on - MIPIBacklightOn - backlight on
752 * ... ... ... issue mem cmds ...
753 * - backlight off - MIPIBacklightOff - backlight off
754 * - wait t6 - wait t6
755 * - MIPIDisplayOff
756 * - turn off DPI - turn off DPI - disable pipe dsr mode
757 * - MIPITearOff
758 * - MIPIDisplayOff - MIPIDisplayOff
759 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
760 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
761 * - wait t3 - wait t3
762 * - power off - MIPIPanelPowerOff - power off
763 * - wait t4 - wait t4
764 */
765
766 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
767 struct intel_crtc_state *pipe_config,
768 struct drm_connector_state *conn_state)
769 {
770 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
771 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
772 enum port port;
773 u32 val;
774
775 DRM_DEBUG_KMS("\n");
776
777 /*
778 * The BIOS may leave the PLL in a wonky state where it doesn't
779 * lock. It needs to be fully powered down to fix it.
780 */
781 intel_disable_dsi_pll(encoder);
782 intel_enable_dsi_pll(encoder, pipe_config);
783
784 if (IS_BROXTON(dev_priv)) {
785 /* Add MIPI IO reset programming for modeset */
786 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
787 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
788 val | MIPIO_RST_CTRL);
789
790 /* Power up DSI regulator */
791 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
792 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
793 }
794
795 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
796 u32 val;
797
798 /* Disable DPOunit clock gating, can stall pipe */
799 val = I915_READ(DSPCLK_GATE_D);
800 val |= DPOUNIT_CLOCK_GATE_DISABLE;
801 I915_WRITE(DSPCLK_GATE_D, val);
802 }
803
804 intel_dsi_prepare(encoder, pipe_config);
805
806 /* Power on, try both CRC pmic gpio and VBT */
807 if (intel_dsi->gpio_panel)
808 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
809 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
810 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
811
812 /* Deassert reset */
813 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
814
815 /* Put device in ready state (LP-11) */
816 intel_dsi_device_ready(encoder);
817
818 /* Send initialization commands in LP mode */
819 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
820
821 /* Enable port in pre-enable phase itself because as per hw team
822 * recommendation, port should be enabled befor plane & pipe */
823 if (is_cmd_mode(intel_dsi)) {
824 for_each_dsi_port(port, intel_dsi->ports)
825 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
826 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
827 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
828 } else {
829 msleep(20); /* XXX */
830 for_each_dsi_port(port, intel_dsi->ports)
831 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
832 intel_dsi_msleep(intel_dsi, 100);
833
834 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
835
836 intel_dsi_port_enable(encoder);
837 }
838
839 intel_panel_enable_backlight(intel_dsi->attached_connector);
840 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
841 }
842
843 /*
844 * DSI port enable has to be done before pipe and plane enable, so we do it in
845 * the pre_enable hook.
846 */
847 static void intel_dsi_enable_nop(struct intel_encoder *encoder,
848 struct intel_crtc_state *pipe_config,
849 struct drm_connector_state *conn_state)
850 {
851 DRM_DEBUG_KMS("\n");
852 }
853
854 /*
855 * DSI port disable has to be done after pipe and plane disable, so we do it in
856 * the post_disable hook.
857 */
858 static void intel_dsi_disable(struct intel_encoder *encoder,
859 struct intel_crtc_state *old_crtc_state,
860 struct drm_connector_state *old_conn_state)
861 {
862 struct drm_device *dev = encoder->base.dev;
863 struct drm_i915_private *dev_priv = dev->dev_private;
864 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
865 enum port port;
866
867 DRM_DEBUG_KMS("\n");
868
869 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
870 intel_panel_disable_backlight(intel_dsi->attached_connector);
871
872 /*
873 * Disable Device ready before the port shutdown in order
874 * to avoid split screen
875 */
876 if (IS_BROXTON(dev_priv)) {
877 for_each_dsi_port(port, intel_dsi->ports)
878 I915_WRITE(MIPI_DEVICE_READY(port), 0);
879 }
880
881 /*
882 * According to the spec we should send SHUTDOWN before
883 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
884 * has shown that the v3 sequence works for v2 VBTs too
885 */
886 if (is_vid_mode(intel_dsi)) {
887 /* Send Shutdown command to the panel in LP mode */
888 for_each_dsi_port(port, intel_dsi->ports)
889 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
890 msleep(10);
891 }
892 }
893
894 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
895 {
896 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
897
898 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
899 IS_BROXTON(dev_priv))
900 vlv_dsi_clear_device_ready(encoder);
901 else if (IS_GEMINILAKE(dev_priv))
902 glk_dsi_clear_device_ready(encoder);
903 }
904
905 static void intel_dsi_post_disable(struct intel_encoder *encoder,
906 struct intel_crtc_state *pipe_config,
907 struct drm_connector_state *conn_state)
908 {
909 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
910 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
911 enum port port;
912 u32 val;
913
914 DRM_DEBUG_KMS("\n");
915
916 if (is_vid_mode(intel_dsi)) {
917 for_each_dsi_port(port, intel_dsi->ports)
918 wait_for_dsi_fifo_empty(intel_dsi, port);
919
920 intel_dsi_port_disable(encoder);
921 usleep_range(2000, 5000);
922 }
923
924 intel_dsi_unprepare(encoder);
925
926 /*
927 * if disable packets are sent before sending shutdown packet then in
928 * some next enable sequence send turn on packet error is observed
929 */
930 if (is_cmd_mode(intel_dsi))
931 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
932 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
933
934 /* Transition to LP-00 */
935 intel_dsi_clear_device_ready(encoder);
936
937 if (IS_BROXTON(dev_priv)) {
938 /* Power down DSI regulator to save power */
939 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
940 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
941
942 /* Add MIPI IO reset programming for modeset */
943 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
944 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
945 val & ~MIPIO_RST_CTRL);
946 }
947
948 intel_disable_dsi_pll(encoder);
949
950 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
951 u32 val;
952
953 val = I915_READ(DSPCLK_GATE_D);
954 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
955 I915_WRITE(DSPCLK_GATE_D, val);
956 }
957
958 /* Assert reset */
959 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
960
961 /* Power off, try both CRC pmic gpio and VBT */
962 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
963 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
964 if (intel_dsi->gpio_panel)
965 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
966
967 /*
968 * FIXME As we do with eDP, just make a note of the time here
969 * and perform the wait before the next panel power on.
970 */
971 intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
972 }
973
974 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
975 enum pipe *pipe)
976 {
977 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
978 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
979 enum port port;
980 bool active = false;
981
982 DRM_DEBUG_KMS("\n");
983
984 if (!intel_display_power_get_if_enabled(dev_priv,
985 encoder->power_domain))
986 return false;
987
988 /*
989 * On Broxton the PLL needs to be enabled with a valid divider
990 * configuration, otherwise accessing DSI registers will hang the
991 * machine. See BSpec North Display Engine registers/MIPI[BXT].
992 */
993 if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
994 goto out_put_power;
995
996 /* XXX: this only works for one DSI output */
997 for_each_dsi_port(port, intel_dsi->ports) {
998 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
999 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
1000 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
1001
1002 /*
1003 * Due to some hardware limitations on VLV/CHV, the DPI enable
1004 * bit in port C control register does not get set. As a
1005 * workaround, check pipe B conf instead.
1006 */
1007 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1008 port == PORT_C)
1009 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1010
1011 /* Try command mode if video mode not enabled */
1012 if (!enabled) {
1013 u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
1014 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1015 }
1016
1017 if (!enabled)
1018 continue;
1019
1020 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1021 continue;
1022
1023 if (IS_GEN9_LP(dev_priv)) {
1024 u32 tmp = I915_READ(MIPI_CTRL(port));
1025 tmp &= BXT_PIPE_SELECT_MASK;
1026 tmp >>= BXT_PIPE_SELECT_SHIFT;
1027
1028 if (WARN_ON(tmp > PIPE_C))
1029 continue;
1030
1031 *pipe = tmp;
1032 } else {
1033 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1034 }
1035
1036 active = true;
1037 break;
1038 }
1039
1040 out_put_power:
1041 intel_display_power_put(dev_priv, encoder->power_domain);
1042
1043 return active;
1044 }
1045
1046 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1047 struct intel_crtc_state *pipe_config)
1048 {
1049 struct drm_device *dev = encoder->base.dev;
1050 struct drm_i915_private *dev_priv = to_i915(dev);
1051 struct drm_display_mode *adjusted_mode =
1052 &pipe_config->base.adjusted_mode;
1053 struct drm_display_mode *adjusted_mode_sw;
1054 struct intel_crtc *intel_crtc;
1055 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1056 unsigned int lane_count = intel_dsi->lane_count;
1057 unsigned int bpp, fmt;
1058 enum port port;
1059 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1060 u16 hfp_sw, hsync_sw, hbp_sw;
1061 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1062 crtc_hblank_start_sw, crtc_hblank_end_sw;
1063
1064 /* FIXME: hw readout should not depend on SW state */
1065 intel_crtc = to_intel_crtc(encoder->base.crtc);
1066 adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode;
1067
1068 /*
1069 * Atleast one port is active as encoder->get_config called only if
1070 * encoder->get_hw_state() returns true.
1071 */
1072 for_each_dsi_port(port, intel_dsi->ports) {
1073 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1074 break;
1075 }
1076
1077 fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1078 pipe_config->pipe_bpp =
1079 mipi_dsi_pixel_format_to_bpp(
1080 pixel_format_from_register_bits(fmt));
1081 bpp = pipe_config->pipe_bpp;
1082
1083 /* In terms of pixels */
1084 adjusted_mode->crtc_hdisplay =
1085 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1086 adjusted_mode->crtc_vdisplay =
1087 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1088 adjusted_mode->crtc_vtotal =
1089 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1090
1091 hactive = adjusted_mode->crtc_hdisplay;
1092 hfp = I915_READ(MIPI_HFP_COUNT(port));
1093
1094 /*
1095 * Meaningful for video mode non-burst sync pulse mode only,
1096 * can be zero for non-burst sync events and burst modes
1097 */
1098 hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1099 hbp = I915_READ(MIPI_HBP_COUNT(port));
1100
1101 /* harizontal values are in terms of high speed byte clock */
1102 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1103 intel_dsi->burst_mode_ratio);
1104 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1105 intel_dsi->burst_mode_ratio);
1106 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1107 intel_dsi->burst_mode_ratio);
1108
1109 if (intel_dsi->dual_link) {
1110 hfp *= 2;
1111 hsync *= 2;
1112 hbp *= 2;
1113 }
1114
1115 /* vertical values are in terms of lines */
1116 vfp = I915_READ(MIPI_VFP_COUNT(port));
1117 vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1118 vbp = I915_READ(MIPI_VBP_COUNT(port));
1119
1120 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1121 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1122 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1123 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1124 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1125
1126 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1127 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1128 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1129 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1130
1131 /*
1132 * In BXT DSI there is no regs programmed with few horizontal timings
1133 * in Pixels but txbyteclkhs.. So retrieval process adds some
1134 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1135 * Actually here for the given adjusted_mode, we are calculating the
1136 * value programmed to the port and then back to the horizontal timing
1137 * param in pixels. This is the expected value, including roundup errors
1138 * And if that is same as retrieved value from port, then
1139 * (HW state) adjusted_mode's horizontal timings are corrected to
1140 * match with SW state to nullify the errors.
1141 */
1142 /* Calculating the value programmed to the Port register */
1143 hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1144 adjusted_mode_sw->crtc_hdisplay;
1145 hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1146 adjusted_mode_sw->crtc_hsync_start;
1147 hbp_sw = adjusted_mode_sw->crtc_htotal -
1148 adjusted_mode_sw->crtc_hsync_end;
1149
1150 if (intel_dsi->dual_link) {
1151 hfp_sw /= 2;
1152 hsync_sw /= 2;
1153 hbp_sw /= 2;
1154 }
1155
1156 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1157 intel_dsi->burst_mode_ratio);
1158 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1159 intel_dsi->burst_mode_ratio);
1160 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1161 intel_dsi->burst_mode_ratio);
1162
1163 /* Reverse calculating the adjusted mode parameters from port reg vals*/
1164 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1165 intel_dsi->burst_mode_ratio);
1166 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1167 intel_dsi->burst_mode_ratio);
1168 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1169 intel_dsi->burst_mode_ratio);
1170
1171 if (intel_dsi->dual_link) {
1172 hfp_sw *= 2;
1173 hsync_sw *= 2;
1174 hbp_sw *= 2;
1175 }
1176
1177 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1178 hsync_sw + hbp_sw;
1179 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1180 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1181 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1182 crtc_hblank_end_sw = crtc_htotal_sw;
1183
1184 if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1185 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1186
1187 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1188 adjusted_mode->crtc_hsync_start =
1189 adjusted_mode_sw->crtc_hsync_start;
1190
1191 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1192 adjusted_mode->crtc_hsync_end =
1193 adjusted_mode_sw->crtc_hsync_end;
1194
1195 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1196 adjusted_mode->crtc_hblank_start =
1197 adjusted_mode_sw->crtc_hblank_start;
1198
1199 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1200 adjusted_mode->crtc_hblank_end =
1201 adjusted_mode_sw->crtc_hblank_end;
1202 }
1203
1204 static void intel_dsi_get_config(struct intel_encoder *encoder,
1205 struct intel_crtc_state *pipe_config)
1206 {
1207 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1208 u32 pclk;
1209 DRM_DEBUG_KMS("\n");
1210
1211 if (IS_GEN9_LP(dev_priv))
1212 bxt_dsi_get_pipe_config(encoder, pipe_config);
1213
1214 pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
1215 pipe_config);
1216 if (!pclk)
1217 return;
1218
1219 pipe_config->base.adjusted_mode.crtc_clock = pclk;
1220 pipe_config->port_clock = pclk;
1221 }
1222
1223 static enum drm_mode_status
1224 intel_dsi_mode_valid(struct drm_connector *connector,
1225 struct drm_display_mode *mode)
1226 {
1227 struct intel_connector *intel_connector = to_intel_connector(connector);
1228 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
1229 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1230
1231 DRM_DEBUG_KMS("\n");
1232
1233 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
1234 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
1235 return MODE_NO_DBLESCAN;
1236 }
1237
1238 if (fixed_mode) {
1239 if (mode->hdisplay > fixed_mode->hdisplay)
1240 return MODE_PANEL;
1241 if (mode->vdisplay > fixed_mode->vdisplay)
1242 return MODE_PANEL;
1243 if (fixed_mode->clock > max_dotclk)
1244 return MODE_CLOCK_HIGH;
1245 }
1246
1247 return MODE_OK;
1248 }
1249
1250 /* return txclkesc cycles in terms of divider and duration in us */
1251 static u16 txclkesc(u32 divider, unsigned int us)
1252 {
1253 switch (divider) {
1254 case ESCAPE_CLOCK_DIVIDER_1:
1255 default:
1256 return 20 * us;
1257 case ESCAPE_CLOCK_DIVIDER_2:
1258 return 10 * us;
1259 case ESCAPE_CLOCK_DIVIDER_4:
1260 return 5 * us;
1261 }
1262 }
1263
1264 static void set_dsi_timings(struct drm_encoder *encoder,
1265 const struct drm_display_mode *adjusted_mode)
1266 {
1267 struct drm_device *dev = encoder->dev;
1268 struct drm_i915_private *dev_priv = to_i915(dev);
1269 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1270 enum port port;
1271 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1272 unsigned int lane_count = intel_dsi->lane_count;
1273
1274 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1275
1276 hactive = adjusted_mode->crtc_hdisplay;
1277 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1278 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1279 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1280
1281 if (intel_dsi->dual_link) {
1282 hactive /= 2;
1283 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1284 hactive += intel_dsi->pixel_overlap;
1285 hfp /= 2;
1286 hsync /= 2;
1287 hbp /= 2;
1288 }
1289
1290 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1291 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1292 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1293
1294 /* horizontal values are in terms of high speed byte clock */
1295 hactive = txbyteclkhs(hactive, bpp, lane_count,
1296 intel_dsi->burst_mode_ratio);
1297 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1298 hsync = txbyteclkhs(hsync, bpp, lane_count,
1299 intel_dsi->burst_mode_ratio);
1300 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1301
1302 for_each_dsi_port(port, intel_dsi->ports) {
1303 if (IS_GEN9_LP(dev_priv)) {
1304 /*
1305 * Program hdisplay and vdisplay on MIPI transcoder.
1306 * This is different from calculated hactive and
1307 * vactive, as they are calculated per channel basis,
1308 * whereas these values should be based on resolution.
1309 */
1310 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1311 adjusted_mode->crtc_hdisplay);
1312 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1313 adjusted_mode->crtc_vdisplay);
1314 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1315 adjusted_mode->crtc_vtotal);
1316 }
1317
1318 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1319 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1320
1321 /* meaningful for video mode non-burst sync pulse mode only,
1322 * can be zero for non-burst sync events and burst modes */
1323 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1324 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1325
1326 /* vertical values are in terms of lines */
1327 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1328 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1329 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1330 }
1331 }
1332
1333 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1334 {
1335 switch (fmt) {
1336 case MIPI_DSI_FMT_RGB888:
1337 return VID_MODE_FORMAT_RGB888;
1338 case MIPI_DSI_FMT_RGB666:
1339 return VID_MODE_FORMAT_RGB666;
1340 case MIPI_DSI_FMT_RGB666_PACKED:
1341 return VID_MODE_FORMAT_RGB666_PACKED;
1342 case MIPI_DSI_FMT_RGB565:
1343 return VID_MODE_FORMAT_RGB565;
1344 default:
1345 MISSING_CASE(fmt);
1346 return VID_MODE_FORMAT_RGB666;
1347 }
1348 }
1349
1350 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1351 struct intel_crtc_state *pipe_config)
1352 {
1353 struct drm_encoder *encoder = &intel_encoder->base;
1354 struct drm_device *dev = encoder->dev;
1355 struct drm_i915_private *dev_priv = to_i915(dev);
1356 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1357 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1358 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1359 enum port port;
1360 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1361 u32 val, tmp;
1362 u16 mode_hdisplay;
1363
1364 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1365
1366 mode_hdisplay = adjusted_mode->crtc_hdisplay;
1367
1368 if (intel_dsi->dual_link) {
1369 mode_hdisplay /= 2;
1370 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1371 mode_hdisplay += intel_dsi->pixel_overlap;
1372 }
1373
1374 for_each_dsi_port(port, intel_dsi->ports) {
1375 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1376 /*
1377 * escape clock divider, 20MHz, shared for A and C.
1378 * device ready must be off when doing this! txclkesc?
1379 */
1380 tmp = I915_READ(MIPI_CTRL(PORT_A));
1381 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1382 I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1383 ESCAPE_CLOCK_DIVIDER_1);
1384
1385 /* read request priority is per pipe */
1386 tmp = I915_READ(MIPI_CTRL(port));
1387 tmp &= ~READ_REQUEST_PRIORITY_MASK;
1388 I915_WRITE(MIPI_CTRL(port), tmp |
1389 READ_REQUEST_PRIORITY_HIGH);
1390 } else if (IS_GEN9_LP(dev_priv)) {
1391 enum pipe pipe = intel_crtc->pipe;
1392
1393 tmp = I915_READ(MIPI_CTRL(port));
1394 tmp &= ~BXT_PIPE_SELECT_MASK;
1395
1396 tmp |= BXT_PIPE_SELECT(pipe);
1397 I915_WRITE(MIPI_CTRL(port), tmp);
1398 }
1399
1400 /* XXX: why here, why like this? handling in irq handler?! */
1401 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1402 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1403
1404 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1405
1406 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1407 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1408 mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1409 }
1410
1411 set_dsi_timings(encoder, adjusted_mode);
1412
1413 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1414 if (is_cmd_mode(intel_dsi)) {
1415 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1416 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1417 } else {
1418 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1419 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1420 }
1421
1422 tmp = 0;
1423 if (intel_dsi->eotp_pkt == 0)
1424 tmp |= EOT_DISABLE;
1425 if (intel_dsi->clock_stop)
1426 tmp |= CLOCKSTOP;
1427
1428 if (IS_GEN9_LP(dev_priv)) {
1429 tmp |= BXT_DPHY_DEFEATURE_EN;
1430 if (!is_cmd_mode(intel_dsi))
1431 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1432 }
1433
1434 for_each_dsi_port(port, intel_dsi->ports) {
1435 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1436
1437 /* timeouts for recovery. one frame IIUC. if counter expires,
1438 * EOT and stop state. */
1439
1440 /*
1441 * In burst mode, value greater than one DPI line Time in byte
1442 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1443 * said value is recommended.
1444 *
1445 * In non-burst mode, Value greater than one DPI frame time in
1446 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1447 * said value is recommended.
1448 *
1449 * In DBI only mode, value greater than one DBI frame time in
1450 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1451 * said value is recommended.
1452 */
1453
1454 if (is_vid_mode(intel_dsi) &&
1455 intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1456 I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1457 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1458 intel_dsi->lane_count,
1459 intel_dsi->burst_mode_ratio) + 1);
1460 } else {
1461 I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1462 txbyteclkhs(adjusted_mode->crtc_vtotal *
1463 adjusted_mode->crtc_htotal,
1464 bpp, intel_dsi->lane_count,
1465 intel_dsi->burst_mode_ratio) + 1);
1466 }
1467 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1468 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1469 intel_dsi->turn_arnd_val);
1470 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1471 intel_dsi->rst_timer_val);
1472
1473 /* dphy stuff */
1474
1475 /* in terms of low power clock */
1476 I915_WRITE(MIPI_INIT_COUNT(port),
1477 txclkesc(intel_dsi->escape_clk_div, 100));
1478
1479 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1480 /*
1481 * BXT spec says write MIPI_INIT_COUNT for
1482 * both the ports, even if only one is
1483 * getting used. So write the other port
1484 * if not in dual link mode.
1485 */
1486 I915_WRITE(MIPI_INIT_COUNT(port ==
1487 PORT_A ? PORT_C : PORT_A),
1488 intel_dsi->init_count);
1489 }
1490
1491 /* recovery disables */
1492 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1493
1494 /* in terms of low power clock */
1495 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1496
1497 /* in terms of txbyteclkhs. actual high to low switch +
1498 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1499 *
1500 * XXX: write MIPI_STOP_STATE_STALL?
1501 */
1502 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1503 intel_dsi->hs_to_lp_count);
1504
1505 /* XXX: low power clock equivalence in terms of byte clock.
1506 * the number of byte clocks occupied in one low power clock.
1507 * based on txbyteclkhs and txclkesc.
1508 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1509 * ) / 105.???
1510 */
1511 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1512
1513 if (IS_GEMINILAKE(dev_priv)) {
1514 I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1515 intel_dsi->lp_byte_clk);
1516 /* Shadow of DPHY reg */
1517 I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1518 intel_dsi->dphy_reg);
1519 }
1520
1521 /* the bw essential for transmitting 16 long packets containing
1522 * 252 bytes meant for dcs write memory command is programmed in
1523 * this register in terms of byte clocks. based on dsi transfer
1524 * rate and the number of lanes configured the time taken to
1525 * transmit 16 long packets in a dsi stream varies. */
1526 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1527
1528 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1529 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1530 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1531
1532 if (is_vid_mode(intel_dsi))
1533 /* Some panels might have resolution which is not a
1534 * multiple of 64 like 1366 x 768. Enable RANDOM
1535 * resolution support for such panels by default */
1536 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1537 intel_dsi->video_frmt_cfg_bits |
1538 intel_dsi->video_mode_format |
1539 IP_TG_CONFIG |
1540 RANDOM_DPI_DISPLAY_RESOLUTION);
1541 }
1542 }
1543
1544 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1545 {
1546 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1547 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1548 enum port port;
1549 u32 val;
1550
1551 if (!IS_GEMINILAKE(dev_priv)) {
1552 for_each_dsi_port(port, intel_dsi->ports) {
1553 /* Panel commands can be sent when clock is in LP11 */
1554 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1555
1556 intel_dsi_reset_clocks(encoder, port);
1557 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1558
1559 val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1560 val &= ~VID_MODE_FORMAT_MASK;
1561 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1562
1563 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1564 }
1565 }
1566 }
1567
1568 static int intel_dsi_get_modes(struct drm_connector *connector)
1569 {
1570 struct intel_connector *intel_connector = to_intel_connector(connector);
1571 struct drm_display_mode *mode;
1572
1573 DRM_DEBUG_KMS("\n");
1574
1575 if (!intel_connector->panel.fixed_mode) {
1576 DRM_DEBUG_KMS("no fixed mode\n");
1577 return 0;
1578 }
1579
1580 mode = drm_mode_duplicate(connector->dev,
1581 intel_connector->panel.fixed_mode);
1582 if (!mode) {
1583 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1584 return 0;
1585 }
1586
1587 drm_mode_probed_add(connector, mode);
1588 return 1;
1589 }
1590
1591 static int intel_dsi_set_property(struct drm_connector *connector,
1592 struct drm_property *property,
1593 uint64_t val)
1594 {
1595 struct drm_device *dev = connector->dev;
1596 struct intel_connector *intel_connector = to_intel_connector(connector);
1597 struct drm_crtc *crtc;
1598 int ret;
1599
1600 ret = drm_object_property_set_value(&connector->base, property, val);
1601 if (ret)
1602 return ret;
1603
1604 if (property == dev->mode_config.scaling_mode_property) {
1605 if (val == DRM_MODE_SCALE_NONE) {
1606 DRM_DEBUG_KMS("no scaling not supported\n");
1607 return -EINVAL;
1608 }
1609 if (HAS_GMCH_DISPLAY(to_i915(dev)) &&
1610 val == DRM_MODE_SCALE_CENTER) {
1611 DRM_DEBUG_KMS("centering not supported\n");
1612 return -EINVAL;
1613 }
1614
1615 if (intel_connector->panel.fitting_mode == val)
1616 return 0;
1617
1618 intel_connector->panel.fitting_mode = val;
1619 }
1620
1621 crtc = connector->state->crtc;
1622 if (crtc && crtc->state->enable) {
1623 /*
1624 * If the CRTC is enabled, the display will be changed
1625 * according to the new panel fitting mode.
1626 */
1627 intel_crtc_restore_mode(crtc);
1628 }
1629
1630 return 0;
1631 }
1632
1633 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1634 {
1635 struct intel_connector *intel_connector = to_intel_connector(connector);
1636
1637 DRM_DEBUG_KMS("\n");
1638 intel_panel_fini(&intel_connector->panel);
1639 drm_connector_cleanup(connector);
1640 kfree(connector);
1641 }
1642
1643 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1644 {
1645 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1646
1647 /* dispose of the gpios */
1648 if (intel_dsi->gpio_panel)
1649 gpiod_put(intel_dsi->gpio_panel);
1650
1651 intel_encoder_destroy(encoder);
1652 }
1653
1654 static const struct drm_encoder_funcs intel_dsi_funcs = {
1655 .destroy = intel_dsi_encoder_destroy,
1656 };
1657
1658 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1659 .get_modes = intel_dsi_get_modes,
1660 .mode_valid = intel_dsi_mode_valid,
1661 };
1662
1663 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1664 .dpms = drm_atomic_helper_connector_dpms,
1665 .late_register = intel_connector_register,
1666 .early_unregister = intel_connector_unregister,
1667 .destroy = intel_dsi_connector_destroy,
1668 .fill_modes = drm_helper_probe_single_connector_modes,
1669 .set_property = intel_dsi_set_property,
1670 .atomic_get_property = intel_connector_atomic_get_property,
1671 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1672 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1673 };
1674
1675 static void intel_dsi_add_properties(struct intel_connector *connector)
1676 {
1677 struct drm_device *dev = connector->base.dev;
1678
1679 if (connector->panel.fixed_mode) {
1680 drm_mode_create_scaling_mode_property(dev);
1681 drm_object_attach_property(&connector->base.base,
1682 dev->mode_config.scaling_mode_property,
1683 DRM_MODE_SCALE_ASPECT);
1684 connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
1685 }
1686 }
1687
1688 void intel_dsi_init(struct drm_i915_private *dev_priv)
1689 {
1690 struct drm_device *dev = &dev_priv->drm;
1691 struct intel_dsi *intel_dsi;
1692 struct intel_encoder *intel_encoder;
1693 struct drm_encoder *encoder;
1694 struct intel_connector *intel_connector;
1695 struct drm_connector *connector;
1696 struct drm_display_mode *scan, *fixed_mode = NULL;
1697 enum port port;
1698
1699 DRM_DEBUG_KMS("\n");
1700
1701 /* There is no detection method for MIPI so rely on VBT */
1702 if (!intel_bios_is_dsi_present(dev_priv, &port))
1703 return;
1704
1705 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1706 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1707 } else if (IS_GEN9_LP(dev_priv)) {
1708 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1709 } else {
1710 DRM_ERROR("Unsupported Mipi device to reg base");
1711 return;
1712 }
1713
1714 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1715 if (!intel_dsi)
1716 return;
1717
1718 intel_connector = intel_connector_alloc();
1719 if (!intel_connector) {
1720 kfree(intel_dsi);
1721 return;
1722 }
1723
1724 intel_encoder = &intel_dsi->base;
1725 encoder = &intel_encoder->base;
1726 intel_dsi->attached_connector = intel_connector;
1727
1728 connector = &intel_connector->base;
1729
1730 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1731 "DSI %c", port_name(port));
1732
1733 intel_encoder->compute_config = intel_dsi_compute_config;
1734 intel_encoder->pre_enable = intel_dsi_pre_enable;
1735 intel_encoder->enable = intel_dsi_enable_nop;
1736 intel_encoder->disable = intel_dsi_disable;
1737 intel_encoder->post_disable = intel_dsi_post_disable;
1738 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1739 intel_encoder->get_config = intel_dsi_get_config;
1740
1741 intel_connector->get_hw_state = intel_connector_get_hw_state;
1742
1743 intel_encoder->port = port;
1744
1745 /*
1746 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1747 * port C. BXT isn't limited like this.
1748 */
1749 if (IS_GEN9_LP(dev_priv))
1750 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1751 else if (port == PORT_A)
1752 intel_encoder->crtc_mask = BIT(PIPE_A);
1753 else
1754 intel_encoder->crtc_mask = BIT(PIPE_B);
1755
1756 if (dev_priv->vbt.dsi.config->dual_link) {
1757 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1758
1759 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
1760 case DL_DCS_PORT_A:
1761 intel_dsi->dcs_backlight_ports = BIT(PORT_A);
1762 break;
1763 case DL_DCS_PORT_C:
1764 intel_dsi->dcs_backlight_ports = BIT(PORT_C);
1765 break;
1766 default:
1767 case DL_DCS_PORT_A_AND_C:
1768 intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C);
1769 break;
1770 }
1771
1772 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
1773 case DL_DCS_PORT_A:
1774 intel_dsi->dcs_cabc_ports = BIT(PORT_A);
1775 break;
1776 case DL_DCS_PORT_C:
1777 intel_dsi->dcs_cabc_ports = BIT(PORT_C);
1778 break;
1779 default:
1780 case DL_DCS_PORT_A_AND_C:
1781 intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C);
1782 break;
1783 }
1784 } else {
1785 intel_dsi->ports = BIT(port);
1786 intel_dsi->dcs_backlight_ports = BIT(port);
1787 intel_dsi->dcs_cabc_ports = BIT(port);
1788 }
1789
1790 if (!dev_priv->vbt.dsi.config->cabc_supported)
1791 intel_dsi->dcs_cabc_ports = 0;
1792
1793 /* Create a DSI host (and a device) for each port. */
1794 for_each_dsi_port(port, intel_dsi->ports) {
1795 struct intel_dsi_host *host;
1796
1797 host = intel_dsi_host_init(intel_dsi, port);
1798 if (!host)
1799 goto err;
1800
1801 intel_dsi->dsi_hosts[port] = host;
1802 }
1803
1804 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1805 DRM_DEBUG_KMS("no device found\n");
1806 goto err;
1807 }
1808
1809 /*
1810 * In case of BYT with CRC PMIC, we need to use GPIO for
1811 * Panel control.
1812 */
1813 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1814 (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
1815 intel_dsi->gpio_panel =
1816 gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1817
1818 if (IS_ERR(intel_dsi->gpio_panel)) {
1819 DRM_ERROR("Failed to own gpio for panel control\n");
1820 intel_dsi->gpio_panel = NULL;
1821 }
1822 }
1823
1824 intel_encoder->type = INTEL_OUTPUT_DSI;
1825 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1826 intel_encoder->cloneable = 0;
1827 drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1828 DRM_MODE_CONNECTOR_DSI);
1829
1830 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1831
1832 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1833 connector->interlace_allowed = false;
1834 connector->doublescan_allowed = false;
1835
1836 intel_connector_attach_encoder(intel_connector, intel_encoder);
1837
1838 mutex_lock(&dev->mode_config.mutex);
1839 intel_dsi_vbt_get_modes(intel_dsi);
1840 list_for_each_entry(scan, &connector->probed_modes, head) {
1841 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1842 fixed_mode = drm_mode_duplicate(dev, scan);
1843 break;
1844 }
1845 }
1846 mutex_unlock(&dev->mode_config.mutex);
1847
1848 if (!fixed_mode) {
1849 DRM_DEBUG_KMS("no fixed mode\n");
1850 goto err;
1851 }
1852
1853 connector->display_info.width_mm = fixed_mode->width_mm;
1854 connector->display_info.height_mm = fixed_mode->height_mm;
1855
1856 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1857 intel_panel_setup_backlight(connector, INVALID_PIPE);
1858
1859 intel_dsi_add_properties(intel_connector);
1860
1861 return;
1862
1863 err:
1864 drm_encoder_cleanup(&intel_encoder->base);
1865 kfree(intel_dsi);
1866 kfree(intel_connector);
1867 }
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