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mtd: mxc_nand: put several more fields into devtype_data
[linux-2.6/btrfs-unstable.git] / drivers / mtd / nand / mxc_nand.c
blob35c928ac190193359b2a4b81406fa3fb844eece0
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
35
36 #include <asm/mach/flash.h>
37 #include <mach/mxc_nand.h>
38 #include <mach/hardware.h>
39
40 #define DRIVER_NAME "mxc_nand"
41
42 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
43 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
44 #define nfc_is_v3_2() (cpu_is_mx51() || cpu_is_mx53())
45 #define nfc_is_v3() nfc_is_v3_2()
46
47 /* Addresses for NFC registers */
48 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
49 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
50 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
51 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
52 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
53 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
54 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
55 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
56 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
57 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
58 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
59 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
60 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
61 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
62 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
63 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
64 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
65 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
66 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
67 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
68 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
69 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
70
71 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
72 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
73 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
74 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
75 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
76 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
77 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
78 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
79 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
80 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
81
82 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
83
84 /*
85 * Operation modes for the NFC. Valid for v1, v2 and v3
86 * type controllers.
87 */
88 #define NFC_CMD (1 << 0)
89 #define NFC_ADDR (1 << 1)
90 #define NFC_INPUT (1 << 2)
91 #define NFC_OUTPUT (1 << 3)
92 #define NFC_ID (1 << 4)
93 #define NFC_STATUS (1 << 5)
94
95 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
96 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
97
98 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
99 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
100 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
101
102 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
103
104 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
105
106 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
107 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
108 #define NFC_V3_WRPROT_LOCK (1 << 1)
109 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
110 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
111
112 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
113
114 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
115 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
116 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
117 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
118 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
119 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
120 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
122 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
123 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
124 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
125 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
126 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
127 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
128
129 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
130 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
131 #define NFC_V3_CONFIG3_FW8 (1 << 3)
132 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
133 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
134 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
135 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
136
137 #define NFC_V3_IPC (host->regs_ip + 0x2C)
138 #define NFC_V3_IPC_CREQ (1 << 0)
139 #define NFC_V3_IPC_INT (1 << 31)
140
141 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
142
143 struct mxc_nand_host;
144
145 struct mxc_nand_devtype_data {
146 void (*preset)(struct mtd_info *);
147 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
148 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
149 void (*send_page)(struct mtd_info *, unsigned int);
150 void (*send_read_id)(struct mxc_nand_host *);
151 uint16_t (*get_dev_status)(struct mxc_nand_host *);
152 int (*check_int)(struct mxc_nand_host *);
153 void (*irq_control)(struct mxc_nand_host *, int);
154 u32 (*get_ecc_status)(struct mxc_nand_host *);
155 struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
156 void (*select_chip)(struct mtd_info *mtd, int chip);
157 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
158 u_char *read_ecc, u_char *calc_ecc);
159
160 /*
161 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
162 * (CONFIG1:INT_MSK is set). To handle this the driver uses
163 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
164 */
165 int irqpending_quirk;
166 int needs_ip;
167
168 size_t regs_offset;
169 size_t spare0_offset;
170 size_t axi_offset;
171
172 int spare_len;
173 int eccbytes;
174 int eccsize;
175 };
176
177 struct mxc_nand_host {
178 struct mtd_info mtd;
179 struct nand_chip nand;
180 struct device *dev;
181
182 void *spare0;
183 void *main_area0;
184
185 void __iomem *base;
186 void __iomem *regs;
187 void __iomem *regs_axi;
188 void __iomem *regs_ip;
189 int status_request;
190 struct clk *clk;
191 int clk_act;
192 int irq;
193 int eccsize;
194 int active_cs;
195
196 struct completion op_completion;
197
198 uint8_t *data_buf;
199 unsigned int buf_start;
200
201 const struct mxc_nand_devtype_data *devtype_data;
202 };
203
204 /* OOB placement block for use with hardware ecc generation */
205 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
206 .eccbytes = 5,
207 .eccpos = {6, 7, 8, 9, 10},
208 .oobfree = {{0, 5}, {12, 4}, }
209 };
210
211 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
212 .eccbytes = 20,
213 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
214 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
215 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
216 };
217
218 /* OOB description for 512 byte pages with 16 byte OOB */
219 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
220 .eccbytes = 1 * 9,
221 .eccpos = {
222 7, 8, 9, 10, 11, 12, 13, 14, 15
223 },
224 .oobfree = {
225 {.offset = 0, .length = 5}
226 }
227 };
228
229 /* OOB description for 2048 byte pages with 64 byte OOB */
230 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
231 .eccbytes = 4 * 9,
232 .eccpos = {
233 7, 8, 9, 10, 11, 12, 13, 14, 15,
234 23, 24, 25, 26, 27, 28, 29, 30, 31,
235 39, 40, 41, 42, 43, 44, 45, 46, 47,
236 55, 56, 57, 58, 59, 60, 61, 62, 63
237 },
238 .oobfree = {
239 {.offset = 2, .length = 4},
240 {.offset = 16, .length = 7},
241 {.offset = 32, .length = 7},
242 {.offset = 48, .length = 7}
243 }
244 };
245
246 /* OOB description for 4096 byte pages with 128 byte OOB */
247 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
248 .eccbytes = 8 * 9,
249 .eccpos = {
250 7, 8, 9, 10, 11, 12, 13, 14, 15,
251 23, 24, 25, 26, 27, 28, 29, 30, 31,
252 39, 40, 41, 42, 43, 44, 45, 46, 47,
253 55, 56, 57, 58, 59, 60, 61, 62, 63,
254 71, 72, 73, 74, 75, 76, 77, 78, 79,
255 87, 88, 89, 90, 91, 92, 93, 94, 95,
256 103, 104, 105, 106, 107, 108, 109, 110, 111,
257 119, 120, 121, 122, 123, 124, 125, 126, 127,
258 },
259 .oobfree = {
260 {.offset = 2, .length = 4},
261 {.offset = 16, .length = 7},
262 {.offset = 32, .length = 7},
263 {.offset = 48, .length = 7},
264 {.offset = 64, .length = 7},
265 {.offset = 80, .length = 7},
266 {.offset = 96, .length = 7},
267 {.offset = 112, .length = 7},
268 }
269 };
270
271 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
272
273 static int check_int_v3(struct mxc_nand_host *host)
274 {
275 uint32_t tmp;
276
277 tmp = readl(NFC_V3_IPC);
278 if (!(tmp & NFC_V3_IPC_INT))
279 return 0;
280
281 tmp &= ~NFC_V3_IPC_INT;
282 writel(tmp, NFC_V3_IPC);
283
284 return 1;
285 }
286
287 static int check_int_v1_v2(struct mxc_nand_host *host)
288 {
289 uint32_t tmp;
290
291 tmp = readw(NFC_V1_V2_CONFIG2);
292 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
293 return 0;
294
295 if (!host->devtype_data->irqpending_quirk)
296 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
297
298 return 1;
299 }
300
301 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
302 {
303 uint16_t tmp;
304
305 tmp = readw(NFC_V1_V2_CONFIG1);
306
307 if (activate)
308 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
309 else
310 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
311
312 writew(tmp, NFC_V1_V2_CONFIG1);
313 }
314
315 static void irq_control_v3(struct mxc_nand_host *host, int activate)
316 {
317 uint32_t tmp;
318
319 tmp = readl(NFC_V3_CONFIG2);
320
321 if (activate)
322 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
323 else
324 tmp |= NFC_V3_CONFIG2_INT_MSK;
325
326 writel(tmp, NFC_V3_CONFIG2);
327 }
328
329 static void irq_control(struct mxc_nand_host *host, int activate)
330 {
331 if (host->devtype_data->irqpending_quirk) {
332 if (activate)
333 enable_irq(host->irq);
334 else
335 disable_irq_nosync(host->irq);
336 } else {
337 host->devtype_data->irq_control(host, activate);
338 }
339 }
340
341 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
342 {
343 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
344 }
345
346 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
347 {
348 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
349 }
350
351 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
352 {
353 return readl(NFC_V3_ECC_STATUS_RESULT);
354 }
355
356 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
357 {
358 struct mxc_nand_host *host = dev_id;
359
360 if (!host->devtype_data->check_int(host))
361 return IRQ_NONE;
362
363 irq_control(host, 0);
364
365 complete(&host->op_completion);
366
367 return IRQ_HANDLED;
368 }
369
370 /* This function polls the NANDFC to wait for the basic operation to
371 * complete by checking the INT bit of config2 register.
372 */
373 static void wait_op_done(struct mxc_nand_host *host, int useirq)
374 {
375 int max_retries = 8000;
376
377 if (useirq) {
378 if (!host->devtype_data->check_int(host)) {
379 INIT_COMPLETION(host->op_completion);
380 irq_control(host, 1);
381 wait_for_completion(&host->op_completion);
382 }
383 } else {
384 while (max_retries-- > 0) {
385 if (host->devtype_data->check_int(host))
386 break;
387
388 udelay(1);
389 }
390 if (max_retries < 0)
391 pr_debug("%s: INT not set\n", __func__);
392 }
393 }
394
395 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
396 {
397 /* fill command */
398 writel(cmd, NFC_V3_FLASH_CMD);
399
400 /* send out command */
401 writel(NFC_CMD, NFC_V3_LAUNCH);
402
403 /* Wait for operation to complete */
404 wait_op_done(host, useirq);
405 }
406
407 /* This function issues the specified command to the NAND device and
408 * waits for completion. */
409 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
410 {
411 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
412
413 writew(cmd, NFC_V1_V2_FLASH_CMD);
414 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
415
416 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
417 int max_retries = 100;
418 /* Reset completion is indicated by NFC_CONFIG2 */
419 /* being set to 0 */
420 while (max_retries-- > 0) {
421 if (readw(NFC_V1_V2_CONFIG2) == 0) {
422 break;
423 }
424 udelay(1);
425 }
426 if (max_retries < 0)
427 pr_debug("%s: RESET failed\n", __func__);
428 } else {
429 /* Wait for operation to complete */
430 wait_op_done(host, useirq);
431 }
432 }
433
434 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
435 {
436 /* fill address */
437 writel(addr, NFC_V3_FLASH_ADDR0);
438
439 /* send out address */
440 writel(NFC_ADDR, NFC_V3_LAUNCH);
441
442 wait_op_done(host, 0);
443 }
444
445 /* This function sends an address (or partial address) to the
446 * NAND device. The address is used to select the source/destination for
447 * a NAND command. */
448 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
449 {
450 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
451
452 writew(addr, NFC_V1_V2_FLASH_ADDR);
453 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
454
455 /* Wait for operation to complete */
456 wait_op_done(host, islast);
457 }
458
459 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
460 {
461 struct nand_chip *nand_chip = mtd->priv;
462 struct mxc_nand_host *host = nand_chip->priv;
463 uint32_t tmp;
464
465 tmp = readl(NFC_V3_CONFIG1);
466 tmp &= ~(7 << 4);
467 writel(tmp, NFC_V3_CONFIG1);
468
469 /* transfer data from NFC ram to nand */
470 writel(ops, NFC_V3_LAUNCH);
471
472 wait_op_done(host, false);
473 }
474
475 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
476 {
477 struct nand_chip *nand_chip = mtd->priv;
478 struct mxc_nand_host *host = nand_chip->priv;
479
480 /* NANDFC buffer 0 is used for page read/write */
481 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
482
483 writew(ops, NFC_V1_V2_CONFIG2);
484
485 /* Wait for operation to complete */
486 wait_op_done(host, true);
487 }
488
489 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
490 {
491 struct nand_chip *nand_chip = mtd->priv;
492 struct mxc_nand_host *host = nand_chip->priv;
493 int bufs, i;
494
495 if (mtd->writesize > 512)
496 bufs = 4;
497 else
498 bufs = 1;
499
500 for (i = 0; i < bufs; i++) {
501
502 /* NANDFC buffer 0 is used for page read/write */
503 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
504
505 writew(ops, NFC_V1_V2_CONFIG2);
506
507 /* Wait for operation to complete */
508 wait_op_done(host, true);
509 }
510 }
511
512 static void send_read_id_v3(struct mxc_nand_host *host)
513 {
514 /* Read ID into main buffer */
515 writel(NFC_ID, NFC_V3_LAUNCH);
516
517 wait_op_done(host, true);
518
519 memcpy(host->data_buf, host->main_area0, 16);
520 }
521
522 /* Request the NANDFC to perform a read of the NAND device ID. */
523 static void send_read_id_v1_v2(struct mxc_nand_host *host)
524 {
525 struct nand_chip *this = &host->nand;
526
527 /* NANDFC buffer 0 is used for device ID output */
528 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
529
530 writew(NFC_ID, NFC_V1_V2_CONFIG2);
531
532 /* Wait for operation to complete */
533 wait_op_done(host, true);
534
535 memcpy(host->data_buf, host->main_area0, 16);
536
537 if (this->options & NAND_BUSWIDTH_16) {
538 /* compress the ID info */
539 host->data_buf[1] = host->data_buf[2];
540 host->data_buf[2] = host->data_buf[4];
541 host->data_buf[3] = host->data_buf[6];
542 host->data_buf[4] = host->data_buf[8];
543 host->data_buf[5] = host->data_buf[10];
544 }
545 }
546
547 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
548 {
549 writew(NFC_STATUS, NFC_V3_LAUNCH);
550 wait_op_done(host, true);
551
552 return readl(NFC_V3_CONFIG1) >> 16;
553 }
554
555 /* This function requests the NANDFC to perform a read of the
556 * NAND device status and returns the current status. */
557 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
558 {
559 void __iomem *main_buf = host->main_area0;
560 uint32_t store;
561 uint16_t ret;
562
563 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
564
565 /*
566 * The device status is stored in main_area0. To
567 * prevent corruption of the buffer save the value
568 * and restore it afterwards.
569 */
570 store = readl(main_buf);
571
572 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
573 wait_op_done(host, true);
574
575 ret = readw(main_buf);
576
577 writel(store, main_buf);
578
579 return ret;
580 }
581
582 /* This functions is used by upper layer to checks if device is ready */
583 static int mxc_nand_dev_ready(struct mtd_info *mtd)
584 {
585 /*
586 * NFC handles R/B internally. Therefore, this function
587 * always returns status as ready.
588 */
589 return 1;
590 }
591
592 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
593 {
594 /*
595 * If HW ECC is enabled, we turn it on during init. There is
596 * no need to enable again here.
597 */
598 }
599
600 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
601 u_char *read_ecc, u_char *calc_ecc)
602 {
603 struct nand_chip *nand_chip = mtd->priv;
604 struct mxc_nand_host *host = nand_chip->priv;
605
606 /*
607 * 1-Bit errors are automatically corrected in HW. No need for
608 * additional correction. 2-Bit errors cannot be corrected by
609 * HW ECC, so we need to return failure
610 */
611 uint16_t ecc_status = get_ecc_status_v1(host);
612
613 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
614 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
615 return -1;
616 }
617
618 return 0;
619 }
620
621 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
622 u_char *read_ecc, u_char *calc_ecc)
623 {
624 struct nand_chip *nand_chip = mtd->priv;
625 struct mxc_nand_host *host = nand_chip->priv;
626 u32 ecc_stat, err;
627 int no_subpages = 1;
628 int ret = 0;
629 u8 ecc_bit_mask, err_limit;
630
631 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
632 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
633
634 no_subpages = mtd->writesize >> 9;
635
636 ecc_stat = host->devtype_data->get_ecc_status(host);
637
638 do {
639 err = ecc_stat & ecc_bit_mask;
640 if (err > err_limit) {
641 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
642 return -1;
643 } else {
644 ret += err;
645 }
646 ecc_stat >>= 4;
647 } while (--no_subpages);
648
649 mtd->ecc_stats.corrected += ret;
650 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
651
652 return ret;
653 }
654
655 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
656 u_char *ecc_code)
657 {
658 return 0;
659 }
660
661 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
662 {
663 struct nand_chip *nand_chip = mtd->priv;
664 struct mxc_nand_host *host = nand_chip->priv;
665 uint8_t ret;
666
667 /* Check for status request */
668 if (host->status_request)
669 return host->devtype_data->get_dev_status(host) & 0xFF;
670
671 ret = *(uint8_t *)(host->data_buf + host->buf_start);
672 host->buf_start++;
673
674 return ret;
675 }
676
677 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
678 {
679 struct nand_chip *nand_chip = mtd->priv;
680 struct mxc_nand_host *host = nand_chip->priv;
681 uint16_t ret;
682
683 ret = *(uint16_t *)(host->data_buf + host->buf_start);
684 host->buf_start += 2;
685
686 return ret;
687 }
688
689 /* Write data of length len to buffer buf. The data to be
690 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
691 * Operation by the NFC, the data is written to NAND Flash */
692 static void mxc_nand_write_buf(struct mtd_info *mtd,
693 const u_char *buf, int len)
694 {
695 struct nand_chip *nand_chip = mtd->priv;
696 struct mxc_nand_host *host = nand_chip->priv;
697 u16 col = host->buf_start;
698 int n = mtd->oobsize + mtd->writesize - col;
699
700 n = min(n, len);
701
702 memcpy(host->data_buf + col, buf, n);
703
704 host->buf_start += n;
705 }
706
707 /* Read the data buffer from the NAND Flash. To read the data from NAND
708 * Flash first the data output cycle is initiated by the NFC, which copies
709 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
710 */
711 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
712 {
713 struct nand_chip *nand_chip = mtd->priv;
714 struct mxc_nand_host *host = nand_chip->priv;
715 u16 col = host->buf_start;
716 int n = mtd->oobsize + mtd->writesize - col;
717
718 n = min(n, len);
719
720 memcpy(buf, host->data_buf + col, n);
721
722 host->buf_start += n;
723 }
724
725 /* Used by the upper layer to verify the data in NAND Flash
726 * with the data in the buf. */
727 static int mxc_nand_verify_buf(struct mtd_info *mtd,
728 const u_char *buf, int len)
729 {
730 return -EFAULT;
731 }
732
733 /* This function is used by upper layer for select and
734 * deselect of the NAND chip */
735 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
736 {
737 struct nand_chip *nand_chip = mtd->priv;
738 struct mxc_nand_host *host = nand_chip->priv;
739
740 if (chip == -1) {
741 /* Disable the NFC clock */
742 if (host->clk_act) {
743 clk_disable(host->clk);
744 host->clk_act = 0;
745 }
746 return;
747 }
748
749 if (!host->clk_act) {
750 /* Enable the NFC clock */
751 clk_enable(host->clk);
752 host->clk_act = 1;
753 }
754 }
755
756 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
757 {
758 struct nand_chip *nand_chip = mtd->priv;
759 struct mxc_nand_host *host = nand_chip->priv;
760
761 if (chip == -1) {
762 /* Disable the NFC clock */
763 if (host->clk_act) {
764 clk_disable(host->clk);
765 host->clk_act = 0;
766 }
767 return;
768 }
769
770 if (!host->clk_act) {
771 /* Enable the NFC clock */
772 clk_enable(host->clk);
773 host->clk_act = 1;
774 }
775
776 host->active_cs = chip;
777 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
778 }
779
780 /*
781 * Function to transfer data to/from spare area.
782 */
783 static void copy_spare(struct mtd_info *mtd, bool bfrom)
784 {
785 struct nand_chip *this = mtd->priv;
786 struct mxc_nand_host *host = this->priv;
787 u16 i, j;
788 u16 n = mtd->writesize >> 9;
789 u8 *d = host->data_buf + mtd->writesize;
790 u8 *s = host->spare0;
791 u16 t = host->devtype_data->spare_len;
792
793 j = (mtd->oobsize / n >> 1) << 1;
794
795 if (bfrom) {
796 for (i = 0; i < n - 1; i++)
797 memcpy(d + i * j, s + i * t, j);
798
799 /* the last section */
800 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
801 } else {
802 for (i = 0; i < n - 1; i++)
803 memcpy(&s[i * t], &d[i * j], j);
804
805 /* the last section */
806 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
807 }
808 }
809
810 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
811 {
812 struct nand_chip *nand_chip = mtd->priv;
813 struct mxc_nand_host *host = nand_chip->priv;
814
815 /* Write out column address, if necessary */
816 if (column != -1) {
817 /*
818 * MXC NANDFC can only perform full page+spare or
819 * spare-only read/write. When the upper layers
820 * perform a read/write buf operation, the saved column
821 * address is used to index into the full page.
822 */
823 host->devtype_data->send_addr(host, 0, page_addr == -1);
824 if (mtd->writesize > 512)
825 /* another col addr cycle for 2k page */
826 host->devtype_data->send_addr(host, 0, false);
827 }
828
829 /* Write out page address, if necessary */
830 if (page_addr != -1) {
831 /* paddr_0 - p_addr_7 */
832 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
833
834 if (mtd->writesize > 512) {
835 if (mtd->size >= 0x10000000) {
836 /* paddr_8 - paddr_15 */
837 host->devtype_data->send_addr(host,
838 (page_addr >> 8) & 0xff,
839 false);
840 host->devtype_data->send_addr(host,
841 (page_addr >> 16) & 0xff,
842 true);
843 } else
844 /* paddr_8 - paddr_15 */
845 host->devtype_data->send_addr(host,
846 (page_addr >> 8) & 0xff, true);
847 } else {
848 /* One more address cycle for higher density devices */
849 if (mtd->size >= 0x4000000) {
850 /* paddr_8 - paddr_15 */
851 host->devtype_data->send_addr(host,
852 (page_addr >> 8) & 0xff,
853 false);
854 host->devtype_data->send_addr(host,
855 (page_addr >> 16) & 0xff,
856 true);
857 } else
858 /* paddr_8 - paddr_15 */
859 host->devtype_data->send_addr(host,
860 (page_addr >> 8) & 0xff, true);
861 }
862 }
863 }
864
865 /*
866 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
867 * on how much oob the nand chip has. For 8bit ecc we need at least
868 * 26 bytes of oob data per 512 byte block.
869 */
870 static int get_eccsize(struct mtd_info *mtd)
871 {
872 int oobbytes_per_512 = 0;
873
874 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
875
876 if (oobbytes_per_512 < 26)
877 return 4;
878 else
879 return 8;
880 }
881
882 static void preset_v1(struct mtd_info *mtd)
883 {
884 struct nand_chip *nand_chip = mtd->priv;
885 struct mxc_nand_host *host = nand_chip->priv;
886 uint16_t config1 = 0;
887
888 if (nand_chip->ecc.mode == NAND_ECC_HW)
889 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
890
891 if (!host->devtype_data->irqpending_quirk)
892 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
893
894 host->eccsize = 1;
895
896 writew(config1, NFC_V1_V2_CONFIG1);
897 /* preset operation */
898
899 /* Unlock the internal RAM Buffer */
900 writew(0x2, NFC_V1_V2_CONFIG);
901
902 /* Blocks to be unlocked */
903 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
904 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
905
906 /* Unlock Block Command for given address range */
907 writew(0x4, NFC_V1_V2_WRPROT);
908 }
909
910 static void preset_v2(struct mtd_info *mtd)
911 {
912 struct nand_chip *nand_chip = mtd->priv;
913 struct mxc_nand_host *host = nand_chip->priv;
914 uint16_t config1 = 0;
915
916 if (nand_chip->ecc.mode == NAND_ECC_HW)
917 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
918
919 config1 |= NFC_V2_CONFIG1_FP_INT;
920
921 if (!host->devtype_data->irqpending_quirk)
922 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
923
924 if (mtd->writesize) {
925 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
926
927 host->eccsize = get_eccsize(mtd);
928 if (host->eccsize == 4)
929 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
930
931 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
932 } else {
933 host->eccsize = 1;
934 }
935
936 writew(config1, NFC_V1_V2_CONFIG1);
937 /* preset operation */
938
939 /* Unlock the internal RAM Buffer */
940 writew(0x2, NFC_V1_V2_CONFIG);
941
942 /* Blocks to be unlocked */
943 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
944 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
945 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
946 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
947 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
948 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
949 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
950 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
951
952 /* Unlock Block Command for given address range */
953 writew(0x4, NFC_V1_V2_WRPROT);
954 }
955
956 static void preset_v3(struct mtd_info *mtd)
957 {
958 struct nand_chip *chip = mtd->priv;
959 struct mxc_nand_host *host = chip->priv;
960 uint32_t config2, config3;
961 int i, addr_phases;
962
963 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
964 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
965
966 /* Unlock the internal RAM Buffer */
967 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
968 NFC_V3_WRPROT);
969
970 /* Blocks to be unlocked */
971 for (i = 0; i < NAND_MAX_CHIPS; i++)
972 writel(0x0 | (0xffff << 16),
973 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
974
975 writel(0, NFC_V3_IPC);
976
977 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
978 NFC_V3_CONFIG2_2CMD_PHASES |
979 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
980 NFC_V3_CONFIG2_ST_CMD(0x70) |
981 NFC_V3_CONFIG2_INT_MSK |
982 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
983
984 if (chip->ecc.mode == NAND_ECC_HW)
985 config2 |= NFC_V3_CONFIG2_ECC_EN;
986
987 addr_phases = fls(chip->pagemask) >> 3;
988
989 if (mtd->writesize == 2048) {
990 config2 |= NFC_V3_CONFIG2_PS_2048;
991 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
992 } else if (mtd->writesize == 4096) {
993 config2 |= NFC_V3_CONFIG2_PS_4096;
994 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
995 } else {
996 config2 |= NFC_V3_CONFIG2_PS_512;
997 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
998 }
999
1000 if (mtd->writesize) {
1001 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
1002 host->eccsize = get_eccsize(mtd);
1003 if (host->eccsize == 8)
1004 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1005 }
1006
1007 writel(config2, NFC_V3_CONFIG2);
1008
1009 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1010 NFC_V3_CONFIG3_NO_SDMA |
1011 NFC_V3_CONFIG3_RBB_MODE |
1012 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1013 NFC_V3_CONFIG3_ADD_OP(0);
1014
1015 if (!(chip->options & NAND_BUSWIDTH_16))
1016 config3 |= NFC_V3_CONFIG3_FW8;
1017
1018 writel(config3, NFC_V3_CONFIG3);
1019
1020 writel(0, NFC_V3_DELAY_LINE);
1021 }
1022
1023 /* Used by the upper layer to write command to NAND Flash for
1024 * different operations to be carried out on NAND Flash */
1025 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1026 int column, int page_addr)
1027 {
1028 struct nand_chip *nand_chip = mtd->priv;
1029 struct mxc_nand_host *host = nand_chip->priv;
1030
1031 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1032 command, column, page_addr);
1033
1034 /* Reset command state information */
1035 host->status_request = false;
1036
1037 /* Command pre-processing step */
1038 switch (command) {
1039 case NAND_CMD_RESET:
1040 host->devtype_data->preset(mtd);
1041 host->devtype_data->send_cmd(host, command, false);
1042 break;
1043
1044 case NAND_CMD_STATUS:
1045 host->buf_start = 0;
1046 host->status_request = true;
1047
1048 host->devtype_data->send_cmd(host, command, true);
1049 mxc_do_addr_cycle(mtd, column, page_addr);
1050 break;
1051
1052 case NAND_CMD_READ0:
1053 case NAND_CMD_READOOB:
1054 if (command == NAND_CMD_READ0)
1055 host->buf_start = column;
1056 else
1057 host->buf_start = column + mtd->writesize;
1058
1059 command = NAND_CMD_READ0; /* only READ0 is valid */
1060
1061 host->devtype_data->send_cmd(host, command, false);
1062 mxc_do_addr_cycle(mtd, column, page_addr);
1063
1064 if (mtd->writesize > 512)
1065 host->devtype_data->send_cmd(host,
1066 NAND_CMD_READSTART, true);
1067
1068 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1069
1070 memcpy(host->data_buf, host->main_area0, mtd->writesize);
1071 copy_spare(mtd, true);
1072 break;
1073
1074 case NAND_CMD_SEQIN:
1075 if (column >= mtd->writesize)
1076 /* call ourself to read a page */
1077 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1078
1079 host->buf_start = column;
1080
1081 host->devtype_data->send_cmd(host, command, false);
1082 mxc_do_addr_cycle(mtd, column, page_addr);
1083 break;
1084
1085 case NAND_CMD_PAGEPROG:
1086 memcpy(host->main_area0, host->data_buf, mtd->writesize);
1087 copy_spare(mtd, false);
1088 host->devtype_data->send_page(mtd, NFC_INPUT);
1089 host->devtype_data->send_cmd(host, command, true);
1090 mxc_do_addr_cycle(mtd, column, page_addr);
1091 break;
1092
1093 case NAND_CMD_READID:
1094 host->devtype_data->send_cmd(host, command, true);
1095 mxc_do_addr_cycle(mtd, column, page_addr);
1096 host->devtype_data->send_read_id(host);
1097 host->buf_start = column;
1098 break;
1099
1100 case NAND_CMD_ERASE1:
1101 case NAND_CMD_ERASE2:
1102 host->devtype_data->send_cmd(host, command, false);
1103 mxc_do_addr_cycle(mtd, column, page_addr);
1104
1105 break;
1106 }
1107 }
1108
1109 /*
1110 * The generic flash bbt decriptors overlap with our ecc
1111 * hardware, so define some i.MX specific ones.
1112 */
1113 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1114 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1115
1116 static struct nand_bbt_descr bbt_main_descr = {
1117 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1118 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1119 .offs = 0,
1120 .len = 4,
1121 .veroffs = 4,
1122 .maxblocks = 4,
1123 .pattern = bbt_pattern,
1124 };
1125
1126 static struct nand_bbt_descr bbt_mirror_descr = {
1127 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1128 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1129 .offs = 0,
1130 .len = 4,
1131 .veroffs = 4,
1132 .maxblocks = 4,
1133 .pattern = mirror_pattern,
1134 };
1135
1136 /* v1 + irqpending_quirk: i.MX21 */
1137 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1138 .preset = preset_v1,
1139 .send_cmd = send_cmd_v1_v2,
1140 .send_addr = send_addr_v1_v2,
1141 .send_page = send_page_v1,
1142 .send_read_id = send_read_id_v1_v2,
1143 .get_dev_status = get_dev_status_v1_v2,
1144 .check_int = check_int_v1_v2,
1145 .irq_control = irq_control_v1_v2,
1146 .get_ecc_status = get_ecc_status_v1,
1147 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1148 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1149 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1150 .select_chip = mxc_nand_select_chip_v1_v3,
1151 .correct_data = mxc_nand_correct_data_v1,
1152 .irqpending_quirk = 1,
1153 .needs_ip = 0,
1154 .regs_offset = 0xe00,
1155 .spare0_offset = 0x800,
1156 .spare_len = 16,
1157 .eccbytes = 3,
1158 .eccsize = 1,
1159 };
1160
1161 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1162 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1163 .preset = preset_v1,
1164 .send_cmd = send_cmd_v1_v2,
1165 .send_addr = send_addr_v1_v2,
1166 .send_page = send_page_v1,
1167 .send_read_id = send_read_id_v1_v2,
1168 .get_dev_status = get_dev_status_v1_v2,
1169 .check_int = check_int_v1_v2,
1170 .irq_control = irq_control_v1_v2,
1171 .get_ecc_status = get_ecc_status_v1,
1172 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1173 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1174 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1175 .select_chip = mxc_nand_select_chip_v1_v3,
1176 .correct_data = mxc_nand_correct_data_v1,
1177 .irqpending_quirk = 0,
1178 .needs_ip = 0,
1179 .regs_offset = 0xe00,
1180 .spare0_offset = 0x800,
1181 .axi_offset = 0,
1182 .spare_len = 16,
1183 .eccbytes = 3,
1184 .eccsize = 1,
1185 };
1186
1187 /* v21: i.MX25, i.MX35 */
1188 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1189 .preset = preset_v2,
1190 .send_cmd = send_cmd_v1_v2,
1191 .send_addr = send_addr_v1_v2,
1192 .send_page = send_page_v2,
1193 .send_read_id = send_read_id_v1_v2,
1194 .get_dev_status = get_dev_status_v1_v2,
1195 .check_int = check_int_v1_v2,
1196 .irq_control = irq_control_v1_v2,
1197 .get_ecc_status = get_ecc_status_v2,
1198 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1199 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1200 .ecclayout_4k = &nandv2_hw_eccoob_4k,
1201 .select_chip = mxc_nand_select_chip_v2,
1202 .correct_data = mxc_nand_correct_data_v2_v3,
1203 .irqpending_quirk = 0,
1204 .needs_ip = 0,
1205 .regs_offset = 0x1e00,
1206 .spare0_offset = 0x1000,
1207 .axi_offset = 0,
1208 .spare_len = 64,
1209 .eccbytes = 9,
1210 .eccsize = 0,
1211 };
1212
1213 /* v3: i.MX51, i.MX53 */
1214 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1215 .preset = preset_v3,
1216 .send_cmd = send_cmd_v3,
1217 .send_addr = send_addr_v3,
1218 .send_page = send_page_v3,
1219 .send_read_id = send_read_id_v3,
1220 .get_dev_status = get_dev_status_v3,
1221 .check_int = check_int_v3,
1222 .irq_control = irq_control_v3,
1223 .get_ecc_status = get_ecc_status_v3,
1224 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1225 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1226 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1227 .select_chip = mxc_nand_select_chip_v1_v3,
1228 .correct_data = mxc_nand_correct_data_v2_v3,
1229 .irqpending_quirk = 0,
1230 .needs_ip = 1,
1231 .regs_offset = 0,
1232 .spare0_offset = 0x1000,
1233 .axi_offset = 0x1e00,
1234 .spare_len = 64,
1235 .eccbytes = 0,
1236 .eccsize = 0,
1237 };
1238
1239 static int __init mxcnd_probe(struct platform_device *pdev)
1240 {
1241 struct nand_chip *this;
1242 struct mtd_info *mtd;
1243 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
1244 struct mxc_nand_host *host;
1245 struct resource *res;
1246 int err = 0;
1247
1248 /* Allocate memory for MTD device structure and private data */
1249 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
1250 NAND_MAX_OOBSIZE, GFP_KERNEL);
1251 if (!host)
1252 return -ENOMEM;
1253
1254 host->data_buf = (uint8_t *)(host + 1);
1255
1256 host->dev = &pdev->dev;
1257 /* structures must be linked */
1258 this = &host->nand;
1259 mtd = &host->mtd;
1260 mtd->priv = this;
1261 mtd->owner = THIS_MODULE;
1262 mtd->dev.parent = &pdev->dev;
1263 mtd->name = DRIVER_NAME;
1264
1265 /* 50 us command delay time */
1266 this->chip_delay = 5;
1267
1268 this->priv = host;
1269 this->dev_ready = mxc_nand_dev_ready;
1270 this->cmdfunc = mxc_nand_command;
1271 this->read_byte = mxc_nand_read_byte;
1272 this->read_word = mxc_nand_read_word;
1273 this->write_buf = mxc_nand_write_buf;
1274 this->read_buf = mxc_nand_read_buf;
1275 this->verify_buf = mxc_nand_verify_buf;
1276
1277 host->clk = clk_get(&pdev->dev, "nfc");
1278 if (IS_ERR(host->clk)) {
1279 err = PTR_ERR(host->clk);
1280 goto eclk;
1281 }
1282
1283 clk_enable(host->clk);
1284 host->clk_act = 1;
1285
1286 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1287 if (!res) {
1288 err = -ENODEV;
1289 goto eres;
1290 }
1291
1292 host->base = ioremap(res->start, resource_size(res));
1293 if (!host->base) {
1294 err = -ENOMEM;
1295 goto eres;
1296 }
1297
1298 host->main_area0 = host->base;
1299
1300 if (nfc_is_v1()) {
1301 if (cpu_is_mx21())
1302 host->devtype_data = &imx21_nand_devtype_data;
1303 else
1304 host->devtype_data = &imx27_nand_devtype_data;
1305 } else if (nfc_is_v21()) {
1306 host->devtype_data = &imx25_nand_devtype_data;
1307 } else if (nfc_is_v3_2()) {
1308 host->devtype_data = &imx51_nand_devtype_data;
1309 } else
1310 BUG();
1311
1312 if (host->devtype_data->regs_offset)
1313 host->regs = host->base + host->devtype_data->regs_offset;
1314 host->spare0 = host->base + host->devtype_data->spare0_offset;
1315 if (host->devtype_data->axi_offset)
1316 host->regs_axi = host->base + host->devtype_data->axi_offset;
1317
1318 this->ecc.bytes = host->devtype_data->eccbytes;
1319 host->eccsize = host->devtype_data->eccsize;
1320
1321 this->select_chip = host->devtype_data->select_chip;
1322 this->ecc.size = 512;
1323 this->ecc.layout = host->devtype_data->ecclayout_512;
1324
1325 if (host->devtype_data->needs_ip) {
1326 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1327 if (!res) {
1328 err = -ENODEV;
1329 goto eirq;
1330 }
1331 host->regs_ip = ioremap(res->start, resource_size(res));
1332 if (!host->regs_ip) {
1333 err = -ENOMEM;
1334 goto eirq;
1335 }
1336 }
1337
1338 if (pdata->hw_ecc) {
1339 this->ecc.calculate = mxc_nand_calculate_ecc;
1340 this->ecc.hwctl = mxc_nand_enable_hwecc;
1341 this->ecc.correct = host->devtype_data->correct_data;
1342 this->ecc.mode = NAND_ECC_HW;
1343 } else {
1344 this->ecc.mode = NAND_ECC_SOFT;
1345 }
1346
1347 /* NAND bus width determines access funtions used by upper layer */
1348 if (pdata->width == 2)
1349 this->options |= NAND_BUSWIDTH_16;
1350
1351 if (pdata->flash_bbt) {
1352 this->bbt_td = &bbt_main_descr;
1353 this->bbt_md = &bbt_mirror_descr;
1354 /* update flash based bbt */
1355 this->bbt_options |= NAND_BBT_USE_FLASH;
1356 }
1357
1358 init_completion(&host->op_completion);
1359
1360 host->irq = platform_get_irq(pdev, 0);
1361
1362 /*
1363 * Use host->devtype_data->irq_control() here instead of irq_control()
1364 * because we must not disable_irq_nosync without having requested the
1365 * irq.
1366 */
1367 host->devtype_data->irq_control(host, 0);
1368
1369 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
1370 if (err)
1371 goto eirq;
1372
1373 /*
1374 * Now that we "own" the interrupt make sure the interrupt mask bit is
1375 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1376 * on this machine.
1377 */
1378 if (host->devtype_data->irqpending_quirk) {
1379 disable_irq_nosync(host->irq);
1380 host->devtype_data->irq_control(host, 1);
1381 }
1382
1383 /* first scan to find the device and get the page size */
1384 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1385 err = -ENXIO;
1386 goto escan;
1387 }
1388
1389 /* Call preset again, with correct writesize this time */
1390 host->devtype_data->preset(mtd);
1391
1392 if (mtd->writesize == 2048)
1393 this->ecc.layout = host->devtype_data->ecclayout_2k;
1394 else if (mtd->writesize == 4096)
1395 this->ecc.layout = host->devtype_data->ecclayout_4k;
1396
1397 /* second phase scan */
1398 if (nand_scan_tail(mtd)) {
1399 err = -ENXIO;
1400 goto escan;
1401 }
1402
1403 if (this->ecc.mode == NAND_ECC_HW) {
1404 if (nfc_is_v1())
1405 this->ecc.strength = 1;
1406 else
1407 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1408 }
1409
1410 /* Register the partitions */
1411 mtd_device_parse_register(mtd, part_probes, NULL, pdata->parts,
1412 pdata->nr_parts);
1413
1414 platform_set_drvdata(pdev, host);
1415
1416 return 0;
1417
1418 escan:
1419 free_irq(host->irq, host);
1420 eirq:
1421 if (host->regs_ip)
1422 iounmap(host->regs_ip);
1423 iounmap(host->base);
1424 eres:
1425 clk_put(host->clk);
1426 eclk:
1427 kfree(host);
1428
1429 return err;
1430 }
1431
1432 static int __devexit mxcnd_remove(struct platform_device *pdev)
1433 {
1434 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1435
1436 clk_put(host->clk);
1437
1438 platform_set_drvdata(pdev, NULL);
1439
1440 nand_release(&host->mtd);
1441 free_irq(host->irq, host);
1442 if (host->regs_ip)
1443 iounmap(host->regs_ip);
1444 iounmap(host->base);
1445 kfree(host);
1446
1447 return 0;
1448 }
1449
1450 static struct platform_driver mxcnd_driver = {
1451 .driver = {
1452 .name = DRIVER_NAME,
1453 .owner = THIS_MODULE,
1454 },
1455 .remove = __devexit_p(mxcnd_remove),
1456 };
1457
1458 static int __init mxc_nd_init(void)
1459 {
1460 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1461 }
1462
1463 static void __exit mxc_nd_cleanup(void)
1464 {
1465 /* Unregister the device structure */
1466 platform_driver_unregister(&mxcnd_driver);
1467 }
1468
1469 module_init(mxc_nd_init);
1470 module_exit(mxc_nd_cleanup);
1471
1472 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1473 MODULE_DESCRIPTION("MXC NAND MTD driver");
1474 MODULE_LICENSE("GPL");
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