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iwlwifi: do not clear data after chain noise calib
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
bloba0669ea427909cf431fbb56f549994a237ebf473
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <net/mac80211.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40
41 #include "iwl-eeprom.h"
42 #include "iwl-dev.h"
43 #include "iwl-core.h"
44 #include "iwl-io.h"
45 #include "iwl-helpers.h"
46 #include "iwl-calib.h"
47 #include "iwl-sta.h"
48 #include "iwl-agn-led.h"
49 #include "iwl-agn.h"
50 #include "iwl-agn-debugfs.h"
51
52 static int iwl4965_send_tx_power(struct iwl_priv *priv);
53 static int iwl4965_hw_get_temperature(struct iwl_priv *priv);
54
55 /* Highest firmware API version supported */
56 #define IWL4965_UCODE_API_MAX 2
57
58 /* Lowest firmware API version supported */
59 #define IWL4965_UCODE_API_MIN 2
60
61 #define IWL4965_FW_PRE "iwlwifi-4965-"
62 #define _IWL4965_MODULE_FIRMWARE(api) IWL4965_FW_PRE #api ".ucode"
63 #define IWL4965_MODULE_FIRMWARE(api) _IWL4965_MODULE_FIRMWARE(api)
64
65 /* check contents of special bootstrap uCode SRAM */
66 static int iwl4965_verify_bsm(struct iwl_priv *priv)
67 {
68 __le32 *image = priv->ucode_boot.v_addr;
69 u32 len = priv->ucode_boot.len;
70 u32 reg;
71 u32 val;
72
73 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
74
75 /* verify BSM SRAM contents */
76 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
77 for (reg = BSM_SRAM_LOWER_BOUND;
78 reg < BSM_SRAM_LOWER_BOUND + len;
79 reg += sizeof(u32), image++) {
80 val = iwl_read_prph(priv, reg);
81 if (val != le32_to_cpu(*image)) {
82 IWL_ERR(priv, "BSM uCode verification failed at "
83 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
84 BSM_SRAM_LOWER_BOUND,
85 reg - BSM_SRAM_LOWER_BOUND, len,
86 val, le32_to_cpu(*image));
87 return -EIO;
88 }
89 }
90
91 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
92
93 return 0;
94 }
95
96 /**
97 * iwl4965_load_bsm - Load bootstrap instructions
98 *
99 * BSM operation:
100 *
101 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
102 * in special SRAM that does not power down during RFKILL. When powering back
103 * up after power-saving sleeps (or during initial uCode load), the BSM loads
104 * the bootstrap program into the on-board processor, and starts it.
105 *
106 * The bootstrap program loads (via DMA) instructions and data for a new
107 * program from host DRAM locations indicated by the host driver in the
108 * BSM_DRAM_* registers. Once the new program is loaded, it starts
109 * automatically.
110 *
111 * When initializing the NIC, the host driver points the BSM to the
112 * "initialize" uCode image. This uCode sets up some internal data, then
113 * notifies host via "initialize alive" that it is complete.
114 *
115 * The host then replaces the BSM_DRAM_* pointer values to point to the
116 * normal runtime uCode instructions and a backup uCode data cache buffer
117 * (filled initially with starting data values for the on-board processor),
118 * then triggers the "initialize" uCode to load and launch the runtime uCode,
119 * which begins normal operation.
120 *
121 * When doing a power-save shutdown, runtime uCode saves data SRAM into
122 * the backup data cache in DRAM before SRAM is powered down.
123 *
124 * When powering back up, the BSM loads the bootstrap program. This reloads
125 * the runtime uCode instructions and the backup data cache into SRAM,
126 * and re-launches the runtime uCode from where it left off.
127 */
128 static int iwl4965_load_bsm(struct iwl_priv *priv)
129 {
130 __le32 *image = priv->ucode_boot.v_addr;
131 u32 len = priv->ucode_boot.len;
132 dma_addr_t pinst;
133 dma_addr_t pdata;
134 u32 inst_len;
135 u32 data_len;
136 int i;
137 u32 done;
138 u32 reg_offset;
139 int ret;
140
141 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
142
143 priv->ucode_type = UCODE_RT;
144
145 /* make sure bootstrap program is no larger than BSM's SRAM size */
146 if (len > IWL49_MAX_BSM_SIZE)
147 return -EINVAL;
148
149 /* Tell bootstrap uCode where to find the "Initialize" uCode
150 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
151 * NOTE: iwl_init_alive_start() will replace these values,
152 * after the "initialize" uCode has run, to point to
153 * runtime/protocol instructions and backup data cache.
154 */
155 pinst = priv->ucode_init.p_addr >> 4;
156 pdata = priv->ucode_init_data.p_addr >> 4;
157 inst_len = priv->ucode_init.len;
158 data_len = priv->ucode_init_data.len;
159
160 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
161 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
162 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
163 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
164
165 /* Fill BSM memory with bootstrap instructions */
166 for (reg_offset = BSM_SRAM_LOWER_BOUND;
167 reg_offset < BSM_SRAM_LOWER_BOUND + len;
168 reg_offset += sizeof(u32), image++)
169 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
170
171 ret = iwl4965_verify_bsm(priv);
172 if (ret)
173 return ret;
174
175 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
176 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
177 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
178 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
179
180 /* Load bootstrap code into instruction SRAM now,
181 * to prepare to load "initialize" uCode */
182 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
183
184 /* Wait for load of bootstrap uCode to finish */
185 for (i = 0; i < 100; i++) {
186 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
187 if (!(done & BSM_WR_CTRL_REG_BIT_START))
188 break;
189 udelay(10);
190 }
191 if (i < 100)
192 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
193 else {
194 IWL_ERR(priv, "BSM write did not complete!\n");
195 return -EIO;
196 }
197
198 /* Enable future boot loads whenever power management unit triggers it
199 * (e.g. when powering back up after power-save shutdown) */
200 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
201
202
203 return 0;
204 }
205
206 /**
207 * iwl4965_set_ucode_ptrs - Set uCode address location
208 *
209 * Tell initialization uCode where to find runtime uCode.
210 *
211 * BSM registers initially contain pointers to initialization uCode.
212 * We need to replace them to load runtime uCode inst and data,
213 * and to save runtime data when powering down.
214 */
215 static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
216 {
217 dma_addr_t pinst;
218 dma_addr_t pdata;
219 int ret = 0;
220
221 /* bits 35:4 for 4965 */
222 pinst = priv->ucode_code.p_addr >> 4;
223 pdata = priv->ucode_data_backup.p_addr >> 4;
224
225 /* Tell bootstrap uCode where to find image to load */
226 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
227 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
228 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
229 priv->ucode_data.len);
230
231 /* Inst byte count must be last to set up, bit 31 signals uCode
232 * that all new ptr/size info is in place */
233 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
234 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
235 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
236
237 return ret;
238 }
239
240 /**
241 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
242 *
243 * Called after REPLY_ALIVE notification received from "initialize" uCode.
244 *
245 * The 4965 "initialize" ALIVE reply contains calibration data for:
246 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
247 * (3945 does not contain this data).
248 *
249 * Tell "initialize" uCode to go ahead and load the runtime uCode.
250 */
251 static void iwl4965_init_alive_start(struct iwl_priv *priv)
252 {
253 /* Check alive response for "valid" sign from uCode */
254 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
255 /* We had an error bringing up the hardware, so take it
256 * all the way back down so we can try again */
257 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
258 goto restart;
259 }
260
261 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
262 * This is a paranoid check, because we would not have gotten the
263 * "initialize" alive if code weren't properly loaded. */
264 if (iwl_verify_ucode(priv)) {
265 /* Runtime instruction load was bad;
266 * take it all the way back down so we can try again */
267 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
268 goto restart;
269 }
270
271 /* Calculate temperature */
272 priv->temperature = iwl4965_hw_get_temperature(priv);
273
274 /* Send pointers to protocol/runtime uCode image ... init code will
275 * load and launch runtime uCode, which will send us another "Alive"
276 * notification. */
277 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
278 if (iwl4965_set_ucode_ptrs(priv)) {
279 /* Runtime instruction load won't happen;
280 * take it all the way back down so we can try again */
281 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
282 goto restart;
283 }
284 return;
285
286 restart:
287 queue_work(priv->workqueue, &priv->restart);
288 }
289
290 static bool is_ht40_channel(__le32 rxon_flags)
291 {
292 int chan_mod = le32_to_cpu(rxon_flags & RXON_FLG_CHANNEL_MODE_MSK)
293 >> RXON_FLG_CHANNEL_MODE_POS;
294 return ((chan_mod == CHANNEL_MODE_PURE_40) ||
295 (chan_mod == CHANNEL_MODE_MIXED));
296 }
297
298 /*
299 * EEPROM handlers
300 */
301 static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv)
302 {
303 return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
304 }
305
306 /*
307 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
308 * must be called under priv->lock and mac access
309 */
310 static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
311 {
312 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
313 }
314
315 static void iwl4965_nic_config(struct iwl_priv *priv)
316 {
317 unsigned long flags;
318 u16 radio_cfg;
319
320 spin_lock_irqsave(&priv->lock, flags);
321
322 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
323
324 /* write radio config values to register */
325 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
326 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
327 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
328 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
329 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
330
331 /* set CSR_HW_CONFIG_REG for uCode use */
332 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
333 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
334 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
335
336 priv->calib_info = (struct iwl_eeprom_calib_info *)
337 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
338
339 spin_unlock_irqrestore(&priv->lock, flags);
340 }
341
342 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
343 * Called after every association, but this runs only once!
344 * ... once chain noise is calibrated the first time, it's good forever. */
345 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
346 {
347 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
348
349 if ((data->state == IWL_CHAIN_NOISE_ALIVE) &&
350 iwl_is_associated(priv)) {
351 struct iwl_calib_diff_gain_cmd cmd;
352
353 /* clear data for chain noise calibration algorithm */
354 data->chain_noise_a = 0;
355 data->chain_noise_b = 0;
356 data->chain_noise_c = 0;
357 data->chain_signal_a = 0;
358 data->chain_signal_b = 0;
359 data->chain_signal_c = 0;
360 data->beacon_count = 0;
361
362 memset(&cmd, 0, sizeof(cmd));
363 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
364 cmd.diff_gain_a = 0;
365 cmd.diff_gain_b = 0;
366 cmd.diff_gain_c = 0;
367 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
368 sizeof(cmd), &cmd))
369 IWL_ERR(priv,
370 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
371 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
372 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
373 }
374 }
375
376 static void iwl4965_gain_computation(struct iwl_priv *priv,
377 u32 *average_noise,
378 u16 min_average_noise_antenna_i,
379 u32 min_average_noise,
380 u8 default_chain)
381 {
382 int i, ret;
383 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
384
385 data->delta_gain_code[min_average_noise_antenna_i] = 0;
386
387 for (i = default_chain; i < NUM_RX_CHAINS; i++) {
388 s32 delta_g = 0;
389
390 if (!(data->disconn_array[i]) &&
391 (data->delta_gain_code[i] ==
392 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
393 delta_g = average_noise[i] - min_average_noise;
394 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
395 data->delta_gain_code[i] =
396 min(data->delta_gain_code[i],
397 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
398
399 data->delta_gain_code[i] =
400 (data->delta_gain_code[i] | (1 << 2));
401 } else {
402 data->delta_gain_code[i] = 0;
403 }
404 }
405 IWL_DEBUG_CALIB(priv, "delta_gain_codes: a %d b %d c %d\n",
406 data->delta_gain_code[0],
407 data->delta_gain_code[1],
408 data->delta_gain_code[2]);
409
410 /* Differential gain gets sent to uCode only once */
411 if (!data->radio_write) {
412 struct iwl_calib_diff_gain_cmd cmd;
413 data->radio_write = 1;
414
415 memset(&cmd, 0, sizeof(cmd));
416 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
417 cmd.diff_gain_a = data->delta_gain_code[0];
418 cmd.diff_gain_b = data->delta_gain_code[1];
419 cmd.diff_gain_c = data->delta_gain_code[2];
420 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
421 sizeof(cmd), &cmd);
422 if (ret)
423 IWL_DEBUG_CALIB(priv, "fail sending cmd "
424 "REPLY_PHY_CALIBRATION_CMD\n");
425
426 /* TODO we might want recalculate
427 * rx_chain in rxon cmd */
428
429 /* Mark so we run this algo only once! */
430 data->state = IWL_CHAIN_NOISE_CALIBRATED;
431 }
432 }
433
434 static void iwl4965_bg_txpower_work(struct work_struct *work)
435 {
436 struct iwl_priv *priv = container_of(work, struct iwl_priv,
437 txpower_work);
438
439 /* If a scan happened to start before we got here
440 * then just return; the statistics notification will
441 * kick off another scheduled work to compensate for
442 * any temperature delta we missed here. */
443 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
444 test_bit(STATUS_SCANNING, &priv->status))
445 return;
446
447 mutex_lock(&priv->mutex);
448
449 /* Regardless of if we are associated, we must reconfigure the
450 * TX power since frames can be sent on non-radar channels while
451 * not associated */
452 iwl4965_send_tx_power(priv);
453
454 /* Update last_temperature to keep is_calib_needed from running
455 * when it isn't needed... */
456 priv->last_temperature = priv->temperature;
457
458 mutex_unlock(&priv->mutex);
459 }
460
461 /*
462 * Acquire priv->lock before calling this function !
463 */
464 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
465 {
466 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
467 (index & 0xff) | (txq_id << 8));
468 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
469 }
470
471 /**
472 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
473 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
474 * @scd_retry: (1) Indicates queue will be used in aggregation mode
475 *
476 * NOTE: Acquire priv->lock before calling this function !
477 */
478 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
479 struct iwl_tx_queue *txq,
480 int tx_fifo_id, int scd_retry)
481 {
482 int txq_id = txq->q.id;
483
484 /* Find out whether to activate Tx queue */
485 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
486
487 /* Set up and activate */
488 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
489 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
490 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
491 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
492 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
493 IWL49_SCD_QUEUE_STTS_REG_MSK);
494
495 txq->sched_retry = scd_retry;
496
497 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
498 active ? "Activate" : "Deactivate",
499 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
500 }
501
502 static const s8 default_queue_to_tx_fifo[] = {
503 IWL_TX_FIFO_VO,
504 IWL_TX_FIFO_VI,
505 IWL_TX_FIFO_BE,
506 IWL_TX_FIFO_BK,
507 IWL49_CMD_FIFO_NUM,
508 IWL_TX_FIFO_UNUSED,
509 IWL_TX_FIFO_UNUSED,
510 };
511
512 static int iwl4965_alive_notify(struct iwl_priv *priv)
513 {
514 u32 a;
515 unsigned long flags;
516 int i, chan;
517 u32 reg_val;
518
519 spin_lock_irqsave(&priv->lock, flags);
520
521 /* Clear 4965's internal Tx Scheduler data base */
522 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
523 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
524 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
525 iwl_write_targ_mem(priv, a, 0);
526 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
527 iwl_write_targ_mem(priv, a, 0);
528 for (; a < priv->scd_base_addr +
529 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
530 iwl_write_targ_mem(priv, a, 0);
531
532 /* Tel 4965 where to find Tx byte count tables */
533 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
534 priv->scd_bc_tbls.dma >> 10);
535
536 /* Enable DMA channel */
537 for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
538 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
539 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
540 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
541
542 /* Update FH chicken bits */
543 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
544 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
545 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
546
547 /* Disable chain mode for all queues */
548 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
549
550 /* Initialize each Tx queue (including the command queue) */
551 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
552
553 /* TFD circular buffer read/write indexes */
554 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
555 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
556
557 /* Max Tx Window size for Scheduler-ACK mode */
558 iwl_write_targ_mem(priv, priv->scd_base_addr +
559 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
560 (SCD_WIN_SIZE <<
561 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
562 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
563
564 /* Frame limit */
565 iwl_write_targ_mem(priv, priv->scd_base_addr +
566 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
567 sizeof(u32),
568 (SCD_FRAME_LIMIT <<
569 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
570 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
571
572 }
573 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
574 (1 << priv->hw_params.max_txq_num) - 1);
575
576 /* Activate all Tx DMA/FIFO channels */
577 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
578
579 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
580
581 /* make sure all queue are not stopped */
582 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
583 for (i = 0; i < 4; i++)
584 atomic_set(&priv->queue_stop_count[i], 0);
585
586 /* reset to 0 to enable all the queue first */
587 priv->txq_ctx_active_msk = 0;
588 /* Map each Tx/cmd queue to its corresponding fifo */
589 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
590 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
591 int ac = default_queue_to_tx_fifo[i];
592
593 iwl_txq_ctx_activate(priv, i);
594
595 if (ac == IWL_TX_FIFO_UNUSED)
596 continue;
597
598 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
599 }
600
601 spin_unlock_irqrestore(&priv->lock, flags);
602
603 return 0;
604 }
605
606 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
607 .min_nrg_cck = 97,
608 .max_nrg_cck = 0, /* not used, set to 0 */
609
610 .auto_corr_min_ofdm = 85,
611 .auto_corr_min_ofdm_mrc = 170,
612 .auto_corr_min_ofdm_x1 = 105,
613 .auto_corr_min_ofdm_mrc_x1 = 220,
614
615 .auto_corr_max_ofdm = 120,
616 .auto_corr_max_ofdm_mrc = 210,
617 .auto_corr_max_ofdm_x1 = 140,
618 .auto_corr_max_ofdm_mrc_x1 = 270,
619
620 .auto_corr_min_cck = 125,
621 .auto_corr_max_cck = 200,
622 .auto_corr_min_cck_mrc = 200,
623 .auto_corr_max_cck_mrc = 400,
624
625 .nrg_th_cck = 100,
626 .nrg_th_ofdm = 100,
627
628 .barker_corr_th_min = 190,
629 .barker_corr_th_min_mrc = 390,
630 .nrg_th_cca = 62,
631 };
632
633 static void iwl4965_set_ct_threshold(struct iwl_priv *priv)
634 {
635 /* want Kelvin */
636 priv->hw_params.ct_kill_threshold =
637 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
638 }
639
640 /**
641 * iwl4965_hw_set_hw_params
642 *
643 * Called when initializing driver
644 */
645 static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
646 {
647 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
648 priv->cfg->mod_params->num_of_queues <= IWL49_NUM_QUEUES)
649 priv->cfg->num_of_queues =
650 priv->cfg->mod_params->num_of_queues;
651
652 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
653 priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
654 priv->hw_params.scd_bc_tbls_size =
655 priv->cfg->num_of_queues *
656 sizeof(struct iwl4965_scd_bc_tbl);
657 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
658 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
659 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
660 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
661 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
662 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
663 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
664
665 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
666
667 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
668 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
669 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
670 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
671 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
672 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
673
674 priv->hw_params.sens = &iwl4965_sensitivity;
675
676 return 0;
677 }
678
679 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
680 {
681 s32 sign = 1;
682
683 if (num < 0) {
684 sign = -sign;
685 num = -num;
686 }
687 if (denom < 0) {
688 sign = -sign;
689 denom = -denom;
690 }
691 *res = 1;
692 *res = ((num * 2 + denom) / (denom * 2)) * sign;
693
694 return 1;
695 }
696
697 /**
698 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
699 *
700 * Determines power supply voltage compensation for txpower calculations.
701 * Returns number of 1/2-dB steps to subtract from gain table index,
702 * to compensate for difference between power supply voltage during
703 * factory measurements, vs. current power supply voltage.
704 *
705 * Voltage indication is higher for lower voltage.
706 * Lower voltage requires more gain (lower gain table index).
707 */
708 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
709 s32 current_voltage)
710 {
711 s32 comp = 0;
712
713 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
714 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
715 return 0;
716
717 iwl4965_math_div_round(current_voltage - eeprom_voltage,
718 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
719
720 if (current_voltage > eeprom_voltage)
721 comp *= 2;
722 if ((comp < -2) || (comp > 2))
723 comp = 0;
724
725 return comp;
726 }
727
728 static s32 iwl4965_get_tx_atten_grp(u16 channel)
729 {
730 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
731 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
732 return CALIB_CH_GROUP_5;
733
734 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
735 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
736 return CALIB_CH_GROUP_1;
737
738 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
739 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
740 return CALIB_CH_GROUP_2;
741
742 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
743 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
744 return CALIB_CH_GROUP_3;
745
746 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
747 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
748 return CALIB_CH_GROUP_4;
749
750 return -1;
751 }
752
753 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
754 {
755 s32 b = -1;
756
757 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
758 if (priv->calib_info->band_info[b].ch_from == 0)
759 continue;
760
761 if ((channel >= priv->calib_info->band_info[b].ch_from)
762 && (channel <= priv->calib_info->band_info[b].ch_to))
763 break;
764 }
765
766 return b;
767 }
768
769 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
770 {
771 s32 val;
772
773 if (x2 == x1)
774 return y1;
775 else {
776 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
777 return val + y2;
778 }
779 }
780
781 /**
782 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
783 *
784 * Interpolates factory measurements from the two sample channels within a
785 * sub-band, to apply to channel of interest. Interpolation is proportional to
786 * differences in channel frequencies, which is proportional to differences
787 * in channel number.
788 */
789 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
790 struct iwl_eeprom_calib_ch_info *chan_info)
791 {
792 s32 s = -1;
793 u32 c;
794 u32 m;
795 const struct iwl_eeprom_calib_measure *m1;
796 const struct iwl_eeprom_calib_measure *m2;
797 struct iwl_eeprom_calib_measure *omeas;
798 u32 ch_i1;
799 u32 ch_i2;
800
801 s = iwl4965_get_sub_band(priv, channel);
802 if (s >= EEPROM_TX_POWER_BANDS) {
803 IWL_ERR(priv, "Tx Power can not find channel %d\n", channel);
804 return -1;
805 }
806
807 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
808 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
809 chan_info->ch_num = (u8) channel;
810
811 IWL_DEBUG_TXPOWER(priv, "channel %d subband %d factory cal ch %d & %d\n",
812 channel, s, ch_i1, ch_i2);
813
814 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
815 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
816 m1 = &(priv->calib_info->band_info[s].ch1.
817 measurements[c][m]);
818 m2 = &(priv->calib_info->band_info[s].ch2.
819 measurements[c][m]);
820 omeas = &(chan_info->measurements[c][m]);
821
822 omeas->actual_pow =
823 (u8) iwl4965_interpolate_value(channel, ch_i1,
824 m1->actual_pow,
825 ch_i2,
826 m2->actual_pow);
827 omeas->gain_idx =
828 (u8) iwl4965_interpolate_value(channel, ch_i1,
829 m1->gain_idx, ch_i2,
830 m2->gain_idx);
831 omeas->temperature =
832 (u8) iwl4965_interpolate_value(channel, ch_i1,
833 m1->temperature,
834 ch_i2,
835 m2->temperature);
836 omeas->pa_det =
837 (s8) iwl4965_interpolate_value(channel, ch_i1,
838 m1->pa_det, ch_i2,
839 m2->pa_det);
840
841 IWL_DEBUG_TXPOWER(priv,
842 "chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
843 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
844 IWL_DEBUG_TXPOWER(priv,
845 "chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
846 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
847 IWL_DEBUG_TXPOWER(priv,
848 "chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
849 m1->pa_det, m2->pa_det, omeas->pa_det);
850 IWL_DEBUG_TXPOWER(priv,
851 "chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
852 m1->temperature, m2->temperature,
853 omeas->temperature);
854 }
855 }
856
857 return 0;
858 }
859
860 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
861 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
862 static s32 back_off_table[] = {
863 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
864 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
865 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
866 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
867 10 /* CCK */
868 };
869
870 /* Thermal compensation values for txpower for various frequency ranges ...
871 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
872 static struct iwl4965_txpower_comp_entry {
873 s32 degrees_per_05db_a;
874 s32 degrees_per_05db_a_denom;
875 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
876 {9, 2}, /* group 0 5.2, ch 34-43 */
877 {4, 1}, /* group 1 5.2, ch 44-70 */
878 {4, 1}, /* group 2 5.2, ch 71-124 */
879 {4, 1}, /* group 3 5.2, ch 125-200 */
880 {3, 1} /* group 4 2.4, ch all */
881 };
882
883 static s32 get_min_power_index(s32 rate_power_index, u32 band)
884 {
885 if (!band) {
886 if ((rate_power_index & 7) <= 4)
887 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
888 }
889 return MIN_TX_GAIN_INDEX;
890 }
891
892 struct gain_entry {
893 u8 dsp;
894 u8 radio;
895 };
896
897 static const struct gain_entry gain_table[2][108] = {
898 /* 5.2GHz power gain index table */
899 {
900 {123, 0x3F}, /* highest txpower */
901 {117, 0x3F},
902 {110, 0x3F},
903 {104, 0x3F},
904 {98, 0x3F},
905 {110, 0x3E},
906 {104, 0x3E},
907 {98, 0x3E},
908 {110, 0x3D},
909 {104, 0x3D},
910 {98, 0x3D},
911 {110, 0x3C},
912 {104, 0x3C},
913 {98, 0x3C},
914 {110, 0x3B},
915 {104, 0x3B},
916 {98, 0x3B},
917 {110, 0x3A},
918 {104, 0x3A},
919 {98, 0x3A},
920 {110, 0x39},
921 {104, 0x39},
922 {98, 0x39},
923 {110, 0x38},
924 {104, 0x38},
925 {98, 0x38},
926 {110, 0x37},
927 {104, 0x37},
928 {98, 0x37},
929 {110, 0x36},
930 {104, 0x36},
931 {98, 0x36},
932 {110, 0x35},
933 {104, 0x35},
934 {98, 0x35},
935 {110, 0x34},
936 {104, 0x34},
937 {98, 0x34},
938 {110, 0x33},
939 {104, 0x33},
940 {98, 0x33},
941 {110, 0x32},
942 {104, 0x32},
943 {98, 0x32},
944 {110, 0x31},
945 {104, 0x31},
946 {98, 0x31},
947 {110, 0x30},
948 {104, 0x30},
949 {98, 0x30},
950 {110, 0x25},
951 {104, 0x25},
952 {98, 0x25},
953 {110, 0x24},
954 {104, 0x24},
955 {98, 0x24},
956 {110, 0x23},
957 {104, 0x23},
958 {98, 0x23},
959 {110, 0x22},
960 {104, 0x18},
961 {98, 0x18},
962 {110, 0x17},
963 {104, 0x17},
964 {98, 0x17},
965 {110, 0x16},
966 {104, 0x16},
967 {98, 0x16},
968 {110, 0x15},
969 {104, 0x15},
970 {98, 0x15},
971 {110, 0x14},
972 {104, 0x14},
973 {98, 0x14},
974 {110, 0x13},
975 {104, 0x13},
976 {98, 0x13},
977 {110, 0x12},
978 {104, 0x08},
979 {98, 0x08},
980 {110, 0x07},
981 {104, 0x07},
982 {98, 0x07},
983 {110, 0x06},
984 {104, 0x06},
985 {98, 0x06},
986 {110, 0x05},
987 {104, 0x05},
988 {98, 0x05},
989 {110, 0x04},
990 {104, 0x04},
991 {98, 0x04},
992 {110, 0x03},
993 {104, 0x03},
994 {98, 0x03},
995 {110, 0x02},
996 {104, 0x02},
997 {98, 0x02},
998 {110, 0x01},
999 {104, 0x01},
1000 {98, 0x01},
1001 {110, 0x00},
1002 {104, 0x00},
1003 {98, 0x00},
1004 {93, 0x00},
1005 {88, 0x00},
1006 {83, 0x00},
1007 {78, 0x00},
1008 },
1009 /* 2.4GHz power gain index table */
1010 {
1011 {110, 0x3f}, /* highest txpower */
1012 {104, 0x3f},
1013 {98, 0x3f},
1014 {110, 0x3e},
1015 {104, 0x3e},
1016 {98, 0x3e},
1017 {110, 0x3d},
1018 {104, 0x3d},
1019 {98, 0x3d},
1020 {110, 0x3c},
1021 {104, 0x3c},
1022 {98, 0x3c},
1023 {110, 0x3b},
1024 {104, 0x3b},
1025 {98, 0x3b},
1026 {110, 0x3a},
1027 {104, 0x3a},
1028 {98, 0x3a},
1029 {110, 0x39},
1030 {104, 0x39},
1031 {98, 0x39},
1032 {110, 0x38},
1033 {104, 0x38},
1034 {98, 0x38},
1035 {110, 0x37},
1036 {104, 0x37},
1037 {98, 0x37},
1038 {110, 0x36},
1039 {104, 0x36},
1040 {98, 0x36},
1041 {110, 0x35},
1042 {104, 0x35},
1043 {98, 0x35},
1044 {110, 0x34},
1045 {104, 0x34},
1046 {98, 0x34},
1047 {110, 0x33},
1048 {104, 0x33},
1049 {98, 0x33},
1050 {110, 0x32},
1051 {104, 0x32},
1052 {98, 0x32},
1053 {110, 0x31},
1054 {104, 0x31},
1055 {98, 0x31},
1056 {110, 0x30},
1057 {104, 0x30},
1058 {98, 0x30},
1059 {110, 0x6},
1060 {104, 0x6},
1061 {98, 0x6},
1062 {110, 0x5},
1063 {104, 0x5},
1064 {98, 0x5},
1065 {110, 0x4},
1066 {104, 0x4},
1067 {98, 0x4},
1068 {110, 0x3},
1069 {104, 0x3},
1070 {98, 0x3},
1071 {110, 0x2},
1072 {104, 0x2},
1073 {98, 0x2},
1074 {110, 0x1},
1075 {104, 0x1},
1076 {98, 0x1},
1077 {110, 0x0},
1078 {104, 0x0},
1079 {98, 0x0},
1080 {97, 0},
1081 {96, 0},
1082 {95, 0},
1083 {94, 0},
1084 {93, 0},
1085 {92, 0},
1086 {91, 0},
1087 {90, 0},
1088 {89, 0},
1089 {88, 0},
1090 {87, 0},
1091 {86, 0},
1092 {85, 0},
1093 {84, 0},
1094 {83, 0},
1095 {82, 0},
1096 {81, 0},
1097 {80, 0},
1098 {79, 0},
1099 {78, 0},
1100 {77, 0},
1101 {76, 0},
1102 {75, 0},
1103 {74, 0},
1104 {73, 0},
1105 {72, 0},
1106 {71, 0},
1107 {70, 0},
1108 {69, 0},
1109 {68, 0},
1110 {67, 0},
1111 {66, 0},
1112 {65, 0},
1113 {64, 0},
1114 {63, 0},
1115 {62, 0},
1116 {61, 0},
1117 {60, 0},
1118 {59, 0},
1119 }
1120 };
1121
1122 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1123 u8 is_ht40, u8 ctrl_chan_high,
1124 struct iwl4965_tx_power_db *tx_power_tbl)
1125 {
1126 u8 saturation_power;
1127 s32 target_power;
1128 s32 user_target_power;
1129 s32 power_limit;
1130 s32 current_temp;
1131 s32 reg_limit;
1132 s32 current_regulatory;
1133 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1134 int i;
1135 int c;
1136 const struct iwl_channel_info *ch_info = NULL;
1137 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1138 const struct iwl_eeprom_calib_measure *measurement;
1139 s16 voltage;
1140 s32 init_voltage;
1141 s32 voltage_compensation;
1142 s32 degrees_per_05db_num;
1143 s32 degrees_per_05db_denom;
1144 s32 factory_temp;
1145 s32 temperature_comp[2];
1146 s32 factory_gain_index[2];
1147 s32 factory_actual_pwr[2];
1148 s32 power_index;
1149
1150 /* tx_power_user_lmt is in dBm, convert to half-dBm (half-dB units
1151 * are used for indexing into txpower table) */
1152 user_target_power = 2 * priv->tx_power_user_lmt;
1153
1154 /* Get current (RXON) channel, band, width */
1155 IWL_DEBUG_TXPOWER(priv, "chan %d band %d is_ht40 %d\n", channel, band,
1156 is_ht40);
1157
1158 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1159
1160 if (!is_channel_valid(ch_info))
1161 return -EINVAL;
1162
1163 /* get txatten group, used to select 1) thermal txpower adjustment
1164 * and 2) mimo txpower balance between Tx chains. */
1165 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1166 if (txatten_grp < 0) {
1167 IWL_ERR(priv, "Can't find txatten group for channel %d.\n",
1168 channel);
1169 return -EINVAL;
1170 }
1171
1172 IWL_DEBUG_TXPOWER(priv, "channel %d belongs to txatten group %d\n",
1173 channel, txatten_grp);
1174
1175 if (is_ht40) {
1176 if (ctrl_chan_high)
1177 channel -= 2;
1178 else
1179 channel += 2;
1180 }
1181
1182 /* hardware txpower limits ...
1183 * saturation (clipping distortion) txpowers are in half-dBm */
1184 if (band)
1185 saturation_power = priv->calib_info->saturation_power24;
1186 else
1187 saturation_power = priv->calib_info->saturation_power52;
1188
1189 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1190 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1191 if (band)
1192 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1193 else
1194 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1195 }
1196
1197 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1198 * max_power_avg values are in dBm, convert * 2 */
1199 if (is_ht40)
1200 reg_limit = ch_info->ht40_max_power_avg * 2;
1201 else
1202 reg_limit = ch_info->max_power_avg * 2;
1203
1204 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1205 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1206 if (band)
1207 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1208 else
1209 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1210 }
1211
1212 /* Interpolate txpower calibration values for this channel,
1213 * based on factory calibration tests on spaced channels. */
1214 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1215
1216 /* calculate tx gain adjustment based on power supply voltage */
1217 voltage = le16_to_cpu(priv->calib_info->voltage);
1218 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1219 voltage_compensation =
1220 iwl4965_get_voltage_compensation(voltage, init_voltage);
1221
1222 IWL_DEBUG_TXPOWER(priv, "curr volt %d eeprom volt %d volt comp %d\n",
1223 init_voltage,
1224 voltage, voltage_compensation);
1225
1226 /* get current temperature (Celsius) */
1227 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1228 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1229 current_temp = KELVIN_TO_CELSIUS(current_temp);
1230
1231 /* select thermal txpower adjustment params, based on channel group
1232 * (same frequency group used for mimo txatten adjustment) */
1233 degrees_per_05db_num =
1234 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1235 degrees_per_05db_denom =
1236 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1237
1238 /* get per-chain txpower values from factory measurements */
1239 for (c = 0; c < 2; c++) {
1240 measurement = &ch_eeprom_info.measurements[c][1];
1241
1242 /* txgain adjustment (in half-dB steps) based on difference
1243 * between factory and current temperature */
1244 factory_temp = measurement->temperature;
1245 iwl4965_math_div_round((current_temp - factory_temp) *
1246 degrees_per_05db_denom,
1247 degrees_per_05db_num,
1248 &temperature_comp[c]);
1249
1250 factory_gain_index[c] = measurement->gain_idx;
1251 factory_actual_pwr[c] = measurement->actual_pow;
1252
1253 IWL_DEBUG_TXPOWER(priv, "chain = %d\n", c);
1254 IWL_DEBUG_TXPOWER(priv, "fctry tmp %d, "
1255 "curr tmp %d, comp %d steps\n",
1256 factory_temp, current_temp,
1257 temperature_comp[c]);
1258
1259 IWL_DEBUG_TXPOWER(priv, "fctry idx %d, fctry pwr %d\n",
1260 factory_gain_index[c],
1261 factory_actual_pwr[c]);
1262 }
1263
1264 /* for each of 33 bit-rates (including 1 for CCK) */
1265 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1266 u8 is_mimo_rate;
1267 union iwl4965_tx_power_dual_stream tx_power;
1268
1269 /* for mimo, reduce each chain's txpower by half
1270 * (3dB, 6 steps), so total output power is regulatory
1271 * compliant. */
1272 if (i & 0x8) {
1273 current_regulatory = reg_limit -
1274 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1275 is_mimo_rate = 1;
1276 } else {
1277 current_regulatory = reg_limit;
1278 is_mimo_rate = 0;
1279 }
1280
1281 /* find txpower limit, either hardware or regulatory */
1282 power_limit = saturation_power - back_off_table[i];
1283 if (power_limit > current_regulatory)
1284 power_limit = current_regulatory;
1285
1286 /* reduce user's txpower request if necessary
1287 * for this rate on this channel */
1288 target_power = user_target_power;
1289 if (target_power > power_limit)
1290 target_power = power_limit;
1291
1292 IWL_DEBUG_TXPOWER(priv, "rate %d sat %d reg %d usr %d tgt %d\n",
1293 i, saturation_power - back_off_table[i],
1294 current_regulatory, user_target_power,
1295 target_power);
1296
1297 /* for each of 2 Tx chains (radio transmitters) */
1298 for (c = 0; c < 2; c++) {
1299 s32 atten_value;
1300
1301 if (is_mimo_rate)
1302 atten_value =
1303 (s32)le32_to_cpu(priv->card_alive_init.
1304 tx_atten[txatten_grp][c]);
1305 else
1306 atten_value = 0;
1307
1308 /* calculate index; higher index means lower txpower */
1309 power_index = (u8) (factory_gain_index[c] -
1310 (target_power -
1311 factory_actual_pwr[c]) -
1312 temperature_comp[c] -
1313 voltage_compensation +
1314 atten_value);
1315
1316 /* IWL_DEBUG_TXPOWER(priv, "calculated txpower index %d\n",
1317 power_index); */
1318
1319 if (power_index < get_min_power_index(i, band))
1320 power_index = get_min_power_index(i, band);
1321
1322 /* adjust 5 GHz index to support negative indexes */
1323 if (!band)
1324 power_index += 9;
1325
1326 /* CCK, rate 32, reduce txpower for CCK */
1327 if (i == POWER_TABLE_CCK_ENTRY)
1328 power_index +=
1329 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1330
1331 /* stay within the table! */
1332 if (power_index > 107) {
1333 IWL_WARN(priv, "txpower index %d > 107\n",
1334 power_index);
1335 power_index = 107;
1336 }
1337 if (power_index < 0) {
1338 IWL_WARN(priv, "txpower index %d < 0\n",
1339 power_index);
1340 power_index = 0;
1341 }
1342
1343 /* fill txpower command for this rate/chain */
1344 tx_power.s.radio_tx_gain[c] =
1345 gain_table[band][power_index].radio;
1346 tx_power.s.dsp_predis_atten[c] =
1347 gain_table[band][power_index].dsp;
1348
1349 IWL_DEBUG_TXPOWER(priv, "chain %d mimo %d index %d "
1350 "gain 0x%02x dsp %d\n",
1351 c, atten_value, power_index,
1352 tx_power.s.radio_tx_gain[c],
1353 tx_power.s.dsp_predis_atten[c]);
1354 } /* for each chain */
1355
1356 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1357
1358 } /* for each rate */
1359
1360 return 0;
1361 }
1362
1363 /**
1364 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
1365 *
1366 * Uses the active RXON for channel, band, and characteristics (ht40, high)
1367 * The power limit is taken from priv->tx_power_user_lmt.
1368 */
1369 static int iwl4965_send_tx_power(struct iwl_priv *priv)
1370 {
1371 struct iwl4965_txpowertable_cmd cmd = { 0 };
1372 int ret;
1373 u8 band = 0;
1374 bool is_ht40 = false;
1375 u8 ctrl_chan_high = 0;
1376
1377 if (test_bit(STATUS_SCANNING, &priv->status)) {
1378 /* If this gets hit a lot, switch it to a BUG() and catch
1379 * the stack trace to find out who is calling this during
1380 * a scan. */
1381 IWL_WARN(priv, "TX Power requested while scanning!\n");
1382 return -EAGAIN;
1383 }
1384
1385 band = priv->band == IEEE80211_BAND_2GHZ;
1386
1387 is_ht40 = is_ht40_channel(priv->active_rxon.flags);
1388
1389 if (is_ht40 &&
1390 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1391 ctrl_chan_high = 1;
1392
1393 cmd.band = band;
1394 cmd.channel = priv->active_rxon.channel;
1395
1396 ret = iwl4965_fill_txpower_tbl(priv, band,
1397 le16_to_cpu(priv->active_rxon.channel),
1398 is_ht40, ctrl_chan_high, &cmd.tx_power);
1399 if (ret)
1400 goto out;
1401
1402 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1403
1404 out:
1405 return ret;
1406 }
1407
1408 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1409 {
1410 int ret = 0;
1411 struct iwl4965_rxon_assoc_cmd rxon_assoc;
1412 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1413 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1414
1415 if ((rxon1->flags == rxon2->flags) &&
1416 (rxon1->filter_flags == rxon2->filter_flags) &&
1417 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1418 (rxon1->ofdm_ht_single_stream_basic_rates ==
1419 rxon2->ofdm_ht_single_stream_basic_rates) &&
1420 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1421 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1422 (rxon1->rx_chain == rxon2->rx_chain) &&
1423 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1424 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1425 return 0;
1426 }
1427
1428 rxon_assoc.flags = priv->staging_rxon.flags;
1429 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1430 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1431 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1432 rxon_assoc.reserved = 0;
1433 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1434 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1435 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1436 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1437 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1438
1439 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1440 sizeof(rxon_assoc), &rxon_assoc, NULL);
1441 if (ret)
1442 return ret;
1443
1444 return ret;
1445 }
1446
1447 static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1448 {
1449 int rc;
1450 u8 band = 0;
1451 bool is_ht40 = false;
1452 u8 ctrl_chan_high = 0;
1453 struct iwl4965_channel_switch_cmd cmd;
1454 const struct iwl_channel_info *ch_info;
1455
1456 band = priv->band == IEEE80211_BAND_2GHZ;
1457
1458 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1459
1460 is_ht40 = is_ht40_channel(priv->staging_rxon.flags);
1461
1462 if (is_ht40 &&
1463 (priv->staging_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1464 ctrl_chan_high = 1;
1465
1466 cmd.band = band;
1467 cmd.expect_beacon = 0;
1468 cmd.channel = cpu_to_le16(channel);
1469 cmd.rxon_flags = priv->staging_rxon.flags;
1470 cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
1471 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1472 if (ch_info)
1473 cmd.expect_beacon = is_channel_radar(ch_info);
1474 else {
1475 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1476 priv->active_rxon.channel, channel);
1477 return -EFAULT;
1478 }
1479
1480 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_ht40,
1481 ctrl_chan_high, &cmd.tx_power);
1482 if (rc) {
1483 IWL_DEBUG_11H(priv, "error:%d fill txpower_tbl\n", rc);
1484 return rc;
1485 }
1486
1487 priv->switch_rxon.channel = cpu_to_le16(channel);
1488 priv->switch_rxon.switch_in_progress = true;
1489
1490 return iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
1491 }
1492
1493 /**
1494 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
1495 */
1496 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
1497 struct iwl_tx_queue *txq,
1498 u16 byte_cnt)
1499 {
1500 struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
1501 int txq_id = txq->q.id;
1502 int write_ptr = txq->q.write_ptr;
1503 int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1504 __le16 bc_ent;
1505
1506 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
1507
1508 bc_ent = cpu_to_le16(len & 0xFFF);
1509 /* Set up byte count within first 256 entries */
1510 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
1511
1512 /* If within first 64 entries, duplicate at end */
1513 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
1514 scd_bc_tbl[txq_id].
1515 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
1516 }
1517
1518 /**
1519 * sign_extend - Sign extend a value using specified bit as sign-bit
1520 *
1521 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1522 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1523 *
1524 * @param oper value to sign extend
1525 * @param index 0 based bit index (0<=index<32) to sign bit
1526 */
1527 static s32 sign_extend(u32 oper, int index)
1528 {
1529 u8 shift = 31 - index;
1530
1531 return (s32)(oper << shift) >> shift;
1532 }
1533
1534 /**
1535 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
1536 * @statistics: Provides the temperature reading from the uCode
1537 *
1538 * A return of <0 indicates bogus data in the statistics
1539 */
1540 static int iwl4965_hw_get_temperature(struct iwl_priv *priv)
1541 {
1542 s32 temperature;
1543 s32 vt;
1544 s32 R1, R2, R3;
1545 u32 R4;
1546
1547 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1548 (priv->statistics.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK)) {
1549 IWL_DEBUG_TEMP(priv, "Running HT40 temperature calibration\n");
1550 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1551 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1552 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1553 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1554 } else {
1555 IWL_DEBUG_TEMP(priv, "Running temperature calibration\n");
1556 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1557 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1558 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1559 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1560 }
1561
1562 /*
1563 * Temperature is only 23 bits, so sign extend out to 32.
1564 *
1565 * NOTE If we haven't received a statistics notification yet
1566 * with an updated temperature, use R4 provided to us in the
1567 * "initialize" ALIVE response.
1568 */
1569 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1570 vt = sign_extend(R4, 23);
1571 else
1572 vt = sign_extend(
1573 le32_to_cpu(priv->statistics.general.temperature), 23);
1574
1575 IWL_DEBUG_TEMP(priv, "Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
1576
1577 if (R3 == R1) {
1578 IWL_ERR(priv, "Calibration conflict R1 == R3\n");
1579 return -1;
1580 }
1581
1582 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1583 * Add offset to center the adjustment around 0 degrees Centigrade. */
1584 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1585 temperature /= (R3 - R1);
1586 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
1587
1588 IWL_DEBUG_TEMP(priv, "Calibrated temperature: %dK, %dC\n",
1589 temperature, KELVIN_TO_CELSIUS(temperature));
1590
1591 return temperature;
1592 }
1593
1594 /* Adjust Txpower only if temperature variance is greater than threshold. */
1595 #define IWL_TEMPERATURE_THRESHOLD 3
1596
1597 /**
1598 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1599 *
1600 * If the temperature changed has changed sufficiently, then a recalibration
1601 * is needed.
1602 *
1603 * Assumes caller will replace priv->last_temperature once calibration
1604 * executed.
1605 */
1606 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
1607 {
1608 int temp_diff;
1609
1610 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1611 IWL_DEBUG_TEMP(priv, "Temperature not updated -- no statistics.\n");
1612 return 0;
1613 }
1614
1615 temp_diff = priv->temperature - priv->last_temperature;
1616
1617 /* get absolute value */
1618 if (temp_diff < 0) {
1619 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d\n", temp_diff);
1620 temp_diff = -temp_diff;
1621 } else if (temp_diff == 0)
1622 IWL_DEBUG_POWER(priv, "Temperature unchanged\n");
1623 else
1624 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d\n", temp_diff);
1625
1626 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1627 IWL_DEBUG_POWER(priv, " => thermal txpower calib not needed\n");
1628 return 0;
1629 }
1630
1631 IWL_DEBUG_POWER(priv, " => thermal txpower calib needed\n");
1632
1633 return 1;
1634 }
1635
1636 static void iwl4965_temperature_calib(struct iwl_priv *priv)
1637 {
1638 s32 temp;
1639
1640 temp = iwl4965_hw_get_temperature(priv);
1641 if (temp < 0)
1642 return;
1643
1644 if (priv->temperature != temp) {
1645 if (priv->temperature)
1646 IWL_DEBUG_TEMP(priv, "Temperature changed "
1647 "from %dC to %dC\n",
1648 KELVIN_TO_CELSIUS(priv->temperature),
1649 KELVIN_TO_CELSIUS(temp));
1650 else
1651 IWL_DEBUG_TEMP(priv, "Temperature "
1652 "initialized to %dC\n",
1653 KELVIN_TO_CELSIUS(temp));
1654 }
1655
1656 priv->temperature = temp;
1657 iwl_tt_handler(priv);
1658 set_bit(STATUS_TEMPERATURE, &priv->status);
1659
1660 if (!priv->disable_tx_power_cal &&
1661 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1662 iwl4965_is_temp_calib_needed(priv))
1663 queue_work(priv->workqueue, &priv->txpower_work);
1664 }
1665
1666 /**
1667 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1668 */
1669 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
1670 u16 txq_id)
1671 {
1672 /* Simply stop the queue, but don't change any configuration;
1673 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1674 iwl_write_prph(priv,
1675 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1676 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1677 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1678 }
1679
1680 /**
1681 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
1682 * priv->lock must be held by the caller
1683 */
1684 static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1685 u16 ssn_idx, u8 tx_fifo)
1686 {
1687 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1688 (IWL49_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
1689 <= txq_id)) {
1690 IWL_WARN(priv,
1691 "queue number out of range: %d, must be %d to %d\n",
1692 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1693 IWL49_FIRST_AMPDU_QUEUE +
1694 priv->cfg->num_of_ampdu_queues - 1);
1695 return -EINVAL;
1696 }
1697
1698 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1699
1700 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1701
1702 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1703 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1704 /* supposes that ssn_idx is valid (!= 0xFFF) */
1705 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1706
1707 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1708 iwl_txq_ctx_deactivate(priv, txq_id);
1709 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1710
1711 return 0;
1712 }
1713
1714 /**
1715 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1716 */
1717 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
1718 u16 txq_id)
1719 {
1720 u32 tbl_dw_addr;
1721 u32 tbl_dw;
1722 u16 scd_q2ratid;
1723
1724 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1725
1726 tbl_dw_addr = priv->scd_base_addr +
1727 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
1728
1729 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
1730
1731 if (txq_id & 0x1)
1732 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1733 else
1734 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1735
1736 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
1737
1738 return 0;
1739 }
1740
1741
1742 /**
1743 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1744 *
1745 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
1746 * i.e. it must be one of the higher queues used for aggregation
1747 */
1748 static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1749 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1750 {
1751 unsigned long flags;
1752 u16 ra_tid;
1753
1754 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1755 (IWL49_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
1756 <= txq_id)) {
1757 IWL_WARN(priv,
1758 "queue number out of range: %d, must be %d to %d\n",
1759 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1760 IWL49_FIRST_AMPDU_QUEUE +
1761 priv->cfg->num_of_ampdu_queues - 1);
1762 return -EINVAL;
1763 }
1764
1765 ra_tid = BUILD_RAxTID(sta_id, tid);
1766
1767 /* Modify device's station table to Tx this TID */
1768 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1769
1770 spin_lock_irqsave(&priv->lock, flags);
1771
1772 /* Stop this Tx queue before configuring it */
1773 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1774
1775 /* Map receiver-address / traffic-ID to this queue */
1776 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1777
1778 /* Set this queue as a chain-building queue */
1779 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1780
1781 /* Place first TFD at index corresponding to start sequence number.
1782 * Assumes that ssn_idx is valid (!= 0xFFF) */
1783 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1784 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1785 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1786
1787 /* Set up Tx window size and frame limit for this queue */
1788 iwl_write_targ_mem(priv,
1789 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1790 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1791 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1792
1793 iwl_write_targ_mem(priv, priv->scd_base_addr +
1794 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1795 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1796 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1797
1798 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1799
1800 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1801 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1802
1803 spin_unlock_irqrestore(&priv->lock, flags);
1804
1805 return 0;
1806 }
1807
1808
1809 static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
1810 {
1811 switch (cmd_id) {
1812 case REPLY_RXON:
1813 return (u16) sizeof(struct iwl4965_rxon_cmd);
1814 default:
1815 return len;
1816 }
1817 }
1818
1819 static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1820 {
1821 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
1822 addsta->mode = cmd->mode;
1823 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
1824 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
1825 addsta->station_flags = cmd->station_flags;
1826 addsta->station_flags_msk = cmd->station_flags_msk;
1827 addsta->tid_disable_tx = cmd->tid_disable_tx;
1828 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
1829 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
1830 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
1831 addsta->sleep_tx_count = cmd->sleep_tx_count;
1832 addsta->reserved1 = cpu_to_le16(0);
1833 addsta->reserved2 = cpu_to_le16(0);
1834
1835 return (u16)sizeof(struct iwl4965_addsta_cmd);
1836 }
1837
1838 static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
1839 {
1840 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
1841 }
1842
1843 /**
1844 * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
1845 */
1846 static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
1847 struct iwl_ht_agg *agg,
1848 struct iwl4965_tx_resp *tx_resp,
1849 int txq_id, u16 start_idx)
1850 {
1851 u16 status;
1852 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
1853 struct ieee80211_tx_info *info = NULL;
1854 struct ieee80211_hdr *hdr = NULL;
1855 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1856 int i, sh, idx;
1857 u16 seq;
1858 if (agg->wait_for_ba)
1859 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1860
1861 agg->frame_count = tx_resp->frame_count;
1862 agg->start_idx = start_idx;
1863 agg->rate_n_flags = rate_n_flags;
1864 agg->bitmap = 0;
1865
1866 /* num frames attempted by Tx command */
1867 if (agg->frame_count == 1) {
1868 /* Only one frame was attempted; no block-ack will arrive */
1869 status = le16_to_cpu(frame_status[0].status);
1870 idx = start_idx;
1871
1872 /* FIXME: code repetition */
1873 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1874 agg->frame_count, agg->start_idx, idx);
1875
1876 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1877 info->status.rates[0].count = tx_resp->failure_frame + 1;
1878 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1879 info->flags |= iwl_tx_status_to_mac80211(status);
1880 iwlagn_hwrate_to_tx_control(priv, rate_n_flags, info);
1881 /* FIXME: code repetition end */
1882
1883 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1884 status & 0xff, tx_resp->failure_frame);
1885 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1886
1887 agg->wait_for_ba = 0;
1888 } else {
1889 /* Two or more frames were attempted; expect block-ack */
1890 u64 bitmap = 0;
1891 int start = agg->start_idx;
1892
1893 /* Construct bit-map of pending frames within Tx window */
1894 for (i = 0; i < agg->frame_count; i++) {
1895 u16 sc;
1896 status = le16_to_cpu(frame_status[i].status);
1897 seq = le16_to_cpu(frame_status[i].sequence);
1898 idx = SEQ_TO_INDEX(seq);
1899 txq_id = SEQ_TO_QUEUE(seq);
1900
1901 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1902 AGG_TX_STATE_ABORT_MSK))
1903 continue;
1904
1905 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1906 agg->frame_count, txq_id, idx);
1907
1908 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1909 if (!hdr) {
1910 IWL_ERR(priv,
1911 "BUG_ON idx doesn't point to valid skb"
1912 " idx=%d, txq_id=%d\n", idx, txq_id);
1913 return -1;
1914 }
1915
1916 sc = le16_to_cpu(hdr->seq_ctrl);
1917 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1918 IWL_ERR(priv,
1919 "BUG_ON idx doesn't match seq control"
1920 " idx=%d, seq_idx=%d, seq=%d\n",
1921 idx, SEQ_TO_SN(sc), hdr->seq_ctrl);
1922 return -1;
1923 }
1924
1925 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1926 i, idx, SEQ_TO_SN(sc));
1927
1928 sh = idx - start;
1929 if (sh > 64) {
1930 sh = (start - idx) + 0xff;
1931 bitmap = bitmap << sh;
1932 sh = 0;
1933 start = idx;
1934 } else if (sh < -64)
1935 sh = 0xff - (start - idx);
1936 else if (sh < 0) {
1937 sh = start - idx;
1938 start = idx;
1939 bitmap = bitmap << sh;
1940 sh = 0;
1941 }
1942 bitmap |= 1ULL << sh;
1943 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1944 start, (unsigned long long)bitmap);
1945 }
1946
1947 agg->bitmap = bitmap;
1948 agg->start_idx = start;
1949 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1950 agg->frame_count, agg->start_idx,
1951 (unsigned long long)agg->bitmap);
1952
1953 if (bitmap)
1954 agg->wait_for_ba = 1;
1955 }
1956 return 0;
1957 }
1958
1959 static u8 iwl_find_station(struct iwl_priv *priv, const u8 *addr)
1960 {
1961 int i;
1962 int start = 0;
1963 int ret = IWL_INVALID_STATION;
1964 unsigned long flags;
1965
1966 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
1967 (priv->iw_mode == NL80211_IFTYPE_AP))
1968 start = IWL_STA_ID;
1969
1970 if (is_broadcast_ether_addr(addr))
1971 return priv->hw_params.bcast_sta_id;
1972
1973 spin_lock_irqsave(&priv->sta_lock, flags);
1974 for (i = start; i < priv->hw_params.max_stations; i++)
1975 if (priv->stations[i].used &&
1976 (!compare_ether_addr(priv->stations[i].sta.sta.addr,
1977 addr))) {
1978 ret = i;
1979 goto out;
1980 }
1981
1982 IWL_DEBUG_ASSOC_LIMIT(priv, "can not find STA %pM total %d\n",
1983 addr, priv->num_stations);
1984
1985 out:
1986 /*
1987 * It may be possible that more commands interacting with stations
1988 * arrive before we completed processing the adding of
1989 * station
1990 */
1991 if (ret != IWL_INVALID_STATION &&
1992 (!(priv->stations[ret].used & IWL_STA_UCODE_ACTIVE) ||
1993 ((priv->stations[ret].used & IWL_STA_UCODE_ACTIVE) &&
1994 (priv->stations[ret].used & IWL_STA_UCODE_INPROGRESS)))) {
1995 IWL_ERR(priv, "Requested station info for sta %d before ready.\n",
1996 ret);
1997 ret = IWL_INVALID_STATION;
1998 }
1999 spin_unlock_irqrestore(&priv->sta_lock, flags);
2000 return ret;
2001 }
2002
2003 static int iwl_get_ra_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
2004 {
2005 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
2006 return IWL_AP_ID;
2007 } else {
2008 u8 *da = ieee80211_get_DA(hdr);
2009 return iwl_find_station(priv, da);
2010 }
2011 }
2012
2013 /**
2014 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
2015 */
2016 static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
2017 struct iwl_rx_mem_buffer *rxb)
2018 {
2019 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2020 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2021 int txq_id = SEQ_TO_QUEUE(sequence);
2022 int index = SEQ_TO_INDEX(sequence);
2023 struct iwl_tx_queue *txq = &priv->txq[txq_id];
2024 struct ieee80211_hdr *hdr;
2025 struct ieee80211_tx_info *info;
2026 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2027 u32 status = le32_to_cpu(tx_resp->u.status);
2028 int uninitialized_var(tid);
2029 int sta_id;
2030 int freed;
2031 u8 *qc = NULL;
2032 unsigned long flags;
2033
2034 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
2035 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
2036 "is out of range [0-%d] %d %d\n", txq_id,
2037 index, txq->q.n_bd, txq->q.write_ptr,
2038 txq->q.read_ptr);
2039 return;
2040 }
2041
2042 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
2043 memset(&info->status, 0, sizeof(info->status));
2044
2045 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
2046 if (ieee80211_is_data_qos(hdr->frame_control)) {
2047 qc = ieee80211_get_qos_ctl(hdr);
2048 tid = qc[0] & 0xf;
2049 }
2050
2051 sta_id = iwl_get_ra_sta_id(priv, hdr);
2052 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2053 IWL_ERR(priv, "Station not known\n");
2054 return;
2055 }
2056
2057 spin_lock_irqsave(&priv->sta_lock, flags);
2058 if (txq->sched_retry) {
2059 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2060 struct iwl_ht_agg *agg = NULL;
2061 WARN_ON(!qc);
2062
2063 agg = &priv->stations[sta_id].tid[tid].agg;
2064
2065 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
2066
2067 /* check if BAR is needed */
2068 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2069 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2070
2071 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2072 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2073 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim scd_ssn "
2074 "%d index %d\n", scd_ssn , index);
2075 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
2076 if (qc)
2077 iwl_free_tfds_in_queue(priv, sta_id,
2078 tid, freed);
2079
2080 if (priv->mac80211_registered &&
2081 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
2082 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
2083 if (agg->state == IWL_AGG_OFF)
2084 iwl_wake_queue(priv, txq_id);
2085 else
2086 iwl_wake_queue(priv, txq->swq_id);
2087 }
2088 }
2089 } else {
2090 info->status.rates[0].count = tx_resp->failure_frame + 1;
2091 info->flags |= iwl_tx_status_to_mac80211(status);
2092 iwlagn_hwrate_to_tx_control(priv,
2093 le32_to_cpu(tx_resp->rate_n_flags),
2094 info);
2095
2096 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) "
2097 "rate_n_flags 0x%x retries %d\n",
2098 txq_id,
2099 iwl_get_tx_fail_reason(status), status,
2100 le32_to_cpu(tx_resp->rate_n_flags),
2101 tx_resp->failure_frame);
2102
2103 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
2104 if (qc && likely(sta_id != IWL_INVALID_STATION))
2105 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
2106 else if (sta_id == IWL_INVALID_STATION)
2107 IWL_DEBUG_TX_REPLY(priv, "Station not known\n");
2108
2109 if (priv->mac80211_registered &&
2110 (iwl_queue_space(&txq->q) > txq->q.low_mark))
2111 iwl_wake_queue(priv, txq_id);
2112 }
2113 if (qc && likely(sta_id != IWL_INVALID_STATION))
2114 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
2115
2116 iwl_check_abort_status(priv, tx_resp->frame_count, status);
2117
2118 spin_unlock_irqrestore(&priv->sta_lock, flags);
2119 }
2120
2121 static int iwl4965_calc_rssi(struct iwl_priv *priv,
2122 struct iwl_rx_phy_res *rx_resp)
2123 {
2124 /* data from PHY/DSP regarding signal strength, etc.,
2125 * contents are always there, not configurable by host. */
2126 struct iwl4965_rx_non_cfg_phy *ncphy =
2127 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
2128 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
2129 >> IWL49_AGC_DB_POS;
2130
2131 u32 valid_antennae =
2132 (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
2133 >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
2134 u8 max_rssi = 0;
2135 u32 i;
2136
2137 /* Find max rssi among 3 possible receivers.
2138 * These values are measured by the digital signal processor (DSP).
2139 * They should stay fairly constant even as the signal strength varies,
2140 * if the radio's automatic gain control (AGC) is working right.
2141 * AGC value (see below) will provide the "interesting" info. */
2142 for (i = 0; i < 3; i++)
2143 if (valid_antennae & (1 << i))
2144 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2145
2146 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2147 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2148 max_rssi, agc);
2149
2150 /* dBm = max_rssi dB - agc dB - constant.
2151 * Higher AGC (higher radio gain) means lower signal. */
2152 return max_rssi - agc - IWLAGN_RSSI_OFFSET;
2153 }
2154
2155
2156 /* Set up 4965-specific Rx frame reply handlers */
2157 static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
2158 {
2159 /* Legacy Rx frames */
2160 priv->rx_handlers[REPLY_RX] = iwlagn_rx_reply_rx;
2161 /* Tx response */
2162 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
2163 }
2164
2165 static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
2166 {
2167 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
2168 }
2169
2170 static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
2171 {
2172 cancel_work_sync(&priv->txpower_work);
2173 }
2174
2175 static struct iwl_hcmd_ops iwl4965_hcmd = {
2176 .rxon_assoc = iwl4965_send_rxon_assoc,
2177 .commit_rxon = iwl_commit_rxon,
2178 .set_rxon_chain = iwl_set_rxon_chain,
2179 .send_bt_config = iwl_send_bt_config,
2180 };
2181
2182 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
2183 .get_hcmd_size = iwl4965_get_hcmd_size,
2184 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
2185 .chain_noise_reset = iwl4965_chain_noise_reset,
2186 .gain_computation = iwl4965_gain_computation,
2187 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2188 .calc_rssi = iwl4965_calc_rssi,
2189 .request_scan = iwlagn_request_scan,
2190 };
2191
2192 static struct iwl_lib_ops iwl4965_lib = {
2193 .set_hw_params = iwl4965_hw_set_hw_params,
2194 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
2195 .txq_set_sched = iwl4965_txq_set_sched,
2196 .txq_agg_enable = iwl4965_txq_agg_enable,
2197 .txq_agg_disable = iwl4965_txq_agg_disable,
2198 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
2199 .txq_free_tfd = iwl_hw_txq_free_tfd,
2200 .txq_init = iwl_hw_tx_queue_init,
2201 .rx_handler_setup = iwl4965_rx_handler_setup,
2202 .setup_deferred_work = iwl4965_setup_deferred_work,
2203 .cancel_deferred_work = iwl4965_cancel_deferred_work,
2204 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2205 .alive_notify = iwl4965_alive_notify,
2206 .init_alive_start = iwl4965_init_alive_start,
2207 .load_ucode = iwl4965_load_bsm,
2208 .dump_nic_event_log = iwl_dump_nic_event_log,
2209 .dump_nic_error_log = iwl_dump_nic_error_log,
2210 .dump_fh = iwl_dump_fh,
2211 .set_channel_switch = iwl4965_hw_channel_switch,
2212 .apm_ops = {
2213 .init = iwl_apm_init,
2214 .stop = iwl_apm_stop,
2215 .config = iwl4965_nic_config,
2216 .set_pwr_src = iwl_set_pwr_src,
2217 },
2218 .eeprom_ops = {
2219 .regulatory_bands = {
2220 EEPROM_REGULATORY_BAND_1_CHANNELS,
2221 EEPROM_REGULATORY_BAND_2_CHANNELS,
2222 EEPROM_REGULATORY_BAND_3_CHANNELS,
2223 EEPROM_REGULATORY_BAND_4_CHANNELS,
2224 EEPROM_REGULATORY_BAND_5_CHANNELS,
2225 EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS,
2226 EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS
2227 },
2228 .verify_signature = iwlcore_eeprom_verify_signature,
2229 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2230 .release_semaphore = iwlcore_eeprom_release_semaphore,
2231 .calib_version = iwl4965_eeprom_calib_version,
2232 .query_addr = iwlcore_eeprom_query_addr,
2233 },
2234 .send_tx_power = iwl4965_send_tx_power,
2235 .update_chain_flags = iwl_update_chain_flags,
2236 .post_associate = iwl_post_associate,
2237 .config_ap = iwl_config_ap,
2238 .isr = iwl_isr_legacy,
2239 .temp_ops = {
2240 .temperature = iwl4965_temperature_calib,
2241 .set_ct_kill = iwl4965_set_ct_threshold,
2242 },
2243 .manage_ibss_station = iwlagn_manage_ibss_station,
2244 .debugfs_ops = {
2245 .rx_stats_read = iwl_ucode_rx_stats_read,
2246 .tx_stats_read = iwl_ucode_tx_stats_read,
2247 .general_stats_read = iwl_ucode_general_stats_read,
2248 },
2249 .check_plcp_health = iwl_good_plcp_health,
2250 };
2251
2252 static const struct iwl_ops iwl4965_ops = {
2253 .lib = &iwl4965_lib,
2254 .hcmd = &iwl4965_hcmd,
2255 .utils = &iwl4965_hcmd_utils,
2256 .led = &iwlagn_led_ops,
2257 };
2258
2259 struct iwl_cfg iwl4965_agn_cfg = {
2260 .name = "Intel(R) Wireless WiFi Link 4965AGN",
2261 .fw_name_pre = IWL4965_FW_PRE,
2262 .ucode_api_max = IWL4965_UCODE_API_MAX,
2263 .ucode_api_min = IWL4965_UCODE_API_MIN,
2264 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
2265 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
2266 .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
2267 .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
2268 .ops = &iwl4965_ops,
2269 .num_of_queues = IWL49_NUM_QUEUES,
2270 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
2271 .mod_params = &iwlagn_mod_params,
2272 .valid_tx_ant = ANT_AB,
2273 .valid_rx_ant = ANT_ABC,
2274 .pll_cfg_val = 0,
2275 .set_l0s = true,
2276 .use_bsm = true,
2277 .use_isr_legacy = true,
2278 .ht_greenfield_support = false,
2279 .broken_powersave = true,
2280 .led_compensation = 61,
2281 .chain_noise_num_beacons = IWL4965_CAL_NUM_BEACONS,
2282 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2283 .monitor_recover_period = IWL_MONITORING_PERIOD,
2284 .temperature_kelvin = true,
2285 .max_event_log_size = 512,
2286 .tx_power_by_driver = true,
2287 .ucode_tracing = true,
2288 .sensitivity_calib_by_driver = true,
2289 .chain_noise_calib_by_driver = true,
2290 /*
2291 * Force use of chains B and C for scan RX on 5 GHz band
2292 * because the device has off-channel reception on chain A.
2293 */
2294 .scan_antennas[IEEE80211_BAND_5GHZ] = ANT_BC,
2295 };
2296
2297 /* Module firmware */
2298 MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE(IWL4965_UCODE_API_MAX));
2299
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