2 * Copyright (C) 2003-2015 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/gpio.h>
16 #include <linux/platform_device.h>
17 #include <linux/of_device.h>
18 #include <linux/module.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
23 * XLP GPIO has multiple 32 bit registers for each feature where each register
24 * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
25 * require 3 32-bit registers for each feature.
26 * Here we only define offset of the first register for each feature. Offset of
27 * the registers for pins greater than 32 can be calculated as following(Use
28 * GPIO_INT_STAT as example):
30 * offset = (gpio / XLP_GPIO_REGSZ) * 4;
31 * reg_addr = addr + offset;
33 * where addr is base address of the that feature register and gpio is the pin.
35 #define GPIO_OUTPUT_EN 0x00
36 #define GPIO_PADDRV 0x08
37 #define GPIO_INT_EN00 0x18
38 #define GPIO_INT_EN10 0x20
39 #define GPIO_INT_EN20 0x28
40 #define GPIO_INT_EN30 0x30
41 #define GPIO_INT_POL 0x38
42 #define GPIO_INT_TYPE 0x40
43 #define GPIO_INT_STAT 0x48
45 #define GPIO_9XX_BYTESWAP 0X00
46 #define GPIO_9XX_CTRL 0X04
47 #define GPIO_9XX_OUTPUT_EN 0x14
48 #define GPIO_9XX_PADDRV 0x24
50 * Only for 4 interrupt enable reg are defined for now,
51 * total reg available are 12.
53 #define GPIO_9XX_INT_EN00 0x44
54 #define GPIO_9XX_INT_EN10 0x54
55 #define GPIO_9XX_INT_EN20 0x64
56 #define GPIO_9XX_INT_EN30 0x74
57 #define GPIO_9XX_INT_POL 0x104
58 #define GPIO_9XX_INT_TYPE 0x114
59 #define GPIO_9XX_INT_STAT 0x124
61 #define GPIO_3XX_INT_EN00 0x18
62 #define GPIO_3XX_INT_EN10 0x20
63 #define GPIO_3XX_INT_EN20 0x28
64 #define GPIO_3XX_INT_EN30 0x30
65 #define GPIO_3XX_INT_POL 0x78
66 #define GPIO_3XX_INT_TYPE 0x80
67 #define GPIO_3XX_INT_STAT 0x88
69 /* Interrupt type register mask */
70 #define XLP_GPIO_IRQ_TYPE_LVL 0x0
71 #define XLP_GPIO_IRQ_TYPE_EDGE 0x1
73 /* Interrupt polarity register mask */
74 #define XLP_GPIO_IRQ_POL_HIGH 0x0
75 #define XLP_GPIO_IRQ_POL_LOW 0x1
77 #define XLP_GPIO_REGSZ 32
78 #define XLP_GPIO_IRQ_BASE 768
79 #define XLP_MAX_NR_GPIO 96
81 /* XLP variants supported by this driver */
83 XLP_GPIO_VARIANT_XLP832
= 1,
84 XLP_GPIO_VARIANT_XLP316
,
85 XLP_GPIO_VARIANT_XLP208
,
86 XLP_GPIO_VARIANT_XLP980
,
87 XLP_GPIO_VARIANT_XLP532
90 struct xlp_gpio_priv
{
91 struct gpio_chip chip
;
92 DECLARE_BITMAP(gpio_enabled_mask
, XLP_MAX_NR_GPIO
);
93 void __iomem
*gpio_intr_en
; /* pointer to first intr enable reg */
94 void __iomem
*gpio_intr_stat
; /* pointer to first intr status reg */
95 void __iomem
*gpio_intr_type
; /* pointer to first intr type reg */
96 void __iomem
*gpio_intr_pol
; /* pointer to first intr polarity reg */
97 void __iomem
*gpio_out_en
; /* pointer to first output enable reg */
98 void __iomem
*gpio_paddrv
; /* pointer to first pad drive reg */
102 static struct xlp_gpio_priv
*gpio_chip_to_xlp_priv(struct gpio_chip
*gc
)
104 return container_of(gc
, struct xlp_gpio_priv
, chip
);
107 static int xlp_gpio_get_reg(void __iomem
*addr
, unsigned gpio
)
111 pos
= gpio
% XLP_GPIO_REGSZ
;
112 regset
= (gpio
/ XLP_GPIO_REGSZ
) * 4;
113 return !!(readl(addr
+ regset
) & BIT(pos
));
116 static void xlp_gpio_set_reg(void __iomem
*addr
, unsigned gpio
, int state
)
118 u32 value
, pos
, regset
;
120 pos
= gpio
% XLP_GPIO_REGSZ
;
121 regset
= (gpio
/ XLP_GPIO_REGSZ
) * 4;
122 value
= readl(addr
+ regset
);
129 writel(value
, addr
+ regset
);
132 static void xlp_gpio_irq_disable(struct irq_data
*d
)
134 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
135 struct xlp_gpio_priv
*priv
= gpio_chip_to_xlp_priv(gc
);
138 spin_lock_irqsave(&priv
->lock
, flags
);
139 xlp_gpio_set_reg(priv
->gpio_intr_en
, d
->hwirq
, 0x0);
140 __clear_bit(d
->hwirq
, priv
->gpio_enabled_mask
);
141 spin_unlock_irqrestore(&priv
->lock
, flags
);
144 static void xlp_gpio_irq_mask_ack(struct irq_data
*d
)
146 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
147 struct xlp_gpio_priv
*priv
= gpio_chip_to_xlp_priv(gc
);
150 spin_lock_irqsave(&priv
->lock
, flags
);
151 xlp_gpio_set_reg(priv
->gpio_intr_en
, d
->hwirq
, 0x0);
152 xlp_gpio_set_reg(priv
->gpio_intr_stat
, d
->hwirq
, 0x1);
153 __clear_bit(d
->hwirq
, priv
->gpio_enabled_mask
);
154 spin_unlock_irqrestore(&priv
->lock
, flags
);
157 static void xlp_gpio_irq_unmask(struct irq_data
*d
)
159 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
160 struct xlp_gpio_priv
*priv
= gpio_chip_to_xlp_priv(gc
);
163 spin_lock_irqsave(&priv
->lock
, flags
);
164 xlp_gpio_set_reg(priv
->gpio_intr_en
, d
->hwirq
, 0x1);
165 __set_bit(d
->hwirq
, priv
->gpio_enabled_mask
);
166 spin_unlock_irqrestore(&priv
->lock
, flags
);
169 static int xlp_gpio_set_irq_type(struct irq_data
*d
, unsigned int type
)
171 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
172 struct xlp_gpio_priv
*priv
= gpio_chip_to_xlp_priv(gc
);
176 case IRQ_TYPE_EDGE_RISING
:
177 irq_type
= XLP_GPIO_IRQ_TYPE_EDGE
;
178 pol
= XLP_GPIO_IRQ_POL_HIGH
;
180 case IRQ_TYPE_EDGE_FALLING
:
181 irq_type
= XLP_GPIO_IRQ_TYPE_EDGE
;
182 pol
= XLP_GPIO_IRQ_POL_LOW
;
184 case IRQ_TYPE_LEVEL_HIGH
:
185 irq_type
= XLP_GPIO_IRQ_TYPE_LVL
;
186 pol
= XLP_GPIO_IRQ_POL_HIGH
;
188 case IRQ_TYPE_LEVEL_LOW
:
189 irq_type
= XLP_GPIO_IRQ_TYPE_LVL
;
190 pol
= XLP_GPIO_IRQ_POL_LOW
;
196 xlp_gpio_set_reg(priv
->gpio_intr_type
, d
->hwirq
, irq_type
);
197 xlp_gpio_set_reg(priv
->gpio_intr_pol
, d
->hwirq
, pol
);
202 static struct irq_chip xlp_gpio_irq_chip
= {
204 .irq_mask_ack
= xlp_gpio_irq_mask_ack
,
205 .irq_disable
= xlp_gpio_irq_disable
,
206 .irq_set_type
= xlp_gpio_set_irq_type
,
207 .irq_unmask
= xlp_gpio_irq_unmask
,
208 .flags
= IRQCHIP_ONESHOT_SAFE
,
211 static irqreturn_t
xlp_gpio_generic_handler(int irq
, void *data
)
213 struct xlp_gpio_priv
*priv
= data
;
219 for_each_set_bit(gpio
, priv
->gpio_enabled_mask
, XLP_MAX_NR_GPIO
) {
220 if (regoff
!= gpio
/ XLP_GPIO_REGSZ
) {
221 regoff
= gpio
/ XLP_GPIO_REGSZ
;
222 gpio_stat
= readl(priv
->gpio_intr_stat
+ regoff
* 4);
224 if (gpio_stat
& BIT(gpio
% XLP_GPIO_REGSZ
))
225 generic_handle_irq(irq_find_mapping(
226 priv
->chip
.irqdomain
, gpio
));
232 static int xlp_gpio_dir_output(struct gpio_chip
*gc
, unsigned gpio
, int state
)
234 struct xlp_gpio_priv
*priv
= gpio_chip_to_xlp_priv(gc
);
236 BUG_ON(gpio
>= gc
->ngpio
);
237 xlp_gpio_set_reg(priv
->gpio_out_en
, gpio
, 0x1);
242 static int xlp_gpio_dir_input(struct gpio_chip
*gc
, unsigned gpio
)
244 struct xlp_gpio_priv
*priv
= gpio_chip_to_xlp_priv(gc
);
246 BUG_ON(gpio
>= gc
->ngpio
);
247 xlp_gpio_set_reg(priv
->gpio_out_en
, gpio
, 0x0);
252 static int xlp_gpio_get(struct gpio_chip
*gc
, unsigned gpio
)
254 struct xlp_gpio_priv
*priv
= gpio_chip_to_xlp_priv(gc
);
256 BUG_ON(gpio
>= gc
->ngpio
);
257 return xlp_gpio_get_reg(priv
->gpio_paddrv
, gpio
);
260 static void xlp_gpio_set(struct gpio_chip
*gc
, unsigned gpio
, int state
)
262 struct xlp_gpio_priv
*priv
= gpio_chip_to_xlp_priv(gc
);
264 BUG_ON(gpio
>= gc
->ngpio
);
265 xlp_gpio_set_reg(priv
->gpio_paddrv
, gpio
, state
);
268 static const struct of_device_id xlp_gpio_of_ids
[] = {
270 .compatible
= "netlogic,xlp832-gpio",
271 .data
= (void *)XLP_GPIO_VARIANT_XLP832
,
274 .compatible
= "netlogic,xlp316-gpio",
275 .data
= (void *)XLP_GPIO_VARIANT_XLP316
,
278 .compatible
= "netlogic,xlp208-gpio",
279 .data
= (void *)XLP_GPIO_VARIANT_XLP208
,
282 .compatible
= "netlogic,xlp980-gpio",
283 .data
= (void *)XLP_GPIO_VARIANT_XLP980
,
286 .compatible
= "netlogic,xlp532-gpio",
287 .data
= (void *)XLP_GPIO_VARIANT_XLP532
,
291 MODULE_DEVICE_TABLE(of
, xlp_gpio_of_ids
);
293 static int xlp_gpio_probe(struct platform_device
*pdev
)
295 struct gpio_chip
*gc
;
296 struct resource
*iores
;
297 struct xlp_gpio_priv
*priv
;
298 const struct of_device_id
*of_id
;
299 void __iomem
*gpio_base
;
300 int irq_base
, irq
, err
;
304 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
308 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
312 gpio_base
= devm_ioremap_resource(&pdev
->dev
, iores
);
313 if (IS_ERR(gpio_base
))
314 return PTR_ERR(gpio_base
);
316 irq
= platform_get_irq(pdev
, 0);
320 of_id
= of_match_device(xlp_gpio_of_ids
, &pdev
->dev
);
322 dev_err(&pdev
->dev
, "Failed to get soc type!\n");
326 soc_type
= (uintptr_t) of_id
->data
;
329 case XLP_GPIO_VARIANT_XLP832
:
330 priv
->gpio_out_en
= gpio_base
+ GPIO_OUTPUT_EN
;
331 priv
->gpio_paddrv
= gpio_base
+ GPIO_PADDRV
;
332 priv
->gpio_intr_stat
= gpio_base
+ GPIO_INT_STAT
;
333 priv
->gpio_intr_type
= gpio_base
+ GPIO_INT_TYPE
;
334 priv
->gpio_intr_pol
= gpio_base
+ GPIO_INT_POL
;
335 priv
->gpio_intr_en
= gpio_base
+ GPIO_INT_EN00
;
338 case XLP_GPIO_VARIANT_XLP208
:
339 case XLP_GPIO_VARIANT_XLP316
:
340 priv
->gpio_out_en
= gpio_base
+ GPIO_OUTPUT_EN
;
341 priv
->gpio_paddrv
= gpio_base
+ GPIO_PADDRV
;
342 priv
->gpio_intr_stat
= gpio_base
+ GPIO_3XX_INT_STAT
;
343 priv
->gpio_intr_type
= gpio_base
+ GPIO_3XX_INT_TYPE
;
344 priv
->gpio_intr_pol
= gpio_base
+ GPIO_3XX_INT_POL
;
345 priv
->gpio_intr_en
= gpio_base
+ GPIO_3XX_INT_EN00
;
347 ngpio
= (soc_type
== XLP_GPIO_VARIANT_XLP208
) ? 42 : 57;
349 case XLP_GPIO_VARIANT_XLP980
:
350 case XLP_GPIO_VARIANT_XLP532
:
351 priv
->gpio_out_en
= gpio_base
+ GPIO_9XX_OUTPUT_EN
;
352 priv
->gpio_paddrv
= gpio_base
+ GPIO_9XX_PADDRV
;
353 priv
->gpio_intr_stat
= gpio_base
+ GPIO_9XX_INT_STAT
;
354 priv
->gpio_intr_type
= gpio_base
+ GPIO_9XX_INT_TYPE
;
355 priv
->gpio_intr_pol
= gpio_base
+ GPIO_9XX_INT_POL
;
356 priv
->gpio_intr_en
= gpio_base
+ GPIO_9XX_INT_EN00
;
358 ngpio
= (soc_type
== XLP_GPIO_VARIANT_XLP980
) ? 66 : 67;
361 dev_err(&pdev
->dev
, "Unknown Processor type!\n");
365 bitmap_zero(priv
->gpio_enabled_mask
, XLP_MAX_NR_GPIO
);
369 gc
->owner
= THIS_MODULE
;
370 gc
->label
= dev_name(&pdev
->dev
);
372 gc
->dev
= &pdev
->dev
;
374 gc
->of_node
= pdev
->dev
.of_node
;
375 gc
->direction_output
= xlp_gpio_dir_output
;
376 gc
->direction_input
= xlp_gpio_dir_input
;
377 gc
->set
= xlp_gpio_set
;
378 gc
->get
= xlp_gpio_get
;
380 spin_lock_init(&priv
->lock
);
382 err
= devm_request_irq(&pdev
->dev
, irq
, xlp_gpio_generic_handler
,
383 IRQ_TYPE_NONE
, pdev
->name
, priv
);
387 irq_base
= irq_alloc_descs(-1, XLP_GPIO_IRQ_BASE
, gc
->ngpio
, 0);
389 dev_err(&pdev
->dev
, "Failed to allocate IRQ numbers\n");
393 err
= gpiochip_add(gc
);
397 err
= gpiochip_irqchip_add(gc
, &xlp_gpio_irq_chip
, irq_base
,
398 handle_level_irq
, IRQ_TYPE_NONE
);
400 dev_err(&pdev
->dev
, "Could not connect irqchip to gpiochip!\n");
401 goto out_gpio_remove
;
404 dev_info(&pdev
->dev
, "registered %d GPIOs\n", gc
->ngpio
);
411 irq_free_descs(irq_base
, gc
->ngpio
);
415 static struct platform_driver xlp_gpio_driver
= {
418 .of_match_table
= xlp_gpio_of_ids
,
420 .probe
= xlp_gpio_probe
,
422 module_platform_driver(xlp_gpio_driver
);
424 MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
425 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
426 MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
427 MODULE_LICENSE("GPL v2");