| blob | cd39632a646edd2cbddb3aa06c328d1d81f8dac9 |
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
12 *
13 * Derived from book3s_rmhandlers.S and other files, which are:
14 *
15 * Copyright SUSE Linux Products GmbH 2009
16 *
17 * Authors: Alexander Graf <agraf@suse.de>
18 */
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
22 #include <asm/reg.h>
23 #include <asm/mmu.h>
24 #include <asm/page.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
32 #ifdef __LITTLE_ENDIAN__
33 #error Need to fix lppaca and SLB shadow accesses in little endian mode
34 #endif
36 /*****************************************************************************
37 * *
38 * Real Mode handlers that need to be in the linear mapping *
39 * *
40 ****************************************************************************/
42 .globl kvmppc_skip_interrupt
43 kvmppc_skip_interrupt:
44 mfspr r13,SPRN_SRR0
45 addi r13,r13,4
46 mtspr SPRN_SRR0,r13
47 GET_SCRATCH0(r13)
48 rfid
49 b .
51 .globl kvmppc_skip_Hinterrupt
52 kvmppc_skip_Hinterrupt:
53 mfspr r13,SPRN_HSRR0
54 addi r13,r13,4
55 mtspr SPRN_HSRR0,r13
56 GET_SCRATCH0(r13)
57 hrfid
58 b .
60 /*
61 * Call kvmppc_hv_entry in real mode.
62 * Must be called with interrupts hard-disabled.
63 *
64 * Input Registers:
65 *
66 * LR = return address to continue at after eventually re-enabling MMU
67 */
68 _GLOBAL(kvmppc_hv_entry_trampoline)
69 mflr r0
70 std r0, PPC_LR_STKOFF(r1)
71 stdu r1, -112(r1)
72 mfmsr r10
73 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
74 li r0,MSR_RI
75 andc r0,r10,r0
76 li r6,MSR_IR | MSR_DR
77 andc r6,r10,r6
78 mtmsrd r0,1 /* clear RI in MSR */
79 mtsrr0 r5
80 mtsrr1 r6
81 RFI
83 kvmppc_call_hv_entry:
84 bl kvmppc_hv_entry
86 /* Back from guest - restore host state and return to caller */
88 /* Restore host DABR and DABRX */
89 ld r5,HSTATE_DABR(r13)
90 li r6,7
91 mtspr SPRN_DABR,r5
92 mtspr SPRN_DABRX,r6
94 /* Restore SPRG3 */
95 ld r3,PACA_SPRG3(r13)
96 mtspr SPRN_SPRG3,r3
98 /*
99 * Reload DEC. HDEC interrupts were disabled when
100 * we reloaded the host's LPCR value.
101 */
102 ld r3, HSTATE_DECEXP(r13)
103 mftb r4
104 subf r4, r4, r3
105 mtspr SPRN_DEC, r4
107 /* Reload the host's PMU registers */
108 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
109 lbz r4, LPPACA_PMCINUSE(r3)
110 cmpwi r4, 0
111 beq 23f /* skip if not */
112 lwz r3, HSTATE_PMC(r13)
113 lwz r4, HSTATE_PMC + 4(r13)
114 lwz r5, HSTATE_PMC + 8(r13)
115 lwz r6, HSTATE_PMC + 12(r13)
116 lwz r8, HSTATE_PMC + 16(r13)
117 lwz r9, HSTATE_PMC + 20(r13)
118 BEGIN_FTR_SECTION
119 lwz r10, HSTATE_PMC + 24(r13)
120 lwz r11, HSTATE_PMC + 28(r13)
121 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
122 mtspr SPRN_PMC1, r3
123 mtspr SPRN_PMC2, r4
124 mtspr SPRN_PMC3, r5
125 mtspr SPRN_PMC4, r6
126 mtspr SPRN_PMC5, r8
127 mtspr SPRN_PMC6, r9
128 BEGIN_FTR_SECTION
129 mtspr SPRN_PMC7, r10
130 mtspr SPRN_PMC8, r11
131 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
132 ld r3, HSTATE_MMCR(r13)
133 ld r4, HSTATE_MMCR + 8(r13)
134 ld r5, HSTATE_MMCR + 16(r13)
135 mtspr SPRN_MMCR1, r4
136 mtspr SPRN_MMCRA, r5
137 mtspr SPRN_MMCR0, r3
138 isync
139 23:
141 /*
142 * For external and machine check interrupts, we need
143 * to call the Linux handler to process the interrupt.
144 * We do that by jumping to absolute address 0x500 for
145 * external interrupts, or the machine_check_fwnmi label
146 * for machine checks (since firmware might have patched
147 * the vector area at 0x200). The [h]rfid at the end of the
148 * handler will return to the book3s_hv_interrupts.S code.
149 * For other interrupts we do the rfid to get back
150 * to the book3s_hv_interrupts.S code here.
151 */
152 ld r8, 112+PPC_LR_STKOFF(r1)
153 addi r1, r1, 112
154 ld r7, HSTATE_HOST_MSR(r13)
156 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
157 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
158 BEGIN_FTR_SECTION
159 beq 11f
160 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
162 /* RFI into the highmem handler, or branch to interrupt handler */
163 mfmsr r6
164 li r0, MSR_RI
165 andc r6, r6, r0
166 mtmsrd r6, 1 /* Clear RI in MSR */
167 mtsrr0 r8
168 mtsrr1 r7
169 beqa 0x500 /* external interrupt (PPC970) */
170 beq cr1, 13f /* machine check */
171 RFI
173 /* On POWER7, we have external interrupts set to use HSRR0/1 */
174 11: mtspr SPRN_HSRR0, r8
175 mtspr SPRN_HSRR1, r7
176 ba 0x500
178 13: b machine_check_fwnmi
181 /*
182 * We come in here when wakened from nap mode on a secondary hw thread.
183 * Relocation is off and most register values are lost.
184 * r13 points to the PACA.
185 */
186 .globl kvm_start_guest
187 kvm_start_guest:
188 ld r1,PACAEMERGSP(r13)
189 subi r1,r1,STACK_FRAME_OVERHEAD
190 ld r2,PACATOC(r13)
192 li r0,KVM_HWTHREAD_IN_KVM
193 stb r0,HSTATE_HWTHREAD_STATE(r13)
195 /* NV GPR values from power7_idle() will no longer be valid */
196 li r0,1
197 stb r0,PACA_NAPSTATELOST(r13)
199 /* were we napping due to cede? */
200 lbz r0,HSTATE_NAPPING(r13)
201 cmpwi r0,0
202 bne kvm_end_cede
204 /*
205 * We weren't napping due to cede, so this must be a secondary
206 * thread being woken up to run a guest, or being woken up due
207 * to a stray IPI. (Or due to some machine check or hypervisor
208 * maintenance interrupt while the core is in KVM.)
209 */
211 /* Check the wake reason in SRR1 to see why we got here */
212 mfspr r3,SPRN_SRR1
213 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
214 cmpwi r3,4 /* was it an external interrupt? */
215 bne 27f /* if not */
216 ld r5,HSTATE_XICS_PHYS(r13)
217 li r7,XICS_XIRR /* if it was an external interrupt, */
218 lwzcix r8,r5,r7 /* get and ack the interrupt */
219 sync
220 clrldi. r9,r8,40 /* get interrupt source ID. */
221 beq 28f /* none there? */
222 cmpwi r9,XICS_IPI /* was it an IPI? */
223 bne 29f
224 li r0,0xff
225 li r6,XICS_MFRR
226 stbcix r0,r5,r6 /* clear IPI */
227 stwcix r8,r5,r7 /* EOI the interrupt */
228 sync /* order loading of vcpu after that */
230 /* get vcpu pointer, NULL if we have no vcpu to run */
231 ld r4,HSTATE_KVM_VCPU(r13)
232 cmpdi r4,0
233 /* if we have no vcpu to run, go back to sleep */
234 beq kvm_no_guest
235 b 30f
237 27: /* XXX should handle hypervisor maintenance interrupts etc. here */
238 b kvm_no_guest
239 28: /* SRR1 said external but ICP said nope?? */
240 b kvm_no_guest
241 29: /* External non-IPI interrupt to offline secondary thread? help?? */
242 stw r8,HSTATE_SAVED_XIRR(r13)
243 b kvm_no_guest
245 30: bl kvmppc_hv_entry
247 /* Back from the guest, go back to nap */
248 /* Clear our vcpu pointer so we don't come back in early */
249 li r0, 0
250 std r0, HSTATE_KVM_VCPU(r13)
251 lwsync
252 /* Clear any pending IPI - we're an offline thread */
253 ld r5, HSTATE_XICS_PHYS(r13)
254 li r7, XICS_XIRR
255 lwzcix r3, r5, r7 /* ack any pending interrupt */
256 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
257 beq 37f
258 sync
259 li r0, 0xff
260 li r6, XICS_MFRR
261 stbcix r0, r5, r6 /* clear the IPI */
262 stwcix r3, r5, r7 /* EOI it */
263 37: sync
265 /* increment the nap count and then go to nap mode */
266 ld r4, HSTATE_KVM_VCORE(r13)
267 addi r4, r4, VCORE_NAP_COUNT
268 lwsync /* make previous updates visible */
269 51: lwarx r3, 0, r4
270 addi r3, r3, 1
271 stwcx. r3, 0, r4
272 bne 51b
274 kvm_no_guest:
275 li r0, KVM_HWTHREAD_IN_NAP
276 stb r0, HSTATE_HWTHREAD_STATE(r13)
277 li r3, LPCR_PECE0
278 mfspr r4, SPRN_LPCR
279 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
280 mtspr SPRN_LPCR, r4
281 isync
282 std r0, HSTATE_SCRATCH0(r13)
283 ptesync
284 ld r0, HSTATE_SCRATCH0(r13)
285 1: cmpd r0, r0
286 bne 1b
287 nap
288 b .
290 /******************************************************************************
291 * *
292 * Entry code *
293 * *
294 *****************************************************************************/
296 .global kvmppc_hv_entry
297 kvmppc_hv_entry:
299 /* Required state:
300 *
301 * R4 = vcpu pointer
302 * MSR = ~IR|DR
303 * R13 = PACA
304 * R1 = host R1
305 * all other volatile GPRS = free
306 */
307 mflr r0
308 std r0, PPC_LR_STKOFF(r1)
309 stdu r1, -112(r1)
311 /* Set partition DABR */
312 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
313 li r5,3
314 ld r6,VCPU_DABR(r4)
315 mtspr SPRN_DABRX,r5
316 mtspr SPRN_DABR,r6
317 BEGIN_FTR_SECTION
318 isync
319 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
321 /* Load guest PMU registers */
322 /* R4 is live here (vcpu pointer) */
323 li r3, 1
324 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
325 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
326 isync
327 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
328 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
329 lwz r6, VCPU_PMC + 8(r4)
330 lwz r7, VCPU_PMC + 12(r4)
331 lwz r8, VCPU_PMC + 16(r4)
332 lwz r9, VCPU_PMC + 20(r4)
333 BEGIN_FTR_SECTION
334 lwz r10, VCPU_PMC + 24(r4)
335 lwz r11, VCPU_PMC + 28(r4)
336 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
337 mtspr SPRN_PMC1, r3
338 mtspr SPRN_PMC2, r5
339 mtspr SPRN_PMC3, r6
340 mtspr SPRN_PMC4, r7
341 mtspr SPRN_PMC5, r8
342 mtspr SPRN_PMC6, r9
343 BEGIN_FTR_SECTION
344 mtspr SPRN_PMC7, r10
345 mtspr SPRN_PMC8, r11
346 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
347 ld r3, VCPU_MMCR(r4)
348 ld r5, VCPU_MMCR + 8(r4)
349 ld r6, VCPU_MMCR + 16(r4)
350 ld r7, VCPU_SIAR(r4)
351 ld r8, VCPU_SDAR(r4)
352 mtspr SPRN_MMCR1, r5
353 mtspr SPRN_MMCRA, r6
354 mtspr SPRN_SIAR, r7
355 mtspr SPRN_SDAR, r8
356 mtspr SPRN_MMCR0, r3
357 isync
359 /* Load up FP, VMX and VSX registers */
360 bl kvmppc_load_fp
362 ld r14, VCPU_GPR(R14)(r4)
363 ld r15, VCPU_GPR(R15)(r4)
364 ld r16, VCPU_GPR(R16)(r4)
365 ld r17, VCPU_GPR(R17)(r4)
366 ld r18, VCPU_GPR(R18)(r4)
367 ld r19, VCPU_GPR(R19)(r4)
368 ld r20, VCPU_GPR(R20)(r4)
369 ld r21, VCPU_GPR(R21)(r4)
370 ld r22, VCPU_GPR(R22)(r4)
371 ld r23, VCPU_GPR(R23)(r4)
372 ld r24, VCPU_GPR(R24)(r4)
373 ld r25, VCPU_GPR(R25)(r4)
374 ld r26, VCPU_GPR(R26)(r4)
375 ld r27, VCPU_GPR(R27)(r4)
376 ld r28, VCPU_GPR(R28)(r4)
377 ld r29, VCPU_GPR(R29)(r4)
378 ld r30, VCPU_GPR(R30)(r4)
379 ld r31, VCPU_GPR(R31)(r4)
381 BEGIN_FTR_SECTION
382 /* Switch DSCR to guest value */
383 ld r5, VCPU_DSCR(r4)
384 mtspr SPRN_DSCR, r5
385 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
387 /*
388 * Set the decrementer to the guest decrementer.
389 */
390 ld r8,VCPU_DEC_EXPIRES(r4)
391 mftb r7
392 subf r3,r7,r8
393 mtspr SPRN_DEC,r3
394 stw r3,VCPU_DEC(r4)
396 ld r5, VCPU_SPRG0(r4)
397 ld r6, VCPU_SPRG1(r4)
398 ld r7, VCPU_SPRG2(r4)
399 ld r8, VCPU_SPRG3(r4)
400 mtspr SPRN_SPRG0, r5
401 mtspr SPRN_SPRG1, r6
402 mtspr SPRN_SPRG2, r7
403 mtspr SPRN_SPRG3, r8
405 /* Save R1 in the PACA */
406 std r1, HSTATE_HOST_R1(r13)
408 /* Load up DAR and DSISR */
409 ld r5, VCPU_DAR(r4)
410 lwz r6, VCPU_DSISR(r4)
411 mtspr SPRN_DAR, r5
412 mtspr SPRN_DSISR, r6
414 BEGIN_FTR_SECTION
415 /* Restore AMR and UAMOR, set AMOR to all 1s */
416 ld r5,VCPU_AMR(r4)
417 ld r6,VCPU_UAMOR(r4)
418 li r7,-1
419 mtspr SPRN_AMR,r5
420 mtspr SPRN_UAMOR,r6
421 mtspr SPRN_AMOR,r7
422 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
424 /* Clear out SLB */
425 li r6,0
426 slbmte r6,r6
427 slbia
428 ptesync
430 BEGIN_FTR_SECTION
431 b 30f
432 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
433 /*
434 * POWER7 host -> guest partition switch code.
435 * We don't have to lock against concurrent tlbies,
436 * but we do have to coordinate across hardware threads.
437 */
438 /* Increment entry count iff exit count is zero. */
439 ld r5,HSTATE_KVM_VCORE(r13)
440 addi r9,r5,VCORE_ENTRY_EXIT
441 21: lwarx r3,0,r9
442 cmpwi r3,0x100 /* any threads starting to exit? */
443 bge secondary_too_late /* if so we're too late to the party */
444 addi r3,r3,1
445 stwcx. r3,0,r9
446 bne 21b
448 /* Primary thread switches to guest partition. */
449 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
450 lwz r6,VCPU_PTID(r4)
451 cmpwi r6,0
452 bne 20f
453 ld r6,KVM_SDR1(r9)
454 lwz r7,KVM_LPID(r9)
455 li r0,LPID_RSVD /* switch to reserved LPID */
456 mtspr SPRN_LPID,r0
457 ptesync
458 mtspr SPRN_SDR1,r6 /* switch to partition page table */
459 mtspr SPRN_LPID,r7
460 isync
462 /* See if we need to flush the TLB */
463 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
464 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
465 srdi r6,r6,6 /* doubleword number */
466 sldi r6,r6,3 /* address offset */
467 add r6,r6,r9
468 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
469 li r0,1
470 sld r0,r0,r7
471 ld r7,0(r6)
472 and. r7,r7,r0
473 beq 22f
474 23: ldarx r7,0,r6 /* if set, clear the bit */
475 andc r7,r7,r0
476 stdcx. r7,0,r6
477 bne 23b
478 li r6,128 /* and flush the TLB */
479 mtctr r6
480 li r7,0x800 /* IS field = 0b10 */
481 ptesync
482 28: tlbiel r7
483 addi r7,r7,0x1000
484 bdnz 28b
485 ptesync
487 /* Add timebase offset onto timebase */
488 22: ld r8,VCORE_TB_OFFSET(r5)
489 cmpdi r8,0
490 beq 37f
491 mftb r6 /* current host timebase */
492 add r8,r8,r6
493 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
494 mftb r7 /* check if lower 24 bits overflowed */
495 clrldi r6,r6,40
496 clrldi r7,r7,40
497 cmpld r7,r6
498 bge 37f
499 addis r8,r8,0x100 /* if so, increment upper 40 bits */
500 mtspr SPRN_TBU40,r8
502 /* Load guest PCR value to select appropriate compat mode */
503 37: ld r7, VCORE_PCR(r5)
504 cmpdi r7, 0
505 beq 38f
506 mtspr SPRN_PCR, r7
507 38:
508 li r0,1
509 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
510 b 10f
512 /* Secondary threads wait for primary to have done partition switch */
513 20: lbz r0,VCORE_IN_GUEST(r5)
514 cmpwi r0,0
515 beq 20b
517 /* Set LPCR and RMOR. */
518 10: ld r8,VCORE_LPCR(r5)
519 mtspr SPRN_LPCR,r8
520 ld r8,KVM_RMOR(r9)
521 mtspr SPRN_RMOR,r8
522 isync
524 /* Increment yield count if they have a VPA */
525 ld r3, VCPU_VPA(r4)
526 cmpdi r3, 0
527 beq 25f
528 lwz r5, LPPACA_YIELDCOUNT(r3)
529 addi r5, r5, 1
530 stw r5, LPPACA_YIELDCOUNT(r3)
531 li r6, 1
532 stb r6, VCPU_VPA_DIRTY(r4)
533 25:
534 /* Check if HDEC expires soon */
535 mfspr r3,SPRN_HDEC
536 cmpwi r3,10
537 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
538 mr r9,r4
539 blt hdec_soon
541 /* Save purr/spurr */
542 mfspr r5,SPRN_PURR
543 mfspr r6,SPRN_SPURR
544 std r5,HSTATE_PURR(r13)
545 std r6,HSTATE_SPURR(r13)
546 ld r7,VCPU_PURR(r4)
547 ld r8,VCPU_SPURR(r4)
548 mtspr SPRN_PURR,r7
549 mtspr SPRN_SPURR,r8
550 b 31f
552 /*
553 * PPC970 host -> guest partition switch code.
554 * We have to lock against concurrent tlbies,
555 * using native_tlbie_lock to lock against host tlbies
556 * and kvm->arch.tlbie_lock to lock against guest tlbies.
557 * We also have to invalidate the TLB since its
558 * entries aren't tagged with the LPID.
559 */
560 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
562 /* first take native_tlbie_lock */
563 .section ".toc","aw"
564 toc_tlbie_lock:
565 .tc native_tlbie_lock[TC],native_tlbie_lock
566 .previous
567 ld r3,toc_tlbie_lock@toc(2)
568 #ifdef __BIG_ENDIAN__
569 lwz r8,PACA_LOCK_TOKEN(r13)
570 #else
571 lwz r8,PACAPACAINDEX(r13)
572 #endif
573 24: lwarx r0,0,r3
574 cmpwi r0,0
575 bne 24b
576 stwcx. r8,0,r3
577 bne 24b
578 isync
580 ld r5,HSTATE_KVM_VCORE(r13)
581 ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */
582 li r0,0x18f
583 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
584 or r0,r7,r0
585 ptesync
586 sync
587 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
588 isync
589 li r0,0
590 stw r0,0(r3) /* drop native_tlbie_lock */
592 /* invalidate the whole TLB */
593 li r0,256
594 mtctr r0
595 li r6,0
596 25: tlbiel r6
597 addi r6,r6,0x1000
598 bdnz 25b
599 ptesync
601 /* Take the guest's tlbie_lock */
602 addi r3,r9,KVM_TLBIE_LOCK
603 24: lwarx r0,0,r3
604 cmpwi r0,0
605 bne 24b
606 stwcx. r8,0,r3
607 bne 24b
608 isync
609 ld r6,KVM_SDR1(r9)
610 mtspr SPRN_SDR1,r6 /* switch to partition page table */
612 /* Set up HID4 with the guest's LPID etc. */
613 sync
614 mtspr SPRN_HID4,r7
615 isync
617 /* drop the guest's tlbie_lock */
618 li r0,0
619 stw r0,0(r3)
621 /* Check if HDEC expires soon */
622 mfspr r3,SPRN_HDEC
623 cmpwi r3,10
624 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
625 mr r9,r4
626 blt hdec_soon
628 /* Enable HDEC interrupts */
629 mfspr r0,SPRN_HID0
630 li r3,1
631 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
632 sync
633 mtspr SPRN_HID0,r0
634 mfspr r0,SPRN_HID0
635 mfspr r0,SPRN_HID0
636 mfspr r0,SPRN_HID0
637 mfspr r0,SPRN_HID0
638 mfspr r0,SPRN_HID0
639 mfspr r0,SPRN_HID0
641 /* Load up guest SLB entries */
642 31: lwz r5,VCPU_SLB_MAX(r4)
643 cmpwi r5,0
644 beq 9f
645 mtctr r5
646 addi r6,r4,VCPU_SLB
647 1: ld r8,VCPU_SLB_E(r6)
648 ld r9,VCPU_SLB_V(r6)
649 slbmte r9,r8
650 addi r6,r6,VCPU_SLB_SIZE
651 bdnz 1b
652 9:
654 /* Restore state of CTRL run bit; assume 1 on entry */
655 lwz r5,VCPU_CTRL(r4)
656 andi. r5,r5,1
657 bne 4f
658 mfspr r6,SPRN_CTRLF
659 clrrdi r6,r6,1
660 mtspr SPRN_CTRLT,r6
661 4:
662 ld r6, VCPU_CTR(r4)
663 lwz r7, VCPU_XER(r4)
665 mtctr r6
666 mtxer r7
668 ld r10, VCPU_PC(r4)
669 ld r11, VCPU_MSR(r4)
670 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
671 ld r6, VCPU_SRR0(r4)
672 ld r7, VCPU_SRR1(r4)
674 /* r11 = vcpu->arch.msr & ~MSR_HV */
675 rldicl r11, r11, 63 - MSR_HV_LG, 1
676 rotldi r11, r11, 1 + MSR_HV_LG
677 ori r11, r11, MSR_ME
679 /* Check if we can deliver an external or decrementer interrupt now */
680 ld r0,VCPU_PENDING_EXC(r4)
681 lis r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
682 and r0,r0,r8
683 cmpdi cr1,r0,0
684 andi. r0,r11,MSR_EE
685 beq cr1,11f
686 BEGIN_FTR_SECTION
687 mfspr r8,SPRN_LPCR
688 ori r8,r8,LPCR_MER
689 mtspr SPRN_LPCR,r8
690 isync
691 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
692 beq 5f
693 li r0,BOOK3S_INTERRUPT_EXTERNAL
694 12: mr r6,r10
695 mr r10,r0
696 mr r7,r11
697 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
698 rotldi r11,r11,63
699 b 5f
700 11: beq 5f
701 mfspr r0,SPRN_DEC
702 cmpwi r0,0
703 li r0,BOOK3S_INTERRUPT_DECREMENTER
704 blt 12b
706 /* Move SRR0 and SRR1 into the respective regs */
707 5: mtspr SPRN_SRR0, r6
708 mtspr SPRN_SRR1, r7
710 fast_guest_return:
711 li r0,0
712 stb r0,VCPU_CEDED(r4) /* cancel cede */
713 mtspr SPRN_HSRR0,r10
714 mtspr SPRN_HSRR1,r11
716 /* Activate guest mode, so faults get handled by KVM */
717 li r9, KVM_GUEST_MODE_GUEST
718 stb r9, HSTATE_IN_GUEST(r13)
720 /* Enter guest */
722 BEGIN_FTR_SECTION
723 ld r5, VCPU_CFAR(r4)
724 mtspr SPRN_CFAR, r5
725 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
726 BEGIN_FTR_SECTION
727 ld r0, VCPU_PPR(r4)
728 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
730 ld r5, VCPU_LR(r4)
731 lwz r6, VCPU_CR(r4)
732 mtlr r5
733 mtcr r6
735 ld r1, VCPU_GPR(R1)(r4)
736 ld r2, VCPU_GPR(R2)(r4)
737 ld r3, VCPU_GPR(R3)(r4)
738 ld r5, VCPU_GPR(R5)(r4)
739 ld r6, VCPU_GPR(R6)(r4)
740 ld r7, VCPU_GPR(R7)(r4)
741 ld r8, VCPU_GPR(R8)(r4)
742 ld r9, VCPU_GPR(R9)(r4)
743 ld r10, VCPU_GPR(R10)(r4)
744 ld r11, VCPU_GPR(R11)(r4)
745 ld r12, VCPU_GPR(R12)(r4)
746 ld r13, VCPU_GPR(R13)(r4)
748 BEGIN_FTR_SECTION
749 mtspr SPRN_PPR, r0
750 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
751 ld r0, VCPU_GPR(R0)(r4)
752 ld r4, VCPU_GPR(R4)(r4)
754 hrfid
755 b .
757 /******************************************************************************
758 * *
759 * Exit code *
760 * *
761 *****************************************************************************/
763 /*
764 * We come here from the first-level interrupt handlers.
765 */
766 .globl kvmppc_interrupt
767 kvmppc_interrupt:
768 /*
769 * Register contents:
770 * R12 = interrupt vector
771 * R13 = PACA
772 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
773 * guest R13 saved in SPRN_SCRATCH0
774 */
775 /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
776 std r9, HSTATE_HOST_R2(r13)
777 ld r9, HSTATE_KVM_VCPU(r13)
779 /* Save registers */
781 std r0, VCPU_GPR(R0)(r9)
782 std r1, VCPU_GPR(R1)(r9)
783 std r2, VCPU_GPR(R2)(r9)
784 std r3, VCPU_GPR(R3)(r9)
785 std r4, VCPU_GPR(R4)(r9)
786 std r5, VCPU_GPR(R5)(r9)
787 std r6, VCPU_GPR(R6)(r9)
788 std r7, VCPU_GPR(R7)(r9)
789 std r8, VCPU_GPR(R8)(r9)
790 ld r0, HSTATE_HOST_R2(r13)
791 std r0, VCPU_GPR(R9)(r9)
792 std r10, VCPU_GPR(R10)(r9)
793 std r11, VCPU_GPR(R11)(r9)
794 ld r3, HSTATE_SCRATCH0(r13)
795 lwz r4, HSTATE_SCRATCH1(r13)
796 std r3, VCPU_GPR(R12)(r9)
797 stw r4, VCPU_CR(r9)
798 BEGIN_FTR_SECTION
799 ld r3, HSTATE_CFAR(r13)
800 std r3, VCPU_CFAR(r9)
801 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
802 BEGIN_FTR_SECTION
803 ld r4, HSTATE_PPR(r13)
804 std r4, VCPU_PPR(r9)
805 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
807 /* Restore R1/R2 so we can handle faults */
808 ld r1, HSTATE_HOST_R1(r13)
809 ld r2, PACATOC(r13)
811 mfspr r10, SPRN_SRR0
812 mfspr r11, SPRN_SRR1
813 std r10, VCPU_SRR0(r9)
814 std r11, VCPU_SRR1(r9)
815 andi. r0, r12, 2 /* need to read HSRR0/1? */
816 beq 1f
817 mfspr r10, SPRN_HSRR0
818 mfspr r11, SPRN_HSRR1
819 clrrdi r12, r12, 2
820 1: std r10, VCPU_PC(r9)
821 std r11, VCPU_MSR(r9)
823 GET_SCRATCH0(r3)
824 mflr r4
825 std r3, VCPU_GPR(R13)(r9)
826 std r4, VCPU_LR(r9)
828 /* Unset guest mode */
829 li r0, KVM_GUEST_MODE_NONE
830 stb r0, HSTATE_IN_GUEST(r13)
832 stw r12,VCPU_TRAP(r9)
834 /* Save HEIR (HV emulation assist reg) in last_inst
835 if this is an HEI (HV emulation interrupt, e40) */
836 li r3,KVM_INST_FETCH_FAILED
837 BEGIN_FTR_SECTION
838 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
839 bne 11f
840 mfspr r3,SPRN_HEIR
841 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
842 11: stw r3,VCPU_LAST_INST(r9)
844 /* these are volatile across C function calls */
845 mfctr r3
846 mfxer r4
847 std r3, VCPU_CTR(r9)
848 stw r4, VCPU_XER(r9)
850 BEGIN_FTR_SECTION
851 /* If this is a page table miss then see if it's theirs or ours */
852 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
853 beq kvmppc_hdsi
854 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
855 beq kvmppc_hisi
856 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
858 /* See if this is a leftover HDEC interrupt */
859 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
860 bne 2f
861 mfspr r3,SPRN_HDEC
862 cmpwi r3,0
863 bge ignore_hdec
864 2:
865 /* See if this is an hcall we can handle in real mode */
866 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
867 beq hcall_try_real_mode
869 /* Only handle external interrupts here on arch 206 and later */
870 BEGIN_FTR_SECTION
871 b ext_interrupt_to_host
872 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
874 /* External interrupt ? */
875 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
876 bne+ ext_interrupt_to_host
878 /* External interrupt, first check for host_ipi. If this is
879 * set, we know the host wants us out so let's do it now
880 */
881 do_ext_interrupt:
882 bl kvmppc_read_intr
883 cmpdi r3, 0
884 bgt ext_interrupt_to_host
886 /* Allright, looks like an IPI for the guest, we need to set MER */
887 /* Check if any CPU is heading out to the host, if so head out too */
888 ld r5, HSTATE_KVM_VCORE(r13)
889 lwz r0, VCORE_ENTRY_EXIT(r5)
890 cmpwi r0, 0x100
891 bge ext_interrupt_to_host
893 /* See if there is a pending interrupt for the guest */
894 mfspr r8, SPRN_LPCR
895 ld r0, VCPU_PENDING_EXC(r9)
896 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
897 rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
898 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
899 beq 2f
901 /* And if the guest EE is set, we can deliver immediately, else
902 * we return to the guest with MER set
903 */
904 andi. r0, r11, MSR_EE
905 beq 2f
906 mtspr SPRN_SRR0, r10
907 mtspr SPRN_SRR1, r11
908 li r10, BOOK3S_INTERRUPT_EXTERNAL
909 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
910 rotldi r11, r11, 63
911 2: mr r4, r9
912 mtspr SPRN_LPCR, r8
913 b fast_guest_return
915 ext_interrupt_to_host:
917 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
918 /* Save more register state */
919 mfdar r6
920 mfdsisr r7
921 std r6, VCPU_DAR(r9)
922 stw r7, VCPU_DSISR(r9)
923 BEGIN_FTR_SECTION
924 /* don't overwrite fault_dar/fault_dsisr if HDSI */
925 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
926 beq 6f
927 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
928 std r6, VCPU_FAULT_DAR(r9)
929 stw r7, VCPU_FAULT_DSISR(r9)
931 /* See if it is a machine check */
932 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
933 beq machine_check_realmode
934 mc_cont:
936 /* Save guest CTRL register, set runlatch to 1 */
937 6: mfspr r6,SPRN_CTRLF
938 stw r6,VCPU_CTRL(r9)
939 andi. r0,r6,1
940 bne 4f
941 ori r6,r6,1
942 mtspr SPRN_CTRLT,r6
943 4:
944 /* Read the guest SLB and save it away */
945 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
946 mtctr r0
947 li r6,0
948 addi r7,r9,VCPU_SLB
949 li r5,0
950 1: slbmfee r8,r6
951 andis. r0,r8,SLB_ESID_V@h
952 beq 2f
953 add r8,r8,r6 /* put index in */
954 slbmfev r3,r6
955 std r8,VCPU_SLB_E(r7)
956 std r3,VCPU_SLB_V(r7)
957 addi r7,r7,VCPU_SLB_SIZE
958 addi r5,r5,1
959 2: addi r6,r6,1
960 bdnz 1b
961 stw r5,VCPU_SLB_MAX(r9)
963 /*
964 * Save the guest PURR/SPURR
965 */
966 BEGIN_FTR_SECTION
967 mfspr r5,SPRN_PURR
968 mfspr r6,SPRN_SPURR
969 ld r7,VCPU_PURR(r9)
970 ld r8,VCPU_SPURR(r9)
971 std r5,VCPU_PURR(r9)
972 std r6,VCPU_SPURR(r9)
973 subf r5,r7,r5
974 subf r6,r8,r6
976 /*
977 * Restore host PURR/SPURR and add guest times
978 * so that the time in the guest gets accounted.
979 */
980 ld r3,HSTATE_PURR(r13)
981 ld r4,HSTATE_SPURR(r13)
982 add r3,r3,r5
983 add r4,r4,r6
984 mtspr SPRN_PURR,r3
985 mtspr SPRN_SPURR,r4
986 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
988 /* Clear out SLB */
989 li r5,0
990 slbmte r5,r5
991 slbia
992 ptesync
994 hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */
995 BEGIN_FTR_SECTION
996 b 32f
997 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
998 /*
999 * POWER7 guest -> host partition switch code.
1000 * We don't have to lock against tlbies but we do
1001 * have to coordinate the hardware threads.
1002 */
1003 /* Increment the threads-exiting-guest count in the 0xff00
1004 bits of vcore->entry_exit_count */
1005 lwsync
1006 ld r5,HSTATE_KVM_VCORE(r13)
1007 addi r6,r5,VCORE_ENTRY_EXIT
1008 41: lwarx r3,0,r6
1009 addi r0,r3,0x100
1010 stwcx. r0,0,r6
1011 bne 41b
1012 lwsync
1014 /*
1015 * At this point we have an interrupt that we have to pass
1016 * up to the kernel or qemu; we can't handle it in real mode.
1017 * Thus we have to do a partition switch, so we have to
1018 * collect the other threads, if we are the first thread
1019 * to take an interrupt. To do this, we set the HDEC to 0,
1020 * which causes an HDEC interrupt in all threads within 2ns
1021 * because the HDEC register is shared between all 4 threads.
1022 * However, we don't need to bother if this is an HDEC
1023 * interrupt, since the other threads will already be on their
1024 * way here in that case.
1025 */
1026 cmpwi r3,0x100 /* Are we the first here? */
1027 bge 43f
1028 cmpwi r3,1 /* Are any other threads in the guest? */
1029 ble 43f
1030 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1031 beq 40f
1032 li r0,0
1033 mtspr SPRN_HDEC,r0
1034 40:
1035 /*
1036 * Send an IPI to any napping threads, since an HDEC interrupt
1037 * doesn't wake CPUs up from nap.
1038 */
1039 lwz r3,VCORE_NAPPING_THREADS(r5)
1040 lwz r4,VCPU_PTID(r9)
1041 li r0,1
1042 sld r0,r0,r4
1043 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1044 beq 43f
1045 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1046 subf r6,r4,r13
1047 42: andi. r0,r3,1
1048 beq 44f
1049 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1050 li r0,IPI_PRIORITY
1051 li r7,XICS_MFRR
1052 stbcix r0,r7,r8 /* trigger the IPI */
1053 44: srdi. r3,r3,1
1054 addi r6,r6,PACA_SIZE
1055 bne 42b
1057 /* Secondary threads wait for primary to do partition switch */
1058 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1059 ld r5,HSTATE_KVM_VCORE(r13)
1060 lwz r3,VCPU_PTID(r9)
1061 cmpwi r3,0
1062 beq 15f
1063 HMT_LOW
1064 13: lbz r3,VCORE_IN_GUEST(r5)
1065 cmpwi r3,0
1066 bne 13b
1067 HMT_MEDIUM
1068 b 16f
1070 /* Primary thread waits for all the secondaries to exit guest */
1071 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1072 srwi r0,r3,8
1073 clrldi r3,r3,56
1074 cmpw r3,r0
1075 bne 15b
1076 isync
1078 /* Primary thread switches back to host partition */
1079 ld r6,KVM_HOST_SDR1(r4)
1080 lwz r7,KVM_HOST_LPID(r4)
1081 li r8,LPID_RSVD /* switch to reserved LPID */
1082 mtspr SPRN_LPID,r8
1083 ptesync
1084 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1085 mtspr SPRN_LPID,r7
1086 isync
1088 /* Subtract timebase offset from timebase */
1089 ld r8,VCORE_TB_OFFSET(r5)
1090 cmpdi r8,0
1091 beq 17f
1092 mftb r6 /* current host timebase */
1093 subf r8,r8,r6
1094 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1095 mftb r7 /* check if lower 24 bits overflowed */
1096 clrldi r6,r6,40
1097 clrldi r7,r7,40
1098 cmpld r7,r6
1099 bge 17f
1100 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1101 mtspr SPRN_TBU40,r8
1103 /* Reset PCR */
1104 17: ld r0, VCORE_PCR(r5)
1105 cmpdi r0, 0
1106 beq 18f
1107 li r0, 0
1108 mtspr SPRN_PCR, r0
1109 18:
1110 /* Signal secondary CPUs to continue */
1111 stb r0,VCORE_IN_GUEST(r5)
1112 lis r8,0x7fff /* MAX_INT@h */
1113 mtspr SPRN_HDEC,r8
1115 16: ld r8,KVM_HOST_LPCR(r4)
1116 mtspr SPRN_LPCR,r8
1117 isync
1118 b 33f
1120 /*
1121 * PPC970 guest -> host partition switch code.
1122 * We have to lock against concurrent tlbies, and
1123 * we have to flush the whole TLB.
1124 */
1125 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1127 /* Take the guest's tlbie_lock */
1128 #ifdef __BIG_ENDIAN__
1129 lwz r8,PACA_LOCK_TOKEN(r13)
1130 #else
1131 lwz r8,PACAPACAINDEX(r13)
1132 #endif
1133 addi r3,r4,KVM_TLBIE_LOCK
1134 24: lwarx r0,0,r3
1135 cmpwi r0,0
1136 bne 24b
1137 stwcx. r8,0,r3
1138 bne 24b
1139 isync
1141 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1142 li r0,0x18f
1143 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1144 or r0,r7,r0
1145 ptesync
1146 sync
1147 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1148 isync
1149 li r0,0
1150 stw r0,0(r3) /* drop guest tlbie_lock */
1152 /* invalidate the whole TLB */
1153 li r0,256
1154 mtctr r0
1155 li r6,0
1156 25: tlbiel r6
1157 addi r6,r6,0x1000
1158 bdnz 25b
1159 ptesync
1161 /* take native_tlbie_lock */
1162 ld r3,toc_tlbie_lock@toc(2)
1163 24: lwarx r0,0,r3
1164 cmpwi r0,0
1165 bne 24b
1166 stwcx. r8,0,r3
1167 bne 24b
1168 isync
1170 ld r6,KVM_HOST_SDR1(r4)
1171 mtspr SPRN_SDR1,r6 /* switch to host page table */
1173 /* Set up host HID4 value */
1174 sync
1175 mtspr SPRN_HID4,r7
1176 isync
1177 li r0,0
1178 stw r0,0(r3) /* drop native_tlbie_lock */
1180 lis r8,0x7fff /* MAX_INT@h */
1181 mtspr SPRN_HDEC,r8
1183 /* Disable HDEC interrupts */
1184 mfspr r0,SPRN_HID0
1185 li r3,0
1186 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1187 sync
1188 mtspr SPRN_HID0,r0
1189 mfspr r0,SPRN_HID0
1190 mfspr r0,SPRN_HID0
1191 mfspr r0,SPRN_HID0
1192 mfspr r0,SPRN_HID0
1193 mfspr r0,SPRN_HID0
1194 mfspr r0,SPRN_HID0
1196 /* load host SLB entries */
1197 33: ld r8,PACA_SLBSHADOWPTR(r13)
1199 .rept SLB_NUM_BOLTED
1200 ld r5,SLBSHADOW_SAVEAREA(r8)
1201 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1202 andis. r7,r5,SLB_ESID_V@h
1203 beq 1f
1204 slbmte r6,r5
1205 1: addi r8,r8,16
1206 .endr
1208 /* Save DEC */
1209 mfspr r5,SPRN_DEC
1210 mftb r6
1211 extsw r5,r5
1212 add r5,r5,r6
1213 std r5,VCPU_DEC_EXPIRES(r9)
1215 /* Save and reset AMR and UAMOR before turning on the MMU */
1216 BEGIN_FTR_SECTION
1217 mfspr r5,SPRN_AMR
1218 mfspr r6,SPRN_UAMOR
1219 std r5,VCPU_AMR(r9)
1220 std r6,VCPU_UAMOR(r9)
1221 li r6,0
1222 mtspr SPRN_AMR,r6
1223 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1225 /* Switch DSCR back to host value */
1226 BEGIN_FTR_SECTION
1227 mfspr r8, SPRN_DSCR
1228 ld r7, HSTATE_DSCR(r13)
1229 std r8, VCPU_DSCR(r7)
1230 mtspr SPRN_DSCR, r7
1231 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1233 /* Save non-volatile GPRs */
1234 std r14, VCPU_GPR(R14)(r9)
1235 std r15, VCPU_GPR(R15)(r9)
1236 std r16, VCPU_GPR(R16)(r9)
1237 std r17, VCPU_GPR(R17)(r9)
1238 std r18, VCPU_GPR(R18)(r9)
1239 std r19, VCPU_GPR(R19)(r9)
1240 std r20, VCPU_GPR(R20)(r9)
1241 std r21, VCPU_GPR(R21)(r9)
1242 std r22, VCPU_GPR(R22)(r9)
1243 std r23, VCPU_GPR(R23)(r9)
1244 std r24, VCPU_GPR(R24)(r9)
1245 std r25, VCPU_GPR(R25)(r9)
1246 std r26, VCPU_GPR(R26)(r9)
1247 std r27, VCPU_GPR(R27)(r9)
1248 std r28, VCPU_GPR(R28)(r9)
1249 std r29, VCPU_GPR(R29)(r9)
1250 std r30, VCPU_GPR(R30)(r9)
1251 std r31, VCPU_GPR(R31)(r9)
1253 /* Save SPRGs */
1254 mfspr r3, SPRN_SPRG0
1255 mfspr r4, SPRN_SPRG1
1256 mfspr r5, SPRN_SPRG2
1257 mfspr r6, SPRN_SPRG3
1258 std r3, VCPU_SPRG0(r9)
1259 std r4, VCPU_SPRG1(r9)
1260 std r5, VCPU_SPRG2(r9)
1261 std r6, VCPU_SPRG3(r9)
1263 /* save FP state */
1264 mr r3, r9
1265 bl .kvmppc_save_fp
1267 /* Increment yield count if they have a VPA */
1268 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1269 cmpdi r8, 0
1270 beq 25f
1271 lwz r3, LPPACA_YIELDCOUNT(r8)
1272 addi r3, r3, 1
1273 stw r3, LPPACA_YIELDCOUNT(r8)
1274 li r3, 1
1275 stb r3, VCPU_VPA_DIRTY(r9)
1276 25:
1277 /* Save PMU registers if requested */
1278 /* r8 and cr0.eq are live here */
1279 li r3, 1
1280 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1281 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1282 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1283 mfspr r6, SPRN_MMCRA
1284 BEGIN_FTR_SECTION
1285 /* On P7, clear MMCRA in order to disable SDAR updates */
1286 li r7, 0
1287 mtspr SPRN_MMCRA, r7
1288 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1289 isync
1290 beq 21f /* if no VPA, save PMU stuff anyway */
1291 lbz r7, LPPACA_PMCINUSE(r8)
1292 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1293 bne 21f
1294 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1295 b 22f
1296 21: mfspr r5, SPRN_MMCR1
1297 mfspr r7, SPRN_SIAR
1298 mfspr r8, SPRN_SDAR
1299 std r4, VCPU_MMCR(r9)
1300 std r5, VCPU_MMCR + 8(r9)
1301 std r6, VCPU_MMCR + 16(r9)
1302 std r7, VCPU_SIAR(r9)
1303 std r8, VCPU_SDAR(r9)
1304 mfspr r3, SPRN_PMC1
1305 mfspr r4, SPRN_PMC2
1306 mfspr r5, SPRN_PMC3
1307 mfspr r6, SPRN_PMC4
1308 mfspr r7, SPRN_PMC5
1309 mfspr r8, SPRN_PMC6
1310 BEGIN_FTR_SECTION
1311 mfspr r10, SPRN_PMC7
1312 mfspr r11, SPRN_PMC8
1313 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1314 stw r3, VCPU_PMC(r9)
1315 stw r4, VCPU_PMC + 4(r9)
1316 stw r5, VCPU_PMC + 8(r9)
1317 stw r6, VCPU_PMC + 12(r9)
1318 stw r7, VCPU_PMC + 16(r9)
1319 stw r8, VCPU_PMC + 20(r9)
1320 BEGIN_FTR_SECTION
1321 stw r10, VCPU_PMC + 24(r9)
1322 stw r11, VCPU_PMC + 28(r9)
1323 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1324 22:
1325 ld r0, 112+PPC_LR_STKOFF(r1)
1326 addi r1, r1, 112
1327 mtlr r0
1328 blr
1329 secondary_too_late:
1330 ld r5,HSTATE_KVM_VCORE(r13)
1331 HMT_LOW
1332 13: lbz r3,VCORE_IN_GUEST(r5)
1333 cmpwi r3,0
1334 bne 13b
1335 HMT_MEDIUM
1336 li r0, KVM_GUEST_MODE_NONE
1337 stb r0, HSTATE_IN_GUEST(r13)
1338 ld r11,PACA_SLBSHADOWPTR(r13)
1340 .rept SLB_NUM_BOLTED
1341 ld r5,SLBSHADOW_SAVEAREA(r11)
1342 ld r6,SLBSHADOW_SAVEAREA+8(r11)
1343 andis. r7,r5,SLB_ESID_V@h
1344 beq 1f
1345 slbmte r6,r5
1346 1: addi r11,r11,16
1347 .endr
1348 b 22b
1350 /*
1351 * Check whether an HDSI is an HPTE not found fault or something else.
1352 * If it is an HPTE not found fault that is due to the guest accessing
1353 * a page that they have mapped but which we have paged out, then
1354 * we continue on with the guest exit path. In all other cases,
1355 * reflect the HDSI to the guest as a DSI.
1356 */
1357 kvmppc_hdsi:
1358 mfspr r4, SPRN_HDAR
1359 mfspr r6, SPRN_HDSISR
1360 /* HPTE not found fault or protection fault? */
1361 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1362 beq 1f /* if not, send it to the guest */
1363 andi. r0, r11, MSR_DR /* data relocation enabled? */
1364 beq 3f
1365 clrrdi r0, r4, 28
1366 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1367 bne 1f /* if no SLB entry found */
1368 4: std r4, VCPU_FAULT_DAR(r9)
1369 stw r6, VCPU_FAULT_DSISR(r9)
1371 /* Search the hash table. */
1372 mr r3, r9 /* vcpu pointer */
1373 li r7, 1 /* data fault */
1374 bl .kvmppc_hpte_hv_fault
1375 ld r9, HSTATE_KVM_VCPU(r13)
1376 ld r10, VCPU_PC(r9)
1377 ld r11, VCPU_MSR(r9)
1378 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1379 cmpdi r3, 0 /* retry the instruction */
1380 beq 6f
1381 cmpdi r3, -1 /* handle in kernel mode */
1382 beq guest_exit_cont
1383 cmpdi r3, -2 /* MMIO emulation; need instr word */
1384 beq 2f
1386 /* Synthesize a DSI for the guest */
1387 ld r4, VCPU_FAULT_DAR(r9)
1388 mr r6, r3
1389 1: mtspr SPRN_DAR, r4
1390 mtspr SPRN_DSISR, r6
1391 mtspr SPRN_SRR0, r10
1392 mtspr SPRN_SRR1, r11
1393 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1394 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1395 rotldi r11, r11, 63
1396 fast_interrupt_c_return:
1397 6: ld r7, VCPU_CTR(r9)
1398 lwz r8, VCPU_XER(r9)
1399 mtctr r7
1400 mtxer r8
1401 mr r4, r9
1402 b fast_guest_return
1404 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1405 ld r5, KVM_VRMA_SLB_V(r5)
1406 b 4b
1408 /* If this is for emulated MMIO, load the instruction word */
1409 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1411 /* Set guest mode to 'jump over instruction' so if lwz faults
1412 * we'll just continue at the next IP. */
1413 li r0, KVM_GUEST_MODE_SKIP
1414 stb r0, HSTATE_IN_GUEST(r13)
1416 /* Do the access with MSR:DR enabled */
1417 mfmsr r3
1418 ori r4, r3, MSR_DR /* Enable paging for data */
1419 mtmsrd r4
1420 lwz r8, 0(r10)
1421 mtmsrd r3
1423 /* Store the result */
1424 stw r8, VCPU_LAST_INST(r9)
1426 /* Unset guest mode. */
1427 li r0, KVM_GUEST_MODE_NONE
1428 stb r0, HSTATE_IN_GUEST(r13)
1429 b guest_exit_cont
1431 /*
1432 * Similarly for an HISI, reflect it to the guest as an ISI unless
1433 * it is an HPTE not found fault for a page that we have paged out.
1434 */
1435 kvmppc_hisi:
1436 andis. r0, r11, SRR1_ISI_NOPT@h
1437 beq 1f
1438 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1439 beq 3f
1440 clrrdi r0, r10, 28
1441 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1442 bne 1f /* if no SLB entry found */
1443 4:
1444 /* Search the hash table. */
1445 mr r3, r9 /* vcpu pointer */
1446 mr r4, r10
1447 mr r6, r11
1448 li r7, 0 /* instruction fault */
1449 bl .kvmppc_hpte_hv_fault
1450 ld r9, HSTATE_KVM_VCPU(r13)
1451 ld r10, VCPU_PC(r9)
1452 ld r11, VCPU_MSR(r9)
1453 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1454 cmpdi r3, 0 /* retry the instruction */
1455 beq fast_interrupt_c_return
1456 cmpdi r3, -1 /* handle in kernel mode */
1457 beq guest_exit_cont
1459 /* Synthesize an ISI for the guest */
1460 mr r11, r3
1461 1: mtspr SPRN_SRR0, r10
1462 mtspr SPRN_SRR1, r11
1463 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1464 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1465 rotldi r11, r11, 63
1466 b fast_interrupt_c_return
1468 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1469 ld r5, KVM_VRMA_SLB_V(r6)
1470 b 4b
1472 /*
1473 * Try to handle an hcall in real mode.
1474 * Returns to the guest if we handle it, or continues on up to
1475 * the kernel if we can't (i.e. if we don't have a handler for
1476 * it, or if the handler returns H_TOO_HARD).
1477 */
1478 .globl hcall_try_real_mode
1479 hcall_try_real_mode:
1480 ld r3,VCPU_GPR(R3)(r9)
1481 andi. r0,r11,MSR_PR
1482 bne guest_exit_cont
1483 clrrdi r3,r3,2
1484 cmpldi r3,hcall_real_table_end - hcall_real_table
1485 bge guest_exit_cont
1486 LOAD_REG_ADDR(r4, hcall_real_table)
1487 lwax r3,r3,r4
1488 cmpwi r3,0
1489 beq guest_exit_cont
1490 add r3,r3,r4
1491 mtctr r3
1492 mr r3,r9 /* get vcpu pointer */
1493 ld r4,VCPU_GPR(R4)(r9)
1494 bctrl
1495 cmpdi r3,H_TOO_HARD
1496 beq hcall_real_fallback
1497 ld r4,HSTATE_KVM_VCPU(r13)
1498 std r3,VCPU_GPR(R3)(r4)
1499 ld r10,VCPU_PC(r4)
1500 ld r11,VCPU_MSR(r4)
1501 b fast_guest_return
1503 /* We've attempted a real mode hcall, but it's punted it back
1504 * to userspace. We need to restore some clobbered volatiles
1505 * before resuming the pass-it-to-qemu path */
1506 hcall_real_fallback:
1507 li r12,BOOK3S_INTERRUPT_SYSCALL
1508 ld r9, HSTATE_KVM_VCPU(r13)
1510 b guest_exit_cont
1512 .globl hcall_real_table
1513 hcall_real_table:
1514 .long 0 /* 0 - unused */
1515 .long .kvmppc_h_remove - hcall_real_table
1516 .long .kvmppc_h_enter - hcall_real_table
1517 .long .kvmppc_h_read - hcall_real_table
1518 .long 0 /* 0x10 - H_CLEAR_MOD */
1519 .long 0 /* 0x14 - H_CLEAR_REF */
1520 .long .kvmppc_h_protect - hcall_real_table
1521 .long 0 /* 0x1c - H_GET_TCE */
1522 .long .kvmppc_h_put_tce - hcall_real_table
1523 .long 0 /* 0x24 - H_SET_SPRG0 */
1524 .long .kvmppc_h_set_dabr - hcall_real_table
1525 .long 0 /* 0x2c */
1526 .long 0 /* 0x30 */
1527 .long 0 /* 0x34 */
1528 .long 0 /* 0x38 */
1529 .long 0 /* 0x3c */
1530 .long 0 /* 0x40 */
1531 .long 0 /* 0x44 */
1532 .long 0 /* 0x48 */
1533 .long 0 /* 0x4c */
1534 .long 0 /* 0x50 */
1535 .long 0 /* 0x54 */
1536 .long 0 /* 0x58 */
1537 .long 0 /* 0x5c */
1538 .long 0 /* 0x60 */
1539 #ifdef CONFIG_KVM_XICS
1540 .long .kvmppc_rm_h_eoi - hcall_real_table
1541 .long .kvmppc_rm_h_cppr - hcall_real_table
1542 .long .kvmppc_rm_h_ipi - hcall_real_table
1543 .long 0 /* 0x70 - H_IPOLL */
1544 .long .kvmppc_rm_h_xirr - hcall_real_table
1545 #else
1546 .long 0 /* 0x64 - H_EOI */
1547 .long 0 /* 0x68 - H_CPPR */
1548 .long 0 /* 0x6c - H_IPI */
1549 .long 0 /* 0x70 - H_IPOLL */
1550 .long 0 /* 0x74 - H_XIRR */
1551 #endif
1552 .long 0 /* 0x78 */
1553 .long 0 /* 0x7c */
1554 .long 0 /* 0x80 */
1555 .long 0 /* 0x84 */
1556 .long 0 /* 0x88 */
1557 .long 0 /* 0x8c */
1558 .long 0 /* 0x90 */
1559 .long 0 /* 0x94 */
1560 .long 0 /* 0x98 */
1561 .long 0 /* 0x9c */
1562 .long 0 /* 0xa0 */
1563 .long 0 /* 0xa4 */
1564 .long 0 /* 0xa8 */
1565 .long 0 /* 0xac */
1566 .long 0 /* 0xb0 */
1567 .long 0 /* 0xb4 */
1568 .long 0 /* 0xb8 */
1569 .long 0 /* 0xbc */
1570 .long 0 /* 0xc0 */
1571 .long 0 /* 0xc4 */
1572 .long 0 /* 0xc8 */
1573 .long 0 /* 0xcc */
1574 .long 0 /* 0xd0 */
1575 .long 0 /* 0xd4 */
1576 .long 0 /* 0xd8 */
1577 .long 0 /* 0xdc */
1578 .long .kvmppc_h_cede - hcall_real_table
1579 .long 0 /* 0xe4 */
1580 .long 0 /* 0xe8 */
1581 .long 0 /* 0xec */
1582 .long 0 /* 0xf0 */
1583 .long 0 /* 0xf4 */
1584 .long 0 /* 0xf8 */
1585 .long 0 /* 0xfc */
1586 .long 0 /* 0x100 */
1587 .long 0 /* 0x104 */
1588 .long 0 /* 0x108 */
1589 .long 0 /* 0x10c */
1590 .long 0 /* 0x110 */
1591 .long 0 /* 0x114 */
1592 .long 0 /* 0x118 */
1593 .long 0 /* 0x11c */
1594 .long 0 /* 0x120 */
1595 .long .kvmppc_h_bulk_remove - hcall_real_table
1596 hcall_real_table_end:
1598 ignore_hdec:
1599 mr r4,r9
1600 b fast_guest_return
1602 _GLOBAL(kvmppc_h_set_dabr)
1603 std r4,VCPU_DABR(r3)
1604 /* Work around P7 bug where DABR can get corrupted on mtspr */
1605 1: mtspr SPRN_DABR,r4
1606 mfspr r5, SPRN_DABR
1607 cmpd r4, r5
1608 bne 1b
1609 isync
1610 li r3,0
1611 blr
1613 _GLOBAL(kvmppc_h_cede)
1614 ori r11,r11,MSR_EE
1615 std r11,VCPU_MSR(r3)
1616 li r0,1
1617 stb r0,VCPU_CEDED(r3)
1618 sync /* order setting ceded vs. testing prodded */
1619 lbz r5,VCPU_PRODDED(r3)
1620 cmpwi r5,0
1621 bne kvm_cede_prodded
1622 li r0,0 /* set trap to 0 to say hcall is handled */
1623 stw r0,VCPU_TRAP(r3)
1624 li r0,H_SUCCESS
1625 std r0,VCPU_GPR(R3)(r3)
1626 BEGIN_FTR_SECTION
1627 b kvm_cede_exit /* just send it up to host on 970 */
1628 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1630 /*
1631 * Set our bit in the bitmask of napping threads unless all the
1632 * other threads are already napping, in which case we send this
1633 * up to the host.
1634 */
1635 ld r5,HSTATE_KVM_VCORE(r13)
1636 lwz r6,VCPU_PTID(r3)
1637 lwz r8,VCORE_ENTRY_EXIT(r5)
1638 clrldi r8,r8,56
1639 li r0,1
1640 sld r0,r0,r6
1641 addi r6,r5,VCORE_NAPPING_THREADS
1642 31: lwarx r4,0,r6
1643 or r4,r4,r0
1644 PPC_POPCNTW(R7,R4)
1645 cmpw r7,r8
1646 bge kvm_cede_exit
1647 stwcx. r4,0,r6
1648 bne 31b
1649 li r0,1
1650 stb r0,HSTATE_NAPPING(r13)
1651 /* order napping_threads update vs testing entry_exit_count */
1652 lwsync
1653 mr r4,r3
1654 lwz r7,VCORE_ENTRY_EXIT(r5)
1655 cmpwi r7,0x100
1656 bge 33f /* another thread already exiting */
1658 /*
1659 * Although not specifically required by the architecture, POWER7
1660 * preserves the following registers in nap mode, even if an SMT mode
1661 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1662 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1663 */
1664 /* Save non-volatile GPRs */
1665 std r14, VCPU_GPR(R14)(r3)
1666 std r15, VCPU_GPR(R15)(r3)
1667 std r16, VCPU_GPR(R16)(r3)
1668 std r17, VCPU_GPR(R17)(r3)
1669 std r18, VCPU_GPR(R18)(r3)
1670 std r19, VCPU_GPR(R19)(r3)
1671 std r20, VCPU_GPR(R20)(r3)
1672 std r21, VCPU_GPR(R21)(r3)
1673 std r22, VCPU_GPR(R22)(r3)
1674 std r23, VCPU_GPR(R23)(r3)
1675 std r24, VCPU_GPR(R24)(r3)
1676 std r25, VCPU_GPR(R25)(r3)
1677 std r26, VCPU_GPR(R26)(r3)
1678 std r27, VCPU_GPR(R27)(r3)
1679 std r28, VCPU_GPR(R28)(r3)
1680 std r29, VCPU_GPR(R29)(r3)
1681 std r30, VCPU_GPR(R30)(r3)
1682 std r31, VCPU_GPR(R31)(r3)
1684 /* save FP state */
1685 bl .kvmppc_save_fp
1687 /*
1688 * Take a nap until a decrementer or external interrupt occurs,
1689 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1690 */
1691 li r0,1
1692 stb r0,HSTATE_HWTHREAD_REQ(r13)
1693 mfspr r5,SPRN_LPCR
1694 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1695 mtspr SPRN_LPCR,r5
1696 isync
1697 li r0, 0
1698 std r0, HSTATE_SCRATCH0(r13)
1699 ptesync
1700 ld r0, HSTATE_SCRATCH0(r13)
1701 1: cmpd r0, r0
1702 bne 1b
1703 nap
1704 b .
1706 kvm_end_cede:
1707 /* get vcpu pointer */
1708 ld r4, HSTATE_KVM_VCPU(r13)
1710 /* Woken by external or decrementer interrupt */
1711 ld r1, HSTATE_HOST_R1(r13)
1713 /* load up FP state */
1714 bl kvmppc_load_fp
1716 /* Load NV GPRS */
1717 ld r14, VCPU_GPR(R14)(r4)
1718 ld r15, VCPU_GPR(R15)(r4)
1719 ld r16, VCPU_GPR(R16)(r4)
1720 ld r17, VCPU_GPR(R17)(r4)
1721 ld r18, VCPU_GPR(R18)(r4)
1722 ld r19, VCPU_GPR(R19)(r4)
1723 ld r20, VCPU_GPR(R20)(r4)
1724 ld r21, VCPU_GPR(R21)(r4)
1725 ld r22, VCPU_GPR(R22)(r4)
1726 ld r23, VCPU_GPR(R23)(r4)
1727 ld r24, VCPU_GPR(R24)(r4)
1728 ld r25, VCPU_GPR(R25)(r4)
1729 ld r26, VCPU_GPR(R26)(r4)
1730 ld r27, VCPU_GPR(R27)(r4)
1731 ld r28, VCPU_GPR(R28)(r4)
1732 ld r29, VCPU_GPR(R29)(r4)
1733 ld r30, VCPU_GPR(R30)(r4)
1734 ld r31, VCPU_GPR(R31)(r4)
1736 /* clear our bit in vcore->napping_threads */
1737 33: ld r5,HSTATE_KVM_VCORE(r13)
1738 lwz r3,VCPU_PTID(r4)
1739 li r0,1
1740 sld r0,r0,r3
1741 addi r6,r5,VCORE_NAPPING_THREADS
1742 32: lwarx r7,0,r6
1743 andc r7,r7,r0
1744 stwcx. r7,0,r6
1745 bne 32b
1746 li r0,0
1747 stb r0,HSTATE_NAPPING(r13)
1749 /* Check the wake reason in SRR1 to see why we got here */
1750 mfspr r3, SPRN_SRR1
1751 rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */
1752 cmpwi r3, 4 /* was it an external interrupt? */
1753 li r12, BOOK3S_INTERRUPT_EXTERNAL
1754 mr r9, r4
1755 ld r10, VCPU_PC(r9)
1756 ld r11, VCPU_MSR(r9)
1757 beq do_ext_interrupt /* if so */
1759 /* see if any other thread is already exiting */
1760 lwz r0,VCORE_ENTRY_EXIT(r5)
1761 cmpwi r0,0x100
1762 blt kvmppc_cede_reentry /* if not go back to guest */
1764 /* some threads are exiting, so go to the guest exit path */
1765 b hcall_real_fallback
1767 /* cede when already previously prodded case */
1768 kvm_cede_prodded:
1769 li r0,0
1770 stb r0,VCPU_PRODDED(r3)
1771 sync /* order testing prodded vs. clearing ceded */
1772 stb r0,VCPU_CEDED(r3)
1773 li r3,H_SUCCESS
1774 blr
1776 /* we've ceded but we want to give control to the host */
1777 kvm_cede_exit:
1778 b hcall_real_fallback
1780 /* Try to handle a machine check in real mode */
1781 machine_check_realmode:
1782 mr r3, r9 /* get vcpu pointer */
1783 bl .kvmppc_realmode_machine_check
1784 nop
1785 cmpdi r3, 0 /* continue exiting from guest? */
1786 ld r9, HSTATE_KVM_VCPU(r13)
1787 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1788 beq mc_cont
1789 /* If not, deliver a machine check. SRR0/1 are already set */
1790 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
1791 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1792 rotldi r11, r11, 63
1793 b fast_interrupt_c_return
1795 /*
1796 * Determine what sort of external interrupt is pending (if any).
1797 * Returns:
1798 * 0 if no interrupt is pending
1799 * 1 if an interrupt is pending that needs to be handled by the host
1800 * -1 if there was a guest wakeup IPI (which has now been cleared)
1801 */
1802 kvmppc_read_intr:
1803 /* see if a host IPI is pending */
1804 li r3, 1
1805 lbz r0, HSTATE_HOST_IPI(r13)
1806 cmpwi r0, 0
1807 bne 1f
1809 /* Now read the interrupt from the ICP */
1810 ld r6, HSTATE_XICS_PHYS(r13)
1811 li r7, XICS_XIRR
1812 cmpdi r6, 0
1813 beq- 1f
1814 lwzcix r0, r6, r7
1815 rlwinm. r3, r0, 0, 0xffffff
1816 sync
1817 beq 1f /* if nothing pending in the ICP */
1819 /* We found something in the ICP...
1820 *
1821 * If it's not an IPI, stash it in the PACA and return to
1822 * the host, we don't (yet) handle directing real external
1823 * interrupts directly to the guest
1824 */
1825 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
1826 li r3, 1
1827 bne 42f
1829 /* It's an IPI, clear the MFRR and EOI it */
1830 li r3, 0xff
1831 li r8, XICS_MFRR
1832 stbcix r3, r6, r8 /* clear the IPI */
1833 stwcix r0, r6, r7 /* EOI it */
1834 sync
1836 /* We need to re-check host IPI now in case it got set in the
1837 * meantime. If it's clear, we bounce the interrupt to the
1838 * guest
1839 */
1840 lbz r0, HSTATE_HOST_IPI(r13)
1841 cmpwi r0, 0
1842 bne- 43f
1844 /* OK, it's an IPI for us */
1845 li r3, -1
1846 1: blr
1848 42: /* It's not an IPI and it's for the host, stash it in the PACA
1849 * before exit, it will be picked up by the host ICP driver
1850 */
1851 stw r0, HSTATE_SAVED_XIRR(r13)
1852 b 1b
1854 43: /* We raced with the host, we need to resend that IPI, bummer */
1855 li r0, IPI_PRIORITY
1856 stbcix r0, r6, r8 /* set the IPI */
1857 sync
1858 b 1b
1860 /*
1861 * Save away FP, VMX and VSX registers.
1862 * r3 = vcpu pointer
1863 */
1864 _GLOBAL(kvmppc_save_fp)
1865 mfmsr r5
1866 ori r8,r5,MSR_FP
1867 #ifdef CONFIG_ALTIVEC
1868 BEGIN_FTR_SECTION
1869 oris r8,r8,MSR_VEC@h
1870 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1871 #endif
1872 #ifdef CONFIG_VSX
1873 BEGIN_FTR_SECTION
1874 oris r8,r8,MSR_VSX@h
1875 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1876 #endif
1877 mtmsrd r8
1878 isync
1879 #ifdef CONFIG_VSX
1880 BEGIN_FTR_SECTION
1881 reg = 0
1882 .rept 32
1883 li r6,reg*16+VCPU_VSRS
1884 STXVD2X(reg,R6,R3)
1885 reg = reg + 1
1886 .endr
1887 FTR_SECTION_ELSE
1888 #endif
1889 reg = 0
1890 .rept 32
1891 stfd reg,reg*8+VCPU_FPRS(r3)
1892 reg = reg + 1
1893 .endr
1894 #ifdef CONFIG_VSX
1895 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1896 #endif
1897 mffs fr0
1898 stfd fr0,VCPU_FPSCR(r3)
1900 #ifdef CONFIG_ALTIVEC
1901 BEGIN_FTR_SECTION
1902 reg = 0
1903 .rept 32
1904 li r6,reg*16+VCPU_VRS
1905 stvx reg,r6,r3
1906 reg = reg + 1
1907 .endr
1908 mfvscr vr0
1909 li r6,VCPU_VSCR
1910 stvx vr0,r6,r3
1911 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1912 #endif
1913 mfspr r6,SPRN_VRSAVE
1914 stw r6,VCPU_VRSAVE(r3)
1915 mtmsrd r5
1916 isync
1917 blr
1919 /*
1920 * Load up FP, VMX and VSX registers
1921 * r4 = vcpu pointer
1922 */
1923 .globl kvmppc_load_fp
1924 kvmppc_load_fp:
1925 mfmsr r9
1926 ori r8,r9,MSR_FP
1927 #ifdef CONFIG_ALTIVEC
1928 BEGIN_FTR_SECTION
1929 oris r8,r8,MSR_VEC@h
1930 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1931 #endif
1932 #ifdef CONFIG_VSX
1933 BEGIN_FTR_SECTION
1934 oris r8,r8,MSR_VSX@h
1935 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1936 #endif
1937 mtmsrd r8
1938 isync
1939 lfd fr0,VCPU_FPSCR(r4)
1940 MTFSF_L(fr0)
1941 #ifdef CONFIG_VSX
1942 BEGIN_FTR_SECTION
1943 reg = 0
1944 .rept 32
1945 li r7,reg*16+VCPU_VSRS
1946 LXVD2X(reg,R7,R4)
1947 reg = reg + 1
1948 .endr
1949 FTR_SECTION_ELSE
1950 #endif
1951 reg = 0
1952 .rept 32
1953 lfd reg,reg*8+VCPU_FPRS(r4)
1954 reg = reg + 1
1955 .endr
1956 #ifdef CONFIG_VSX
1957 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1958 #endif
1960 #ifdef CONFIG_ALTIVEC
1961 BEGIN_FTR_SECTION
1962 li r7,VCPU_VSCR
1963 lvx vr0,r7,r4
1964 mtvscr vr0
1965 reg = 0
1966 .rept 32
1967 li r7,reg*16+VCPU_VRS
1968 lvx reg,r7,r4
1969 reg = reg + 1
1970 .endr
1971 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1972 #endif
1973 lwz r7,VCPU_VRSAVE(r4)
1974 mtspr SPRN_VRSAVE,r7
1975 blr