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ath9k: Refactor hw.c
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / ath9k / hw.c
blobe05c9ef55e471327fa1a213db3e74446ccfaf27e
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "core.h"
21 #include "hw.h"
22 #include "reg.h"
23 #include "phy.h"
24 #include "initvals.h"
25
26 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
27
28 extern struct hal_percal_data iq_cal_multi_sample;
29 extern struct hal_percal_data iq_cal_single_sample;
30 extern struct hal_percal_data adc_gain_cal_multi_sample;
31 extern struct hal_percal_data adc_gain_cal_single_sample;
32 extern struct hal_percal_data adc_dc_cal_multi_sample;
33 extern struct hal_percal_data adc_dc_cal_single_sample;
34 extern struct hal_percal_data adc_init_dc_cal;
35
36 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
37 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
38 enum ath9k_ht_macmode macmode);
39 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
40 struct ar5416_eeprom *pEepData,
41 u32 reg, u32 value);
42 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
43 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
44
45 /********************/
46 /* Helper Functions */
47 /********************/
48
49 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
50 {
51 if (ah->ah_curchan != NULL)
52 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
53 else
54 return clks / CLOCK_RATE[ATH9K_MODE_11B];
55 }
56
57 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
58 {
59 struct ath9k_channel *chan = ah->ah_curchan;
60
61 if (chan && IS_CHAN_HT40(chan))
62 return ath9k_hw_mac_usec(ah, clks) / 2;
63 else
64 return ath9k_hw_mac_usec(ah, clks);
65 }
66
67 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
68 {
69 if (ah->ah_curchan != NULL)
70 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
71 ah->ah_curchan)];
72 else
73 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
74 }
75
76 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
77 {
78 struct ath9k_channel *chan = ah->ah_curchan;
79
80 if (chan && IS_CHAN_HT40(chan))
81 return ath9k_hw_mac_clks(ah, usecs) * 2;
82 else
83 return ath9k_hw_mac_clks(ah, usecs);
84 }
85
86 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
87 const struct ath9k_channel *chan)
88 {
89 if (IS_CHAN_CCK(chan))
90 return ATH9K_MODE_11A;
91 if (IS_CHAN_G(chan))
92 return ATH9K_MODE_11G;
93 return ATH9K_MODE_11A;
94 }
95
96 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
97 {
98 int i;
99
100 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
101 if ((REG_READ(ah, reg) & mask) == val)
102 return true;
103
104 udelay(AH_TIME_QUANTUM);
105 }
106 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
107 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
108 __func__, reg, REG_READ(ah, reg), mask, val);
109
110 return false;
111 }
112
113 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
114 {
115 u32 retval;
116 int i;
117
118 for (i = 0, retval = 0; i < n; i++) {
119 retval = (retval << 1) | (val & 1);
120 val >>= 1;
121 }
122 return retval;
123 }
124
125 bool ath9k_get_channel_edges(struct ath_hal *ah,
126 u16 flags, u16 *low,
127 u16 *high)
128 {
129 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
130
131 if (flags & CHANNEL_5GHZ) {
132 *low = pCap->low_5ghz_chan;
133 *high = pCap->high_5ghz_chan;
134 return true;
135 }
136 if ((flags & CHANNEL_2GHZ)) {
137 *low = pCap->low_2ghz_chan;
138 *high = pCap->high_2ghz_chan;
139 return true;
140 }
141 return false;
142 }
143
144 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
145 const struct ath9k_rate_table *rates,
146 u32 frameLen, u16 rateix,
147 bool shortPreamble)
148 {
149 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
150 u32 kbps;
151
152 kbps = rates->info[rateix].rateKbps;
153
154 if (kbps == 0)
155 return 0;
156
157 switch (rates->info[rateix].phy) {
158 case PHY_CCK:
159 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
160 if (shortPreamble && rates->info[rateix].shortPreamble)
161 phyTime >>= 1;
162 numBits = frameLen << 3;
163 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
164 break;
165 case PHY_OFDM:
166 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
167 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
168 numBits = OFDM_PLCP_BITS + (frameLen << 3);
169 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
170 txTime = OFDM_SIFS_TIME_QUARTER
171 + OFDM_PREAMBLE_TIME_QUARTER
172 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
173 } else if (ah->ah_curchan &&
174 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
175 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
176 numBits = OFDM_PLCP_BITS + (frameLen << 3);
177 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
178 txTime = OFDM_SIFS_TIME_HALF +
179 OFDM_PREAMBLE_TIME_HALF
180 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
181 } else {
182 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
183 numBits = OFDM_PLCP_BITS + (frameLen << 3);
184 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
185 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
186 + (numSymbols * OFDM_SYMBOL_TIME);
187 }
188 break;
189 default:
190 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
191 "%s: unknown phy %u (rate ix %u)\n", __func__,
192 rates->info[rateix].phy, rateix);
193 txTime = 0;
194 break;
195 }
196
197 return txTime;
198 }
199
200 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
201 {
202 if (flags & CHANNEL_2GHZ) {
203 if (freq == 2484)
204 return 14;
205 if (freq < 2484)
206 return (freq - 2407) / 5;
207 else
208 return 15 + ((freq - 2512) / 20);
209 } else if (flags & CHANNEL_5GHZ) {
210 if (ath9k_regd_is_public_safety_sku(ah) &&
211 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
212 return ((freq * 10) +
213 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
214 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
215 return (freq - 4000) / 5;
216 } else {
217 return (freq - 5000) / 5;
218 }
219 } else {
220 if (freq == 2484)
221 return 14;
222 if (freq < 2484)
223 return (freq - 2407) / 5;
224 if (freq < 5000) {
225 if (ath9k_regd_is_public_safety_sku(ah)
226 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
227 return ((freq * 10) +
228 (((freq % 5) ==
229 2) ? 5 : 0) - 49400) / 5;
230 } else if (freq > 4900) {
231 return (freq - 4000) / 5;
232 } else {
233 return 15 + ((freq - 2512) / 20);
234 }
235 }
236 return (freq - 5000) / 5;
237 }
238 }
239
240 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
241 struct ath9k_channel *chan,
242 struct chan_centers *centers)
243 {
244 int8_t extoff;
245 struct ath_hal_5416 *ahp = AH5416(ah);
246
247 if (!IS_CHAN_HT40(chan)) {
248 centers->ctl_center = centers->ext_center =
249 centers->synth_center = chan->channel;
250 return;
251 }
252
253 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
254 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
255 centers->synth_center =
256 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
257 extoff = 1;
258 } else {
259 centers->synth_center =
260 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
261 extoff = -1;
262 }
263
264 centers->ctl_center =
265 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
266 centers->ext_center =
267 centers->synth_center + (extoff *
268 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
269 HT40_CHANNEL_CENTER_SHIFT : 15));
270
271 }
272
273 /******************/
274 /* Chip Revisions */
275 /******************/
276
277 static void ath9k_hw_read_revisions(struct ath_hal *ah)
278 {
279 u32 val;
280
281 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
282
283 if (val == 0xFF) {
284 val = REG_READ(ah, AR_SREV);
285 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
286 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
287 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
288 } else {
289 if (!AR_SREV_9100(ah))
290 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
291
292 ah->ah_macRev = val & AR_SREV_REVISION;
293
294 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
295 ah->ah_isPciExpress = true;
296 }
297 }
298
299 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
300 {
301 u32 val;
302 int i;
303
304 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
305
306 for (i = 0; i < 8; i++)
307 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
308 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
309 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
310
311 return ath9k_hw_reverse_bits(val, 8);
312 }
313
314 /************************************/
315 /* HW Attach, Detach, Init Routines */
316 /************************************/
317
318 static void ath9k_hw_disablepcie(struct ath_hal *ah)
319 {
320 if (!AR_SREV_9100(ah))
321 return;
322
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
325 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
327 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
328 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
329 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
330 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
332
333 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
334 }
335
336 static bool ath9k_hw_chip_test(struct ath_hal *ah)
337 {
338 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
339 u32 regHold[2];
340 u32 patternData[4] = { 0x55555555,
341 0xaaaaaaaa,
342 0x66666666,
343 0x99999999 };
344 int i, j;
345
346 for (i = 0; i < 2; i++) {
347 u32 addr = regAddr[i];
348 u32 wrData, rdData;
349
350 regHold[i] = REG_READ(ah, addr);
351 for (j = 0; j < 0x100; j++) {
352 wrData = (j << 16) | j;
353 REG_WRITE(ah, addr, wrData);
354 rdData = REG_READ(ah, addr);
355 if (rdData != wrData) {
356 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
357 "%s: address test failed "
358 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
359 __func__, addr, wrData, rdData);
360 return false;
361 }
362 }
363 for (j = 0; j < 4; j++) {
364 wrData = patternData[j];
365 REG_WRITE(ah, addr, wrData);
366 rdData = REG_READ(ah, addr);
367 if (wrData != rdData) {
368 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
369 "%s: address test failed "
370 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
371 __func__, addr, wrData, rdData);
372 return false;
373 }
374 }
375 REG_WRITE(ah, regAddr[i], regHold[i]);
376 }
377 udelay(100);
378 return true;
379 }
380
381 static const char *ath9k_hw_devname(u16 devid)
382 {
383 switch (devid) {
384 case AR5416_DEVID_PCI:
385 case AR5416_DEVID_PCIE:
386 return "Atheros 5416";
387 case AR9160_DEVID_PCI:
388 return "Atheros 9160";
389 case AR9280_DEVID_PCI:
390 case AR9280_DEVID_PCIE:
391 return "Atheros 9280";
392 }
393
394 return NULL;
395 }
396
397 static void ath9k_hw_set_defaults(struct ath_hal *ah)
398 {
399 int i;
400
401 ah->ah_config.dma_beacon_response_time = 2;
402 ah->ah_config.sw_beacon_response_time = 10;
403 ah->ah_config.additional_swba_backoff = 0;
404 ah->ah_config.ack_6mb = 0x0;
405 ah->ah_config.cwm_ignore_extcca = 0;
406 ah->ah_config.pcie_powersave_enable = 0;
407 ah->ah_config.pcie_l1skp_enable = 0;
408 ah->ah_config.pcie_clock_req = 0;
409 ah->ah_config.pcie_power_reset = 0x100;
410 ah->ah_config.pcie_restore = 0;
411 ah->ah_config.pcie_waen = 0;
412 ah->ah_config.analog_shiftreg = 1;
413 ah->ah_config.ht_enable = 1;
414 ah->ah_config.ofdm_trig_low = 200;
415 ah->ah_config.ofdm_trig_high = 500;
416 ah->ah_config.cck_trig_high = 200;
417 ah->ah_config.cck_trig_low = 100;
418 ah->ah_config.enable_ani = 1;
419 ah->ah_config.noise_immunity_level = 4;
420 ah->ah_config.ofdm_weaksignal_det = 1;
421 ah->ah_config.cck_weaksignal_thr = 0;
422 ah->ah_config.spur_immunity_level = 2;
423 ah->ah_config.firstep_level = 0;
424 ah->ah_config.rssi_thr_high = 40;
425 ah->ah_config.rssi_thr_low = 7;
426 ah->ah_config.diversity_control = 0;
427 ah->ah_config.antenna_switch_swap = 0;
428
429 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
430 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
431 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
432 }
433
434 ah->ah_config.intr_mitigation = 1;
435 }
436
437 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
438 struct ath_softc *sc,
439 void __iomem *mem,
440 int *status)
441 {
442 static const u8 defbssidmask[ETH_ALEN] =
443 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
444 struct ath_hal_5416 *ahp;
445 struct ath_hal *ah;
446
447 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
448 if (ahp == NULL) {
449 DPRINTF(sc, ATH_DBG_FATAL,
450 "%s: cannot allocate memory for state block\n",
451 __func__);
452 *status = -ENOMEM;
453 return NULL;
454 }
455
456 ah = &ahp->ah;
457 ah->ah_sc = sc;
458 ah->ah_sh = mem;
459 ah->ah_magic = AR5416_MAGIC;
460 ah->ah_countryCode = CTRY_DEFAULT;
461 ah->ah_devid = devid;
462 ah->ah_subvendorid = 0;
463
464 ah->ah_flags = 0;
465 if ((devid == AR5416_AR9100_DEVID))
466 ah->ah_macVersion = AR_SREV_VERSION_9100;
467 if (!AR_SREV_9100(ah))
468 ah->ah_flags = AH_USE_EEPROM;
469
470 ah->ah_powerLimit = MAX_RATE_POWER;
471 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
472 ahp->ah_atimWindow = 0;
473 ahp->ah_diversityControl = ah->ah_config.diversity_control;
474 ahp->ah_antennaSwitchSwap =
475 ah->ah_config.antenna_switch_swap;
476 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
477 ahp->ah_beaconInterval = 100;
478 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
479 ahp->ah_slottime = (u32) -1;
480 ahp->ah_acktimeout = (u32) -1;
481 ahp->ah_ctstimeout = (u32) -1;
482 ahp->ah_globaltxtimeout = (u32) -1;
483 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
484
485 ahp->ah_gBeaconRate = 0;
486
487 return ahp;
488 }
489
490 static int ath9k_hw_rfattach(struct ath_hal *ah)
491 {
492 bool rfStatus = false;
493 int ecode = 0;
494
495 rfStatus = ath9k_hw_init_rf(ah, &ecode);
496 if (!rfStatus) {
497 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
498 "%s: RF setup failed, status %u\n", __func__,
499 ecode);
500 return ecode;
501 }
502
503 return 0;
504 }
505
506 static int ath9k_hw_rf_claim(struct ath_hal *ah)
507 {
508 u32 val;
509
510 REG_WRITE(ah, AR_PHY(0), 0x00000007);
511
512 val = ath9k_hw_get_radiorev(ah);
513 switch (val & AR_RADIO_SREV_MAJOR) {
514 case 0:
515 val = AR_RAD5133_SREV_MAJOR;
516 break;
517 case AR_RAD5133_SREV_MAJOR:
518 case AR_RAD5122_SREV_MAJOR:
519 case AR_RAD2133_SREV_MAJOR:
520 case AR_RAD2122_SREV_MAJOR:
521 break;
522 default:
523 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
524 "%s: 5G Radio Chip Rev 0x%02X is not "
525 "supported by this driver\n",
526 __func__, ah->ah_analog5GhzRev);
527 return -EOPNOTSUPP;
528 }
529
530 ah->ah_analog5GhzRev = val;
531
532 return 0;
533 }
534
535 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
536 {
537 u32 sum;
538 int i;
539 u16 eeval;
540 struct ath_hal_5416 *ahp = AH5416(ah);
541
542 sum = 0;
543 for (i = 0; i < 3; i++) {
544 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
545 sum += eeval;
546 ahp->ah_macaddr[2 * i] = eeval >> 8;
547 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
548 }
549 if (sum == 0 || sum == 0xffff * 3) {
550 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
551 "%s: mac address read failed: %pM\n", __func__,
552 ahp->ah_macaddr);
553 return -EADDRNOTAVAIL;
554 }
555
556 return 0;
557 }
558
559 static int ath9k_hw_post_attach(struct ath_hal *ah)
560 {
561 int ecode;
562
563 if (!ath9k_hw_chip_test(ah)) {
564 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
565 "%s: hardware self-test failed\n", __func__);
566 return -ENODEV;
567 }
568
569 ecode = ath9k_hw_rf_claim(ah);
570 if (ecode != 0)
571 return ecode;
572
573 ecode = ath9k_hw_eeprom_attach(ah);
574 if (ecode != 0)
575 return ecode;
576 ecode = ath9k_hw_rfattach(ah);
577 if (ecode != 0)
578 return ecode;
579
580 if (!AR_SREV_9100(ah)) {
581 ath9k_hw_ani_setup(ah);
582 ath9k_hw_ani_attach(ah);
583 }
584
585 return 0;
586 }
587
588 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
589 void __iomem *mem, int *status)
590 {
591 struct ath_hal_5416 *ahp;
592 struct ath_hal *ah;
593 int ecode;
594 #ifndef CONFIG_SLOW_ANT_DIV
595 u32 i;
596 u32 j;
597 #endif
598
599 ahp = ath9k_hw_newstate(devid, sc, mem, status);
600 if (ahp == NULL)
601 return NULL;
602
603 ah = &ahp->ah;
604
605 ath9k_hw_set_defaults(ah);
606
607 if (ah->ah_config.intr_mitigation != 0)
608 ahp->ah_intrMitigation = true;
609
610 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
611 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
612 __func__);
613 ecode = -EIO;
614 goto bad;
615 }
616
617 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
618 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
619 __func__);
620 ecode = -EIO;
621 goto bad;
622 }
623
624 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
625 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
626 ah->ah_config.serialize_regmode =
627 SER_REG_MODE_ON;
628 } else {
629 ah->ah_config.serialize_regmode =
630 SER_REG_MODE_OFF;
631 }
632 }
633
634 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
635 "%s: serialize_regmode is %d\n",
636 __func__, ah->ah_config.serialize_regmode);
637
638 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
639 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
640 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
641 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
642 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
643 "%s: Mac Chip Rev 0x%02x.%x is not supported by "
644 "this driver\n", __func__,
645 ah->ah_macVersion, ah->ah_macRev);
646 ecode = -EOPNOTSUPP;
647 goto bad;
648 }
649
650 if (AR_SREV_9100(ah)) {
651 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
652 ahp->ah_suppCals = IQ_MISMATCH_CAL;
653 ah->ah_isPciExpress = false;
654 }
655 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
656
657 if (AR_SREV_9160_10_OR_LATER(ah)) {
658 if (AR_SREV_9280_10_OR_LATER(ah)) {
659 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
660 ahp->ah_adcGainCalData.calData =
661 &adc_gain_cal_single_sample;
662 ahp->ah_adcDcCalData.calData =
663 &adc_dc_cal_single_sample;
664 ahp->ah_adcDcCalInitData.calData =
665 &adc_init_dc_cal;
666 } else {
667 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
668 ahp->ah_adcGainCalData.calData =
669 &adc_gain_cal_multi_sample;
670 ahp->ah_adcDcCalData.calData =
671 &adc_dc_cal_multi_sample;
672 ahp->ah_adcDcCalInitData.calData =
673 &adc_init_dc_cal;
674 }
675 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
676 }
677
678 if (AR_SREV_9160(ah)) {
679 ah->ah_config.enable_ani = 1;
680 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
681 ATH9K_ANI_FIRSTEP_LEVEL);
682 } else {
683 ahp->ah_ani_function = ATH9K_ANI_ALL;
684 if (AR_SREV_9280_10_OR_LATER(ah)) {
685 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
686 }
687 }
688
689 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
690 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
691 ah->ah_macVersion, ah->ah_macRev);
692
693 if (AR_SREV_9280_20_OR_LATER(ah)) {
694 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
695 ARRAY_SIZE(ar9280Modes_9280_2), 6);
696 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
697 ARRAY_SIZE(ar9280Common_9280_2), 2);
698
699 if (ah->ah_config.pcie_clock_req) {
700 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
701 ar9280PciePhy_clkreq_off_L1_9280,
702 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
703 } else {
704 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
705 ar9280PciePhy_clkreq_always_on_L1_9280,
706 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
707 }
708 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
709 ar9280Modes_fast_clock_9280_2,
710 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
711 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
712 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
713 ARRAY_SIZE(ar9280Modes_9280), 6);
714 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
715 ARRAY_SIZE(ar9280Common_9280), 2);
716 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
717 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
718 ARRAY_SIZE(ar5416Modes_9160), 6);
719 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
720 ARRAY_SIZE(ar5416Common_9160), 2);
721 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
722 ARRAY_SIZE(ar5416Bank0_9160), 2);
723 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
724 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
725 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
726 ARRAY_SIZE(ar5416Bank1_9160), 2);
727 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
728 ARRAY_SIZE(ar5416Bank2_9160), 2);
729 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
730 ARRAY_SIZE(ar5416Bank3_9160), 3);
731 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
732 ARRAY_SIZE(ar5416Bank6_9160), 3);
733 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
734 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
735 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
736 ARRAY_SIZE(ar5416Bank7_9160), 2);
737 if (AR_SREV_9160_11(ah)) {
738 INIT_INI_ARRAY(&ahp->ah_iniAddac,
739 ar5416Addac_91601_1,
740 ARRAY_SIZE(ar5416Addac_91601_1), 2);
741 } else {
742 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
743 ARRAY_SIZE(ar5416Addac_9160), 2);
744 }
745 } else if (AR_SREV_9100_OR_LATER(ah)) {
746 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
747 ARRAY_SIZE(ar5416Modes_9100), 6);
748 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
749 ARRAY_SIZE(ar5416Common_9100), 2);
750 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
751 ARRAY_SIZE(ar5416Bank0_9100), 2);
752 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
753 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
754 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
755 ARRAY_SIZE(ar5416Bank1_9100), 2);
756 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
757 ARRAY_SIZE(ar5416Bank2_9100), 2);
758 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
759 ARRAY_SIZE(ar5416Bank3_9100), 3);
760 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
761 ARRAY_SIZE(ar5416Bank6_9100), 3);
762 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
763 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
764 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
765 ARRAY_SIZE(ar5416Bank7_9100), 2);
766 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
767 ARRAY_SIZE(ar5416Addac_9100), 2);
768 } else {
769 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
770 ARRAY_SIZE(ar5416Modes), 6);
771 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
772 ARRAY_SIZE(ar5416Common), 2);
773 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
774 ARRAY_SIZE(ar5416Bank0), 2);
775 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
776 ARRAY_SIZE(ar5416BB_RfGain), 3);
777 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
778 ARRAY_SIZE(ar5416Bank1), 2);
779 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
780 ARRAY_SIZE(ar5416Bank2), 2);
781 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
782 ARRAY_SIZE(ar5416Bank3), 3);
783 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
784 ARRAY_SIZE(ar5416Bank6), 3);
785 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
786 ARRAY_SIZE(ar5416Bank6TPC), 3);
787 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
788 ARRAY_SIZE(ar5416Bank7), 2);
789 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
790 ARRAY_SIZE(ar5416Addac), 2);
791 }
792
793 if (ah->ah_isPciExpress)
794 ath9k_hw_configpcipowersave(ah, 0);
795 else
796 ath9k_hw_disablepcie(ah);
797
798 ecode = ath9k_hw_post_attach(ah);
799 if (ecode != 0)
800 goto bad;
801
802 #ifndef CONFIG_SLOW_ANT_DIV
803 if (ah->ah_devid == AR9280_DEVID_PCI) {
804 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
805 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
806
807 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
808 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
809
810 INI_RA(&ahp->ah_iniModes, i, j) =
811 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
812 reg, val);
813 }
814 }
815 }
816 #endif
817 if (!ath9k_hw_fill_cap_info(ah)) {
818 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
819 "%s:failed ath9k_hw_fill_cap_info\n", __func__);
820 ecode = -EINVAL;
821 goto bad;
822 }
823
824 ecode = ath9k_hw_init_macaddr(ah);
825 if (ecode != 0) {
826 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
827 "%s: failed initializing mac address\n",
828 __func__);
829 goto bad;
830 }
831
832 if (AR_SREV_9285(ah))
833 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
834 else
835 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
836
837 ath9k_init_nfcal_hist_buffer(ah);
838
839 return ah;
840 bad:
841 if (ahp)
842 ath9k_hw_detach((struct ath_hal *) ahp);
843 if (status)
844 *status = ecode;
845
846 return NULL;
847 }
848
849 static void ath9k_hw_init_bb(struct ath_hal *ah,
850 struct ath9k_channel *chan)
851 {
852 u32 synthDelay;
853
854 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
855 if (IS_CHAN_CCK(chan))
856 synthDelay = (4 * synthDelay) / 22;
857 else
858 synthDelay /= 10;
859
860 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
861
862 udelay(synthDelay + BASE_ACTIVATE_DELAY);
863 }
864
865 static void ath9k_hw_init_qos(struct ath_hal *ah)
866 {
867 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
868 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
869
870 REG_WRITE(ah, AR_QOS_NO_ACK,
871 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
872 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
873 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
874
875 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
876 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
877 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
878 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
879 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
880 }
881
882 static void ath9k_hw_init_pll(struct ath_hal *ah,
883 struct ath9k_channel *chan)
884 {
885 u32 pll;
886
887 if (AR_SREV_9100(ah)) {
888 if (chan && IS_CHAN_5GHZ(chan))
889 pll = 0x1450;
890 else
891 pll = 0x1458;
892 } else {
893 if (AR_SREV_9280_10_OR_LATER(ah)) {
894 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
895
896 if (chan && IS_CHAN_HALF_RATE(chan))
897 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
898 else if (chan && IS_CHAN_QUARTER_RATE(chan))
899 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
900
901 if (chan && IS_CHAN_5GHZ(chan)) {
902 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
903
904
905 if (AR_SREV_9280_20(ah)) {
906 if (((chan->channel % 20) == 0)
907 || ((chan->channel % 10) == 0))
908 pll = 0x2850;
909 else
910 pll = 0x142c;
911 }
912 } else {
913 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
914 }
915
916 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
917
918 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
919
920 if (chan && IS_CHAN_HALF_RATE(chan))
921 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
922 else if (chan && IS_CHAN_QUARTER_RATE(chan))
923 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
924
925 if (chan && IS_CHAN_5GHZ(chan))
926 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
927 else
928 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
929 } else {
930 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
931
932 if (chan && IS_CHAN_HALF_RATE(chan))
933 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
934 else if (chan && IS_CHAN_QUARTER_RATE(chan))
935 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
936
937 if (chan && IS_CHAN_5GHZ(chan))
938 pll |= SM(0xa, AR_RTC_PLL_DIV);
939 else
940 pll |= SM(0xb, AR_RTC_PLL_DIV);
941 }
942 }
943 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
944
945 udelay(RTC_PLL_SETTLE_DELAY);
946
947 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
948 }
949
950 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
951 {
952 struct ath_hal_5416 *ahp = AH5416(ah);
953 int rx_chainmask, tx_chainmask;
954
955 rx_chainmask = ahp->ah_rxchainmask;
956 tx_chainmask = ahp->ah_txchainmask;
957
958 switch (rx_chainmask) {
959 case 0x5:
960 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
961 AR_PHY_SWAP_ALT_CHAIN);
962 case 0x3:
963 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
964 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
965 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
966 break;
967 }
968 case 0x1:
969 case 0x2:
970 if (!AR_SREV_9280(ah))
971 break;
972 case 0x7:
973 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
974 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
975 break;
976 default:
977 break;
978 }
979
980 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
981 if (tx_chainmask == 0x5) {
982 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
983 AR_PHY_SWAP_ALT_CHAIN);
984 }
985 if (AR_SREV_9100(ah))
986 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
987 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
988 }
989
990 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, enum ath9k_opmode opmode)
991 {
992 struct ath_hal_5416 *ahp = AH5416(ah);
993
994 ahp->ah_maskReg = AR_IMR_TXERR |
995 AR_IMR_TXURN |
996 AR_IMR_RXERR |
997 AR_IMR_RXORN |
998 AR_IMR_BCNMISC;
999
1000 if (ahp->ah_intrMitigation)
1001 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1002 else
1003 ahp->ah_maskReg |= AR_IMR_RXOK;
1004
1005 ahp->ah_maskReg |= AR_IMR_TXOK;
1006
1007 if (opmode == ATH9K_M_HOSTAP)
1008 ahp->ah_maskReg |= AR_IMR_MIB;
1009
1010 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1011 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1012
1013 if (!AR_SREV_9100(ah)) {
1014 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1015 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1016 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1017 }
1018 }
1019
1020 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1021 {
1022 struct ath_hal_5416 *ahp = AH5416(ah);
1023
1024 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1025 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
1026 __func__, us);
1027 ahp->ah_acktimeout = (u32) -1;
1028 return false;
1029 } else {
1030 REG_RMW_FIELD(ah, AR_TIME_OUT,
1031 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1032 ahp->ah_acktimeout = us;
1033 return true;
1034 }
1035 }
1036
1037 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1038 {
1039 struct ath_hal_5416 *ahp = AH5416(ah);
1040
1041 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1042 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
1043 __func__, us);
1044 ahp->ah_ctstimeout = (u32) -1;
1045 return false;
1046 } else {
1047 REG_RMW_FIELD(ah, AR_TIME_OUT,
1048 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1049 ahp->ah_ctstimeout = us;
1050 return true;
1051 }
1052 }
1053
1054 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1055 {
1056 struct ath_hal_5416 *ahp = AH5416(ah);
1057
1058 if (tu > 0xFFFF) {
1059 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1060 "%s: bad global tx timeout %u\n", __func__, tu);
1061 ahp->ah_globaltxtimeout = (u32) -1;
1062 return false;
1063 } else {
1064 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1065 ahp->ah_globaltxtimeout = tu;
1066 return true;
1067 }
1068 }
1069
1070 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1071 {
1072 struct ath_hal_5416 *ahp = AH5416(ah);
1073
1074 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
1075 __func__, ahp->ah_miscMode);
1076
1077 if (ahp->ah_miscMode != 0)
1078 REG_WRITE(ah, AR_PCU_MISC,
1079 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1080 if (ahp->ah_slottime != (u32) -1)
1081 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1082 if (ahp->ah_acktimeout != (u32) -1)
1083 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1084 if (ahp->ah_ctstimeout != (u32) -1)
1085 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1086 if (ahp->ah_globaltxtimeout != (u32) -1)
1087 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1088 }
1089
1090 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1091 {
1092 return vendorid == ATHEROS_VENDOR_ID ?
1093 ath9k_hw_devname(devid) : NULL;
1094 }
1095
1096 void ath9k_hw_detach(struct ath_hal *ah)
1097 {
1098 if (!AR_SREV_9100(ah))
1099 ath9k_hw_ani_detach(ah);
1100
1101 ath9k_hw_rfdetach(ah);
1102 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1103 kfree(ah);
1104 }
1105
1106 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1107 void __iomem *mem, int *error)
1108 {
1109 struct ath_hal *ah = NULL;
1110
1111 switch (devid) {
1112 case AR5416_DEVID_PCI:
1113 case AR5416_DEVID_PCIE:
1114 case AR9160_DEVID_PCI:
1115 case AR9280_DEVID_PCI:
1116 case AR9280_DEVID_PCIE:
1117 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1118 break;
1119 default:
1120 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1121 "devid=0x%x not supported.\n", devid);
1122 ah = NULL;
1123 *error = -ENXIO;
1124 break;
1125 }
1126
1127 return ah;
1128 }
1129
1130 /*******/
1131 /* INI */
1132 /*******/
1133
1134 static void ath9k_hw_override_ini(struct ath_hal *ah,
1135 struct ath9k_channel *chan)
1136 {
1137 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1138 AR_SREV_9280_10_OR_LATER(ah))
1139 return;
1140
1141 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1142 }
1143
1144 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1145 struct ar5416_eeprom *pEepData,
1146 u32 reg, u32 value)
1147 {
1148 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1149
1150 switch (ah->ah_devid) {
1151 case AR9280_DEVID_PCI:
1152 if (reg == 0x7894) {
1153 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1154 "ini VAL: %x EEPROM: %x\n", value,
1155 (pBase->version & 0xff));
1156
1157 if ((pBase->version & 0xff) > 0x0a) {
1158 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1159 "PWDCLKIND: %d\n",
1160 pBase->pwdclkind);
1161 value &= ~AR_AN_TOP2_PWDCLKIND;
1162 value |= AR_AN_TOP2_PWDCLKIND &
1163 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1164 } else {
1165 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1166 "PWDCLKIND Earlier Rev\n");
1167 }
1168
1169 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1170 "final ini VAL: %x\n", value);
1171 }
1172 break;
1173 }
1174
1175 return value;
1176 }
1177
1178 static int ath9k_hw_process_ini(struct ath_hal *ah,
1179 struct ath9k_channel *chan,
1180 enum ath9k_ht_macmode macmode)
1181 {
1182 int i, regWrites = 0;
1183 struct ath_hal_5416 *ahp = AH5416(ah);
1184 u32 modesIndex, freqIndex;
1185 int status;
1186
1187 switch (chan->chanmode) {
1188 case CHANNEL_A:
1189 case CHANNEL_A_HT20:
1190 modesIndex = 1;
1191 freqIndex = 1;
1192 break;
1193 case CHANNEL_A_HT40PLUS:
1194 case CHANNEL_A_HT40MINUS:
1195 modesIndex = 2;
1196 freqIndex = 1;
1197 break;
1198 case CHANNEL_G:
1199 case CHANNEL_G_HT20:
1200 case CHANNEL_B:
1201 modesIndex = 4;
1202 freqIndex = 2;
1203 break;
1204 case CHANNEL_G_HT40PLUS:
1205 case CHANNEL_G_HT40MINUS:
1206 modesIndex = 3;
1207 freqIndex = 2;
1208 break;
1209
1210 default:
1211 return -EINVAL;
1212 }
1213
1214 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1215
1216 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1217
1218 ath9k_hw_set_addac(ah, chan);
1219
1220 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1221 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1222 } else {
1223 struct ar5416IniArray temp;
1224 u32 addacSize =
1225 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1226 ahp->ah_iniAddac.ia_columns;
1227
1228 memcpy(ahp->ah_addac5416_21,
1229 ahp->ah_iniAddac.ia_array, addacSize);
1230
1231 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1232
1233 temp.ia_array = ahp->ah_addac5416_21;
1234 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1235 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1236 REG_WRITE_ARRAY(&temp, 1, regWrites);
1237 }
1238
1239 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1240
1241 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1242 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1243 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1244
1245 #ifdef CONFIG_SLOW_ANT_DIV
1246 if (ah->ah_devid == AR9280_DEVID_PCI)
1247 val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg, val);
1248 #endif
1249
1250 REG_WRITE(ah, reg, val);
1251
1252 if (reg >= 0x7800 && reg < 0x78a0
1253 && ah->ah_config.analog_shiftreg) {
1254 udelay(100);
1255 }
1256
1257 DO_DELAY(regWrites);
1258 }
1259
1260 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1261 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1262 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1263
1264 REG_WRITE(ah, reg, val);
1265
1266 if (reg >= 0x7800 && reg < 0x78a0
1267 && ah->ah_config.analog_shiftreg) {
1268 udelay(100);
1269 }
1270
1271 DO_DELAY(regWrites);
1272 }
1273
1274 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1275
1276 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1277 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1278 regWrites);
1279 }
1280
1281 ath9k_hw_override_ini(ah, chan);
1282 ath9k_hw_set_regs(ah, chan, macmode);
1283 ath9k_hw_init_chain_masks(ah);
1284
1285 status = ath9k_hw_set_txpower(ah, chan,
1286 ath9k_regd_get_ctl(ah, chan),
1287 ath9k_regd_get_antenna_allowed(ah,
1288 chan),
1289 chan->maxRegTxPower * 2,
1290 min((u32) MAX_RATE_POWER,
1291 (u32) ah->ah_powerLimit));
1292 if (status != 0) {
1293 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1294 "%s: error init'ing transmit power\n", __func__);
1295 return -EIO;
1296 }
1297
1298 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1299 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1300 "%s: ar5416SetRfRegs failed\n", __func__);
1301 return -EIO;
1302 }
1303
1304 return 0;
1305 }
1306
1307 /****************************************/
1308 /* Reset and Channel Switching Routines */
1309 /****************************************/
1310
1311 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1312 {
1313 u32 rfMode = 0;
1314
1315 if (chan == NULL)
1316 return;
1317
1318 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1319 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1320
1321 if (!AR_SREV_9280_10_OR_LATER(ah))
1322 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1323 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1324
1325 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1326 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1327
1328 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1329 }
1330
1331 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1332 {
1333 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1334 }
1335
1336 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1337 {
1338 u32 regval;
1339
1340 regval = REG_READ(ah, AR_AHB_MODE);
1341 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1342
1343 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1344 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1345
1346 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1347
1348 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1349 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1350
1351 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1352
1353 if (AR_SREV_9285(ah)) {
1354 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1355 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1356 } else {
1357 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1358 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1359 }
1360 }
1361
1362 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1363 {
1364 u32 val;
1365
1366 val = REG_READ(ah, AR_STA_ID1);
1367 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1368 switch (opmode) {
1369 case ATH9K_M_HOSTAP:
1370 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1371 | AR_STA_ID1_KSRCH_MODE);
1372 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1373 break;
1374 case ATH9K_M_IBSS:
1375 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1376 | AR_STA_ID1_KSRCH_MODE);
1377 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1378 break;
1379 case ATH9K_M_STA:
1380 case ATH9K_M_MONITOR:
1381 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1382 break;
1383 }
1384 }
1385
1386 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1387 u32 coef_scaled,
1388 u32 *coef_mantissa,
1389 u32 *coef_exponent)
1390 {
1391 u32 coef_exp, coef_man;
1392
1393 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1394 if ((coef_scaled >> coef_exp) & 0x1)
1395 break;
1396
1397 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1398
1399 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1400
1401 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1402 *coef_exponent = coef_exp - 16;
1403 }
1404
1405 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1406 struct ath9k_channel *chan)
1407 {
1408 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1409 u32 clockMhzScaled = 0x64000000;
1410 struct chan_centers centers;
1411
1412 if (IS_CHAN_HALF_RATE(chan))
1413 clockMhzScaled = clockMhzScaled >> 1;
1414 else if (IS_CHAN_QUARTER_RATE(chan))
1415 clockMhzScaled = clockMhzScaled >> 2;
1416
1417 ath9k_hw_get_channel_centers(ah, chan, &centers);
1418 coef_scaled = clockMhzScaled / centers.synth_center;
1419
1420 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1421 &ds_coef_exp);
1422
1423 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1424 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1425 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1426 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1427
1428 coef_scaled = (9 * coef_scaled) / 10;
1429
1430 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1431 &ds_coef_exp);
1432
1433 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1434 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1435 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1436 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1437 }
1438
1439 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1440 {
1441 u32 rst_flags;
1442 u32 tmpReg;
1443
1444 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1445 AR_RTC_FORCE_WAKE_ON_INT);
1446
1447 if (AR_SREV_9100(ah)) {
1448 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1449 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1450 } else {
1451 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1452 if (tmpReg &
1453 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1454 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1455 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1456 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1457 } else {
1458 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1459 }
1460
1461 rst_flags = AR_RTC_RC_MAC_WARM;
1462 if (type == ATH9K_RESET_COLD)
1463 rst_flags |= AR_RTC_RC_MAC_COLD;
1464 }
1465
1466 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1467 udelay(50);
1468
1469 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1470 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1471 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1472 "%s: RTC stuck in MAC reset\n",
1473 __func__);
1474 return false;
1475 }
1476
1477 if (!AR_SREV_9100(ah))
1478 REG_WRITE(ah, AR_RC, 0);
1479
1480 ath9k_hw_init_pll(ah, NULL);
1481
1482 if (AR_SREV_9100(ah))
1483 udelay(50);
1484
1485 return true;
1486 }
1487
1488 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1489 {
1490 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1491 AR_RTC_FORCE_WAKE_ON_INT);
1492
1493 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1494 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1495
1496 if (!ath9k_hw_wait(ah,
1497 AR_RTC_STATUS,
1498 AR_RTC_STATUS_M,
1499 AR_RTC_STATUS_ON)) {
1500 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
1501 __func__);
1502 return false;
1503 }
1504
1505 ath9k_hw_read_revisions(ah);
1506
1507 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1508 }
1509
1510 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1511 {
1512 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1513 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1514
1515 switch (type) {
1516 case ATH9K_RESET_POWER_ON:
1517 return ath9k_hw_set_reset_power_on(ah);
1518 break;
1519 case ATH9K_RESET_WARM:
1520 case ATH9K_RESET_COLD:
1521 return ath9k_hw_set_reset(ah, type);
1522 break;
1523 default:
1524 return false;
1525 }
1526 }
1527
1528 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1529 enum ath9k_ht_macmode macmode)
1530 {
1531 u32 phymode;
1532 struct ath_hal_5416 *ahp = AH5416(ah);
1533
1534 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1535 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1536
1537 if (IS_CHAN_HT40(chan)) {
1538 phymode |= AR_PHY_FC_DYN2040_EN;
1539
1540 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1541 (chan->chanmode == CHANNEL_G_HT40PLUS))
1542 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1543
1544 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1545 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1546 }
1547 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1548
1549 ath9k_hw_set11nmac2040(ah, macmode);
1550
1551 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1552 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1553 }
1554
1555 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1556 struct ath9k_channel *chan)
1557 {
1558 struct ath_hal_5416 *ahp = AH5416(ah);
1559
1560 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1561 return false;
1562
1563 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1564 return false;
1565
1566 ahp->ah_chipFullSleep = false;
1567
1568 ath9k_hw_init_pll(ah, chan);
1569
1570 ath9k_hw_set_rfmode(ah, chan);
1571
1572 return true;
1573 }
1574
1575 static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1576 struct ath9k_channel *chan)
1577 {
1578 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1579 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1580 "%s: invalid channel %u/0x%x; not marked as "
1581 "2GHz or 5GHz\n", __func__, chan->channel,
1582 chan->channelFlags);
1583 return NULL;
1584 }
1585
1586 if (!IS_CHAN_OFDM(chan) &&
1587 !IS_CHAN_CCK(chan) &&
1588 !IS_CHAN_HT20(chan) &&
1589 !IS_CHAN_HT40(chan)) {
1590 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1591 "%s: invalid channel %u/0x%x; not marked as "
1592 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1593 __func__, chan->channel, chan->channelFlags);
1594 return NULL;
1595 }
1596
1597 return ath9k_regd_check_channel(ah, chan);
1598 }
1599
1600 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1601 struct ath9k_channel *chan,
1602 enum ath9k_ht_macmode macmode)
1603 {
1604 u32 synthDelay, qnum;
1605
1606 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1607 if (ath9k_hw_numtxpending(ah, qnum)) {
1608 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1609 "%s: Transmit frames pending on queue %d\n",
1610 __func__, qnum);
1611 return false;
1612 }
1613 }
1614
1615 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1616 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1617 AR_PHY_RFBUS_GRANT_EN)) {
1618 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
1619 "%s: Could not kill baseband RX\n", __func__);
1620 return false;
1621 }
1622
1623 ath9k_hw_set_regs(ah, chan, macmode);
1624
1625 if (AR_SREV_9280_10_OR_LATER(ah)) {
1626 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1627 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1628 "%s: failed to set channel\n", __func__);
1629 return false;
1630 }
1631 } else {
1632 if (!(ath9k_hw_set_channel(ah, chan))) {
1633 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1634 "%s: failed to set channel\n", __func__);
1635 return false;
1636 }
1637 }
1638
1639 if (ath9k_hw_set_txpower(ah, chan,
1640 ath9k_regd_get_ctl(ah, chan),
1641 ath9k_regd_get_antenna_allowed(ah, chan),
1642 chan->maxRegTxPower * 2,
1643 min((u32) MAX_RATE_POWER,
1644 (u32) ah->ah_powerLimit)) != 0) {
1645 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1646 "%s: error init'ing transmit power\n", __func__);
1647 return false;
1648 }
1649
1650 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1651 if (IS_CHAN_CCK(chan))
1652 synthDelay = (4 * synthDelay) / 22;
1653 else
1654 synthDelay /= 10;
1655
1656 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1657
1658 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1659
1660 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1661 ath9k_hw_set_delta_slope(ah, chan);
1662
1663 if (AR_SREV_9280_10_OR_LATER(ah))
1664 ath9k_hw_9280_spur_mitigate(ah, chan);
1665 else
1666 ath9k_hw_spur_mitigate(ah, chan);
1667
1668 if (!chan->oneTimeCalsDone)
1669 chan->oneTimeCalsDone = true;
1670
1671 return true;
1672 }
1673
1674 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1675 {
1676 int bb_spur = AR_NO_SPUR;
1677 int freq;
1678 int bin, cur_bin;
1679 int bb_spur_off, spur_subchannel_sd;
1680 int spur_freq_sd;
1681 int spur_delta_phase;
1682 int denominator;
1683 int upper, lower, cur_vit_mask;
1684 int tmp, newVal;
1685 int i;
1686 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1687 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1688 };
1689 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1690 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1691 };
1692 int inc[4] = { 0, 100, 0, 0 };
1693 struct chan_centers centers;
1694
1695 int8_t mask_m[123];
1696 int8_t mask_p[123];
1697 int8_t mask_amt;
1698 int tmp_mask;
1699 int cur_bb_spur;
1700 bool is2GHz = IS_CHAN_2GHZ(chan);
1701
1702 memset(&mask_m, 0, sizeof(int8_t) * 123);
1703 memset(&mask_p, 0, sizeof(int8_t) * 123);
1704
1705 ath9k_hw_get_channel_centers(ah, chan, &centers);
1706 freq = centers.synth_center;
1707
1708 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1709 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1710 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1711
1712 if (is2GHz)
1713 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1714 else
1715 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1716
1717 if (AR_NO_SPUR == cur_bb_spur)
1718 break;
1719 cur_bb_spur = cur_bb_spur - freq;
1720
1721 if (IS_CHAN_HT40(chan)) {
1722 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1723 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1724 bb_spur = cur_bb_spur;
1725 break;
1726 }
1727 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1728 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1729 bb_spur = cur_bb_spur;
1730 break;
1731 }
1732 }
1733
1734 if (AR_NO_SPUR == bb_spur) {
1735 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1736 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1737 return;
1738 } else {
1739 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1740 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1741 }
1742
1743 bin = bb_spur * 320;
1744
1745 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1746
1747 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1748 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1749 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1750 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1751 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1752
1753 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1754 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1755 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1756 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1757 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1758 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1759
1760 if (IS_CHAN_HT40(chan)) {
1761 if (bb_spur < 0) {
1762 spur_subchannel_sd = 1;
1763 bb_spur_off = bb_spur + 10;
1764 } else {
1765 spur_subchannel_sd = 0;
1766 bb_spur_off = bb_spur - 10;
1767 }
1768 } else {
1769 spur_subchannel_sd = 0;
1770 bb_spur_off = bb_spur;
1771 }
1772
1773 if (IS_CHAN_HT40(chan))
1774 spur_delta_phase =
1775 ((bb_spur * 262144) /
1776 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1777 else
1778 spur_delta_phase =
1779 ((bb_spur * 524288) /
1780 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1781
1782 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1783 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1784
1785 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1786 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1787 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1788 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1789
1790 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1791 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1792
1793 cur_bin = -6000;
1794 upper = bin + 100;
1795 lower = bin - 100;
1796
1797 for (i = 0; i < 4; i++) {
1798 int pilot_mask = 0;
1799 int chan_mask = 0;
1800 int bp = 0;
1801 for (bp = 0; bp < 30; bp++) {
1802 if ((cur_bin > lower) && (cur_bin < upper)) {
1803 pilot_mask = pilot_mask | 0x1 << bp;
1804 chan_mask = chan_mask | 0x1 << bp;
1805 }
1806 cur_bin += 100;
1807 }
1808 cur_bin += inc[i];
1809 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1810 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1811 }
1812
1813 cur_vit_mask = 6100;
1814 upper = bin + 120;
1815 lower = bin - 120;
1816
1817 for (i = 0; i < 123; i++) {
1818 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1819
1820 /* workaround for gcc bug #37014 */
1821 volatile int tmp = abs(cur_vit_mask - bin);
1822
1823 if (tmp < 75)
1824 mask_amt = 1;
1825 else
1826 mask_amt = 0;
1827 if (cur_vit_mask < 0)
1828 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1829 else
1830 mask_p[cur_vit_mask / 100] = mask_amt;
1831 }
1832 cur_vit_mask -= 100;
1833 }
1834
1835 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1836 | (mask_m[48] << 26) | (mask_m[49] << 24)
1837 | (mask_m[50] << 22) | (mask_m[51] << 20)
1838 | (mask_m[52] << 18) | (mask_m[53] << 16)
1839 | (mask_m[54] << 14) | (mask_m[55] << 12)
1840 | (mask_m[56] << 10) | (mask_m[57] << 8)
1841 | (mask_m[58] << 6) | (mask_m[59] << 4)
1842 | (mask_m[60] << 2) | (mask_m[61] << 0);
1843 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1844 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1845
1846 tmp_mask = (mask_m[31] << 28)
1847 | (mask_m[32] << 26) | (mask_m[33] << 24)
1848 | (mask_m[34] << 22) | (mask_m[35] << 20)
1849 | (mask_m[36] << 18) | (mask_m[37] << 16)
1850 | (mask_m[48] << 14) | (mask_m[39] << 12)
1851 | (mask_m[40] << 10) | (mask_m[41] << 8)
1852 | (mask_m[42] << 6) | (mask_m[43] << 4)
1853 | (mask_m[44] << 2) | (mask_m[45] << 0);
1854 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1855 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1856
1857 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1858 | (mask_m[18] << 26) | (mask_m[18] << 24)
1859 | (mask_m[20] << 22) | (mask_m[20] << 20)
1860 | (mask_m[22] << 18) | (mask_m[22] << 16)
1861 | (mask_m[24] << 14) | (mask_m[24] << 12)
1862 | (mask_m[25] << 10) | (mask_m[26] << 8)
1863 | (mask_m[27] << 6) | (mask_m[28] << 4)
1864 | (mask_m[29] << 2) | (mask_m[30] << 0);
1865 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1866 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1867
1868 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1869 | (mask_m[2] << 26) | (mask_m[3] << 24)
1870 | (mask_m[4] << 22) | (mask_m[5] << 20)
1871 | (mask_m[6] << 18) | (mask_m[7] << 16)
1872 | (mask_m[8] << 14) | (mask_m[9] << 12)
1873 | (mask_m[10] << 10) | (mask_m[11] << 8)
1874 | (mask_m[12] << 6) | (mask_m[13] << 4)
1875 | (mask_m[14] << 2) | (mask_m[15] << 0);
1876 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1877 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1878
1879 tmp_mask = (mask_p[15] << 28)
1880 | (mask_p[14] << 26) | (mask_p[13] << 24)
1881 | (mask_p[12] << 22) | (mask_p[11] << 20)
1882 | (mask_p[10] << 18) | (mask_p[9] << 16)
1883 | (mask_p[8] << 14) | (mask_p[7] << 12)
1884 | (mask_p[6] << 10) | (mask_p[5] << 8)
1885 | (mask_p[4] << 6) | (mask_p[3] << 4)
1886 | (mask_p[2] << 2) | (mask_p[1] << 0);
1887 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1888 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1889
1890 tmp_mask = (mask_p[30] << 28)
1891 | (mask_p[29] << 26) | (mask_p[28] << 24)
1892 | (mask_p[27] << 22) | (mask_p[26] << 20)
1893 | (mask_p[25] << 18) | (mask_p[24] << 16)
1894 | (mask_p[23] << 14) | (mask_p[22] << 12)
1895 | (mask_p[21] << 10) | (mask_p[20] << 8)
1896 | (mask_p[19] << 6) | (mask_p[18] << 4)
1897 | (mask_p[17] << 2) | (mask_p[16] << 0);
1898 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1899 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1900
1901 tmp_mask = (mask_p[45] << 28)
1902 | (mask_p[44] << 26) | (mask_p[43] << 24)
1903 | (mask_p[42] << 22) | (mask_p[41] << 20)
1904 | (mask_p[40] << 18) | (mask_p[39] << 16)
1905 | (mask_p[38] << 14) | (mask_p[37] << 12)
1906 | (mask_p[36] << 10) | (mask_p[35] << 8)
1907 | (mask_p[34] << 6) | (mask_p[33] << 4)
1908 | (mask_p[32] << 2) | (mask_p[31] << 0);
1909 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1910 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1911
1912 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1913 | (mask_p[59] << 26) | (mask_p[58] << 24)
1914 | (mask_p[57] << 22) | (mask_p[56] << 20)
1915 | (mask_p[55] << 18) | (mask_p[54] << 16)
1916 | (mask_p[53] << 14) | (mask_p[52] << 12)
1917 | (mask_p[51] << 10) | (mask_p[50] << 8)
1918 | (mask_p[49] << 6) | (mask_p[48] << 4)
1919 | (mask_p[47] << 2) | (mask_p[46] << 0);
1920 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1921 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1922 }
1923
1924 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1925 {
1926 int bb_spur = AR_NO_SPUR;
1927 int bin, cur_bin;
1928 int spur_freq_sd;
1929 int spur_delta_phase;
1930 int denominator;
1931 int upper, lower, cur_vit_mask;
1932 int tmp, new;
1933 int i;
1934 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1935 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1936 };
1937 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1938 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1939 };
1940 int inc[4] = { 0, 100, 0, 0 };
1941
1942 int8_t mask_m[123];
1943 int8_t mask_p[123];
1944 int8_t mask_amt;
1945 int tmp_mask;
1946 int cur_bb_spur;
1947 bool is2GHz = IS_CHAN_2GHZ(chan);
1948
1949 memset(&mask_m, 0, sizeof(int8_t) * 123);
1950 memset(&mask_p, 0, sizeof(int8_t) * 123);
1951
1952 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1953 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1954 if (AR_NO_SPUR == cur_bb_spur)
1955 break;
1956 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1957 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1958 bb_spur = cur_bb_spur;
1959 break;
1960 }
1961 }
1962
1963 if (AR_NO_SPUR == bb_spur)
1964 return;
1965
1966 bin = bb_spur * 32;
1967
1968 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1969 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1970 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1971 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1972 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1973
1974 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
1975
1976 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1977 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1978 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1979 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1980 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1981 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
1982
1983 spur_delta_phase = ((bb_spur * 524288) / 100) &
1984 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1985
1986 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
1987 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
1988
1989 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1990 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1991 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1992 REG_WRITE(ah, AR_PHY_TIMING11, new);
1993
1994 cur_bin = -6000;
1995 upper = bin + 100;
1996 lower = bin - 100;
1997
1998 for (i = 0; i < 4; i++) {
1999 int pilot_mask = 0;
2000 int chan_mask = 0;
2001 int bp = 0;
2002 for (bp = 0; bp < 30; bp++) {
2003 if ((cur_bin > lower) && (cur_bin < upper)) {
2004 pilot_mask = pilot_mask | 0x1 << bp;
2005 chan_mask = chan_mask | 0x1 << bp;
2006 }
2007 cur_bin += 100;
2008 }
2009 cur_bin += inc[i];
2010 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2011 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2012 }
2013
2014 cur_vit_mask = 6100;
2015 upper = bin + 120;
2016 lower = bin - 120;
2017
2018 for (i = 0; i < 123; i++) {
2019 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2020
2021 /* workaround for gcc bug #37014 */
2022 volatile int tmp = abs(cur_vit_mask - bin);
2023
2024 if (tmp < 75)
2025 mask_amt = 1;
2026 else
2027 mask_amt = 0;
2028 if (cur_vit_mask < 0)
2029 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2030 else
2031 mask_p[cur_vit_mask / 100] = mask_amt;
2032 }
2033 cur_vit_mask -= 100;
2034 }
2035
2036 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2037 | (mask_m[48] << 26) | (mask_m[49] << 24)
2038 | (mask_m[50] << 22) | (mask_m[51] << 20)
2039 | (mask_m[52] << 18) | (mask_m[53] << 16)
2040 | (mask_m[54] << 14) | (mask_m[55] << 12)
2041 | (mask_m[56] << 10) | (mask_m[57] << 8)
2042 | (mask_m[58] << 6) | (mask_m[59] << 4)
2043 | (mask_m[60] << 2) | (mask_m[61] << 0);
2044 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2045 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2046
2047 tmp_mask = (mask_m[31] << 28)
2048 | (mask_m[32] << 26) | (mask_m[33] << 24)
2049 | (mask_m[34] << 22) | (mask_m[35] << 20)
2050 | (mask_m[36] << 18) | (mask_m[37] << 16)
2051 | (mask_m[48] << 14) | (mask_m[39] << 12)
2052 | (mask_m[40] << 10) | (mask_m[41] << 8)
2053 | (mask_m[42] << 6) | (mask_m[43] << 4)
2054 | (mask_m[44] << 2) | (mask_m[45] << 0);
2055 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2056 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2057
2058 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2059 | (mask_m[18] << 26) | (mask_m[18] << 24)
2060 | (mask_m[20] << 22) | (mask_m[20] << 20)
2061 | (mask_m[22] << 18) | (mask_m[22] << 16)
2062 | (mask_m[24] << 14) | (mask_m[24] << 12)
2063 | (mask_m[25] << 10) | (mask_m[26] << 8)
2064 | (mask_m[27] << 6) | (mask_m[28] << 4)
2065 | (mask_m[29] << 2) | (mask_m[30] << 0);
2066 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2067 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2068
2069 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2070 | (mask_m[2] << 26) | (mask_m[3] << 24)
2071 | (mask_m[4] << 22) | (mask_m[5] << 20)
2072 | (mask_m[6] << 18) | (mask_m[7] << 16)
2073 | (mask_m[8] << 14) | (mask_m[9] << 12)
2074 | (mask_m[10] << 10) | (mask_m[11] << 8)
2075 | (mask_m[12] << 6) | (mask_m[13] << 4)
2076 | (mask_m[14] << 2) | (mask_m[15] << 0);
2077 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2078 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2079
2080 tmp_mask = (mask_p[15] << 28)
2081 | (mask_p[14] << 26) | (mask_p[13] << 24)
2082 | (mask_p[12] << 22) | (mask_p[11] << 20)
2083 | (mask_p[10] << 18) | (mask_p[9] << 16)
2084 | (mask_p[8] << 14) | (mask_p[7] << 12)
2085 | (mask_p[6] << 10) | (mask_p[5] << 8)
2086 | (mask_p[4] << 6) | (mask_p[3] << 4)
2087 | (mask_p[2] << 2) | (mask_p[1] << 0);
2088 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2089 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2090
2091 tmp_mask = (mask_p[30] << 28)
2092 | (mask_p[29] << 26) | (mask_p[28] << 24)
2093 | (mask_p[27] << 22) | (mask_p[26] << 20)
2094 | (mask_p[25] << 18) | (mask_p[24] << 16)
2095 | (mask_p[23] << 14) | (mask_p[22] << 12)
2096 | (mask_p[21] << 10) | (mask_p[20] << 8)
2097 | (mask_p[19] << 6) | (mask_p[18] << 4)
2098 | (mask_p[17] << 2) | (mask_p[16] << 0);
2099 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2100 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2101
2102 tmp_mask = (mask_p[45] << 28)
2103 | (mask_p[44] << 26) | (mask_p[43] << 24)
2104 | (mask_p[42] << 22) | (mask_p[41] << 20)
2105 | (mask_p[40] << 18) | (mask_p[39] << 16)
2106 | (mask_p[38] << 14) | (mask_p[37] << 12)
2107 | (mask_p[36] << 10) | (mask_p[35] << 8)
2108 | (mask_p[34] << 6) | (mask_p[33] << 4)
2109 | (mask_p[32] << 2) | (mask_p[31] << 0);
2110 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2111 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2112
2113 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2114 | (mask_p[59] << 26) | (mask_p[58] << 24)
2115 | (mask_p[57] << 22) | (mask_p[56] << 20)
2116 | (mask_p[55] << 18) | (mask_p[54] << 16)
2117 | (mask_p[53] << 14) | (mask_p[52] << 12)
2118 | (mask_p[51] << 10) | (mask_p[50] << 8)
2119 | (mask_p[49] << 6) | (mask_p[48] << 4)
2120 | (mask_p[47] << 2) | (mask_p[46] << 0);
2121 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2122 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2123 }
2124
2125 bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2126 enum ath9k_ht_macmode macmode,
2127 u8 txchainmask, u8 rxchainmask,
2128 enum ath9k_ht_extprotspacing extprotspacing,
2129 bool bChannelChange, int *status)
2130 {
2131 u32 saveLedState;
2132 struct ath_hal_5416 *ahp = AH5416(ah);
2133 struct ath9k_channel *curchan = ah->ah_curchan;
2134 u32 saveDefAntenna;
2135 u32 macStaId1;
2136 int ecode;
2137 int i, rx_chainmask;
2138
2139 ahp->ah_extprotspacing = extprotspacing;
2140 ahp->ah_txchainmask = txchainmask;
2141 ahp->ah_rxchainmask = rxchainmask;
2142
2143 if (AR_SREV_9280(ah)) {
2144 ahp->ah_txchainmask &= 0x3;
2145 ahp->ah_rxchainmask &= 0x3;
2146 }
2147
2148 if (ath9k_hw_check_chan(ah, chan) == NULL) {
2149 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2150 "%s: invalid channel %u/0x%x; no mapping\n",
2151 __func__, chan->channel, chan->channelFlags);
2152 ecode = -EINVAL;
2153 goto bad;
2154 }
2155
2156 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
2157 ecode = -EIO;
2158 goto bad;
2159 }
2160
2161 if (curchan)
2162 ath9k_hw_getnf(ah, curchan);
2163
2164 if (bChannelChange &&
2165 (ahp->ah_chipFullSleep != true) &&
2166 (ah->ah_curchan != NULL) &&
2167 (chan->channel != ah->ah_curchan->channel) &&
2168 ((chan->channelFlags & CHANNEL_ALL) ==
2169 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2170 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2171 !IS_CHAN_A_5MHZ_SPACED(ah->
2172 ah_curchan)))) {
2173
2174 if (ath9k_hw_channel_change(ah, chan, macmode)) {
2175 ath9k_hw_loadnf(ah, ah->ah_curchan);
2176 ath9k_hw_start_nfcal(ah);
2177 return true;
2178 }
2179 }
2180
2181 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2182 if (saveDefAntenna == 0)
2183 saveDefAntenna = 1;
2184
2185 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2186
2187 saveLedState = REG_READ(ah, AR_CFG_LED) &
2188 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2189 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2190
2191 ath9k_hw_mark_phy_inactive(ah);
2192
2193 if (!ath9k_hw_chip_reset(ah, chan)) {
2194 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n",
2195 __func__);
2196 ecode = -EINVAL;
2197 goto bad;
2198 }
2199
2200 if (AR_SREV_9280(ah)) {
2201 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2202 AR_GPIO_JTAG_DISABLE);
2203
2204 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2205 if (IS_CHAN_5GHZ(chan))
2206 ath9k_hw_set_gpio(ah, 9, 0);
2207 else
2208 ath9k_hw_set_gpio(ah, 9, 1);
2209 }
2210 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2211 }
2212
2213 ecode = ath9k_hw_process_ini(ah, chan, macmode);
2214 if (ecode != 0) {
2215 ecode = -EINVAL;
2216 goto bad;
2217 }
2218
2219 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2220 ath9k_hw_set_delta_slope(ah, chan);
2221
2222 if (AR_SREV_9280_10_OR_LATER(ah))
2223 ath9k_hw_9280_spur_mitigate(ah, chan);
2224 else
2225 ath9k_hw_spur_mitigate(ah, chan);
2226
2227 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2228 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2229 "%s: error setting board options\n", __func__);
2230 ecode = -EIO;
2231 goto bad;
2232 }
2233
2234 ath9k_hw_decrease_chain_power(ah, chan);
2235
2236 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2237 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2238 | macStaId1
2239 | AR_STA_ID1_RTS_USE_DEF
2240 | (ah->ah_config.
2241 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2242 | ahp->ah_staId1Defaults);
2243 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2244
2245 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2246 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2247
2248 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2249
2250 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2251 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2252 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2253
2254 REG_WRITE(ah, AR_ISR, ~0);
2255
2256 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2257
2258 if (AR_SREV_9280_10_OR_LATER(ah)) {
2259 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
2260 ecode = -EIO;
2261 goto bad;
2262 }
2263 } else {
2264 if (!(ath9k_hw_set_channel(ah, chan))) {
2265 ecode = -EIO;
2266 goto bad;
2267 }
2268 }
2269
2270 for (i = 0; i < AR_NUM_DCU; i++)
2271 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2272
2273 ahp->ah_intrTxqs = 0;
2274 for (i = 0; i < ah->ah_caps.total_queues; i++)
2275 ath9k_hw_resettxqueue(ah, i);
2276
2277 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2278 ath9k_hw_init_qos(ah);
2279
2280 #ifdef CONFIG_RFKILL
2281 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2282 ath9k_enable_rfkill(ah);
2283 #endif
2284 ath9k_hw_init_user_settings(ah);
2285
2286 REG_WRITE(ah, AR_STA_ID1,
2287 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2288
2289 ath9k_hw_set_dma(ah);
2290
2291 REG_WRITE(ah, AR_OBS, 8);
2292
2293 if (ahp->ah_intrMitigation) {
2294
2295 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2296 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2297 }
2298
2299 ath9k_hw_init_bb(ah, chan);
2300
2301 if (!ath9k_hw_init_cal(ah, chan)){
2302 ecode = -EIO;;
2303 goto bad;
2304 }
2305
2306 rx_chainmask = ahp->ah_rxchainmask;
2307 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2308 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2309 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2310 }
2311
2312 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2313
2314 if (AR_SREV_9100(ah)) {
2315 u32 mask;
2316 mask = REG_READ(ah, AR_CFG);
2317 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2318 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2319 "%s CFG Byte Swap Set 0x%x\n", __func__,
2320 mask);
2321 } else {
2322 mask =
2323 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2324 REG_WRITE(ah, AR_CFG, mask);
2325 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2326 "%s Setting CFG 0x%x\n", __func__,
2327 REG_READ(ah, AR_CFG));
2328 }
2329 } else {
2330 #ifdef __BIG_ENDIAN
2331 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2332 #endif
2333 }
2334
2335 return true;
2336 bad:
2337 if (status)
2338 *status = ecode;
2339 return false;
2340 }
2341
2342 /************************/
2343 /* Key Cache Management */
2344 /************************/
2345
2346 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2347 {
2348 u32 keyType;
2349
2350 if (entry >= ah->ah_caps.keycache_size) {
2351 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2352 "%s: entry %u out of range\n", __func__, entry);
2353 return false;
2354 }
2355
2356 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2357
2358 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2359 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2360 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2361 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2362 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2363 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2364 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2365 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2366
2367 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2368 u16 micentry = entry + 64;
2369
2370 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2371 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2372 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2373 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2374
2375 }
2376
2377 if (ah->ah_curchan == NULL)
2378 return true;
2379
2380 return true;
2381 }
2382
2383 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2384 {
2385 u32 macHi, macLo;
2386
2387 if (entry >= ah->ah_caps.keycache_size) {
2388 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2389 "%s: entry %u out of range\n", __func__, entry);
2390 return false;
2391 }
2392
2393 if (mac != NULL) {
2394 macHi = (mac[5] << 8) | mac[4];
2395 macLo = (mac[3] << 24) |
2396 (mac[2] << 16) |
2397 (mac[1] << 8) |
2398 mac[0];
2399 macLo >>= 1;
2400 macLo |= (macHi & 1) << 31;
2401 macHi >>= 1;
2402 } else {
2403 macLo = macHi = 0;
2404 }
2405 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2406 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2407
2408 return true;
2409 }
2410
2411 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2412 const struct ath9k_keyval *k,
2413 const u8 *mac, int xorKey)
2414 {
2415 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2416 u32 key0, key1, key2, key3, key4;
2417 u32 keyType;
2418 u32 xorMask = xorKey ?
2419 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2420 | ATH9K_KEY_XOR) : 0;
2421 struct ath_hal_5416 *ahp = AH5416(ah);
2422
2423 if (entry >= pCap->keycache_size) {
2424 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2425 "%s: entry %u out of range\n", __func__, entry);
2426 return false;
2427 }
2428
2429 switch (k->kv_type) {
2430 case ATH9K_CIPHER_AES_OCB:
2431 keyType = AR_KEYTABLE_TYPE_AES;
2432 break;
2433 case ATH9K_CIPHER_AES_CCM:
2434 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2435 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2436 "%s: AES-CCM not supported by "
2437 "mac rev 0x%x\n", __func__,
2438 ah->ah_macRev);
2439 return false;
2440 }
2441 keyType = AR_KEYTABLE_TYPE_CCM;
2442 break;
2443 case ATH9K_CIPHER_TKIP:
2444 keyType = AR_KEYTABLE_TYPE_TKIP;
2445 if (ATH9K_IS_MIC_ENABLED(ah)
2446 && entry + 64 >= pCap->keycache_size) {
2447 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2448 "%s: entry %u inappropriate for TKIP\n",
2449 __func__, entry);
2450 return false;
2451 }
2452 break;
2453 case ATH9K_CIPHER_WEP:
2454 if (k->kv_len < LEN_WEP40) {
2455 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2456 "%s: WEP key length %u too small\n",
2457 __func__, k->kv_len);
2458 return false;
2459 }
2460 if (k->kv_len <= LEN_WEP40)
2461 keyType = AR_KEYTABLE_TYPE_40;
2462 else if (k->kv_len <= LEN_WEP104)
2463 keyType = AR_KEYTABLE_TYPE_104;
2464 else
2465 keyType = AR_KEYTABLE_TYPE_128;
2466 break;
2467 case ATH9K_CIPHER_CLR:
2468 keyType = AR_KEYTABLE_TYPE_CLR;
2469 break;
2470 default:
2471 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2472 "%s: cipher %u not supported\n", __func__,
2473 k->kv_type);
2474 return false;
2475 }
2476
2477 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2478 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2479 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2480 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2481 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2482 if (k->kv_len <= LEN_WEP104)
2483 key4 &= 0xff;
2484
2485 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2486 u16 micentry = entry + 64;
2487
2488 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2489 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2490 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2491 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2492 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2493 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2494 (void) ath9k_hw_keysetmac(ah, entry, mac);
2495
2496 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2497 u32 mic0, mic1, mic2, mic3, mic4;
2498
2499 mic0 = get_unaligned_le32(k->kv_mic + 0);
2500 mic2 = get_unaligned_le32(k->kv_mic + 4);
2501 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2502 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2503 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2504 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2505 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2506 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2507 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2508 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2509 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2510 AR_KEYTABLE_TYPE_CLR);
2511
2512 } else {
2513 u32 mic0, mic2;
2514
2515 mic0 = get_unaligned_le32(k->kv_mic + 0);
2516 mic2 = get_unaligned_le32(k->kv_mic + 4);
2517 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2518 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2519 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2520 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2521 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2522 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2523 AR_KEYTABLE_TYPE_CLR);
2524 }
2525 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2526 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2527 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2528 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2529 } else {
2530 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2531 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2532 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2533 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2534 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2535 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2536
2537 (void) ath9k_hw_keysetmac(ah, entry, mac);
2538 }
2539
2540 if (ah->ah_curchan == NULL)
2541 return true;
2542
2543 return true;
2544 }
2545
2546 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2547 {
2548 if (entry < ah->ah_caps.keycache_size) {
2549 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2550 if (val & AR_KEYTABLE_VALID)
2551 return true;
2552 }
2553 return false;
2554 }
2555
2556 /******************************/
2557 /* Power Management (Chipset) */
2558 /******************************/
2559
2560 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2561 {
2562 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2563 if (setChip) {
2564 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2565 AR_RTC_FORCE_WAKE_EN);
2566 if (!AR_SREV_9100(ah))
2567 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2568
2569 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2570 AR_RTC_RESET_EN);
2571 }
2572 }
2573
2574 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2575 {
2576 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577 if (setChip) {
2578 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2579
2580 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2581 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2582 AR_RTC_FORCE_WAKE_ON_INT);
2583 } else {
2584 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2585 AR_RTC_FORCE_WAKE_EN);
2586 }
2587 }
2588 }
2589
2590 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2591 int setChip)
2592 {
2593 u32 val;
2594 int i;
2595
2596 if (setChip) {
2597 if ((REG_READ(ah, AR_RTC_STATUS) &
2598 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2599 if (ath9k_hw_set_reset_reg(ah,
2600 ATH9K_RESET_POWER_ON) != true) {
2601 return false;
2602 }
2603 }
2604 if (AR_SREV_9100(ah))
2605 REG_SET_BIT(ah, AR_RTC_RESET,
2606 AR_RTC_RESET_EN);
2607
2608 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2609 AR_RTC_FORCE_WAKE_EN);
2610 udelay(50);
2611
2612 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2613 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2614 if (val == AR_RTC_STATUS_ON)
2615 break;
2616 udelay(50);
2617 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2618 AR_RTC_FORCE_WAKE_EN);
2619 }
2620 if (i == 0) {
2621 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2622 "%s: Failed to wakeup in %uus\n",
2623 __func__, POWER_UP_TIME / 20);
2624 return false;
2625 }
2626 }
2627
2628 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2629
2630 return true;
2631 }
2632
2633 bool ath9k_hw_setpower(struct ath_hal *ah,
2634 enum ath9k_power_mode mode)
2635 {
2636 struct ath_hal_5416 *ahp = AH5416(ah);
2637 static const char *modes[] = {
2638 "AWAKE",
2639 "FULL-SLEEP",
2640 "NETWORK SLEEP",
2641 "UNDEFINED"
2642 };
2643 int status = true, setChip = true;
2644
2645 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
2646 modes[ahp->ah_powerMode], modes[mode],
2647 setChip ? "set chip " : "");
2648
2649 switch (mode) {
2650 case ATH9K_PM_AWAKE:
2651 status = ath9k_hw_set_power_awake(ah, setChip);
2652 break;
2653 case ATH9K_PM_FULL_SLEEP:
2654 ath9k_set_power_sleep(ah, setChip);
2655 ahp->ah_chipFullSleep = true;
2656 break;
2657 case ATH9K_PM_NETWORK_SLEEP:
2658 ath9k_set_power_network_sleep(ah, setChip);
2659 break;
2660 default:
2661 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2662 "%s: unknown power mode %u\n", __func__, mode);
2663 return false;
2664 }
2665 ahp->ah_powerMode = mode;
2666
2667 return status;
2668 }
2669
2670 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2671 {
2672 struct ath_hal_5416 *ahp = AH5416(ah);
2673 u8 i;
2674
2675 if (ah->ah_isPciExpress != true)
2676 return;
2677
2678 if (ah->ah_config.pcie_powersave_enable == 2)
2679 return;
2680
2681 if (restore)
2682 return;
2683
2684 if (AR_SREV_9280_20_OR_LATER(ah)) {
2685 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2686 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2687 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2688 }
2689 udelay(1000);
2690 } else if (AR_SREV_9280(ah) &&
2691 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2692 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2693 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2694
2695 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2696 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2697 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2698
2699 if (ah->ah_config.pcie_clock_req)
2700 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2701 else
2702 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2703
2704 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2705 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2706 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2707
2708 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2709
2710 udelay(1000);
2711 } else {
2712 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2713 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2714 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2715 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2716 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2717 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2718 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2719 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2720 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2721 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2722 }
2723
2724 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2725
2726 if (ah->ah_config.pcie_waen) {
2727 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2728 } else {
2729 if (AR_SREV_9280(ah))
2730 REG_WRITE(ah, AR_WA, 0x0040073f);
2731 else
2732 REG_WRITE(ah, AR_WA, 0x0000073f);
2733 }
2734 }
2735
2736 /**********************/
2737 /* Interrupt Handling */
2738 /**********************/
2739
2740 bool ath9k_hw_intrpend(struct ath_hal *ah)
2741 {
2742 u32 host_isr;
2743
2744 if (AR_SREV_9100(ah))
2745 return true;
2746
2747 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2748 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2749 return true;
2750
2751 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2752 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2753 && (host_isr != AR_INTR_SPURIOUS))
2754 return true;
2755
2756 return false;
2757 }
2758
2759 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2760 {
2761 u32 isr = 0;
2762 u32 mask2 = 0;
2763 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2764 u32 sync_cause = 0;
2765 bool fatal_int = false;
2766 struct ath_hal_5416 *ahp = AH5416(ah);
2767
2768 if (!AR_SREV_9100(ah)) {
2769 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2770 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2771 == AR_RTC_STATUS_ON) {
2772 isr = REG_READ(ah, AR_ISR);
2773 }
2774 }
2775
2776 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2777 AR_INTR_SYNC_DEFAULT;
2778
2779 *masked = 0;
2780
2781 if (!isr && !sync_cause)
2782 return false;
2783 } else {
2784 *masked = 0;
2785 isr = REG_READ(ah, AR_ISR);
2786 }
2787
2788 if (isr) {
2789 if (isr & AR_ISR_BCNMISC) {
2790 u32 isr2;
2791 isr2 = REG_READ(ah, AR_ISR_S2);
2792 if (isr2 & AR_ISR_S2_TIM)
2793 mask2 |= ATH9K_INT_TIM;
2794 if (isr2 & AR_ISR_S2_DTIM)
2795 mask2 |= ATH9K_INT_DTIM;
2796 if (isr2 & AR_ISR_S2_DTIMSYNC)
2797 mask2 |= ATH9K_INT_DTIMSYNC;
2798 if (isr2 & (AR_ISR_S2_CABEND))
2799 mask2 |= ATH9K_INT_CABEND;
2800 if (isr2 & AR_ISR_S2_GTT)
2801 mask2 |= ATH9K_INT_GTT;
2802 if (isr2 & AR_ISR_S2_CST)
2803 mask2 |= ATH9K_INT_CST;
2804 }
2805
2806 isr = REG_READ(ah, AR_ISR_RAC);
2807 if (isr == 0xffffffff) {
2808 *masked = 0;
2809 return false;
2810 }
2811
2812 *masked = isr & ATH9K_INT_COMMON;
2813
2814 if (ahp->ah_intrMitigation) {
2815 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2816 *masked |= ATH9K_INT_RX;
2817 }
2818
2819 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2820 *masked |= ATH9K_INT_RX;
2821 if (isr &
2822 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2823 AR_ISR_TXEOL)) {
2824 u32 s0_s, s1_s;
2825
2826 *masked |= ATH9K_INT_TX;
2827
2828 s0_s = REG_READ(ah, AR_ISR_S0_S);
2829 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2830 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2831
2832 s1_s = REG_READ(ah, AR_ISR_S1_S);
2833 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2834 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2835 }
2836
2837 if (isr & AR_ISR_RXORN) {
2838 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2839 "%s: receive FIFO overrun interrupt\n",
2840 __func__);
2841 }
2842
2843 if (!AR_SREV_9100(ah)) {
2844 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2845 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2846 if (isr5 & AR_ISR_S5_TIM_TIMER)
2847 *masked |= ATH9K_INT_TIM_TIMER;
2848 }
2849 }
2850
2851 *masked |= mask2;
2852 }
2853
2854 if (AR_SREV_9100(ah))
2855 return true;
2856
2857 if (sync_cause) {
2858 fatal_int =
2859 (sync_cause &
2860 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2861 ? true : false;
2862
2863 if (fatal_int) {
2864 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2865 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2866 "%s: received PCI FATAL interrupt\n",
2867 __func__);
2868 }
2869 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2870 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2871 "%s: received PCI PERR interrupt\n",
2872 __func__);
2873 }
2874 }
2875 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2876 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2877 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
2878 __func__);
2879 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2880 REG_WRITE(ah, AR_RC, 0);
2881 *masked |= ATH9K_INT_FATAL;
2882 }
2883 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2884 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2885 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
2886 __func__);
2887 }
2888
2889 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2890 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2891 }
2892
2893 return true;
2894 }
2895
2896 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2897 {
2898 return AH5416(ah)->ah_maskReg;
2899 }
2900
2901 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2902 {
2903 struct ath_hal_5416 *ahp = AH5416(ah);
2904 u32 omask = ahp->ah_maskReg;
2905 u32 mask, mask2;
2906 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2907
2908 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
2909 omask, ints);
2910
2911 if (omask & ATH9K_INT_GLOBAL) {
2912 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n",
2913 __func__);
2914 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2915 (void) REG_READ(ah, AR_IER);
2916 if (!AR_SREV_9100(ah)) {
2917 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2918 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2919
2920 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2921 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2922 }
2923 }
2924
2925 mask = ints & ATH9K_INT_COMMON;
2926 mask2 = 0;
2927
2928 if (ints & ATH9K_INT_TX) {
2929 if (ahp->ah_txOkInterruptMask)
2930 mask |= AR_IMR_TXOK;
2931 if (ahp->ah_txDescInterruptMask)
2932 mask |= AR_IMR_TXDESC;
2933 if (ahp->ah_txErrInterruptMask)
2934 mask |= AR_IMR_TXERR;
2935 if (ahp->ah_txEolInterruptMask)
2936 mask |= AR_IMR_TXEOL;
2937 }
2938 if (ints & ATH9K_INT_RX) {
2939 mask |= AR_IMR_RXERR;
2940 if (ahp->ah_intrMitigation)
2941 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2942 else
2943 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2944 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2945 mask |= AR_IMR_GENTMR;
2946 }
2947
2948 if (ints & (ATH9K_INT_BMISC)) {
2949 mask |= AR_IMR_BCNMISC;
2950 if (ints & ATH9K_INT_TIM)
2951 mask2 |= AR_IMR_S2_TIM;
2952 if (ints & ATH9K_INT_DTIM)
2953 mask2 |= AR_IMR_S2_DTIM;
2954 if (ints & ATH9K_INT_DTIMSYNC)
2955 mask2 |= AR_IMR_S2_DTIMSYNC;
2956 if (ints & ATH9K_INT_CABEND)
2957 mask2 |= (AR_IMR_S2_CABEND);
2958 }
2959
2960 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2961 mask |= AR_IMR_BCNMISC;
2962 if (ints & ATH9K_INT_GTT)
2963 mask2 |= AR_IMR_S2_GTT;
2964 if (ints & ATH9K_INT_CST)
2965 mask2 |= AR_IMR_S2_CST;
2966 }
2967
2968 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__,
2969 mask);
2970 REG_WRITE(ah, AR_IMR, mask);
2971 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2972 AR_IMR_S2_DTIM |
2973 AR_IMR_S2_DTIMSYNC |
2974 AR_IMR_S2_CABEND |
2975 AR_IMR_S2_CABTO |
2976 AR_IMR_S2_TSFOOR |
2977 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2978 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2979 ahp->ah_maskReg = ints;
2980
2981 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2982 if (ints & ATH9K_INT_TIM_TIMER)
2983 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2984 else
2985 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2986 }
2987
2988 if (ints & ATH9K_INT_GLOBAL) {
2989 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n",
2990 __func__);
2991 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2992 if (!AR_SREV_9100(ah)) {
2993 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2994 AR_INTR_MAC_IRQ);
2995 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2996
2997
2998 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2999 AR_INTR_SYNC_DEFAULT);
3000 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3001 AR_INTR_SYNC_DEFAULT);
3002 }
3003 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3004 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3005 }
3006
3007 return omask;
3008 }
3009
3010 /*******************/
3011 /* Beacon Handling */
3012 /*******************/
3013
3014 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3015 {
3016 struct ath_hal_5416 *ahp = AH5416(ah);
3017 int flags = 0;
3018
3019 ahp->ah_beaconInterval = beacon_period;
3020
3021 switch (ah->ah_opmode) {
3022 case ATH9K_M_STA:
3023 case ATH9K_M_MONITOR:
3024 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3025 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3026 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3027 flags |= AR_TBTT_TIMER_EN;
3028 break;
3029 case ATH9K_M_IBSS:
3030 REG_SET_BIT(ah, AR_TXCFG,
3031 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3032 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3033 TU_TO_USEC(next_beacon +
3034 (ahp->ah_atimWindow ? ahp->
3035 ah_atimWindow : 1)));
3036 flags |= AR_NDP_TIMER_EN;
3037 case ATH9K_M_HOSTAP:
3038 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3039 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3040 TU_TO_USEC(next_beacon -
3041 ah->ah_config.
3042 dma_beacon_response_time));
3043 REG_WRITE(ah, AR_NEXT_SWBA,
3044 TU_TO_USEC(next_beacon -
3045 ah->ah_config.
3046 sw_beacon_response_time));
3047 flags |=
3048 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3049 break;
3050 }
3051
3052 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3053 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3054 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3055 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3056
3057 beacon_period &= ~ATH9K_BEACON_ENA;
3058 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3059 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3060 ath9k_hw_reset_tsf(ah);
3061 }
3062
3063 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3064 }
3065
3066 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3067 const struct ath9k_beacon_state *bs)
3068 {
3069 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3070 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3071
3072 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3073
3074 REG_WRITE(ah, AR_BEACON_PERIOD,
3075 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3076 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3077 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3078
3079 REG_RMW_FIELD(ah, AR_RSSI_THR,
3080 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3081
3082 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3083
3084 if (bs->bs_sleepduration > beaconintval)
3085 beaconintval = bs->bs_sleepduration;
3086
3087 dtimperiod = bs->bs_dtimperiod;
3088 if (bs->bs_sleepduration > dtimperiod)
3089 dtimperiod = bs->bs_sleepduration;
3090
3091 if (beaconintval == dtimperiod)
3092 nextTbtt = bs->bs_nextdtim;
3093 else
3094 nextTbtt = bs->bs_nexttbtt;
3095
3096 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__,
3097 bs->bs_nextdtim);
3098 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__,
3099 nextTbtt);
3100 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__,
3101 beaconintval);
3102 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__,
3103 dtimperiod);
3104
3105 REG_WRITE(ah, AR_NEXT_DTIM,
3106 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3107 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3108
3109 REG_WRITE(ah, AR_SLEEP1,
3110 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3111 | AR_SLEEP1_ASSUME_DTIM);
3112
3113 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3114 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3115 else
3116 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3117
3118 REG_WRITE(ah, AR_SLEEP2,
3119 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3120
3121 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3122 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3123
3124 REG_SET_BIT(ah, AR_TIMER_MODE,
3125 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3126 AR_DTIM_TIMER_EN);
3127
3128 }
3129
3130 /***************/
3131 /* Rate tables */
3132 /***************/
3133
3134 static struct ath9k_rate_table ar5416_11a_table = {
3135 8,
3136 {0},
3137 {
3138 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
3139 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
3140 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
3141 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
3142 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
3143 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
3144 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
3145 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
3146 },
3147 };
3148
3149 static struct ath9k_rate_table ar5416_11b_table = {
3150 4,
3151 {0},
3152 {
3153 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
3154 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
3155 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
3156 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
3157 },
3158 };
3159
3160 static struct ath9k_rate_table ar5416_11g_table = {
3161 12,
3162 {0},
3163 {
3164 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
3165 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
3166 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
3167 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
3168
3169 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
3170 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
3171 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
3172 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
3173 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
3174 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
3175 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
3176 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
3177 },
3178 };
3179
3180 static struct ath9k_rate_table ar5416_11ng_table = {
3181 28,
3182 {0},
3183 {
3184 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
3185 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
3186 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
3187 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
3188
3189 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
3190 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
3191 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
3192 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
3193 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
3194 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
3195 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
3196 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
3197 {true, PHY_HT, 6500, 0x80, 0x00, 0, 4},
3198 {true, PHY_HT, 13000, 0x81, 0x00, 1, 6},
3199 {true, PHY_HT, 19500, 0x82, 0x00, 2, 6},
3200 {true, PHY_HT, 26000, 0x83, 0x00, 3, 8},
3201 {true, PHY_HT, 39000, 0x84, 0x00, 4, 8},
3202 {true, PHY_HT, 52000, 0x85, 0x00, 5, 8},
3203 {true, PHY_HT, 58500, 0x86, 0x00, 6, 8},
3204 {true, PHY_HT, 65000, 0x87, 0x00, 7, 8},
3205 {true, PHY_HT, 13000, 0x88, 0x00, 8, 4},
3206 {true, PHY_HT, 26000, 0x89, 0x00, 9, 6},
3207 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
3208 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
3209 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
3210 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
3211 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
3212 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
3213 },
3214 };
3215
3216 static struct ath9k_rate_table ar5416_11na_table = {
3217 24,
3218 {0},
3219 {
3220 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
3221 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
3222 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
3223 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
3224 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
3225 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
3226 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
3227 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
3228 {true, PHY_HT, 6500, 0x80, 0x00, 0, 0},
3229 {true, PHY_HT, 13000, 0x81, 0x00, 1, 2},
3230 {true, PHY_HT, 19500, 0x82, 0x00, 2, 2},
3231 {true, PHY_HT, 26000, 0x83, 0x00, 3, 4},
3232 {true, PHY_HT, 39000, 0x84, 0x00, 4, 4},
3233 {true, PHY_HT, 52000, 0x85, 0x00, 5, 4},
3234 {true, PHY_HT, 58500, 0x86, 0x00, 6, 4},
3235 {true, PHY_HT, 65000, 0x87, 0x00, 7, 4},
3236 {true, PHY_HT, 13000, 0x88, 0x00, 8, 0},
3237 {true, PHY_HT, 26000, 0x89, 0x00, 9, 2},
3238 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
3239 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
3240 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
3241 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
3242 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
3243 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
3244 },
3245 };
3246
3247 static void ath9k_hw_setup_rate_table(struct ath_hal *ah,
3248 struct ath9k_rate_table *rt)
3249 {
3250 int i;
3251
3252 if (rt->rateCodeToIndex[0] != 0)
3253 return;
3254
3255 for (i = 0; i < 256; i++)
3256 rt->rateCodeToIndex[i] = (u8) -1;
3257
3258 for (i = 0; i < rt->rateCount; i++) {
3259 u8 code = rt->info[i].rateCode;
3260 u8 cix = rt->info[i].controlRate;
3261
3262 rt->rateCodeToIndex[code] = i;
3263 rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
3264
3265 rt->info[i].lpAckDuration =
3266 ath9k_hw_computetxtime(ah, rt,
3267 WLAN_CTRL_FRAME_SIZE,
3268 cix,
3269 false);
3270 rt->info[i].spAckDuration =
3271 ath9k_hw_computetxtime(ah, rt,
3272 WLAN_CTRL_FRAME_SIZE,
3273 cix,
3274 true);
3275 }
3276 }
3277
3278 const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
3279 u32 mode)
3280 {
3281 struct ath9k_rate_table *rt;
3282
3283 switch (mode) {
3284 case ATH9K_MODE_11A:
3285 rt = &ar5416_11a_table;
3286 break;
3287 case ATH9K_MODE_11B:
3288 rt = &ar5416_11b_table;
3289 break;
3290 case ATH9K_MODE_11G:
3291 rt = &ar5416_11g_table;
3292 break;
3293 case ATH9K_MODE_11NG_HT20:
3294 case ATH9K_MODE_11NG_HT40PLUS:
3295 case ATH9K_MODE_11NG_HT40MINUS:
3296 rt = &ar5416_11ng_table;
3297 break;
3298 case ATH9K_MODE_11NA_HT20:
3299 case ATH9K_MODE_11NA_HT40PLUS:
3300 case ATH9K_MODE_11NA_HT40MINUS:
3301 rt = &ar5416_11na_table;
3302 break;
3303 default:
3304 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
3305 __func__, mode);
3306 return NULL;
3307 }
3308
3309 ath9k_hw_setup_rate_table(ah, rt);
3310
3311 return rt;
3312 }
3313
3314 /*******************/
3315 /* HW Capabilities */
3316 /*******************/
3317
3318 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3319 {
3320 struct ath_hal_5416 *ahp = AH5416(ah);
3321 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3322 u16 capField = 0, eeval;
3323
3324 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3325
3326 ah->ah_currentRD = eeval;
3327
3328 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3329 ah->ah_currentRDExt = eeval;
3330
3331 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3332
3333 if (ah->ah_opmode != ATH9K_M_HOSTAP &&
3334 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3335 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3336 ah->ah_currentRD += 5;
3337 else if (ah->ah_currentRD == 0x41)
3338 ah->ah_currentRD = 0x43;
3339 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3340 "%s: regdomain mapped to 0x%x\n", __func__,
3341 ah->ah_currentRD);
3342 }
3343
3344 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3345 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3346
3347 if (eeval & AR5416_OPFLAGS_11A) {
3348 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3349 if (ah->ah_config.ht_enable) {
3350 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3351 set_bit(ATH9K_MODE_11NA_HT20,
3352 pCap->wireless_modes);
3353 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3354 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3355 pCap->wireless_modes);
3356 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3357 pCap->wireless_modes);
3358 }
3359 }
3360 }
3361
3362 if (eeval & AR5416_OPFLAGS_11G) {
3363 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3364 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3365 if (ah->ah_config.ht_enable) {
3366 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3367 set_bit(ATH9K_MODE_11NG_HT20,
3368 pCap->wireless_modes);
3369 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3370 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3371 pCap->wireless_modes);
3372 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3373 pCap->wireless_modes);
3374 }
3375 }
3376 }
3377
3378 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3379 if ((ah->ah_isPciExpress)
3380 || (eeval & AR5416_OPFLAGS_11A)) {
3381 pCap->rx_chainmask =
3382 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3383 } else {
3384 pCap->rx_chainmask =
3385 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3386 }
3387
3388 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3389 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3390
3391 pCap->low_2ghz_chan = 2312;
3392 pCap->high_2ghz_chan = 2732;
3393
3394 pCap->low_5ghz_chan = 4920;
3395 pCap->high_5ghz_chan = 6100;
3396
3397 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3398 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3399 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3400
3401 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3402 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3403 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3404
3405 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3406
3407 if (ah->ah_config.ht_enable)
3408 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3409 else
3410 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3411
3412 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3413 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3414 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3415 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3416
3417 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3418 pCap->total_queues =
3419 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3420 else
3421 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3422
3423 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3424 pCap->keycache_size =
3425 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3426 else
3427 pCap->keycache_size = AR_KEYTABLE_SIZE;
3428
3429 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3430 pCap->num_mr_retries = 4;
3431 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3432
3433 if (AR_SREV_9280_10_OR_LATER(ah))
3434 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3435 else
3436 pCap->num_gpio_pins = AR_NUM_GPIO;
3437
3438 if (AR_SREV_9280_10_OR_LATER(ah)) {
3439 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3440 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3441 } else {
3442 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3443 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3444 }
3445
3446 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3447 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3448 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3449 } else {
3450 pCap->rts_aggr_limit = (8 * 1024);
3451 }
3452
3453 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3454
3455 #ifdef CONFIG_RFKILL
3456 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3457 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3458 ah->ah_rfkill_gpio =
3459 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3460 ah->ah_rfkill_polarity =
3461 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3462
3463 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3464 }
3465 #endif
3466
3467 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3468 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3469 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3470 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3471 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3472 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3473 else
3474 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3475
3476 if (AR_SREV_9280(ah))
3477 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3478 else
3479 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3480
3481 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3482 pCap->reg_cap =
3483 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3484 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3485 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3486 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3487 } else {
3488 pCap->reg_cap =
3489 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3490 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3491 }
3492
3493 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3494
3495 pCap->num_antcfg_5ghz =
3496 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_5GHZ);
3497 pCap->num_antcfg_2ghz =
3498 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_2GHZ);
3499
3500 return true;
3501 }
3502
3503 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3504 u32 capability, u32 *result)
3505 {
3506 struct ath_hal_5416 *ahp = AH5416(ah);
3507 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3508
3509 switch (type) {
3510 case ATH9K_CAP_CIPHER:
3511 switch (capability) {
3512 case ATH9K_CIPHER_AES_CCM:
3513 case ATH9K_CIPHER_AES_OCB:
3514 case ATH9K_CIPHER_TKIP:
3515 case ATH9K_CIPHER_WEP:
3516 case ATH9K_CIPHER_MIC:
3517 case ATH9K_CIPHER_CLR:
3518 return true;
3519 default:
3520 return false;
3521 }
3522 case ATH9K_CAP_TKIP_MIC:
3523 switch (capability) {
3524 case 0:
3525 return true;
3526 case 1:
3527 return (ahp->ah_staId1Defaults &
3528 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3529 false;
3530 }
3531 case ATH9K_CAP_TKIP_SPLIT:
3532 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3533 false : true;
3534 case ATH9K_CAP_WME_TKIPMIC:
3535 return 0;
3536 case ATH9K_CAP_PHYCOUNTERS:
3537 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3538 case ATH9K_CAP_DIVERSITY:
3539 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3540 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3541 true : false;
3542 case ATH9K_CAP_PHYDIAG:
3543 return true;
3544 case ATH9K_CAP_MCAST_KEYSRCH:
3545 switch (capability) {
3546 case 0:
3547 return true;
3548 case 1:
3549 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3550 return false;
3551 } else {
3552 return (ahp->ah_staId1Defaults &
3553 AR_STA_ID1_MCAST_KSRCH) ? true :
3554 false;
3555 }
3556 }
3557 return false;
3558 case ATH9K_CAP_TSF_ADJUST:
3559 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3560 true : false;
3561 case ATH9K_CAP_RFSILENT:
3562 if (capability == 3)
3563 return false;
3564 case ATH9K_CAP_ANT_CFG_2GHZ:
3565 *result = pCap->num_antcfg_2ghz;
3566 return true;
3567 case ATH9K_CAP_ANT_CFG_5GHZ:
3568 *result = pCap->num_antcfg_5ghz;
3569 return true;
3570 case ATH9K_CAP_TXPOW:
3571 switch (capability) {
3572 case 0:
3573 return 0;
3574 case 1:
3575 *result = ah->ah_powerLimit;
3576 return 0;
3577 case 2:
3578 *result = ah->ah_maxPowerLevel;
3579 return 0;
3580 case 3:
3581 *result = ah->ah_tpScale;
3582 return 0;
3583 }
3584 return false;
3585 default:
3586 return false;
3587 }
3588 }
3589
3590 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3591 u32 capability, u32 setting, int *status)
3592 {
3593 struct ath_hal_5416 *ahp = AH5416(ah);
3594 u32 v;
3595
3596 switch (type) {
3597 case ATH9K_CAP_TKIP_MIC:
3598 if (setting)
3599 ahp->ah_staId1Defaults |=
3600 AR_STA_ID1_CRPT_MIC_ENABLE;
3601 else
3602 ahp->ah_staId1Defaults &=
3603 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3604 return true;
3605 case ATH9K_CAP_DIVERSITY:
3606 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3607 if (setting)
3608 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3609 else
3610 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3611 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3612 return true;
3613 case ATH9K_CAP_MCAST_KEYSRCH:
3614 if (setting)
3615 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3616 else
3617 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3618 return true;
3619 case ATH9K_CAP_TSF_ADJUST:
3620 if (setting)
3621 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3622 else
3623 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3624 return true;
3625 default:
3626 return false;
3627 }
3628 }
3629
3630 /****************************/
3631 /* GPIO / RFKILL / Antennae */
3632 /****************************/
3633
3634 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3635 u32 gpio, u32 type)
3636 {
3637 int addr;
3638 u32 gpio_shift, tmp;
3639
3640 if (gpio > 11)
3641 addr = AR_GPIO_OUTPUT_MUX3;
3642 else if (gpio > 5)
3643 addr = AR_GPIO_OUTPUT_MUX2;
3644 else
3645 addr = AR_GPIO_OUTPUT_MUX1;
3646
3647 gpio_shift = (gpio % 6) * 5;
3648
3649 if (AR_SREV_9280_20_OR_LATER(ah)
3650 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3651 REG_RMW(ah, addr, (type << gpio_shift),
3652 (0x1f << gpio_shift));
3653 } else {
3654 tmp = REG_READ(ah, addr);
3655 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3656 tmp &= ~(0x1f << gpio_shift);
3657 tmp |= (type << gpio_shift);
3658 REG_WRITE(ah, addr, tmp);
3659 }
3660 }
3661
3662 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3663 {
3664 u32 gpio_shift;
3665
3666 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3667
3668 gpio_shift = gpio << 1;
3669
3670 REG_RMW(ah,
3671 AR_GPIO_OE_OUT,
3672 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3673 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3674 }
3675
3676 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3677 {
3678 if (gpio >= ah->ah_caps.num_gpio_pins)
3679 return 0xffffffff;
3680
3681 if (AR_SREV_9280_10_OR_LATER(ah)) {
3682 return (MS
3683 (REG_READ(ah, AR_GPIO_IN_OUT),
3684 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
3685 } else {
3686 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
3687 AR_GPIO_BIT(gpio)) != 0;
3688 }
3689 }
3690
3691 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3692 u32 ah_signal_type)
3693 {
3694 u32 gpio_shift;
3695
3696 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3697
3698 gpio_shift = 2 * gpio;
3699
3700 REG_RMW(ah,
3701 AR_GPIO_OE_OUT,
3702 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3703 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3704 }
3705
3706 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3707 {
3708 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3709 AR_GPIO_BIT(gpio));
3710 }
3711
3712 #ifdef CONFIG_RFKILL
3713 void ath9k_enable_rfkill(struct ath_hal *ah)
3714 {
3715 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3716 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3717
3718 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3719 AR_GPIO_INPUT_MUX2_RFSILENT);
3720
3721 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3722 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3723 }
3724 #endif
3725
3726 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
3727 {
3728 struct ath9k_channel *chan = ah->ah_curchan;
3729 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3730 u16 ant_config;
3731 u32 halNumAntConfig;
3732
3733 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3734 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3735
3736 if (cfg < halNumAntConfig) {
3737 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3738 cfg, &ant_config)) {
3739 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3740 return 0;
3741 }
3742 }
3743
3744 return -EINVAL;
3745 }
3746
3747 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3748 {
3749 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3750 }
3751
3752 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3753 {
3754 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3755 }
3756
3757 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3758 enum ath9k_ant_setting settings,
3759 struct ath9k_channel *chan,
3760 u8 *tx_chainmask,
3761 u8 *rx_chainmask,
3762 u8 *antenna_cfgd)
3763 {
3764 struct ath_hal_5416 *ahp = AH5416(ah);
3765 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3766
3767 if (AR_SREV_9280(ah)) {
3768 if (!tx_chainmask_cfg) {
3769
3770 tx_chainmask_cfg = *tx_chainmask;
3771 rx_chainmask_cfg = *rx_chainmask;
3772 }
3773
3774 switch (settings) {
3775 case ATH9K_ANT_FIXED_A:
3776 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3777 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3778 *antenna_cfgd = true;
3779 break;
3780 case ATH9K_ANT_FIXED_B:
3781 if (ah->ah_caps.tx_chainmask >
3782 ATH9K_ANTENNA1_CHAINMASK) {
3783 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3784 }
3785 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3786 *antenna_cfgd = true;
3787 break;
3788 case ATH9K_ANT_VARIABLE:
3789 *tx_chainmask = tx_chainmask_cfg;
3790 *rx_chainmask = rx_chainmask_cfg;
3791 *antenna_cfgd = true;
3792 break;
3793 default:
3794 break;
3795 }
3796 } else {
3797 ahp->ah_diversityControl = settings;
3798 }
3799
3800 return true;
3801 }
3802
3803 /*********************/
3804 /* General Operation */
3805 /*********************/
3806
3807 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3808 {
3809 u32 bits = REG_READ(ah, AR_RX_FILTER);
3810 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3811
3812 if (phybits & AR_PHY_ERR_RADAR)
3813 bits |= ATH9K_RX_FILTER_PHYRADAR;
3814 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3815 bits |= ATH9K_RX_FILTER_PHYERR;
3816
3817 return bits;
3818 }
3819
3820 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3821 {
3822 u32 phybits;
3823
3824 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3825 phybits = 0;
3826 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3827 phybits |= AR_PHY_ERR_RADAR;
3828 if (bits & ATH9K_RX_FILTER_PHYERR)
3829 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3830 REG_WRITE(ah, AR_PHY_ERR, phybits);
3831
3832 if (phybits)
3833 REG_WRITE(ah, AR_RXCFG,
3834 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3835 else
3836 REG_WRITE(ah, AR_RXCFG,
3837 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3838 }
3839
3840 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3841 {
3842 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3843 }
3844
3845 bool ath9k_hw_disable(struct ath_hal *ah)
3846 {
3847 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3848 return false;
3849
3850 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3851 }
3852
3853 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3854 {
3855 struct ath9k_channel *chan = ah->ah_curchan;
3856
3857 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3858
3859 if (ath9k_hw_set_txpower(ah, chan,
3860 ath9k_regd_get_ctl(ah, chan),
3861 ath9k_regd_get_antenna_allowed(ah, chan),
3862 chan->maxRegTxPower * 2,
3863 min((u32) MAX_RATE_POWER,
3864 (u32) ah->ah_powerLimit)) != 0)
3865 return false;
3866
3867 return true;
3868 }
3869
3870 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3871 {
3872 struct ath_hal_5416 *ahp = AH5416(ah);
3873
3874 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3875 }
3876
3877 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3878 {
3879 struct ath_hal_5416 *ahp = AH5416(ah);
3880
3881 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3882
3883 return true;
3884 }
3885
3886 void ath9k_hw_setopmode(struct ath_hal *ah)
3887 {
3888 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3889 }
3890
3891 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3892 {
3893 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3894 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3895 }
3896
3897 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3898 {
3899 struct ath_hal_5416 *ahp = AH5416(ah);
3900
3901 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3902 }
3903
3904 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3905 {
3906 struct ath_hal_5416 *ahp = AH5416(ah);
3907
3908 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3909
3910 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3911 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3912
3913 return true;
3914 }
3915
3916 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3917 {
3918 struct ath_hal_5416 *ahp = AH5416(ah);
3919
3920 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3921 ahp->ah_assocId = assocId;
3922
3923 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3924 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3925 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3926 }
3927
3928 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3929 {
3930 u64 tsf;
3931
3932 tsf = REG_READ(ah, AR_TSF_U32);
3933 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3934
3935 return tsf;
3936 }
3937
3938 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3939 {
3940 int count;
3941
3942 count = 0;
3943 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3944 count++;
3945 if (count > 10) {
3946 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3947 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
3948 __func__);
3949 break;
3950 }
3951 udelay(10);
3952 }
3953 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3954 }
3955
3956 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3957 {
3958 struct ath_hal_5416 *ahp = AH5416(ah);
3959
3960 if (setting)
3961 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3962 else
3963 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3964
3965 return true;
3966 }
3967
3968 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3969 {
3970 struct ath_hal_5416 *ahp = AH5416(ah);
3971
3972 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3973 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
3974 __func__, us);
3975 ahp->ah_slottime = (u32) -1;
3976 return false;
3977 } else {
3978 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3979 ahp->ah_slottime = us;
3980 return true;
3981 }
3982 }
3983
3984 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3985 {
3986 u32 macmode;
3987
3988 if (mode == ATH9K_HT_MACMODE_2040 &&
3989 !ah->ah_config.cwm_ignore_extcca)
3990 macmode = AR_2040_JOINED_RX_CLEAR;
3991 else
3992 macmode = 0;
3993
3994 REG_WRITE(ah, AR_2040_MODE, macmode);
3995 }
(deprecated) Btrfs devel tree