1 /***************************************************************************
2 * Copyright (c) 2005-2009, Broadcom Corporation.
4 * Name: crystalhd_hw . h
7 * BCM70012 Linux driver hardware layer.
11 **********************************************************************
12 * This file is part of the crystalhd device driver.
14 * This driver is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation, version 2 of the License.
18 * This driver is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this driver. If not, see <http://www.gnu.org/licenses/>.
25 **********************************************************************/
27 #ifndef _CRYSTALHD_HW_H_
28 #define _CRYSTALHD_HW_H_
30 #include "crystalhd_misc.h"
31 #include "crystalhd_fw_if.h"
34 #define DMA_ENGINE_CNT 2
35 #define MAX_PIB_Q_DEPTH 64
36 #define MIN_PIB_Q_DEPTH 2
37 #define WR_POINTER_OFF 4
39 #define ASPM_L1_ENABLE (BC_BIT(27))
41 /*************************************************
42 7412 Decoder Registers.
43 **************************************************/
44 #define FW_CMD_BUFF_SZ 64
45 #define TS_Host2CpuSnd 0x00000100
46 #define Hst2CpuMbx1 0x00100F00
47 #define Cpu2HstMbx1 0x00100F04
48 #define MbxStat1 0x00100F08
49 #define Stream2Host_Intr_Sts 0x00100F24
50 #define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */
52 /* TS input status register */
53 #define TS_StreamAFIFOStatus 0x0010044C
54 #define TS_StreamBFIFOStatus 0x0010084C
56 /*UART Selection definitions*/
57 #define UartSelectA 0x00100300
58 #define UartSelectB 0x00100304
60 #define BSVS_UART_DEC_NONE 0x00
61 #define BSVS_UART_DEC_OUTER 0x01
62 #define BSVS_UART_DEC_INNER 0x02
63 #define BSVS_UART_STREAM 0x03
66 #define REG_DecCA_RegCinCTL 0xa00
67 #define REG_DecCA_RegCinBase 0xa0c
68 #define REG_DecCA_RegCinEnd 0xa10
69 #define REG_DecCA_RegCinWrPtr 0xa04
70 #define REG_DecCA_RegCinRdPtr 0xa08
72 #define REG_Dec_TsUser0Base 0x100864
73 #define REG_Dec_TsUser0Rdptr 0x100868
74 #define REG_Dec_TsUser0Wrptr 0x10086C
75 #define REG_Dec_TsUser0End 0x100874
78 #define REG_Dec_TsAudCDB2Base 0x10036c
79 #define REG_Dec_TsAudCDB2Rdptr 0x100378
80 #define REG_Dec_TsAudCDB2Wrptr 0x100374
81 #define REG_Dec_TsAudCDB2End 0x100370
83 /* DRAM bringup Registers */
84 #define SDRAM_PARAM 0x00040804
85 #define SDRAM_PRECHARGE 0x000408B0
86 #define SDRAM_EXT_MODE 0x000408A4
87 #define SDRAM_MODE 0x000408A0
88 #define SDRAM_REFRESH 0x00040890
89 #define SDRAM_REF_PARAM 0x00040808
91 #define DecHt_PllACtl 0x34000C
92 #define DecHt_PllBCtl 0x340010
93 #define DecHt_PllCCtl 0x340014
94 #define DecHt_PllDCtl 0x340034
95 #define DecHt_PllECtl 0x340038
96 #define AUD_DSP_MISC_SOFT_RESET 0x00240104
97 #define AIO_MISC_PLL_RESET 0x0026000C
98 #define PCIE_CLK_REQ_REG 0xDC
99 #define PCI_CLK_REQ_ENABLE (BC_BIT(8))
101 /*************************************************
102 F/W Copy engine definitions..
103 **************************************************/
104 #define BC_FWIMG_ST_ADDR 0x00000000
105 /* FIXME: jarod: there's a kernel function that'll do this for us... */
106 #define rotr32_1(x, n) (((x) >> n) | ((x) << (32 - n)))
107 #define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00))
109 #define DecHt_HostSwReset 0x340000
110 #define BC_DRAM_FW_CFG_ADDR 0x001c2000
112 typedef union _addr_64_
{
122 typedef union _intr_mask_reg_
{
124 uint32_t mask_tx_done
:1;
125 uint32_t mask_tx_err
:1;
126 uint32_t mask_rx_done
:1;
127 uint32_t mask_rx_err
:1;
128 uint32_t mask_pcie_err
:1;
129 uint32_t mask_pcie_rbusmast_err
:1;
130 uint32_t mask_pcie_rgr_bridge
:1;
131 uint32_t reserved
:25;
138 typedef union _link_misc_perst_deco_ctrl_
{
140 uint32_t bcm7412_rst
:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/
141 uint32_t reserved0
:3; /* Reserved.No Effect*/
142 uint32_t stop_bcm_7412_clk
:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/
143 uint32_t reserved1
:27; /* Reseved. No Effect*/
148 } link_misc_perst_deco_ctrl
;
150 typedef union _link_misc_perst_clk_ctrl_
{
152 uint32_t sel_alt_clk
:1; /* When set, selects a 6.75MHz clock as the source of core_clk */
153 uint32_t stop_core_clk
:1; /* When set, stops the branch of core_clk that is not needed for low power operation */
154 uint32_t pll_pwr_dn
:1; /* When set, powers down the main PLL. The alternate clock bit should be set
155 to select an alternate clock before setting this bit.*/
156 uint32_t reserved0
:5; /* Reserved */
157 uint32_t pll_mult
:8; /* This setting controls the multiplier for the PLL. */
158 uint32_t pll_div
:4; /* This setting controls the divider for the PLL. */
159 uint32_t reserved1
:12; /* Reserved */
164 } link_misc_perst_clk_ctrl
;
167 typedef union _link_misc_perst_decoder_ctrl_
{
169 uint32_t bcm_7412_rst
:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/
170 uint32_t res0
:3; /* Reserved.No Effect*/
171 uint32_t stop_7412_clk
:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/
172 uint32_t res1
:27; /* Reseved. No Effect */
177 } link_misc_perst_decoder_ctrl
;
180 typedef union _desc_low_addr_reg_
{
182 uint32_t list_valid
:1;
184 uint32_t low_addr
:27;
191 typedef struct _dma_descriptor_
{ /* 8 32-bit values */
193 uint32_t sdram_buff_addr
:28; /* bits 0-27: SDRAM Address */
194 uint32_t res0
:4; /* bits 28-31: Reserved */
197 uint32_t buff_addr_low
; /* 1 buffer address low */
198 uint32_t buff_addr_high
; /* 2 buffer address high */
201 uint32_t res2
:2; /* 0-1 - Reserved */
202 uint32_t xfer_size
:23; /* 2-24 = Xfer size in words */
203 uint32_t res3
:6; /* 25-30 reserved */
204 uint32_t intr_enable
:1; /* 31 - Interrupt After this desc */
207 uint32_t endian_xlat_align
:2; /* 0-1 Endian Translation */
208 uint32_t next_desc_cont
:1; /* 2 - Next desc is in contig memory */
209 uint32_t res4
:25; /* 3 - 27 Reserved bits */
210 uint32_t fill_bytes
:2; /* 28-29 Bits Fill Bytes */
211 uint32_t dma_dir
:1; /* 30 bit DMA Direction */
212 uint32_t last_rec_indicator
:1; /* 31 bit Last Record Indicator */
215 uint32_t next_desc_addr_low
; /* 32-bits Next Desc Addr lower */
218 uint32_t next_desc_addr_high
; /* 32-bits Next Desc Addr Higher */
221 uint32_t res8
; /* Last 32bits reserved */
223 } dma_descriptor
, *pdma_descriptor
;
226 * We will allocate the memory in 4K pages
227 * the linked list will be a list of 32 byte descriptors.
228 * The virtual address will determine what should be freed.
230 typedef struct _dma_desc_mem_
{
231 pdma_descriptor pdma_desc_start
; /* 32-bytes for dma descriptor. should be first element */
232 dma_addr_t phy_addr
; /* physical address of each DMA desc */
234 struct _dma_desc_mem_
*Next
; /* points to Next Descriptor in chain */
236 } dma_desc_mem
, *pdma_desc_mem
;
240 typedef enum _list_sts_
{
244 rx_waiting_y_intr
= 0x00000001,
245 rx_y_error
= 0x00000004,
247 /* RX-UV Bits 8:16 */
248 rx_waiting_uv_intr
= 0x0000100,
249 rx_uv_error
= 0x0000400,
251 rx_sts_waiting
= (rx_waiting_y_intr
|rx_waiting_uv_intr
),
252 rx_sts_error
= (rx_y_error
|rx_uv_error
),
254 rx_y_mask
= 0x000000FF,
255 rx_uv_mask
= 0x0000FF00,
259 typedef struct _tx_dma_pkt_
{
260 dma_desc_mem desc_mem
;
261 hw_comp_callback call_back
;
262 crystalhd_dio_req
*dio_req
;
263 wait_queue_head_t
*cb_event
;
268 typedef struct _crystalhd_rx_dma_pkt
{
269 dma_desc_mem desc_mem
;
270 crystalhd_dio_req
*dio_req
;
273 BC_PIC_INFO_BLOCK pib
;
274 dma_addr_t uv_phy_addr
;
275 struct _crystalhd_rx_dma_pkt
*next
;
277 } crystalhd_rx_dma_pkt
;
279 struct crystalhd_hw_stats
{
282 uint32_t freeq_count
;
284 uint32_t num_interrupts
;
285 uint32_t dev_interrupts
;
290 struct crystalhd_hw
{
291 tx_dma_pkt tx_pkt_pool
[DMA_ENGINE_CNT
];
294 uint32_t tx_ioq_tag_seed
;
295 uint32_t tx_list_post_index
;
297 crystalhd_rx_dma_pkt
*rx_pkt_pool_head
;
298 uint32_t rx_pkt_tag_seed
;
303 wait_queue_head_t
*pfw_cmd_event
;
306 uint32_t pib_del_Q_addr
;
307 uint32_t pib_rel_Q_addr
;
309 crystalhd_dioq_t
*tx_freeq
;
310 crystalhd_dioq_t
*tx_actq
;
312 /* Rx DMA Engine Specific Locks */
314 uint32_t rx_list_post_index
;
315 list_sts rx_list_sts
[DMA_ENGINE_CNT
];
316 crystalhd_dioq_t
*rx_rdyq
;
317 crystalhd_dioq_t
*rx_freeq
;
318 crystalhd_dioq_t
*rx_actq
;
319 uint32_t stop_pending
;
322 struct crystalhd_hw_stats stats
;
324 /* Core clock in MHz */
325 uint32_t core_clock_mhz
;
330 /* Clock defines for power control */
331 #define CLOCK_PRESET 175
333 /* DMA engine register BIT mask wrappers.. */
334 #define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK
336 #define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \
337 INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \
338 INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \
339 INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \
340 INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \
341 INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \
342 INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \
343 INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK)
345 #define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
346 MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \
347 MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \
348 MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)
350 #define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
351 MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \
352 MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \
353 MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)
355 #define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
356 MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \
357 MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \
358 MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)
360 #define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
361 MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \
362 MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \
363 MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)
366 /**** API Exposed to the other layers ****/
367 BC_STATUS
crystalhd_download_fw(struct crystalhd_adp
*adp
,
368 void *buffer
, uint32_t sz
);
369 BC_STATUS
crystalhd_do_fw_cmd(struct crystalhd_hw
*hw
, BC_FW_CMD
*fw_cmd
);
370 bool crystalhd_hw_interrupt(struct crystalhd_adp
*adp
, struct crystalhd_hw
*hw
);
371 BC_STATUS
crystalhd_hw_open(struct crystalhd_hw
*, struct crystalhd_adp
*);
372 BC_STATUS
crystalhd_hw_close(struct crystalhd_hw
*);
373 BC_STATUS
crystalhd_hw_setup_dma_rings(struct crystalhd_hw
*);
374 BC_STATUS
crystalhd_hw_free_dma_rings(struct crystalhd_hw
*);
377 BC_STATUS
crystalhd_hw_post_tx(struct crystalhd_hw
*hw
, crystalhd_dio_req
*ioreq
,
378 hw_comp_callback call_back
,
379 wait_queue_head_t
*cb_event
,
380 uint32_t *list_id
, uint8_t data_flags
);
382 BC_STATUS
crystalhd_hw_pause(struct crystalhd_hw
*hw
);
383 BC_STATUS
crystalhd_hw_unpause(struct crystalhd_hw
*hw
);
384 BC_STATUS
crystalhd_hw_suspend(struct crystalhd_hw
*hw
);
385 BC_STATUS
crystalhd_hw_cancel_tx(struct crystalhd_hw
*hw
, uint32_t list_id
);
386 BC_STATUS
crystalhd_hw_add_cap_buffer(struct crystalhd_hw
*hw
,
387 crystalhd_dio_req
*ioreq
, bool en_post
);
388 BC_STATUS
crystalhd_hw_get_cap_buffer(struct crystalhd_hw
*hw
,
389 BC_PIC_INFO_BLOCK
*pib
,
390 crystalhd_dio_req
**ioreq
);
391 BC_STATUS
crystalhd_hw_stop_capture(struct crystalhd_hw
*hw
);
392 BC_STATUS
crystalhd_hw_start_capture(struct crystalhd_hw
*hw
);
393 void crystalhd_hw_stats(struct crystalhd_hw
*hw
, struct crystalhd_hw_stats
*stats
);
395 /* API to program the core clock on the decoder */
396 BC_STATUS
crystalhd_hw_set_core_clock(struct crystalhd_hw
*);