2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Adjustable divider clock implementation
13 #include <linux/clk-provider.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
17 #include <linux/err.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
22 * DOC: basic adjustable divider clock that cannot gate
24 * Traits of this clock:
25 * prepare - clk_prepare only ensures that parents are prepared
26 * enable - clk_enable only ensures that parents are enabled
27 * rate - rate is adjustable. clk->rate = parent->rate / divisor
28 * parent - fixed parent. No clk_set_parent support
31 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
33 #define div_mask(d) ((1 << ((d)->width)) - 1)
35 static unsigned int _get_table_maxdiv(const struct clk_div_table
*table
)
37 unsigned int maxdiv
= 0;
38 const struct clk_div_table
*clkt
;
40 for (clkt
= table
; clkt
->div
; clkt
++)
41 if (clkt
->div
> maxdiv
)
46 static unsigned int _get_maxdiv(struct clk_divider
*divider
)
48 if (divider
->flags
& CLK_DIVIDER_ONE_BASED
)
49 return div_mask(divider
);
50 if (divider
->flags
& CLK_DIVIDER_POWER_OF_TWO
)
51 return 1 << div_mask(divider
);
53 return _get_table_maxdiv(divider
->table
);
54 return div_mask(divider
) + 1;
57 static unsigned int _get_table_div(const struct clk_div_table
*table
,
60 const struct clk_div_table
*clkt
;
62 for (clkt
= table
; clkt
->div
; clkt
++)
68 static unsigned int _get_div(struct clk_divider
*divider
, unsigned int val
)
70 if (divider
->flags
& CLK_DIVIDER_ONE_BASED
)
72 if (divider
->flags
& CLK_DIVIDER_POWER_OF_TWO
)
75 return _get_table_div(divider
->table
, val
);
79 static unsigned int _get_table_val(const struct clk_div_table
*table
,
82 const struct clk_div_table
*clkt
;
84 for (clkt
= table
; clkt
->div
; clkt
++)
90 static unsigned int _get_val(struct clk_divider
*divider
, u8 div
)
92 if (divider
->flags
& CLK_DIVIDER_ONE_BASED
)
94 if (divider
->flags
& CLK_DIVIDER_POWER_OF_TWO
)
97 return _get_table_val(divider
->table
, div
);
101 static unsigned long clk_divider_recalc_rate(struct clk_hw
*hw
,
102 unsigned long parent_rate
)
104 struct clk_divider
*divider
= to_clk_divider(hw
);
105 unsigned int div
, val
;
107 val
= readl(divider
->reg
) >> divider
->shift
;
108 val
&= div_mask(divider
);
110 div
= _get_div(divider
, val
);
112 WARN(1, "%s: Invalid divisor for clock %s\n", __func__
,
113 __clk_get_name(hw
->clk
));
117 return parent_rate
/ div
;
121 * The reverse of DIV_ROUND_UP: The maximum number which
124 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
126 static bool _is_valid_table_div(const struct clk_div_table
*table
,
129 const struct clk_div_table
*clkt
;
131 for (clkt
= table
; clkt
->div
; clkt
++)
132 if (clkt
->div
== div
)
137 static bool _is_valid_div(struct clk_divider
*divider
, unsigned int div
)
139 if (divider
->flags
& CLK_DIVIDER_POWER_OF_TWO
)
140 return is_power_of_2(div
);
142 return _is_valid_table_div(divider
->table
, div
);
146 static int clk_divider_bestdiv(struct clk_hw
*hw
, unsigned long rate
,
147 unsigned long *best_parent_rate
)
149 struct clk_divider
*divider
= to_clk_divider(hw
);
151 unsigned long parent_rate
, best
= 0, now
, maxdiv
;
156 maxdiv
= _get_maxdiv(divider
);
158 if (!(__clk_get_flags(hw
->clk
) & CLK_SET_RATE_PARENT
)) {
159 parent_rate
= *best_parent_rate
;
160 bestdiv
= DIV_ROUND_UP(parent_rate
, rate
);
161 bestdiv
= bestdiv
== 0 ? 1 : bestdiv
;
162 bestdiv
= bestdiv
> maxdiv
? maxdiv
: bestdiv
;
167 * The maximum divider we can use without overflowing
168 * unsigned long in rate * i below
170 maxdiv
= min(ULONG_MAX
/ rate
, maxdiv
);
172 for (i
= 1; i
<= maxdiv
; i
++) {
173 if (!_is_valid_div(divider
, i
))
175 parent_rate
= __clk_round_rate(__clk_get_parent(hw
->clk
),
176 MULT_ROUND_UP(rate
, i
));
177 now
= parent_rate
/ i
;
178 if (now
<= rate
&& now
> best
) {
181 *best_parent_rate
= parent_rate
;
186 bestdiv
= _get_maxdiv(divider
);
187 *best_parent_rate
= __clk_round_rate(__clk_get_parent(hw
->clk
), 1);
193 static long clk_divider_round_rate(struct clk_hw
*hw
, unsigned long rate
,
194 unsigned long *prate
)
197 div
= clk_divider_bestdiv(hw
, rate
, prate
);
202 static int clk_divider_set_rate(struct clk_hw
*hw
, unsigned long rate
,
203 unsigned long parent_rate
)
205 struct clk_divider
*divider
= to_clk_divider(hw
);
206 unsigned int div
, value
;
207 unsigned long flags
= 0;
210 div
= parent_rate
/ rate
;
211 value
= _get_val(divider
, div
);
213 if (value
> div_mask(divider
))
214 value
= div_mask(divider
);
217 spin_lock_irqsave(divider
->lock
, flags
);
219 val
= readl(divider
->reg
);
220 val
&= ~(div_mask(divider
) << divider
->shift
);
221 val
|= value
<< divider
->shift
;
222 writel(val
, divider
->reg
);
225 spin_unlock_irqrestore(divider
->lock
, flags
);
230 const struct clk_ops clk_divider_ops
= {
231 .recalc_rate
= clk_divider_recalc_rate
,
232 .round_rate
= clk_divider_round_rate
,
233 .set_rate
= clk_divider_set_rate
,
235 EXPORT_SYMBOL_GPL(clk_divider_ops
);
237 static struct clk
*_register_divider(struct device
*dev
, const char *name
,
238 const char *parent_name
, unsigned long flags
,
239 void __iomem
*reg
, u8 shift
, u8 width
,
240 u8 clk_divider_flags
, const struct clk_div_table
*table
,
243 struct clk_divider
*div
;
245 struct clk_init_data init
;
247 /* allocate the divider */
248 div
= kzalloc(sizeof(struct clk_divider
), GFP_KERNEL
);
250 pr_err("%s: could not allocate divider clk\n", __func__
);
251 return ERR_PTR(-ENOMEM
);
255 init
.ops
= &clk_divider_ops
;
256 init
.flags
= flags
| CLK_IS_BASIC
;
257 init
.parent_names
= (parent_name
? &parent_name
: NULL
);
258 init
.num_parents
= (parent_name
? 1 : 0);
260 /* struct clk_divider assignments */
264 div
->flags
= clk_divider_flags
;
266 div
->hw
.init
= &init
;
269 /* register the clock */
270 clk
= clk_register(dev
, &div
->hw
);
279 * clk_register_divider - register a divider clock with the clock framework
280 * @dev: device registering this clock
281 * @name: name of this clock
282 * @parent_name: name of clock's parent
283 * @flags: framework-specific flags
284 * @reg: register address to adjust divider
285 * @shift: number of bits to shift the bitfield
286 * @width: width of the bitfield
287 * @clk_divider_flags: divider-specific flags for this clock
288 * @lock: shared register lock for this clock
290 struct clk
*clk_register_divider(struct device
*dev
, const char *name
,
291 const char *parent_name
, unsigned long flags
,
292 void __iomem
*reg
, u8 shift
, u8 width
,
293 u8 clk_divider_flags
, spinlock_t
*lock
)
295 return _register_divider(dev
, name
, parent_name
, flags
, reg
, shift
,
296 width
, clk_divider_flags
, NULL
, lock
);
300 * clk_register_divider_table - register a table based divider clock with
301 * the clock framework
302 * @dev: device registering this clock
303 * @name: name of this clock
304 * @parent_name: name of clock's parent
305 * @flags: framework-specific flags
306 * @reg: register address to adjust divider
307 * @shift: number of bits to shift the bitfield
308 * @width: width of the bitfield
309 * @clk_divider_flags: divider-specific flags for this clock
310 * @table: array of divider/value pairs ending with a div set to 0
311 * @lock: shared register lock for this clock
313 struct clk
*clk_register_divider_table(struct device
*dev
, const char *name
,
314 const char *parent_name
, unsigned long flags
,
315 void __iomem
*reg
, u8 shift
, u8 width
,
316 u8 clk_divider_flags
, const struct clk_div_table
*table
,
319 return _register_divider(dev
, name
, parent_name
, flags
, reg
, shift
,
320 width
, clk_divider_flags
, table
, lock
);