1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <drm/intel-gtt.h>
40 #include <linux/backlight.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
44 /* General customization:
47 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
49 #define DRIVER_NAME "i915"
50 #define DRIVER_DESC "Intel Graphics"
51 #define DRIVER_DATE "20080730"
59 #define pipe_name(p) ((p) + 'A')
66 #define plane_name(p) ((p) + 'A')
76 #define port_name(p) ((p) + 'A')
78 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
80 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
82 struct intel_pch_pll
{
83 int refcount
; /* count of number of CRTCs sharing this PLL */
84 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
85 bool on
; /* is the PLL actually active? Disabled during modeset */
90 #define I915_NUM_PLLS 2
95 * 1.2: Add Power Management
96 * 1.3: Add vblank support
97 * 1.4: Fix cmdbuffer path, add heap destroy
98 * 1.5: Add vblank pipe configuration
99 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
100 * - Support vertical blank on secondary display pipe
102 #define DRIVER_MAJOR 1
103 #define DRIVER_MINOR 6
104 #define DRIVER_PATCHLEVEL 0
106 #define WATCH_COHERENCY 0
107 #define WATCH_LISTS 0
109 #define I915_GEM_PHYS_CURSOR_0 1
110 #define I915_GEM_PHYS_CURSOR_1 2
111 #define I915_GEM_PHYS_OVERLAY_REGS 3
112 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
114 struct drm_i915_gem_phys_object
{
116 struct page
**page_list
;
117 drm_dma_handle_t
*handle
;
118 struct drm_i915_gem_object
*cur_obj
;
122 struct mem_block
*next
;
123 struct mem_block
*prev
;
126 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
129 struct opregion_header
;
130 struct opregion_acpi
;
131 struct opregion_swsci
;
132 struct opregion_asle
;
133 struct drm_i915_private
;
135 struct intel_opregion
{
136 struct opregion_header __iomem
*header
;
137 struct opregion_acpi __iomem
*acpi
;
138 struct opregion_swsci __iomem
*swsci
;
139 struct opregion_asle __iomem
*asle
;
141 u32 __iomem
*lid_state
;
143 #define OPREGION_SIZE (8*1024)
145 struct intel_overlay
;
146 struct intel_overlay_error_state
;
148 struct drm_i915_master_private
{
149 drm_local_map_t
*sarea
;
150 struct _drm_i915_sarea
*sarea_priv
;
152 #define I915_FENCE_REG_NONE -1
153 #define I915_MAX_NUM_FENCES 16
154 /* 16 fences + sign bit for FENCE_REG_NONE */
155 #define I915_MAX_NUM_FENCE_BITS 5
157 struct drm_i915_fence_reg
{
158 struct list_head lru_list
;
159 struct drm_i915_gem_object
*obj
;
163 struct sdvo_device_mapping
{
172 struct intel_display_error_state
;
174 struct drm_i915_error_state
{
180 bool waiting
[I915_NUM_RINGS
];
181 u32 pipestat
[I915_MAX_PIPES
];
182 u32 tail
[I915_NUM_RINGS
];
183 u32 head
[I915_NUM_RINGS
];
184 u32 ipeir
[I915_NUM_RINGS
];
185 u32 ipehr
[I915_NUM_RINGS
];
186 u32 instdone
[I915_NUM_RINGS
];
187 u32 acthd
[I915_NUM_RINGS
];
188 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
189 /* our own tracking of ring head and tail */
190 u32 cpu_ring_head
[I915_NUM_RINGS
];
191 u32 cpu_ring_tail
[I915_NUM_RINGS
];
192 u32 error
; /* gen6+ */
193 u32 instpm
[I915_NUM_RINGS
];
194 u32 instps
[I915_NUM_RINGS
];
196 u32 seqno
[I915_NUM_RINGS
];
198 u32 fault_reg
[I915_NUM_RINGS
];
200 u32 faddr
[I915_NUM_RINGS
];
201 u64 fence
[I915_MAX_NUM_FENCES
];
203 struct drm_i915_error_ring
{
204 struct drm_i915_error_object
{
208 } *ringbuffer
, *batchbuffer
;
209 struct drm_i915_error_request
{
215 } ring
[I915_NUM_RINGS
];
216 struct drm_i915_error_buffer
{
223 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
230 } *active_bo
, *pinned_bo
;
231 u32 active_bo_count
, pinned_bo_count
;
232 struct intel_overlay_error_state
*overlay
;
233 struct intel_display_error_state
*display
;
236 struct drm_i915_display_funcs
{
237 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
238 bool (*fbc_enabled
)(struct drm_device
*dev
);
239 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
240 void (*disable_fbc
)(struct drm_device
*dev
);
241 int (*get_display_clock_speed
)(struct drm_device
*dev
);
242 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
243 void (*update_wm
)(struct drm_device
*dev
);
244 void (*update_sprite_wm
)(struct drm_device
*dev
, int pipe
,
245 uint32_t sprite_width
, int pixel_size
);
246 void (*sanitize_pm
)(struct drm_device
*dev
);
247 void (*update_linetime_wm
)(struct drm_device
*dev
, int pipe
,
248 struct drm_display_mode
*mode
);
249 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
250 struct drm_display_mode
*mode
,
251 struct drm_display_mode
*adjusted_mode
,
253 struct drm_framebuffer
*old_fb
);
254 void (*off
)(struct drm_crtc
*crtc
);
255 void (*write_eld
)(struct drm_connector
*connector
,
256 struct drm_crtc
*crtc
);
257 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
258 void (*init_clock_gating
)(struct drm_device
*dev
);
259 void (*init_pch_clock_gating
)(struct drm_device
*dev
);
260 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
261 struct drm_framebuffer
*fb
,
262 struct drm_i915_gem_object
*obj
);
263 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
265 /* clock updates for mode set */
267 /* render clock increase/decrease */
268 /* display clock increase/decrease */
269 /* pll clock increase/decrease */
272 struct drm_i915_gt_funcs
{
273 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
274 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
277 struct intel_device_info
{
297 u8 cursor_needs_physical
:1;
299 u8 overlay_needs_physical
:1;
306 #define I915_PPGTT_PD_ENTRIES 512
307 #define I915_PPGTT_PT_ENTRIES 1024
308 struct i915_hw_ppgtt
{
309 unsigned num_pd_entries
;
310 struct page
**pt_pages
;
312 dma_addr_t
*pt_dma_addr
;
313 dma_addr_t scratch_page_dma_addr
;
317 /* This must match up with the value previously used for execbuf2.rsvd1. */
318 #define DEFAULT_CONTEXT_ID 0
319 struct i915_hw_context
{
322 struct drm_i915_file_private
*file_priv
;
323 struct intel_ring_buffer
*ring
;
324 struct drm_i915_gem_object
*obj
;
328 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
329 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
330 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
331 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
332 FBC_BAD_PLANE
, /* fbc not supported on plane */
333 FBC_NOT_TILED
, /* buffer not tiled */
334 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
339 PCH_NONE
= 0, /* No PCH present */
340 PCH_IBX
, /* Ibexpeak PCH */
341 PCH_CPT
, /* Cougarpoint PCH */
342 PCH_LPT
, /* Lynxpoint PCH */
345 #define QUIRK_PIPEA_FORCE (1<<0)
346 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
347 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
350 struct intel_fbc_work
;
353 struct i2c_adapter adapter
;
357 struct i2c_algo_bit_data bit_algo
;
358 struct drm_i915_private
*dev_priv
;
361 typedef struct drm_i915_private
{
362 struct drm_device
*dev
;
364 const struct intel_device_info
*info
;
366 int relative_constants_mode
;
370 struct drm_i915_gt_funcs gt
;
371 /** gt_fifo_count and the subsequent register write are synchronized
372 * with dev->struct_mutex. */
373 unsigned gt_fifo_count
;
374 /** forcewake_count is protected by gt_lock */
375 unsigned forcewake_count
;
376 /** gt_lock is also taken in irq contexts. */
377 struct spinlock gt_lock
;
379 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
381 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
382 * controller on different i2c buses. */
383 struct mutex gmbus_mutex
;
386 * Base address of the gmbus and gpio block.
388 uint32_t gpio_mmio_base
;
390 struct pci_dev
*bridge_dev
;
391 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
394 drm_dma_handle_t
*status_page_dmah
;
396 struct drm_i915_gem_object
*pwrctx
;
397 struct drm_i915_gem_object
*renderctx
;
399 struct resource mch_res
;
407 atomic_t irq_received
;
409 /* protects the irq masks */
412 /* DPIO indirect register protection */
413 spinlock_t dpio_lock
;
415 /** Cached value of IMR to avoid reads in updating the bitfield */
421 u32 hotplug_supported_mask
;
422 struct work_struct hotplug_work
;
424 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
428 /* For hangcheck timer */
429 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
430 struct timer_list hangcheck_timer
;
432 uint32_t last_acthd
[I915_NUM_RINGS
];
433 uint32_t last_instdone
;
434 uint32_t last_instdone1
;
436 unsigned int stop_rings
;
438 unsigned long cfb_size
;
440 enum plane cfb_plane
;
442 struct intel_fbc_work
*fbc_work
;
444 struct intel_opregion opregion
;
447 struct intel_overlay
*overlay
;
448 bool sprite_scaling_enabled
;
451 int backlight_level
; /* restore backlight to this value */
452 bool backlight_enabled
;
453 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
454 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
456 /* Feature bits from the VBIOS */
457 unsigned int int_tv_support
:1;
458 unsigned int lvds_dither
:1;
459 unsigned int lvds_vbt
:1;
460 unsigned int int_crt_support
:1;
461 unsigned int lvds_use_ssc
:1;
462 unsigned int display_clock_mode
:1;
464 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
465 unsigned int lvds_val
; /* used for checking LVDS channel mode */
475 struct edp_power_seq pps
;
477 bool no_aux_handshake
;
479 struct notifier_block lid_notifier
;
482 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
483 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
484 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
486 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
488 spinlock_t error_lock
;
489 /* Protected by dev->error_lock. */
490 struct drm_i915_error_state
*first_error
;
491 struct work_struct error_work
;
492 struct completion error_completion
;
493 struct workqueue_struct
*wq
;
495 /* Display functions */
496 struct drm_i915_display_funcs display
;
498 /* PCH chipset type */
499 enum intel_pch pch_type
;
501 unsigned long quirks
;
526 u32 saveTRANS_HTOTAL_A
;
527 u32 saveTRANS_HBLANK_A
;
528 u32 saveTRANS_HSYNC_A
;
529 u32 saveTRANS_VTOTAL_A
;
530 u32 saveTRANS_VBLANK_A
;
531 u32 saveTRANS_VSYNC_A
;
539 u32 savePFIT_PGM_RATIOS
;
540 u32 saveBLC_HIST_CTL
;
542 u32 saveBLC_PWM_CTL2
;
543 u32 saveBLC_CPU_PWM_CTL
;
544 u32 saveBLC_CPU_PWM_CTL2
;
557 u32 saveTRANS_HTOTAL_B
;
558 u32 saveTRANS_HBLANK_B
;
559 u32 saveTRANS_HSYNC_B
;
560 u32 saveTRANS_VTOTAL_B
;
561 u32 saveTRANS_VBLANK_B
;
562 u32 saveTRANS_VSYNC_B
;
576 u32 savePP_ON_DELAYS
;
577 u32 savePP_OFF_DELAYS
;
585 u32 savePFIT_CONTROL
;
586 u32 save_palette_a
[256];
587 u32 save_palette_b
[256];
588 u32 saveDPFC_CB_BASE
;
589 u32 saveFBC_CFB_BASE
;
592 u32 saveFBC_CONTROL2
;
602 u32 saveCACHE_MODE_0
;
603 u32 saveMI_ARB_STATE
;
614 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
625 u32 savePIPEA_GMCH_DATA_M
;
626 u32 savePIPEB_GMCH_DATA_M
;
627 u32 savePIPEA_GMCH_DATA_N
;
628 u32 savePIPEB_GMCH_DATA_N
;
629 u32 savePIPEA_DP_LINK_M
;
630 u32 savePIPEB_DP_LINK_M
;
631 u32 savePIPEA_DP_LINK_N
;
632 u32 savePIPEB_DP_LINK_N
;
643 u32 savePCH_DREF_CONTROL
;
644 u32 saveDISP_ARB_CTL
;
645 u32 savePIPEA_DATA_M1
;
646 u32 savePIPEA_DATA_N1
;
647 u32 savePIPEA_LINK_M1
;
648 u32 savePIPEA_LINK_N1
;
649 u32 savePIPEB_DATA_M1
;
650 u32 savePIPEB_DATA_N1
;
651 u32 savePIPEB_LINK_M1
;
652 u32 savePIPEB_LINK_N1
;
653 u32 saveMCHBAR_RENDER_STANDBY
;
654 u32 savePCH_PORT_HOTPLUG
;
657 /** Bridge to intel-gtt-ko */
658 const struct intel_gtt
*gtt
;
659 /** Memory allocator for GTT stolen memory */
660 struct drm_mm stolen
;
661 /** Memory allocator for GTT */
662 struct drm_mm gtt_space
;
663 /** List of all objects in gtt_space. Used to restore gtt
664 * mappings on resume */
665 struct list_head gtt_list
;
667 /** Usable portion of the GTT for GEM */
668 unsigned long gtt_start
;
669 unsigned long gtt_mappable_end
;
670 unsigned long gtt_end
;
672 struct io_mapping
*gtt_mapping
;
673 phys_addr_t gtt_base_addr
;
676 /** PPGTT used for aliasing the PPGTT with the GTT */
677 struct i915_hw_ppgtt
*aliasing_ppgtt
;
681 struct shrinker inactive_shrinker
;
684 * List of objects currently involved in rendering.
686 * Includes buffers having the contents of their GPU caches
687 * flushed, not necessarily primitives. last_rendering_seqno
688 * represents when the rendering involved will be completed.
690 * A reference is held on the buffer while on this list.
692 struct list_head active_list
;
695 * List of objects which are not in the ringbuffer but which
696 * still have a write_domain which needs to be flushed before
699 * last_rendering_seqno is 0 while an object is in this list.
701 * A reference is held on the buffer while on this list.
703 struct list_head flushing_list
;
706 * LRU list of objects which are not in the ringbuffer and
707 * are ready to unbind, but are still in the GTT.
709 * last_rendering_seqno is 0 while an object is in this list.
711 * A reference is not held on the buffer while on this list,
712 * as merely being GTT-bound shouldn't prevent its being
713 * freed, and we'll pull it off the list in the free path.
715 struct list_head inactive_list
;
717 /** LRU list of objects with fence regs on them. */
718 struct list_head fence_list
;
721 * We leave the user IRQ off as much as possible,
722 * but this means that requests will finish and never
723 * be retired once the system goes idle. Set a timer to
724 * fire periodically while the ring is running. When it
725 * fires, go retire requests.
727 struct delayed_work retire_work
;
730 * Are we in a non-interruptible section of code like
736 * Flag if the X Server, and thus DRM, is not currently in
737 * control of the device.
739 * This is set between LeaveVT and EnterVT. It needs to be
740 * replaced with a semaphore. It also needs to be
741 * transitioned away from for kernel modesetting.
746 * Flag if the hardware appears to be wedged.
748 * This is set when attempts to idle the device timeout.
749 * It prevents command submission from occurring and makes
750 * every pending request fail
754 /** Bit 6 swizzling required for X tiling */
755 uint32_t bit_6_swizzle_x
;
756 /** Bit 6 swizzling required for Y tiling */
757 uint32_t bit_6_swizzle_y
;
759 /* storage for physical objects */
760 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
762 /* accounting, useful for userland debugging */
764 size_t mappable_gtt_total
;
765 size_t object_memory
;
769 /* Old dri1 support infrastructure, beware the dragons ya fools entering
772 unsigned allow_batchbuffer
: 1;
773 u32 __iomem
*gfx_hws_cpu_addr
;
776 /* Kernel Modesetting */
778 struct sdvo_device_mapping sdvo_mappings
[2];
779 /* indicate whether the LVDS_BORDER should be enabled or not */
780 unsigned int lvds_border_bits
;
781 /* Panel fitter placement and size for Ironlake+ */
782 u32 pch_pf_pos
, pch_pf_size
;
784 struct drm_crtc
*plane_to_crtc_mapping
[3];
785 struct drm_crtc
*pipe_to_crtc_mapping
[3];
786 wait_queue_head_t pending_flip_queue
;
788 struct intel_pch_pll pch_plls
[I915_NUM_PLLS
];
790 /* Reclocking support */
791 bool render_reclock_avail
;
792 bool lvds_downclock_avail
;
793 /* indicates the reduced downclock for LVDS*/
795 struct work_struct idle_work
;
796 struct timer_list idle_timer
;
800 struct child_device_config
*child_dev
;
801 struct drm_connector
*int_lvds_connector
;
802 struct drm_connector
*int_edp_connector
;
804 bool mchbar_need_disable
;
806 struct work_struct rps_work
;
817 unsigned long last_time1
;
818 unsigned long chipset_power
;
820 struct timespec last_time2
;
821 unsigned long gfx_power
;
825 spinlock_t
*mchdev_lock
;
827 enum no_fbc_reason no_fbc_reason
;
829 struct drm_mm_node
*compressed_fb
;
830 struct drm_mm_node
*compressed_llb
;
832 unsigned long last_gpu_reset
;
834 /* list of fbdev register on this device */
835 struct intel_fbdev
*fbdev
;
837 struct backlight_device
*backlight
;
839 struct drm_property
*broadcast_rgb_property
;
840 struct drm_property
*force_audio_property
;
842 struct work_struct parity_error_work
;
843 bool hw_contexts_disabled
;
844 uint32_t hw_context_size
;
845 } drm_i915_private_t
;
847 /* Iterate over initialised rings */
848 #define for_each_ring(ring__, dev_priv__, i__) \
849 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
850 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
852 enum hdmi_force_audio
{
853 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
854 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
855 HDMI_AUDIO_AUTO
, /* trust EDID */
856 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
859 enum i915_cache_level
{
862 I915_CACHE_LLC_MLC
, /* gen6+ */
865 struct drm_i915_gem_object
{
866 struct drm_gem_object base
;
868 /** Current space allocated to this object in the GTT, if any. */
869 struct drm_mm_node
*gtt_space
;
870 struct list_head gtt_list
;
872 /** This object's place on the active/flushing/inactive lists */
873 struct list_head ring_list
;
874 struct list_head mm_list
;
875 /** This object's place on GPU write list */
876 struct list_head gpu_write_list
;
877 /** This object's place in the batchbuffer or on the eviction list */
878 struct list_head exec_list
;
881 * This is set if the object is on the active or flushing lists
882 * (has pending rendering), and is not set if it's on inactive (ready
885 unsigned int active
:1;
888 * This is set if the object has been written to since last bound
891 unsigned int dirty
:1;
894 * This is set if the object has been written to since the last
897 unsigned int pending_gpu_write
:1;
900 * Fence register bits (if any) for this object. Will be set
901 * as needed when mapped into the GTT.
902 * Protected by dev->struct_mutex.
904 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
907 * Advice: are the backing pages purgeable?
912 * Current tiling mode for the object.
914 unsigned int tiling_mode
:2;
916 * Whether the tiling parameters for the currently associated fence
917 * register have changed. Note that for the purposes of tracking
918 * tiling changes we also treat the unfenced register, the register
919 * slot that the object occupies whilst it executes a fenced
920 * command (such as BLT on gen2/3), as a "fence".
922 unsigned int fence_dirty
:1;
924 /** How many users have pinned this object in GTT space. The following
925 * users can each hold at most one reference: pwrite/pread, pin_ioctl
926 * (via user_pin_count), execbuffer (objects are not allowed multiple
927 * times for the same batchbuffer), and the framebuffer code. When
928 * switching/pageflipping, the framebuffer code has at most two buffers
931 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
932 * bits with absolutely no headroom. So use 4 bits. */
933 unsigned int pin_count
:4;
934 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
937 * Is the object at the current location in the gtt mappable and
938 * fenceable? Used to avoid costly recalculations.
940 unsigned int map_and_fenceable
:1;
943 * Whether the current gtt mapping needs to be mappable (and isn't just
944 * mappable by accident). Track pin and fault separate for a more
945 * accurate mappable working set.
947 unsigned int fault_mappable
:1;
948 unsigned int pin_mappable
:1;
951 * Is the GPU currently using a fence to access this buffer,
953 unsigned int pending_fenced_gpu_access
:1;
954 unsigned int fenced_gpu_access
:1;
956 unsigned int cache_level
:2;
958 unsigned int has_aliasing_ppgtt_mapping
:1;
959 unsigned int has_global_gtt_mapping
:1;
966 struct scatterlist
*sg_list
;
969 /* prime dma-buf support */
970 struct sg_table
*sg_table
;
971 void *dma_buf_vmapping
;
975 * Used for performing relocations during execbuffer insertion.
977 struct hlist_node exec_node
;
978 unsigned long exec_handle
;
979 struct drm_i915_gem_exec_object2
*exec_entry
;
982 * Current offset of the object in GTT space.
984 * This is the same as gtt_space->start
988 struct intel_ring_buffer
*ring
;
990 /** Breadcrumb of last rendering to the buffer. */
991 uint32_t last_rendering_seqno
;
992 /** Breadcrumb of last fenced GPU access to the buffer. */
993 uint32_t last_fenced_seqno
;
995 /** Current tiling stride for the object, if it's tiled. */
998 /** Record of address bit 17 of each page at last unbind. */
999 unsigned long *bit_17
;
1001 /** User space pin count and filp owning the pin */
1002 uint32_t user_pin_count
;
1003 struct drm_file
*pin_filp
;
1005 /** for phy allocated objects */
1006 struct drm_i915_gem_phys_object
*phys_obj
;
1009 * Number of crtcs where this object is currently the fb, but
1010 * will be page flipped away on the next vblank. When it
1011 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1013 atomic_t pending_flip
;
1016 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1019 * Request queue structure.
1021 * The request queue allows us to note sequence numbers that have been emitted
1022 * and may be associated with active buffers to be retired.
1024 * By keeping this list, we can avoid having to do questionable
1025 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1026 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1028 struct drm_i915_gem_request
{
1029 /** On Which ring this request was generated */
1030 struct intel_ring_buffer
*ring
;
1032 /** GEM sequence number associated with this request. */
1035 /** Postion in the ringbuffer of the end of the request */
1038 /** Time at which this request was emitted, in jiffies. */
1039 unsigned long emitted_jiffies
;
1041 /** global list entry for this request */
1042 struct list_head list
;
1044 struct drm_i915_file_private
*file_priv
;
1045 /** file_priv list entry for this request */
1046 struct list_head client_list
;
1049 struct drm_i915_file_private
{
1051 struct spinlock lock
;
1052 struct list_head request_list
;
1054 struct idr context_idr
;
1057 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1059 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1060 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1061 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1062 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1063 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1064 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1065 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1066 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1067 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1068 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1069 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1070 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1071 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1072 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1073 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1074 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1075 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1076 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1077 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1078 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1079 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1080 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1083 * The genX designation typically refers to the render engine, so render
1084 * capability related checks should use IS_GEN, while display and other checks
1085 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1088 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1089 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1090 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1091 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1092 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1093 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1095 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1096 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1097 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1098 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1100 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1101 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1103 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1104 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1106 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1107 * rows, which changed the alignment requirements and fence programming.
1109 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1111 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1112 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1113 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1114 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1115 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1116 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1117 /* dsparb controlled by hw only */
1118 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1120 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1121 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1122 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1124 #define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split)
1125 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1127 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1128 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1129 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1130 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1132 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1134 #include "i915_trace.h"
1137 * RC6 is a special power stage which allows the GPU to enter an very
1138 * low-voltage mode when idle, using down to 0V while at this stage. This
1139 * stage is entered automatically when the GPU is idle when RC6 support is
1140 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1142 * There are different RC6 modes available in Intel GPU, which differentiate
1143 * among each other with the latency required to enter and leave RC6 and
1144 * voltage consumed by the GPU in different states.
1146 * The combination of the following flags define which states GPU is allowed
1147 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1148 * RC6pp is deepest RC6. Their support by hardware varies according to the
1149 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1150 * which brings the most power savings; deeper states save more power, but
1151 * require higher latency to switch to and wake up.
1153 #define INTEL_RC6_ENABLE (1<<0)
1154 #define INTEL_RC6p_ENABLE (1<<1)
1155 #define INTEL_RC6pp_ENABLE (1<<2)
1157 extern struct drm_ioctl_desc i915_ioctls
[];
1158 extern int i915_max_ioctl
;
1159 extern unsigned int i915_fbpercrtc __always_unused
;
1160 extern int i915_panel_ignore_lid __read_mostly
;
1161 extern unsigned int i915_powersave __read_mostly
;
1162 extern int i915_semaphores __read_mostly
;
1163 extern unsigned int i915_lvds_downclock __read_mostly
;
1164 extern int i915_lvds_channel_mode __read_mostly
;
1165 extern int i915_panel_use_ssc __read_mostly
;
1166 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1167 extern int i915_enable_rc6 __read_mostly
;
1168 extern int i915_enable_fbc __read_mostly
;
1169 extern bool i915_enable_hangcheck __read_mostly
;
1170 extern int i915_enable_ppgtt __read_mostly
;
1172 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1173 extern int i915_resume(struct drm_device
*dev
);
1174 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1175 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1178 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1179 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1180 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1181 extern int i915_driver_unload(struct drm_device
*);
1182 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1183 extern void i915_driver_lastclose(struct drm_device
* dev
);
1184 extern void i915_driver_preclose(struct drm_device
*dev
,
1185 struct drm_file
*file_priv
);
1186 extern void i915_driver_postclose(struct drm_device
*dev
,
1187 struct drm_file
*file_priv
);
1188 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1189 #ifdef CONFIG_COMPAT
1190 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1193 extern int i915_emit_box(struct drm_device
*dev
,
1194 struct drm_clip_rect
*box
,
1196 extern int intel_gpu_reset(struct drm_device
*dev
);
1197 extern int i915_reset(struct drm_device
*dev
);
1198 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1199 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1200 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1201 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1205 void i915_hangcheck_elapsed(unsigned long data
);
1206 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1208 extern void intel_irq_init(struct drm_device
*dev
);
1209 extern void intel_gt_init(struct drm_device
*dev
);
1211 void i915_error_state_free(struct kref
*error_ref
);
1214 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1217 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1219 void intel_enable_asle(struct drm_device
*dev
);
1221 #ifdef CONFIG_DEBUG_FS
1222 extern void i915_destroy_error_state(struct drm_device
*dev
);
1224 #define i915_destroy_error_state(x)
1229 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1230 struct drm_file
*file_priv
);
1231 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1232 struct drm_file
*file_priv
);
1233 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1234 struct drm_file
*file_priv
);
1235 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1236 struct drm_file
*file_priv
);
1237 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1238 struct drm_file
*file_priv
);
1239 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1240 struct drm_file
*file_priv
);
1241 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1242 struct drm_file
*file_priv
);
1243 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1244 struct drm_file
*file_priv
);
1245 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1246 struct drm_file
*file_priv
);
1247 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1248 struct drm_file
*file_priv
);
1249 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1250 struct drm_file
*file_priv
);
1251 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1252 struct drm_file
*file_priv
);
1253 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1254 struct drm_file
*file_priv
);
1255 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1256 struct drm_file
*file_priv
);
1257 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1258 struct drm_file
*file_priv
);
1259 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1260 struct drm_file
*file_priv
);
1261 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1262 struct drm_file
*file_priv
);
1263 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1264 struct drm_file
*file_priv
);
1265 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1266 struct drm_file
*file_priv
);
1267 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1268 struct drm_file
*file_priv
);
1269 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1270 struct drm_file
*file_priv
);
1271 void i915_gem_load(struct drm_device
*dev
);
1272 int i915_gem_init_object(struct drm_gem_object
*obj
);
1273 int __must_check
i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
1274 uint32_t invalidate_domains
,
1275 uint32_t flush_domains
);
1276 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1278 void i915_gem_free_object(struct drm_gem_object
*obj
);
1279 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1281 bool map_and_fenceable
);
1282 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1283 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1284 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1285 void i915_gem_lastclose(struct drm_device
*dev
);
1287 int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
,
1289 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1290 int __must_check
i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
);
1291 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1292 struct intel_ring_buffer
*to
);
1293 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1294 struct intel_ring_buffer
*ring
,
1297 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1298 struct drm_device
*dev
,
1299 struct drm_mode_create_dumb
*args
);
1300 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1301 uint32_t handle
, uint64_t *offset
);
1302 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1305 * Returns true if seq1 is later than seq2.
1308 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1310 return (int32_t)(seq1
- seq2
) >= 0;
1313 u32
i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
);
1315 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
1316 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1319 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1321 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1322 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1323 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1330 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1332 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1333 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1334 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1338 void i915_gem_retire_requests(struct drm_device
*dev
);
1339 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
1341 void i915_gem_reset(struct drm_device
*dev
);
1342 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1343 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1344 uint32_t read_domains
,
1345 uint32_t write_domain
);
1346 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1347 int __must_check
i915_gem_init(struct drm_device
*dev
);
1348 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1349 void i915_gem_l3_remap(struct drm_device
*dev
);
1350 void i915_gem_init_swizzling(struct drm_device
*dev
);
1351 void i915_gem_init_ppgtt(struct drm_device
*dev
);
1352 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1353 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1354 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1355 int __must_check
i915_add_request(struct intel_ring_buffer
*ring
,
1356 struct drm_file
*file
,
1357 struct drm_i915_gem_request
*request
);
1358 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
1360 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1362 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1365 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
1367 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1369 struct intel_ring_buffer
*pipelined
);
1370 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1371 struct drm_i915_gem_object
*obj
,
1374 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1375 struct drm_i915_gem_object
*obj
);
1376 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1377 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1380 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1384 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1385 enum i915_cache_level cache_level
);
1387 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
1388 struct dma_buf
*dma_buf
);
1390 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
1391 struct drm_gem_object
*gem_obj
, int flags
);
1393 /* i915_gem_context.c */
1394 void i915_gem_context_init(struct drm_device
*dev
);
1395 void i915_gem_context_fini(struct drm_device
*dev
);
1396 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
1397 int i915_switch_context(struct intel_ring_buffer
*ring
,
1398 struct drm_file
*file
, int to_id
);
1399 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
1400 struct drm_file
*file
);
1401 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
1402 struct drm_file
*file
);
1404 /* i915_gem_gtt.c */
1405 int __must_check
i915_gem_init_aliasing_ppgtt(struct drm_device
*dev
);
1406 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
1407 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
1408 struct drm_i915_gem_object
*obj
,
1409 enum i915_cache_level cache_level
);
1410 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
1411 struct drm_i915_gem_object
*obj
);
1413 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1414 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
1415 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
1416 enum i915_cache_level cache_level
);
1417 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1418 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
1419 void i915_gem_init_global_gtt(struct drm_device
*dev
,
1420 unsigned long start
,
1421 unsigned long mappable_end
,
1424 /* i915_gem_evict.c */
1425 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1426 unsigned alignment
, bool mappable
);
1427 int i915_gem_evict_everything(struct drm_device
*dev
, bool purgeable_only
);
1429 /* i915_gem_stolen.c */
1430 int i915_gem_init_stolen(struct drm_device
*dev
);
1431 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
1433 /* i915_gem_tiling.c */
1434 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1435 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1436 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1438 /* i915_gem_debug.c */
1439 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1440 const char *where
, uint32_t mark
);
1442 int i915_verify_lists(struct drm_device
*dev
);
1444 #define i915_verify_lists(dev) 0
1446 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1448 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1449 const char *where
, uint32_t mark
);
1451 /* i915_debugfs.c */
1452 int i915_debugfs_init(struct drm_minor
*minor
);
1453 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1455 /* i915_suspend.c */
1456 extern int i915_save_state(struct drm_device
*dev
);
1457 extern int i915_restore_state(struct drm_device
*dev
);
1459 /* i915_suspend.c */
1460 extern int i915_save_state(struct drm_device
*dev
);
1461 extern int i915_restore_state(struct drm_device
*dev
);
1464 void i915_setup_sysfs(struct drm_device
*dev_priv
);
1465 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
1468 extern int intel_setup_gmbus(struct drm_device
*dev
);
1469 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1470 extern inline bool intel_gmbus_is_port_valid(unsigned port
)
1472 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
1475 extern struct i2c_adapter
*intel_gmbus_get_adapter(
1476 struct drm_i915_private
*dev_priv
, unsigned port
);
1477 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1478 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1479 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1481 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1483 extern void intel_i2c_reset(struct drm_device
*dev
);
1485 /* intel_opregion.c */
1486 extern int intel_opregion_setup(struct drm_device
*dev
);
1488 extern void intel_opregion_init(struct drm_device
*dev
);
1489 extern void intel_opregion_fini(struct drm_device
*dev
);
1490 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1491 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1492 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1494 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1495 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1496 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1497 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1498 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1503 extern void intel_register_dsm_handler(void);
1504 extern void intel_unregister_dsm_handler(void);
1506 static inline void intel_register_dsm_handler(void) { return; }
1507 static inline void intel_unregister_dsm_handler(void) { return; }
1508 #endif /* CONFIG_ACPI */
1511 extern void intel_modeset_init_hw(struct drm_device
*dev
);
1512 extern void intel_modeset_init(struct drm_device
*dev
);
1513 extern void intel_modeset_gem_init(struct drm_device
*dev
);
1514 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1515 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1516 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1517 extern void intel_disable_fbc(struct drm_device
*dev
);
1518 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1519 extern void ironlake_init_pch_refclk(struct drm_device
*dev
);
1520 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
1521 extern void intel_detect_pch(struct drm_device
*dev
);
1522 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
1523 extern int intel_enable_rc6(const struct drm_device
*dev
);
1525 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
1528 #ifdef CONFIG_DEBUG_FS
1529 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1530 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1532 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
1533 extern void intel_display_print_error_state(struct seq_file
*m
,
1534 struct drm_device
*dev
,
1535 struct intel_display_error_state
*error
);
1538 /* On SNB platform, before reading ring registers forcewake bit
1539 * must be set to prevent GT core from power down and stale values being
1542 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
1543 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
1544 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
);
1546 #define __i915_read(x, y) \
1547 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1555 #define __i915_write(x, y) \
1556 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1564 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1565 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1567 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1568 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1569 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1570 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1572 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1573 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1574 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1575 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1577 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1578 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1580 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1581 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)