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net: dsa: mv88e6xxx: do not support per-port FID
[linux-2.6/btrfs-unstable.git] / drivers / net / dsa / mv88e6xxx.h
blob9b6104b94ce42888dff1af97d311f1e60181f93c
1 /*
2 * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11 #ifndef __MV88E6XXX_H
12 #define __MV88E6XXX_H
13
14 #include <linux/if_vlan.h>
15
16 #ifndef UINT64_MAX
17 #define UINT64_MAX (u64)(~((u64)0))
18 #endif
19
20 #define SMI_CMD 0x00
21 #define SMI_CMD_BUSY BIT(15)
22 #define SMI_CMD_CLAUSE_22 BIT(12)
23 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
24 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
25 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
26 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
27 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
28 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
29 #define SMI_DATA 0x01
30
31 #define REG_PORT(p) (0x10 + (p))
32 #define PORT_STATUS 0x00
33 #define PORT_STATUS_PAUSE_EN BIT(15)
34 #define PORT_STATUS_MY_PAUSE BIT(14)
35 #define PORT_STATUS_HD_FLOW BIT(13)
36 #define PORT_STATUS_PHY_DETECT BIT(12)
37 #define PORT_STATUS_LINK BIT(11)
38 #define PORT_STATUS_DUPLEX BIT(10)
39 #define PORT_STATUS_SPEED_MASK 0x0300
40 #define PORT_STATUS_SPEED_10 0x0000
41 #define PORT_STATUS_SPEED_100 0x0100
42 #define PORT_STATUS_SPEED_1000 0x0200
43 #define PORT_STATUS_EEE BIT(6) /* 6352 */
44 #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */
45 #define PORT_STATUS_MGMII BIT(6) /* 6185 */
46 #define PORT_STATUS_TX_PAUSED BIT(5)
47 #define PORT_STATUS_FLOW_CTRL BIT(4)
48 #define PORT_PCS_CTRL 0x01
49 #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15)
50 #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14)
51 #define PORT_PCS_CTRL_FC BIT(7)
52 #define PORT_PCS_CTRL_FORCE_FC BIT(6)
53 #define PORT_PCS_CTRL_LINK_UP BIT(5)
54 #define PORT_PCS_CTRL_FORCE_LINK BIT(4)
55 #define PORT_PCS_CTRL_DUPLEX_FULL BIT(3)
56 #define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2)
57 #define PORT_PCS_CTRL_10 0x00
58 #define PORT_PCS_CTRL_100 0x01
59 #define PORT_PCS_CTRL_1000 0x02
60 #define PORT_PCS_CTRL_UNFORCED 0x03
61 #define PORT_PAUSE_CTRL 0x02
62 #define PORT_SWITCH_ID 0x03
63 #define PORT_SWITCH_ID_6031 0x0310
64 #define PORT_SWITCH_ID_6035 0x0350
65 #define PORT_SWITCH_ID_6046 0x0480
66 #define PORT_SWITCH_ID_6061 0x0610
67 #define PORT_SWITCH_ID_6065 0x0650
68 #define PORT_SWITCH_ID_6085 0x04a0
69 #define PORT_SWITCH_ID_6092 0x0970
70 #define PORT_SWITCH_ID_6095 0x0950
71 #define PORT_SWITCH_ID_6096 0x0980
72 #define PORT_SWITCH_ID_6097 0x0990
73 #define PORT_SWITCH_ID_6108 0x1070
74 #define PORT_SWITCH_ID_6121 0x1040
75 #define PORT_SWITCH_ID_6122 0x1050
76 #define PORT_SWITCH_ID_6123 0x1210
77 #define PORT_SWITCH_ID_6123_A1 0x1212
78 #define PORT_SWITCH_ID_6123_A2 0x1213
79 #define PORT_SWITCH_ID_6131 0x1060
80 #define PORT_SWITCH_ID_6131_B2 0x1066
81 #define PORT_SWITCH_ID_6152 0x1a40
82 #define PORT_SWITCH_ID_6155 0x1a50
83 #define PORT_SWITCH_ID_6161 0x1610
84 #define PORT_SWITCH_ID_6161_A1 0x1612
85 #define PORT_SWITCH_ID_6161_A2 0x1613
86 #define PORT_SWITCH_ID_6165 0x1650
87 #define PORT_SWITCH_ID_6165_A1 0x1652
88 #define PORT_SWITCH_ID_6165_A2 0x1653
89 #define PORT_SWITCH_ID_6171 0x1710
90 #define PORT_SWITCH_ID_6172 0x1720
91 #define PORT_SWITCH_ID_6175 0x1750
92 #define PORT_SWITCH_ID_6176 0x1760
93 #define PORT_SWITCH_ID_6182 0x1a60
94 #define PORT_SWITCH_ID_6185 0x1a70
95 #define PORT_SWITCH_ID_6240 0x2400
96 #define PORT_SWITCH_ID_6320 0x1150
97 #define PORT_SWITCH_ID_6320_A1 0x1151
98 #define PORT_SWITCH_ID_6320_A2 0x1152
99 #define PORT_SWITCH_ID_6321 0x3100
100 #define PORT_SWITCH_ID_6321_A1 0x3101
101 #define PORT_SWITCH_ID_6321_A2 0x3102
102 #define PORT_SWITCH_ID_6350 0x3710
103 #define PORT_SWITCH_ID_6351 0x3750
104 #define PORT_SWITCH_ID_6352 0x3520
105 #define PORT_SWITCH_ID_6352_A0 0x3521
106 #define PORT_SWITCH_ID_6352_A1 0x3522
107 #define PORT_CONTROL 0x04
108 #define PORT_CONTROL_USE_CORE_TAG BIT(15)
109 #define PORT_CONTROL_DROP_ON_LOCK BIT(14)
110 #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12)
111 #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12)
112 #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12)
113 #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12)
114 #define PORT_CONTROL_HEADER BIT(11)
115 #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10)
116 #define PORT_CONTROL_DOUBLE_TAG BIT(9)
117 #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8)
118 #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8)
119 #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8)
120 #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8)
121 #define PORT_CONTROL_DSA_TAG BIT(8)
122 #define PORT_CONTROL_VLAN_TUNNEL BIT(7)
123 #define PORT_CONTROL_TAG_IF_BOTH BIT(6)
124 #define PORT_CONTROL_USE_IP BIT(5)
125 #define PORT_CONTROL_USE_TAG BIT(4)
126 #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3)
127 #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2)
128 #define PORT_CONTROL_STATE_MASK 0x03
129 #define PORT_CONTROL_STATE_DISABLED 0x00
130 #define PORT_CONTROL_STATE_BLOCKING 0x01
131 #define PORT_CONTROL_STATE_LEARNING 0x02
132 #define PORT_CONTROL_STATE_FORWARDING 0x03
133 #define PORT_CONTROL_1 0x05
134 #define PORT_BASE_VLAN 0x06
135 #define PORT_DEFAULT_VLAN 0x07
136 #define PORT_DEFAULT_VLAN_MASK 0xfff
137 #define PORT_CONTROL_2 0x08
138 #define PORT_CONTROL_2_IGNORE_FCS BIT(15)
139 #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
140 #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
141 #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
142 #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12)
143 #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12)
144 #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12)
145 #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10)
146 #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10)
147 #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10)
148 #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10)
149 #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10)
150 #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9)
151 #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8)
152 #define PORT_CONTROL_2_MAP_DA BIT(7)
153 #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6)
154 #define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6)
155 #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5)
156 #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4)
157 #define PORT_RATE_CONTROL 0x09
158 #define PORT_RATE_CONTROL_2 0x0a
159 #define PORT_ASSOC_VECTOR 0x0b
160 #define PORT_ATU_CONTROL 0x0c
161 #define PORT_PRI_OVERRIDE 0x0d
162 #define PORT_ETH_TYPE 0x0f
163 #define PORT_IN_DISCARD_LO 0x10
164 #define PORT_IN_DISCARD_HI 0x11
165 #define PORT_IN_FILTERED 0x12
166 #define PORT_OUT_FILTERED 0x13
167 #define PORT_TAG_REGMAP_0123 0x18
168 #define PORT_TAG_REGMAP_4567 0x19
169
170 #define REG_GLOBAL 0x1b
171 #define GLOBAL_STATUS 0x00
172 #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
173 /* Two bits for 6165, 6185 etc */
174 #define GLOBAL_STATUS_PPU_MASK (0x3 << 14)
175 #define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14)
176 #define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14)
177 #define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14)
178 #define GLOBAL_STATUS_PPU_POLLING (0x3 << 14)
179 #define GLOBAL_MAC_01 0x01
180 #define GLOBAL_MAC_23 0x02
181 #define GLOBAL_MAC_45 0x03
182 #define GLOBAL_ATU_FID 0x01 /* 6097 6165 6351 6352 */
183 #define GLOBAL_VTU_FID 0x02 /* 6097 6165 6351 6352 */
184 #define GLOBAL_VTU_FID_MASK 0xfff
185 #define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */
186 #define GLOBAL_VTU_SID_MASK 0x3f
187 #define GLOBAL_CONTROL 0x04
188 #define GLOBAL_CONTROL_SW_RESET BIT(15)
189 #define GLOBAL_CONTROL_PPU_ENABLE BIT(14)
190 #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */
191 #define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */
192 #define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */
193 #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */
194 #define GLOBAL_CONTROL_DEVICE_EN BIT(7)
195 #define GLOBAL_CONTROL_STATS_DONE_EN BIT(6)
196 #define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5)
197 #define GLOBAL_CONTROL_VTU_DONE_EN BIT(4)
198 #define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3)
199 #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
200 #define GLOBAL_CONTROL_TCAM_EN BIT(1)
201 #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
202 #define GLOBAL_VTU_OP 0x05
203 #define GLOBAL_VTU_OP_BUSY BIT(15)
204 #define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY)
205 #define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY)
206 #define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY)
207 #define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY)
208 #define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY)
209 #define GLOBAL_VTU_VID 0x06
210 #define GLOBAL_VTU_VID_MASK 0xfff
211 #define GLOBAL_VTU_VID_VALID BIT(12)
212 #define GLOBAL_VTU_DATA_0_3 0x07
213 #define GLOBAL_VTU_DATA_4_7 0x08
214 #define GLOBAL_VTU_DATA_8_11 0x09
215 #define GLOBAL_VTU_STU_DATA_MASK 0x03
216 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00
217 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01
218 #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02
219 #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03
220 #define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00
221 #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01
222 #define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02
223 #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03
224 #define GLOBAL_ATU_CONTROL 0x0a
225 #define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3)
226 #define GLOBAL_ATU_OP 0x0b
227 #define GLOBAL_ATU_OP_BUSY BIT(15)
228 #define GLOBAL_ATU_OP_NOP (0 << 12)
229 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
230 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY)
231 #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
232 #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
233 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
234 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
235 #define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY)
236 #define GLOBAL_ATU_DATA 0x0c
237 #define GLOBAL_ATU_DATA_TRUNK BIT(15)
238 #define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0
239 #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4
240 #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
241 #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
242 #define GLOBAL_ATU_DATA_STATE_MASK 0x0f
243 #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
244 #define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d
245 #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
246 #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f
247 #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05
248 #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
249 #define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e
250 #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f
251 #define GLOBAL_ATU_MAC_01 0x0d
252 #define GLOBAL_ATU_MAC_23 0x0e
253 #define GLOBAL_ATU_MAC_45 0x0f
254 #define GLOBAL_IP_PRI_0 0x10
255 #define GLOBAL_IP_PRI_1 0x11
256 #define GLOBAL_IP_PRI_2 0x12
257 #define GLOBAL_IP_PRI_3 0x13
258 #define GLOBAL_IP_PRI_4 0x14
259 #define GLOBAL_IP_PRI_5 0x15
260 #define GLOBAL_IP_PRI_6 0x16
261 #define GLOBAL_IP_PRI_7 0x17
262 #define GLOBAL_IEEE_PRI 0x18
263 #define GLOBAL_CORE_TAG_TYPE 0x19
264 #define GLOBAL_MONITOR_CONTROL 0x1a
265 #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12
266 #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8
267 #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4
268 #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0
269 #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0)
270 #define GLOBAL_CONTROL_2 0x1c
271 #define GLOBAL_CONTROL_2_NO_CASCADE 0xe000
272 #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000
273
274 #define GLOBAL_STATS_OP 0x1d
275 #define GLOBAL_STATS_OP_BUSY BIT(15)
276 #define GLOBAL_STATS_OP_NOP (0 << 12)
277 #define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY)
278 #define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY)
279 #define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY)
280 #define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY)
281 #define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY)
282 #define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY)
283 #define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY)
284 #define GLOBAL_STATS_COUNTER_32 0x1e
285 #define GLOBAL_STATS_COUNTER_01 0x1f
286
287 #define REG_GLOBAL2 0x1c
288 #define GLOBAL2_INT_SOURCE 0x00
289 #define GLOBAL2_INT_MASK 0x01
290 #define GLOBAL2_MGMT_EN_2X 0x02
291 #define GLOBAL2_MGMT_EN_0X 0x03
292 #define GLOBAL2_FLOW_CONTROL 0x04
293 #define GLOBAL2_SWITCH_MGMT 0x05
294 #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
295 #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14)
296 #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13)
297 #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
298 #define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3)
299 #define GLOBAL2_DEVICE_MAPPING 0x06
300 #define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15)
301 #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8
302 #define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f
303 #define GLOBAL2_TRUNK_MASK 0x07
304 #define GLOBAL2_TRUNK_MASK_UPDATE BIT(15)
305 #define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12
306 #define GLOBAL2_TRUNK_MAPPING 0x08
307 #define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15)
308 #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11
309 #define GLOBAL2_INGRESS_OP 0x09
310 #define GLOBAL2_INGRESS_DATA 0x0a
311 #define GLOBAL2_PVT_ADDR 0x0b
312 #define GLOBAL2_PVT_DATA 0x0c
313 #define GLOBAL2_SWITCH_MAC 0x0d
314 #define GLOBAL2_SWITCH_MAC_BUSY BIT(15)
315 #define GLOBAL2_ATU_STATS 0x0e
316 #define GLOBAL2_PRIO_OVERRIDE 0x0f
317 #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7)
318 #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4
319 #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3)
320 #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0
321 #define GLOBAL2_EEPROM_OP 0x14
322 #define GLOBAL2_EEPROM_OP_BUSY BIT(15)
323 #define GLOBAL2_EEPROM_OP_WRITE ((3 << 12) | GLOBAL2_EEPROM_OP_BUSY)
324 #define GLOBAL2_EEPROM_OP_READ ((4 << 12) | GLOBAL2_EEPROM_OP_BUSY)
325 #define GLOBAL2_EEPROM_OP_LOAD BIT(11)
326 #define GLOBAL2_EEPROM_OP_WRITE_EN BIT(10)
327 #define GLOBAL2_EEPROM_OP_ADDR_MASK 0xff
328 #define GLOBAL2_EEPROM_DATA 0x15
329 #define GLOBAL2_PTP_AVB_OP 0x16
330 #define GLOBAL2_PTP_AVB_DATA 0x17
331 #define GLOBAL2_SMI_OP 0x18
332 #define GLOBAL2_SMI_OP_BUSY BIT(15)
333 #define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12)
334 #define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \
335 GLOBAL2_SMI_OP_CLAUSE_22)
336 #define GLOBAL2_SMI_OP_22_READ ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \
337 GLOBAL2_SMI_OP_CLAUSE_22)
338 #define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) | GLOBAL2_SMI_OP_BUSY)
339 #define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) | GLOBAL2_SMI_OP_BUSY)
340 #define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) | GLOBAL2_SMI_OP_BUSY)
341 #define GLOBAL2_SMI_DATA 0x19
342 #define GLOBAL2_SCRATCH_MISC 0x1a
343 #define GLOBAL2_SCRATCH_BUSY BIT(15)
344 #define GLOBAL2_SCRATCH_REGISTER_SHIFT 8
345 #define GLOBAL2_SCRATCH_VALUE_MASK 0xff
346 #define GLOBAL2_WDOG_CONTROL 0x1b
347 #define GLOBAL2_QOS_WEIGHT 0x1c
348 #define GLOBAL2_MISC 0x1d
349
350 struct mv88e6xxx_atu_entry {
351 u16 fid;
352 u8 state;
353 bool trunk;
354 u16 portv_trunkid;
355 u8 mac[ETH_ALEN];
356 };
357
358 struct mv88e6xxx_vtu_stu_entry {
359 /* VTU only */
360 u16 vid;
361 u16 fid;
362
363 /* VTU and STU */
364 u8 sid;
365 bool valid;
366 u8 data[DSA_MAX_PORTS];
367 };
368
369 struct mv88e6xxx_priv_state {
370 /* When using multi-chip addressing, this mutex protects
371 * access to the indirect access registers. (In single-chip
372 * mode, this mutex is effectively useless.)
373 */
374 struct mutex smi_mutex;
375
376 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
377 /* Handles automatic disabling and re-enabling of the PHY
378 * polling unit.
379 */
380 struct mutex ppu_mutex;
381 int ppu_disabled;
382 struct work_struct ppu_work;
383 struct timer_list ppu_timer;
384 #endif
385
386 /* This mutex serialises access to the statistics unit.
387 * Hold this mutex over snapshot + dump sequences.
388 */
389 struct mutex stats_mutex;
390
391 /* This mutex serializes phy access for chips with
392 * indirect phy addressing. It is unused for chips
393 * with direct phy access.
394 */
395 struct mutex phy_mutex;
396
397 /* This mutex serializes eeprom access for chips with
398 * eeprom support.
399 */
400 struct mutex eeprom_mutex;
401
402 int id; /* switch product id */
403 int num_ports; /* number of switch ports */
404
405 unsigned long port_state_update_mask;
406 u8 port_state[DSA_MAX_PORTS];
407
408 struct work_struct bridge_work;
409
410 struct dentry *dbgfs;
411 };
412
413 struct mv88e6xxx_hw_stat {
414 char string[ETH_GSTRING_LEN];
415 int sizeof_stat;
416 int reg;
417 };
418
419 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active);
420 int mv88e6xxx_setup_ports(struct dsa_switch *ds);
421 int mv88e6xxx_setup_common(struct dsa_switch *ds);
422 int mv88e6xxx_setup_global(struct dsa_switch *ds);
423 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg);
424 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg);
425 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
426 int reg, u16 val);
427 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val);
428 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr);
429 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr);
430 int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum);
431 int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val);
432 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum);
433 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
434 u16 val);
435 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds);
436 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum);
437 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
438 int regnum, u16 val);
439 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data);
440 void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
441 uint64_t *data);
442 int mv88e6xxx_get_sset_count(struct dsa_switch *ds);
443 int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds);
444 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
445 struct phy_device *phydev);
446 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port);
447 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
448 struct ethtool_regs *regs, void *_p);
449 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp);
450 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp);
451 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp);
452 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm);
453 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds);
454 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds);
455 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum);
456 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
457 u16 val);
458 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e);
459 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
460 struct phy_device *phydev, struct ethtool_eee *e);
461 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
462 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
463 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state);
464 int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *vid);
465 int mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 vid);
466 int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
467 bool untagged);
468 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid);
469 int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid,
470 unsigned long *ports, unsigned long *untagged);
471 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
472 const struct switchdev_obj_port_fdb *fdb,
473 struct switchdev_trans *trans);
474 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
475 const struct switchdev_obj_port_fdb *fdb,
476 struct switchdev_trans *trans);
477 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
478 const struct switchdev_obj_port_fdb *fdb);
479 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
480 unsigned char *addr, u16 *vid, bool *is_static);
481 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg);
482 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
483 int reg, int val);
484
485 extern struct dsa_switch_driver mv88e6131_switch_driver;
486 extern struct dsa_switch_driver mv88e6123_61_65_switch_driver;
487 extern struct dsa_switch_driver mv88e6352_switch_driver;
488 extern struct dsa_switch_driver mv88e6171_switch_driver;
489
490 #define REG_READ(addr, reg) \
491 ({ \
492 int __ret; \
493 \
494 __ret = mv88e6xxx_reg_read(ds, addr, reg); \
495 if (__ret < 0) \
496 return __ret; \
497 __ret; \
498 })
499
500 #define REG_WRITE(addr, reg, val) \
501 ({ \
502 int __ret; \
503 \
504 __ret = mv88e6xxx_reg_write(ds, addr, reg, val); \
505 if (__ret < 0) \
506 return __ret; \
507 })
508
509
510
511 #endif
(deprecated) Btrfs devel tree