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ps3: Remove deprecated create_singlethread_workqueue
[linux-2.6/btrfs-unstable.git] / drivers / gpio / gpio-ep93xx.c
blob45d384039e9b1ca13c410fbbcfc3091a51e6bfb0
1 /*
2 * Generic EP93xx GPIO handling
3 *
4 * Copyright (c) 2008 Ryan Mallon
5 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
6 *
7 * Based on code originally from:
8 * linux/arch/arm/mach-ep93xx/core.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/slab.h>
21 #include <linux/gpio/driver.h>
22 /* FIXME: this is here for gpio_to_irq() - get rid of this! */
23 #include <linux/gpio.h>
24
25 #include <mach/hardware.h>
26 #include <mach/gpio-ep93xx.h>
27
28 #define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
29
30 struct ep93xx_gpio {
31 void __iomem *mmio_base;
32 struct gpio_chip gc[8];
33 };
34
35 /*************************************************************************
36 * Interrupt handling for EP93xx on-chip GPIOs
37 *************************************************************************/
38 static unsigned char gpio_int_unmasked[3];
39 static unsigned char gpio_int_enabled[3];
40 static unsigned char gpio_int_type1[3];
41 static unsigned char gpio_int_type2[3];
42 static unsigned char gpio_int_debounce[3];
43
44 /* Port ordering is: A B F */
45 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
46 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
47 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
48 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
49 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
50
51 static void ep93xx_gpio_update_int_params(unsigned port)
52 {
53 BUG_ON(port > 2);
54
55 writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
56
57 writeb_relaxed(gpio_int_type2[port],
58 EP93XX_GPIO_REG(int_type2_register_offset[port]));
59
60 writeb_relaxed(gpio_int_type1[port],
61 EP93XX_GPIO_REG(int_type1_register_offset[port]));
62
63 writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
64 EP93XX_GPIO_REG(int_en_register_offset[port]));
65 }
66
67 static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
68 {
69 int line = irq_to_gpio(irq);
70 int port = line >> 3;
71 int port_mask = 1 << (line & 7);
72
73 if (enable)
74 gpio_int_debounce[port] |= port_mask;
75 else
76 gpio_int_debounce[port] &= ~port_mask;
77
78 writeb(gpio_int_debounce[port],
79 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
80 }
81
82 static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
83 {
84 unsigned char status;
85 int i;
86
87 status = readb(EP93XX_GPIO_A_INT_STATUS);
88 for (i = 0; i < 8; i++) {
89 if (status & (1 << i)) {
90 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
91 generic_handle_irq(gpio_irq);
92 }
93 }
94
95 status = readb(EP93XX_GPIO_B_INT_STATUS);
96 for (i = 0; i < 8; i++) {
97 if (status & (1 << i)) {
98 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
99 generic_handle_irq(gpio_irq);
100 }
101 }
102 }
103
104 static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
105 {
106 /*
107 * map discontiguous hw irq range to continuous sw irq range:
108 *
109 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
110 */
111 unsigned int irq = irq_desc_get_irq(desc);
112 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
113 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
114
115 generic_handle_irq(gpio_irq);
116 }
117
118 static void ep93xx_gpio_irq_ack(struct irq_data *d)
119 {
120 int line = irq_to_gpio(d->irq);
121 int port = line >> 3;
122 int port_mask = 1 << (line & 7);
123
124 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
125 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
126 ep93xx_gpio_update_int_params(port);
127 }
128
129 writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
130 }
131
132 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
133 {
134 int line = irq_to_gpio(d->irq);
135 int port = line >> 3;
136 int port_mask = 1 << (line & 7);
137
138 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
139 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
140
141 gpio_int_unmasked[port] &= ~port_mask;
142 ep93xx_gpio_update_int_params(port);
143
144 writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
145 }
146
147 static void ep93xx_gpio_irq_mask(struct irq_data *d)
148 {
149 int line = irq_to_gpio(d->irq);
150 int port = line >> 3;
151
152 gpio_int_unmasked[port] &= ~(1 << (line & 7));
153 ep93xx_gpio_update_int_params(port);
154 }
155
156 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
157 {
158 int line = irq_to_gpio(d->irq);
159 int port = line >> 3;
160
161 gpio_int_unmasked[port] |= 1 << (line & 7);
162 ep93xx_gpio_update_int_params(port);
163 }
164
165 /*
166 * gpio_int_type1 controls whether the interrupt is level (0) or
167 * edge (1) triggered, while gpio_int_type2 controls whether it
168 * triggers on low/falling (0) or high/rising (1).
169 */
170 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
171 {
172 const int gpio = irq_to_gpio(d->irq);
173 const int port = gpio >> 3;
174 const int port_mask = 1 << (gpio & 7);
175 irq_flow_handler_t handler;
176
177 gpio_direction_input(gpio);
178
179 switch (type) {
180 case IRQ_TYPE_EDGE_RISING:
181 gpio_int_type1[port] |= port_mask;
182 gpio_int_type2[port] |= port_mask;
183 handler = handle_edge_irq;
184 break;
185 case IRQ_TYPE_EDGE_FALLING:
186 gpio_int_type1[port] |= port_mask;
187 gpio_int_type2[port] &= ~port_mask;
188 handler = handle_edge_irq;
189 break;
190 case IRQ_TYPE_LEVEL_HIGH:
191 gpio_int_type1[port] &= ~port_mask;
192 gpio_int_type2[port] |= port_mask;
193 handler = handle_level_irq;
194 break;
195 case IRQ_TYPE_LEVEL_LOW:
196 gpio_int_type1[port] &= ~port_mask;
197 gpio_int_type2[port] &= ~port_mask;
198 handler = handle_level_irq;
199 break;
200 case IRQ_TYPE_EDGE_BOTH:
201 gpio_int_type1[port] |= port_mask;
202 /* set initial polarity based on current input level */
203 if (gpio_get_value(gpio))
204 gpio_int_type2[port] &= ~port_mask; /* falling */
205 else
206 gpio_int_type2[port] |= port_mask; /* rising */
207 handler = handle_edge_irq;
208 break;
209 default:
210 return -EINVAL;
211 }
212
213 irq_set_handler_locked(d, handler);
214
215 gpio_int_enabled[port] |= port_mask;
216
217 ep93xx_gpio_update_int_params(port);
218
219 return 0;
220 }
221
222 static struct irq_chip ep93xx_gpio_irq_chip = {
223 .name = "GPIO",
224 .irq_ack = ep93xx_gpio_irq_ack,
225 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
226 .irq_mask = ep93xx_gpio_irq_mask,
227 .irq_unmask = ep93xx_gpio_irq_unmask,
228 .irq_set_type = ep93xx_gpio_irq_type,
229 };
230
231 static void ep93xx_gpio_init_irq(void)
232 {
233 int gpio_irq;
234
235 for (gpio_irq = gpio_to_irq(0);
236 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
237 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
238 handle_level_irq);
239 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
240 }
241
242 irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
243 ep93xx_gpio_ab_irq_handler);
244 irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
245 ep93xx_gpio_f_irq_handler);
246 irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
247 ep93xx_gpio_f_irq_handler);
248 irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
249 ep93xx_gpio_f_irq_handler);
250 irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
251 ep93xx_gpio_f_irq_handler);
252 irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
253 ep93xx_gpio_f_irq_handler);
254 irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
255 ep93xx_gpio_f_irq_handler);
256 irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
257 ep93xx_gpio_f_irq_handler);
258 irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
259 ep93xx_gpio_f_irq_handler);
260 }
261
262
263 /*************************************************************************
264 * gpiolib interface for EP93xx on-chip GPIOs
265 *************************************************************************/
266 struct ep93xx_gpio_bank {
267 const char *label;
268 int data;
269 int dir;
270 int base;
271 bool has_debounce;
272 };
273
274 #define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
275 { \
276 .label = _label, \
277 .data = _data, \
278 .dir = _dir, \
279 .base = _base, \
280 .has_debounce = _debounce, \
281 }
282
283 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
284 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
285 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
286 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
287 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
288 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
289 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
290 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
291 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
292 };
293
294 static int ep93xx_gpio_set_config(struct gpio_chip *chip, unsigned offset,
295 unsigned long config)
296 {
297 int gpio = chip->base + offset;
298 int irq = gpio_to_irq(gpio);
299 u32 debounce;
300
301 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
302 return -ENOTSUPP;
303
304 if (irq < 0)
305 return -EINVAL;
306
307 debounce = pinconf_to_config_argument(config);
308 ep93xx_gpio_int_debounce(irq, debounce ? true : false);
309
310 return 0;
311 }
312
313 /*
314 * Map GPIO A0..A7 (0..7) to irq 64..71,
315 * B0..B7 (7..15) to irq 72..79, and
316 * F0..F7 (16..24) to irq 80..87.
317 */
318 static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
319 {
320 int gpio = chip->base + offset;
321
322 if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
323 return -EINVAL;
324
325 return 64 + gpio;
326 }
327
328 static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev,
329 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
330 {
331 void __iomem *data = mmio_base + bank->data;
332 void __iomem *dir = mmio_base + bank->dir;
333 int err;
334
335 err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
336 if (err)
337 return err;
338
339 gc->label = bank->label;
340 gc->base = bank->base;
341
342 if (bank->has_debounce) {
343 gc->set_config = ep93xx_gpio_set_config;
344 gc->to_irq = ep93xx_gpio_to_irq;
345 }
346
347 return devm_gpiochip_add_data(dev, gc, NULL);
348 }
349
350 static int ep93xx_gpio_probe(struct platform_device *pdev)
351 {
352 struct ep93xx_gpio *ep93xx_gpio;
353 struct resource *res;
354 int i;
355 struct device *dev = &pdev->dev;
356
357 ep93xx_gpio = devm_kzalloc(dev, sizeof(struct ep93xx_gpio), GFP_KERNEL);
358 if (!ep93xx_gpio)
359 return -ENOMEM;
360
361 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
362 ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res);
363 if (IS_ERR(ep93xx_gpio->mmio_base))
364 return PTR_ERR(ep93xx_gpio->mmio_base);
365
366 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
367 struct gpio_chip *gc = &ep93xx_gpio->gc[i];
368 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
369
370 if (ep93xx_gpio_add_bank(gc, &pdev->dev,
371 ep93xx_gpio->mmio_base, bank))
372 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
373 bank->label);
374 }
375
376 ep93xx_gpio_init_irq();
377
378 return 0;
379 }
380
381 static struct platform_driver ep93xx_gpio_driver = {
382 .driver = {
383 .name = "gpio-ep93xx",
384 },
385 .probe = ep93xx_gpio_probe,
386 };
387
388 static int __init ep93xx_gpio_init(void)
389 {
390 return platform_driver_register(&ep93xx_gpio_driver);
391 }
392 postcore_initcall(ep93xx_gpio_init);
393
394 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
395 "H Hartley Sweeten <hsweeten@visionengravers.com>");
396 MODULE_DESCRIPTION("EP93XX GPIO driver");
397 MODULE_LICENSE("GPL");
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