arch/mips/au1000/common/setup.c

   1 /*
   2  * Copyright 2000 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc.
   4  *              ppopov@mvista.com or source@mvista.com
   5  *
   6  * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28 #include <linux/config.h>
  29 #include <linux/init.h>
  30 #include <linux/sched.h>
  31 #include <linux/ioport.h>
  32 #include <linux/mm.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/module.h>
  36
  37 #include <asm/cpu.h>
  38 #include <asm/bootinfo.h>
  39 #include <asm/irq.h>
  40 #include <asm/mipsregs.h>
  41 #include <asm/reboot.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/mach-au1x00/au1000.h>
  44 #include <asm/time.h>
  45
  46 extern char * __init prom_getcmdline(void);
  47 extern void __init board_setup(void);
  48 extern void au1000_restart(char *);
  49 extern void au1000_halt(void);
  50 extern void au1000_power_off(void);
  51 extern struct resource ioport_resource;
  52 extern struct resource iomem_resource;
  53 extern void (*board_time_init)(void);
  54 extern void au1x_time_init(void);
  55 extern void (*board_timer_setup)(struct irqaction *irq);
  56 extern void au1x_timer_setup(struct irqaction *irq);
  57 extern void au1xxx_time_init(void);
  58 extern void au1xxx_timer_setup(struct irqaction *irq);
  59 extern void set_cpuspec(void);
  60
  61 void __init plat_setup(void)
  62 {
  63         struct  cpu_spec *sp;
  64         char *argptr;
  65         unsigned long prid, cpupll, bclk = 1;
  66
  67         set_cpuspec();
  68         sp = cur_cpu_spec[0];
  69
  70         board_setup();  /* board specific setup */
  71
  72         prid = read_c0_prid();
  73         cpupll = (au_readl(0xB1900060) & 0x3F) * 12;
  74         printk("(PRId %08lx) @ %ldMHZ\n", prid, cpupll);
  75
  76         bclk = sp->cpu_bclk;
  77         if (bclk)
  78         {
  79                 /* Enable BCLK switching */
  80                 bclk = au_readl(0xB190003C);
  81                 au_writel(bclk | 0x60, 0xB190003C);
  82                 printk("BCLK switching enabled!\n");
  83         }
  84
  85         if (sp->cpu_od) {
  86                 /* Various early Au1000 Errata corrected by this */
  87                 set_c0_config(1<<19); /* Set Config[OD] */
  88         }
  89         else {
  90                 /* Clear to obtain best system bus performance */
  91                 clear_c0_config(1<<19); /* Clear Config[OD] */
  92         }
  93
  94         argptr = prom_getcmdline();
  95
  96 #ifdef CONFIG_SERIAL_AU1X00_CONSOLE
  97         if ((argptr = strstr(argptr, "console=")) == NULL) {
  98                 argptr = prom_getcmdline();
  99                 strcat(argptr, " console=ttyS0,115200");
 100         }
 101 #endif
 102
 103 #ifdef CONFIG_FB_AU1100
 104     if ((argptr = strstr(argptr, "video=")) == NULL) {
 105         argptr = prom_getcmdline();
 106         /* default panel */
 107         /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
 108 #ifdef CONFIG_MIPS_HYDROGEN3
 109          strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor");
 110 #endif
 111     }
 112 #endif
 113
 114 #ifdef CONFIG_FB_E1356
 115         if ((argptr = strstr(argptr, "video=")) == NULL) {
 116                 argptr = prom_getcmdline();
 117 #ifdef CONFIG_MIPS_PB1000
 118                 strcat(argptr, " video=e1356fb:system:pb1000,mmunalign:1");
 119 #else
 120                 strcat(argptr, " video=e1356fb:system:pb1500");
 121 #endif
 122         }
 123 #endif
 124
 125 #ifdef CONFIG_FB_XPERT98
 126         if ((argptr = strstr(argptr, "video=")) == NULL) {
 127                 argptr = prom_getcmdline();
 128                 strcat(argptr, " video=atyfb:1024x768-8@70");
 129         }
 130 #endif
 131
 132 #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
 133         /* au1000 does not support vra, au1500 and au1100 do */
 134         strcat(argptr, " au1000_audio=vra");
 135         argptr = prom_getcmdline();
 136 #endif
 137         _machine_restart = au1000_restart;
 138         _machine_halt = au1000_halt;
 139         _machine_power_off = au1000_power_off;
 140         board_time_init = au1xxx_time_init;
 141         board_timer_setup = au1xxx_timer_setup;
 142
 143         /* IO/MEM resources. */
 144         set_io_port_base(0);
 145         ioport_resource.start = IOPORT_RESOURCE_START;
 146         ioport_resource.end = IOPORT_RESOURCE_END;
 147         iomem_resource.start = IOMEM_RESOURCE_START;
 148         iomem_resource.end = IOMEM_RESOURCE_END;
 149
 150         while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
 151         au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
 152         au_sync();
 153         while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
 154         au_writel(0, SYS_TOYTRIM);
 155 }
 156
 157 #if defined(CONFIG_64BIT_PHYS_ADDR)
 158 /* This routine should be valid for all Au1x based boards */
 159 phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
 160 {
 161         u32 start, end;
 162
 163         /* Don't fixup 36 bit addresses */
 164         if ((phys_addr >> 32) != 0) return phys_addr;
 165
 166 #ifdef CONFIG_PCI
 167         start = (u32)Au1500_PCI_MEM_START;
 168         end = (u32)Au1500_PCI_MEM_END;
 169         /* check for pci memory window */
 170         if ((phys_addr >= start) && ((phys_addr + size) < end)) {
 171                 return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START);
 172         }
 173 #endif
 174
 175         /* All Au1x SOCs have a pcmcia controller */
 176         /* We setup our 32 bit pseudo addresses to be equal to the
 177          * 36 bit addr >> 4, to make it easier to check the address
 178          * and fix it.
 179          * The Au1x socket 0 phys attribute address is 0xF 4000 0000.
 180          * The pseudo address we use is 0xF400 0000. Any address over
 181          * 0xF400 0000 is a pcmcia pseudo address.
 182          */
 183         if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) {
 184                 return (phys_t)(phys_addr << 4);
 185         }
 186
 187         /* default nop */
 188         return phys_addr;
 189 }
 190 EXPORT_SYMBOL(__fixup_bigphys_addr);
 191 #endif