2 * ACPI support for Intel Lynxpoint LPSS.
4 * Copyright (C) 2013, Intel Corporation
5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/acpi.h>
14 #include <linux/clk.h>
15 #include <linux/clkdev.h>
16 #include <linux/clk-provider.h>
17 #include <linux/err.h>
19 #include <linux/platform_device.h>
20 #include <linux/platform_data/clk-lpss.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/delay.h>
26 ACPI_MODULE_NAME("acpi_lpss");
28 #ifdef CONFIG_X86_INTEL_LPSS
30 #define LPSS_ADDR(desc) ((unsigned long)&desc)
32 #define LPSS_CLK_SIZE 0x04
33 #define LPSS_LTR_SIZE 0x18
35 /* Offsets relative to LPSS_PRIVATE_OFFSET */
36 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
37 #define LPSS_RESETS 0x04
38 #define LPSS_RESETS_RESET_FUNC BIT(0)
39 #define LPSS_RESETS_RESET_APB BIT(1)
40 #define LPSS_GENERAL 0x08
41 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
42 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
43 #define LPSS_SW_LTR 0x10
44 #define LPSS_AUTO_LTR 0x14
45 #define LPSS_LTR_SNOOP_REQ BIT(15)
46 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
47 #define LPSS_LTR_SNOOP_LAT_1US 0x800
48 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
49 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
50 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
51 #define LPSS_LTR_MAX_VAL 0x3FF
52 #define LPSS_TX_INT 0x20
53 #define LPSS_TX_INT_MASK BIT(1)
55 #define LPSS_PRV_REG_COUNT 9
58 #define LPSS_CLK BIT(0)
59 #define LPSS_CLK_GATE BIT(1)
60 #define LPSS_CLK_DIVIDER BIT(2)
61 #define LPSS_LTR BIT(3)
62 #define LPSS_SAVE_CTX BIT(4)
64 struct lpss_private_data
;
66 struct lpss_device_desc
{
68 const char *clk_con_id
;
69 unsigned int prv_offset
;
70 size_t prv_size_override
;
71 void (*setup
)(struct lpss_private_data
*pdata
);
74 static struct lpss_device_desc lpss_dma_desc
= {
78 struct lpss_private_data
{
79 void __iomem
*mmio_base
;
80 resource_size_t mmio_size
;
81 unsigned int fixed_clk_rate
;
83 const struct lpss_device_desc
*dev_desc
;
84 u32 prv_reg_ctx
[LPSS_PRV_REG_COUNT
];
87 /* UART Component Parameter Register */
88 #define LPSS_UART_CPR 0xF4
89 #define LPSS_UART_CPR_AFCE BIT(4)
91 static void lpss_uart_setup(struct lpss_private_data
*pdata
)
96 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_TX_INT
;
97 val
= readl(pdata
->mmio_base
+ offset
);
98 writel(val
| LPSS_TX_INT_MASK
, pdata
->mmio_base
+ offset
);
100 val
= readl(pdata
->mmio_base
+ LPSS_UART_CPR
);
101 if (!(val
& LPSS_UART_CPR_AFCE
)) {
102 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_GENERAL
;
103 val
= readl(pdata
->mmio_base
+ offset
);
104 val
|= LPSS_GENERAL_UART_RTS_OVRD
;
105 writel(val
, pdata
->mmio_base
+ offset
);
109 static void lpss_deassert_reset(struct lpss_private_data
*pdata
)
114 offset
= pdata
->dev_desc
->prv_offset
+ LPSS_RESETS
;
115 val
= readl(pdata
->mmio_base
+ offset
);
116 val
|= LPSS_RESETS_RESET_APB
| LPSS_RESETS_RESET_FUNC
;
117 writel(val
, pdata
->mmio_base
+ offset
);
120 #define LPSS_I2C_ENABLE 0x6c
122 static void byt_i2c_setup(struct lpss_private_data
*pdata
)
124 lpss_deassert_reset(pdata
);
126 if (readl(pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
))
127 pdata
->fixed_clk_rate
= 133000000;
129 writel(0, pdata
->mmio_base
+ LPSS_I2C_ENABLE
);
132 static struct lpss_device_desc lpt_dev_desc
= {
133 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_LTR
,
137 static struct lpss_device_desc lpt_i2c_dev_desc
= {
138 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_LTR
,
142 static struct lpss_device_desc lpt_uart_dev_desc
= {
143 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_LTR
,
144 .clk_con_id
= "baudclk",
146 .setup
= lpss_uart_setup
,
149 static struct lpss_device_desc lpt_sdio_dev_desc
= {
151 .prv_offset
= 0x1000,
152 .prv_size_override
= 0x1018,
155 static struct lpss_device_desc byt_pwm_dev_desc
= {
156 .flags
= LPSS_SAVE_CTX
,
159 static struct lpss_device_desc byt_uart_dev_desc
= {
160 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
,
161 .clk_con_id
= "baudclk",
163 .setup
= lpss_uart_setup
,
166 static struct lpss_device_desc byt_spi_dev_desc
= {
167 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
,
171 static struct lpss_device_desc byt_sdio_dev_desc
= {
175 static struct lpss_device_desc byt_i2c_dev_desc
= {
176 .flags
= LPSS_CLK
| LPSS_SAVE_CTX
,
178 .setup
= byt_i2c_setup
,
181 static struct lpss_device_desc bsw_spi_dev_desc
= {
182 .flags
= LPSS_CLK
| LPSS_CLK_GATE
| LPSS_CLK_DIVIDER
| LPSS_SAVE_CTX
,
184 .setup
= lpss_deassert_reset
,
189 #define LPSS_ADDR(desc) (0UL)
191 #endif /* CONFIG_X86_INTEL_LPSS */
193 static const struct acpi_device_id acpi_lpss_device_ids
[] = {
194 /* Generic LPSS devices */
195 { "INTL9C60", LPSS_ADDR(lpss_dma_desc
) },
197 /* Lynxpoint LPSS devices */
198 { "INT33C0", LPSS_ADDR(lpt_dev_desc
) },
199 { "INT33C1", LPSS_ADDR(lpt_dev_desc
) },
200 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc
) },
201 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc
) },
202 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc
) },
203 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc
) },
204 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc
) },
207 /* BayTrail LPSS devices */
208 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc
) },
209 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc
) },
210 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc
) },
211 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc
) },
212 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc
) },
216 /* Braswell LPSS devices */
217 { "80862288", LPSS_ADDR(byt_pwm_dev_desc
) },
218 { "8086228A", LPSS_ADDR(byt_uart_dev_desc
) },
219 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc
) },
220 { "808622C1", LPSS_ADDR(byt_i2c_dev_desc
) },
222 { "INT3430", LPSS_ADDR(lpt_dev_desc
) },
223 { "INT3431", LPSS_ADDR(lpt_dev_desc
) },
224 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc
) },
225 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc
) },
226 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc
) },
227 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc
) },
228 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc
) },
231 /* Wildcat Point LPSS devices */
232 { "INT3438", LPSS_ADDR(lpt_dev_desc
) },
237 #ifdef CONFIG_X86_INTEL_LPSS
239 static int is_memory(struct acpi_resource
*res
, void *not_used
)
242 return !acpi_dev_resource_memory(res
, &r
);
245 /* LPSS main clock device. */
246 static struct platform_device
*lpss_clk_dev
;
248 static inline void lpt_register_clock_device(void)
250 lpss_clk_dev
= platform_device_register_simple("clk-lpt", -1, NULL
, 0);
253 static int register_device_clock(struct acpi_device
*adev
,
254 struct lpss_private_data
*pdata
)
256 const struct lpss_device_desc
*dev_desc
= pdata
->dev_desc
;
257 const char *devname
= dev_name(&adev
->dev
);
258 struct clk
*clk
= ERR_PTR(-ENODEV
);
259 struct lpss_clk_data
*clk_data
;
260 const char *parent
, *clk_name
;
261 void __iomem
*prv_base
;
264 lpt_register_clock_device();
266 clk_data
= platform_get_drvdata(lpss_clk_dev
);
271 if (!pdata
->mmio_base
272 || pdata
->mmio_size
< dev_desc
->prv_offset
+ LPSS_CLK_SIZE
)
275 parent
= clk_data
->name
;
276 prv_base
= pdata
->mmio_base
+ dev_desc
->prv_offset
;
278 if (pdata
->fixed_clk_rate
) {
279 clk
= clk_register_fixed_rate(NULL
, devname
, parent
, 0,
280 pdata
->fixed_clk_rate
);
284 if (dev_desc
->flags
& LPSS_CLK_GATE
) {
285 clk
= clk_register_gate(NULL
, devname
, parent
, 0,
286 prv_base
, 0, 0, NULL
);
290 if (dev_desc
->flags
& LPSS_CLK_DIVIDER
) {
291 /* Prevent division by zero */
292 if (!readl(prv_base
))
293 writel(LPSS_CLK_DIVIDER_DEF_MASK
, prv_base
);
295 clk_name
= kasprintf(GFP_KERNEL
, "%s-div", devname
);
298 clk
= clk_register_fractional_divider(NULL
, clk_name
, parent
,
300 1, 15, 16, 15, 0, NULL
);
303 clk_name
= kasprintf(GFP_KERNEL
, "%s-update", devname
);
308 clk
= clk_register_gate(NULL
, clk_name
, parent
,
309 CLK_SET_RATE_PARENT
| CLK_SET_RATE_GATE
,
310 prv_base
, 31, 0, NULL
);
319 clk_register_clkdev(clk
, dev_desc
->clk_con_id
, devname
);
323 static int acpi_lpss_create_device(struct acpi_device
*adev
,
324 const struct acpi_device_id
*id
)
326 struct lpss_device_desc
*dev_desc
;
327 struct lpss_private_data
*pdata
;
328 struct resource_entry
*rentry
;
329 struct list_head resource_list
;
330 struct platform_device
*pdev
;
333 dev_desc
= (struct lpss_device_desc
*)id
->driver_data
;
335 pdev
= acpi_create_platform_device(adev
);
336 return IS_ERR_OR_NULL(pdev
) ? PTR_ERR(pdev
) : 1;
338 pdata
= kzalloc(sizeof(*pdata
), GFP_KERNEL
);
342 INIT_LIST_HEAD(&resource_list
);
343 ret
= acpi_dev_get_resources(adev
, &resource_list
, is_memory
, NULL
);
347 list_for_each_entry(rentry
, &resource_list
, node
)
348 if (resource_type(rentry
->res
) == IORESOURCE_MEM
) {
349 if (dev_desc
->prv_size_override
)
350 pdata
->mmio_size
= dev_desc
->prv_size_override
;
352 pdata
->mmio_size
= resource_size(rentry
->res
);
353 pdata
->mmio_base
= ioremap(rentry
->res
->start
,
355 if (!pdata
->mmio_base
)
360 acpi_dev_free_resource_list(&resource_list
);
362 pdata
->dev_desc
= dev_desc
;
365 dev_desc
->setup(pdata
);
367 if (dev_desc
->flags
& LPSS_CLK
) {
368 ret
= register_device_clock(adev
, pdata
);
370 /* Skip the device, but continue the namespace scan. */
377 * This works around a known issue in ACPI tables where LPSS devices
378 * have _PS0 and _PS3 without _PSC (and no power resources), so
379 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
381 ret
= acpi_device_fix_up_power(adev
);
383 /* Skip the device, but continue the namespace scan. */
388 adev
->driver_data
= pdata
;
389 pdev
= acpi_create_platform_device(adev
);
390 if (!IS_ERR_OR_NULL(pdev
)) {
395 adev
->driver_data
= NULL
;
402 static u32
__lpss_reg_read(struct lpss_private_data
*pdata
, unsigned int reg
)
404 return readl(pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
+ reg
);
407 static void __lpss_reg_write(u32 val
, struct lpss_private_data
*pdata
,
410 writel(val
, pdata
->mmio_base
+ pdata
->dev_desc
->prv_offset
+ reg
);
413 static int lpss_reg_read(struct device
*dev
, unsigned int reg
, u32
*val
)
415 struct acpi_device
*adev
;
416 struct lpss_private_data
*pdata
;
420 ret
= acpi_bus_get_device(ACPI_HANDLE(dev
), &adev
);
424 spin_lock_irqsave(&dev
->power
.lock
, flags
);
425 if (pm_runtime_suspended(dev
)) {
429 pdata
= acpi_driver_data(adev
);
430 if (WARN_ON(!pdata
|| !pdata
->mmio_base
)) {
434 *val
= __lpss_reg_read(pdata
, reg
);
437 spin_unlock_irqrestore(&dev
->power
.lock
, flags
);
441 static ssize_t
lpss_ltr_show(struct device
*dev
, struct device_attribute
*attr
,
448 reg
= strcmp(attr
->attr
.name
, "auto_ltr") ? LPSS_SW_LTR
: LPSS_AUTO_LTR
;
449 ret
= lpss_reg_read(dev
, reg
, <r_value
);
453 return snprintf(buf
, PAGE_SIZE
, "%08x\n", ltr_value
);
456 static ssize_t
lpss_ltr_mode_show(struct device
*dev
,
457 struct device_attribute
*attr
, char *buf
)
463 ret
= lpss_reg_read(dev
, LPSS_GENERAL
, <r_mode
);
467 outstr
= (ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
) ? "sw" : "auto";
468 return sprintf(buf
, "%s\n", outstr
);
471 static DEVICE_ATTR(auto_ltr
, S_IRUSR
, lpss_ltr_show
, NULL
);
472 static DEVICE_ATTR(sw_ltr
, S_IRUSR
, lpss_ltr_show
, NULL
);
473 static DEVICE_ATTR(ltr_mode
, S_IRUSR
, lpss_ltr_mode_show
, NULL
);
475 static struct attribute
*lpss_attrs
[] = {
476 &dev_attr_auto_ltr
.attr
,
477 &dev_attr_sw_ltr
.attr
,
478 &dev_attr_ltr_mode
.attr
,
482 static struct attribute_group lpss_attr_group
= {
487 static void acpi_lpss_set_ltr(struct device
*dev
, s32 val
)
489 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
490 u32 ltr_mode
, ltr_val
;
492 ltr_mode
= __lpss_reg_read(pdata
, LPSS_GENERAL
);
494 if (ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
) {
495 ltr_mode
&= ~LPSS_GENERAL_LTR_MODE_SW
;
496 __lpss_reg_write(ltr_mode
, pdata
, LPSS_GENERAL
);
500 ltr_val
= __lpss_reg_read(pdata
, LPSS_SW_LTR
) & ~LPSS_LTR_SNOOP_MASK
;
501 if (val
>= LPSS_LTR_SNOOP_LAT_CUTOFF
) {
502 ltr_val
|= LPSS_LTR_SNOOP_LAT_32US
;
503 val
= LPSS_LTR_MAX_VAL
;
504 } else if (val
> LPSS_LTR_MAX_VAL
) {
505 ltr_val
|= LPSS_LTR_SNOOP_LAT_32US
| LPSS_LTR_SNOOP_REQ
;
506 val
>>= LPSS_LTR_SNOOP_LAT_SHIFT
;
508 ltr_val
|= LPSS_LTR_SNOOP_LAT_1US
| LPSS_LTR_SNOOP_REQ
;
511 __lpss_reg_write(ltr_val
, pdata
, LPSS_SW_LTR
);
512 if (!(ltr_mode
& LPSS_GENERAL_LTR_MODE_SW
)) {
513 ltr_mode
|= LPSS_GENERAL_LTR_MODE_SW
;
514 __lpss_reg_write(ltr_mode
, pdata
, LPSS_GENERAL
);
520 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
522 * @pdata: pointer to the private data of the LPSS device
524 * Most LPSS devices have private registers which may loose their context when
525 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
528 static void acpi_lpss_save_ctx(struct device
*dev
,
529 struct lpss_private_data
*pdata
)
533 for (i
= 0; i
< LPSS_PRV_REG_COUNT
; i
++) {
534 unsigned long offset
= i
* sizeof(u32
);
536 pdata
->prv_reg_ctx
[i
] = __lpss_reg_read(pdata
, offset
);
537 dev_dbg(dev
, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
538 pdata
->prv_reg_ctx
[i
], offset
);
543 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
545 * @pdata: pointer to the private data of the LPSS device
547 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
549 static void acpi_lpss_restore_ctx(struct device
*dev
,
550 struct lpss_private_data
*pdata
)
555 * The following delay is needed or the subsequent write operations may
556 * fail. The LPSS devices are actually PCI devices and the PCI spec
557 * expects 10ms delay before the device can be accessed after D3 to D0
562 for (i
= 0; i
< LPSS_PRV_REG_COUNT
; i
++) {
563 unsigned long offset
= i
* sizeof(u32
);
565 __lpss_reg_write(pdata
->prv_reg_ctx
[i
], pdata
, offset
);
566 dev_dbg(dev
, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
567 pdata
->prv_reg_ctx
[i
], offset
);
571 #ifdef CONFIG_PM_SLEEP
572 static int acpi_lpss_suspend_late(struct device
*dev
)
574 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
577 ret
= pm_generic_suspend_late(dev
);
581 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
582 acpi_lpss_save_ctx(dev
, pdata
);
584 return acpi_dev_suspend_late(dev
);
587 static int acpi_lpss_resume_early(struct device
*dev
)
589 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
592 ret
= acpi_dev_resume_early(dev
);
596 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
597 acpi_lpss_restore_ctx(dev
, pdata
);
599 return pm_generic_resume_early(dev
);
601 #endif /* CONFIG_PM_SLEEP */
603 static int acpi_lpss_runtime_suspend(struct device
*dev
)
605 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
608 ret
= pm_generic_runtime_suspend(dev
);
612 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
613 acpi_lpss_save_ctx(dev
, pdata
);
615 return acpi_dev_runtime_suspend(dev
);
618 static int acpi_lpss_runtime_resume(struct device
*dev
)
620 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
623 ret
= acpi_dev_runtime_resume(dev
);
627 if (pdata
->dev_desc
->flags
& LPSS_SAVE_CTX
)
628 acpi_lpss_restore_ctx(dev
, pdata
);
630 return pm_generic_runtime_resume(dev
);
632 #endif /* CONFIG_PM */
634 static struct dev_pm_domain acpi_lpss_pm_domain
= {
637 #ifdef CONFIG_PM_SLEEP
638 .prepare
= acpi_subsys_prepare
,
639 .complete
= acpi_subsys_complete
,
640 .suspend
= acpi_subsys_suspend
,
641 .suspend_late
= acpi_lpss_suspend_late
,
642 .resume_early
= acpi_lpss_resume_early
,
643 .freeze
= acpi_subsys_freeze
,
644 .poweroff
= acpi_subsys_suspend
,
645 .poweroff_late
= acpi_lpss_suspend_late
,
646 .restore_early
= acpi_lpss_resume_early
,
648 .runtime_suspend
= acpi_lpss_runtime_suspend
,
649 .runtime_resume
= acpi_lpss_runtime_resume
,
654 static int acpi_lpss_platform_notify(struct notifier_block
*nb
,
655 unsigned long action
, void *data
)
657 struct platform_device
*pdev
= to_platform_device(data
);
658 struct lpss_private_data
*pdata
;
659 struct acpi_device
*adev
;
660 const struct acpi_device_id
*id
;
662 id
= acpi_match_device(acpi_lpss_device_ids
, &pdev
->dev
);
663 if (!id
|| !id
->driver_data
)
666 if (acpi_bus_get_device(ACPI_HANDLE(&pdev
->dev
), &adev
))
669 pdata
= acpi_driver_data(adev
);
673 if (pdata
->mmio_base
&&
674 pdata
->mmio_size
< pdata
->dev_desc
->prv_offset
+ LPSS_LTR_SIZE
) {
675 dev_err(&pdev
->dev
, "MMIO size insufficient to access LTR\n");
680 case BUS_NOTIFY_ADD_DEVICE
:
681 pdev
->dev
.pm_domain
= &acpi_lpss_pm_domain
;
682 if (pdata
->dev_desc
->flags
& LPSS_LTR
)
683 return sysfs_create_group(&pdev
->dev
.kobj
,
686 case BUS_NOTIFY_DEL_DEVICE
:
687 if (pdata
->dev_desc
->flags
& LPSS_LTR
)
688 sysfs_remove_group(&pdev
->dev
.kobj
, &lpss_attr_group
);
689 pdev
->dev
.pm_domain
= NULL
;
698 static struct notifier_block acpi_lpss_nb
= {
699 .notifier_call
= acpi_lpss_platform_notify
,
702 static void acpi_lpss_bind(struct device
*dev
)
704 struct lpss_private_data
*pdata
= acpi_driver_data(ACPI_COMPANION(dev
));
706 if (!pdata
|| !pdata
->mmio_base
|| !(pdata
->dev_desc
->flags
& LPSS_LTR
))
709 if (pdata
->mmio_size
>= pdata
->dev_desc
->prv_offset
+ LPSS_LTR_SIZE
)
710 dev
->power
.set_latency_tolerance
= acpi_lpss_set_ltr
;
712 dev_err(dev
, "MMIO size insufficient to access LTR\n");
715 static void acpi_lpss_unbind(struct device
*dev
)
717 dev
->power
.set_latency_tolerance
= NULL
;
720 static struct acpi_scan_handler lpss_handler
= {
721 .ids
= acpi_lpss_device_ids
,
722 .attach
= acpi_lpss_create_device
,
723 .bind
= acpi_lpss_bind
,
724 .unbind
= acpi_lpss_unbind
,
727 void __init
acpi_lpss_init(void)
729 if (!lpt_clk_init()) {
730 bus_register_notifier(&platform_bus_type
, &acpi_lpss_nb
);
731 acpi_scan_add_handler(&lpss_handler
);
737 static struct acpi_scan_handler lpss_handler
= {
738 .ids
= acpi_lpss_device_ids
,
741 void __init
acpi_lpss_init(void)
743 acpi_scan_add_handler(&lpss_handler
);
746 #endif /* CONFIG_X86_INTEL_LPSS */