2 * Copyright © 2006-2007 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Eric Anholt <eric@anholt.net>
21 #include <linux/i2c.h>
22 #include <linux/pm_runtime.h>
27 #include "psb_intel_drv.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_display.h"
30 #include "psb_powermgmt.h"
33 struct psb_intel_clock_t
{
45 struct psb_intel_range_t
{
49 struct psb_intel_p2_t
{
54 #define INTEL_P2_NUM 2
56 struct psb_intel_limit_t
{
57 struct psb_intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
58 struct psb_intel_p2_t p2
;
61 #define I8XX_DOT_MIN 25000
62 #define I8XX_DOT_MAX 350000
63 #define I8XX_VCO_MIN 930000
64 #define I8XX_VCO_MAX 1400000
68 #define I8XX_M_MAX 140
69 #define I8XX_M1_MIN 18
70 #define I8XX_M1_MAX 26
72 #define I8XX_M2_MAX 16
74 #define I8XX_P_MAX 128
76 #define I8XX_P1_MAX 33
77 #define I8XX_P1_LVDS_MIN 1
78 #define I8XX_P1_LVDS_MAX 6
79 #define I8XX_P2_SLOW 4
80 #define I8XX_P2_FAST 2
81 #define I8XX_P2_LVDS_SLOW 14
82 #define I8XX_P2_LVDS_FAST 14 /* No fast option */
83 #define I8XX_P2_SLOW_LIMIT 165000
85 #define I9XX_DOT_MIN 20000
86 #define I9XX_DOT_MAX 400000
87 #define I9XX_VCO_MIN 1400000
88 #define I9XX_VCO_MAX 2800000
92 #define I9XX_M_MAX 120
93 #define I9XX_M1_MIN 10
94 #define I9XX_M1_MAX 20
97 #define I9XX_P_SDVO_DAC_MIN 5
98 #define I9XX_P_SDVO_DAC_MAX 80
99 #define I9XX_P_LVDS_MIN 7
100 #define I9XX_P_LVDS_MAX 98
101 #define I9XX_P1_MIN 1
102 #define I9XX_P1_MAX 8
103 #define I9XX_P2_SDVO_DAC_SLOW 10
104 #define I9XX_P2_SDVO_DAC_FAST 5
105 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
106 #define I9XX_P2_LVDS_SLOW 14
107 #define I9XX_P2_LVDS_FAST 7
108 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
110 #define INTEL_LIMIT_I8XX_DVO_DAC 0
111 #define INTEL_LIMIT_I8XX_LVDS 1
112 #define INTEL_LIMIT_I9XX_SDVO_DAC 2
113 #define INTEL_LIMIT_I9XX_LVDS 3
115 static const struct psb_intel_limit_t psb_intel_limits
[] = {
116 { /* INTEL_LIMIT_I8XX_DVO_DAC */
117 .dot
= {.min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
118 .vco
= {.min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
119 .n
= {.min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
120 .m
= {.min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
121 .m1
= {.min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
122 .m2
= {.min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
123 .p
= {.min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
124 .p1
= {.min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
125 .p2
= {.dot_limit
= I8XX_P2_SLOW_LIMIT
,
126 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
128 { /* INTEL_LIMIT_I8XX_LVDS */
129 .dot
= {.min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
130 .vco
= {.min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
131 .n
= {.min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
132 .m
= {.min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
133 .m1
= {.min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
134 .m2
= {.min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
135 .p
= {.min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
136 .p1
= {.min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
137 .p2
= {.dot_limit
= I8XX_P2_SLOW_LIMIT
,
138 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
140 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
141 .dot
= {.min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
142 .vco
= {.min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
143 .n
= {.min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
144 .m
= {.min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
145 .m1
= {.min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
146 .m2
= {.min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
147 .p
= {.min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
148 .p1
= {.min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
149 .p2
= {.dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
150 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
=
151 I9XX_P2_SDVO_DAC_FAST
},
153 { /* INTEL_LIMIT_I9XX_LVDS */
154 .dot
= {.min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
155 .vco
= {.min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
156 .n
= {.min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
157 .m
= {.min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
158 .m1
= {.min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
159 .m2
= {.min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
160 .p
= {.min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
161 .p1
= {.min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
162 /* The single-channel range is 25-112Mhz, and dual-channel
163 * is 80-224Mhz. Prefer single channel as much as possible.
165 .p2
= {.dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
166 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
170 static const struct psb_intel_limit_t
*psb_intel_limit(struct drm_crtc
*crtc
)
172 const struct psb_intel_limit_t
*limit
;
174 if (psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
175 limit
= &psb_intel_limits
[INTEL_LIMIT_I9XX_LVDS
];
177 limit
= &psb_intel_limits
[INTEL_LIMIT_I9XX_SDVO_DAC
];
181 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
183 static void i8xx_clock(int refclk
, struct psb_intel_clock_t
*clock
)
185 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
186 clock
->p
= clock
->p1
* clock
->p2
;
187 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
188 clock
->dot
= clock
->vco
/ clock
->p
;
191 /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */
193 static void i9xx_clock(int refclk
, struct psb_intel_clock_t
*clock
)
195 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
196 clock
->p
= clock
->p1
* clock
->p2
;
197 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
198 clock
->dot
= clock
->vco
/ clock
->p
;
201 static void psb_intel_clock(struct drm_device
*dev
, int refclk
,
202 struct psb_intel_clock_t
*clock
)
204 return i9xx_clock(refclk
, clock
);
208 * Returns whether any output on the specified pipe is of the specified type
210 bool psb_intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
212 struct drm_device
*dev
= crtc
->dev
;
213 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
214 struct drm_connector
*l_entry
;
216 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
217 if (l_entry
->encoder
&& l_entry
->encoder
->crtc
== crtc
) {
218 struct psb_intel_output
*psb_intel_output
=
219 to_psb_intel_output(l_entry
);
220 if (psb_intel_output
->type
== type
)
227 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
229 * Returns whether the given set of divisors are valid for a given refclk with
230 * the given connectors.
233 static bool psb_intel_PLL_is_valid(struct drm_crtc
*crtc
,
234 struct psb_intel_clock_t
*clock
)
236 const struct psb_intel_limit_t
*limit
= psb_intel_limit(crtc
);
238 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
239 INTELPllInvalid("p1 out of range\n");
240 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
241 INTELPllInvalid("p out of range\n");
242 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
243 INTELPllInvalid("m2 out of range\n");
244 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
245 INTELPllInvalid("m1 out of range\n");
246 if (clock
->m1
<= clock
->m2
)
247 INTELPllInvalid("m1 <= m2\n");
248 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
249 INTELPllInvalid("m out of range\n");
250 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
251 INTELPllInvalid("n out of range\n");
252 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
253 INTELPllInvalid("vco out of range\n");
254 /* XXX: We may need to be checking "Dot clock"
255 * depending on the multiplier, connector, etc.,
256 * rather than just a single range.
258 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
259 INTELPllInvalid("dot out of range\n");
265 * Returns a set of divisors for the desired target clock with the given
266 * refclk, or FALSE. The returned values represent the clock equation:
267 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
269 static bool psb_intel_find_best_PLL(struct drm_crtc
*crtc
, int target
,
271 struct psb_intel_clock_t
*best_clock
)
273 struct drm_device
*dev
= crtc
->dev
;
274 struct psb_intel_clock_t clock
;
275 const struct psb_intel_limit_t
*limit
= psb_intel_limit(crtc
);
278 if (psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
279 (REG_READ(LVDS
) & LVDS_PORT_EN
) != 0) {
281 * For LVDS, if the panel is on, just rely on its current
282 * settings for dual-channel. We haven't figured out how to
283 * reliably set up different single/dual channel state, if we
286 if ((REG_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
288 clock
.p2
= limit
->p2
.p2_fast
;
290 clock
.p2
= limit
->p2
.p2_slow
;
292 if (target
< limit
->p2
.dot_limit
)
293 clock
.p2
= limit
->p2
.p2_slow
;
295 clock
.p2
= limit
->p2
.p2_fast
;
298 memset(best_clock
, 0, sizeof(*best_clock
));
300 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
302 for (clock
.m2
= limit
->m2
.min
;
303 clock
.m2
< clock
.m1
&& clock
.m2
<= limit
->m2
.max
;
305 for (clock
.n
= limit
->n
.min
;
306 clock
.n
<= limit
->n
.max
; clock
.n
++) {
307 for (clock
.p1
= limit
->p1
.min
;
308 clock
.p1
<= limit
->p1
.max
;
312 psb_intel_clock(dev
, refclk
, &clock
);
314 if (!psb_intel_PLL_is_valid
318 this_err
= abs(clock
.dot
- target
);
319 if (this_err
< err
) {
328 return err
!= target
;
331 void psb_intel_wait_for_vblank(struct drm_device
*dev
)
333 /* Wait for 20ms, i.e. one cycle at 50hz. */
337 int psb_intel_pipe_set_base(struct drm_crtc
*crtc
,
338 int x
, int y
, struct drm_framebuffer
*old_fb
)
340 struct drm_device
*dev
= crtc
->dev
;
341 /* struct drm_i915_master_private *master_priv; */
342 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
343 struct psb_framebuffer
*psbfb
= to_psb_fb(crtc
->fb
);
344 int pipe
= psb_intel_crtc
->pipe
;
345 unsigned long start
, offset
;
346 int dspbase
= (pipe
== 0 ? DSPABASE
: DSPBBASE
);
347 int dspsurf
= (pipe
== 0 ? DSPASURF
: DSPBSURF
);
348 int dspstride
= (pipe
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
349 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
353 PSB_DEBUG_ENTRY("\n");
357 DRM_DEBUG("No FB bound\n");
361 if (!gma_power_begin(dev
, true))
364 /* We are displaying this buffer, make sure it is actually loaded
366 ret
= psb_gtt_pin(psbfb
->gtt
);
368 goto psb_intel_pipe_set_base_exit
;
369 start
= psbfb
->gtt
->offset
;
371 offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
373 REG_WRITE(dspstride
, crtc
->fb
->pitch
);
375 dspcntr
= REG_READ(dspcntr_reg
);
376 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
378 switch (crtc
->fb
->bits_per_pixel
) {
380 dspcntr
|= DISPPLANE_8BPP
;
383 if (crtc
->fb
->depth
== 15)
384 dspcntr
|= DISPPLANE_15_16BPP
;
386 dspcntr
|= DISPPLANE_16BPP
;
390 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
393 DRM_ERROR("Unknown color depth\n");
395 psb_gtt_unpin(psbfb
->gtt
);
396 goto psb_intel_pipe_set_base_exit
;
398 REG_WRITE(dspcntr_reg
, dspcntr
);
401 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", start
, offset
, x
, y
);
402 if (0 /* FIXMEAC - check what PSB needs */) {
403 REG_WRITE(dspbase
, offset
);
405 REG_WRITE(dspsurf
, start
);
408 REG_WRITE(dspbase
, start
+ offset
);
412 /* If there was a previous display we can now unpin it */
414 psb_gtt_unpin(to_psb_fb(old_fb
)->gtt
);
416 psb_intel_pipe_set_base_exit
:
422 * Sets the power management mode of the pipe and plane.
424 * This code should probably grow support for turning the cursor off and back
425 * on appropriately at the same time as we're turning the pipe off/on.
427 static void psb_intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
429 struct drm_device
*dev
= crtc
->dev
;
430 /* struct drm_i915_master_private *master_priv; */
431 /* struct drm_i915_private *dev_priv = dev->dev_private; */
432 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
433 int pipe
= psb_intel_crtc
->pipe
;
434 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
435 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
436 int dspbase_reg
= (pipe
== 0) ? DSPABASE
: DSPBBASE
;
437 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
441 /* XXX: When our outputs are all unaware of DPMS modes other than off
442 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
445 case DRM_MODE_DPMS_ON
:
446 case DRM_MODE_DPMS_STANDBY
:
447 case DRM_MODE_DPMS_SUSPEND
:
448 /* Enable the DPLL */
449 temp
= REG_READ(dpll_reg
);
450 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
451 REG_WRITE(dpll_reg
, temp
);
453 /* Wait for the clocks to stabilize. */
455 REG_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
457 /* Wait for the clocks to stabilize. */
459 REG_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
461 /* Wait for the clocks to stabilize. */
465 /* Enable the pipe */
466 temp
= REG_READ(pipeconf_reg
);
467 if ((temp
& PIPEACONF_ENABLE
) == 0)
468 REG_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
470 /* Enable the plane */
471 temp
= REG_READ(dspcntr_reg
);
472 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
473 REG_WRITE(dspcntr_reg
,
474 temp
| DISPLAY_PLANE_ENABLE
);
475 /* Flush the plane changes */
476 REG_WRITE(dspbase_reg
, REG_READ(dspbase_reg
));
479 psb_intel_crtc_load_lut(crtc
);
481 /* Give the overlay scaler a chance to enable
482 * if it's on this pipe */
483 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
485 case DRM_MODE_DPMS_OFF
:
486 /* Give the overlay scaler a chance to disable
487 * if it's on this pipe */
488 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
490 /* Disable the VGA plane that we never use */
491 REG_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
493 /* Disable display plane */
494 temp
= REG_READ(dspcntr_reg
);
495 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
496 REG_WRITE(dspcntr_reg
,
497 temp
& ~DISPLAY_PLANE_ENABLE
);
498 /* Flush the plane changes */
499 REG_WRITE(dspbase_reg
, REG_READ(dspbase_reg
));
500 REG_READ(dspbase_reg
);
503 /* Next, disable display pipes */
504 temp
= REG_READ(pipeconf_reg
);
505 if ((temp
& PIPEACONF_ENABLE
) != 0) {
506 REG_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
507 REG_READ(pipeconf_reg
);
510 /* Wait for vblank for the disable to take effect. */
511 psb_intel_wait_for_vblank(dev
);
513 temp
= REG_READ(dpll_reg
);
514 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
515 REG_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
519 /* Wait for the clocks to turn off. */
524 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
526 /*Set FIFO Watermarks*/
527 REG_WRITE(DSPARB
, 0x3F3E);
530 static void psb_intel_crtc_prepare(struct drm_crtc
*crtc
)
532 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
533 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
536 static void psb_intel_crtc_commit(struct drm_crtc
*crtc
)
538 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
539 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
542 void psb_intel_encoder_prepare(struct drm_encoder
*encoder
)
544 struct drm_encoder_helper_funcs
*encoder_funcs
=
545 encoder
->helper_private
;
546 /* lvds has its own version of prepare see psb_intel_lvds_prepare */
547 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
550 void psb_intel_encoder_commit(struct drm_encoder
*encoder
)
552 struct drm_encoder_helper_funcs
*encoder_funcs
=
553 encoder
->helper_private
;
554 /* lvds has its own version of commit see psb_intel_lvds_commit */
555 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
558 static bool psb_intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
559 struct drm_display_mode
*mode
,
560 struct drm_display_mode
*adjusted_mode
)
567 * Return the pipe currently connected to the panel fitter,
568 * or -1 if the panel fitter is not present or not in use
570 static int psb_intel_panel_fitter_pipe(struct drm_device
*dev
)
574 pfit_control
= REG_READ(PFIT_CONTROL
);
576 /* See if the panel fitter is in use */
577 if ((pfit_control
& PFIT_ENABLE
) == 0)
579 /* Must be on PIPE 1 for PSB */
583 static int psb_intel_crtc_mode_set(struct drm_crtc
*crtc
,
584 struct drm_display_mode
*mode
,
585 struct drm_display_mode
*adjusted_mode
,
587 struct drm_framebuffer
*old_fb
)
589 struct drm_device
*dev
= crtc
->dev
;
590 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
591 int pipe
= psb_intel_crtc
->pipe
;
592 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
593 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
594 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
595 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
596 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
597 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
598 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
599 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
600 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
601 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
602 int dspsize_reg
= (pipe
== 0) ? DSPASIZE
: DSPBSIZE
;
603 int dsppos_reg
= (pipe
== 0) ? DSPAPOS
: DSPBPOS
;
604 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
606 struct psb_intel_clock_t clock
;
607 u32 dpll
= 0, fp
= 0, dspcntr
, pipeconf
;
608 bool ok
, is_sdvo
= false, is_dvo
= false;
609 bool is_crt
= false, is_lvds
= false, is_tv
= false;
610 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
611 struct drm_connector
*connector
;
613 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
614 struct psb_intel_output
*psb_intel_output
=
615 to_psb_intel_output(connector
);
617 if (!connector
->encoder
618 || connector
->encoder
->crtc
!= crtc
)
621 switch (psb_intel_output
->type
) {
622 case INTEL_OUTPUT_LVDS
:
625 case INTEL_OUTPUT_SDVO
:
628 case INTEL_OUTPUT_DVO
:
631 case INTEL_OUTPUT_TVOUT
:
634 case INTEL_OUTPUT_ANALOG
:
642 ok
= psb_intel_find_best_PLL(crtc
, adjusted_mode
->clock
, refclk
,
645 DRM_ERROR("Couldn't find PLL settings for mode!\n");
649 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
651 dpll
= DPLL_VGA_MODE_DIS
;
653 dpll
|= DPLLB_MODE_LVDS
;
654 dpll
|= DPLL_DVO_HIGH_SPEED
;
656 dpll
|= DPLLB_MODE_DAC_SERIAL
;
658 int sdvo_pixel_multiply
=
659 adjusted_mode
->clock
/ mode
->clock
;
660 dpll
|= DPLL_DVO_HIGH_SPEED
;
662 (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
665 /* compute bitmask from p1 value */
666 dpll
|= (1 << (clock
.p1
- 1)) << 16;
669 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
672 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
675 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
678 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
683 /* XXX: just matching BIOS for now */
684 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
687 dpll
|= PLL_REF_INPUT_DREFCLK
;
690 pipeconf
= REG_READ(pipeconf_reg
);
692 /* Set up the display plane register */
693 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
696 dspcntr
|= DISPPLANE_SEL_PIPE_A
;
698 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
700 dspcntr
|= DISPLAY_PLANE_ENABLE
;
701 pipeconf
|= PIPEACONF_ENABLE
;
702 dpll
|= DPLL_VCO_ENABLE
;
705 /* Disable the panel fitter if it was on our pipe */
706 if (psb_intel_panel_fitter_pipe(dev
) == pipe
)
707 REG_WRITE(PFIT_CONTROL
, 0);
709 DRM_DEBUG("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
710 drm_mode_debug_printmodeline(mode
);
712 if (dpll
& DPLL_VCO_ENABLE
) {
713 REG_WRITE(fp_reg
, fp
);
714 REG_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
719 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
720 * This is an exception to the general rule that mode_set doesn't turn
724 u32 lvds
= REG_READ(LVDS
);
727 LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
|
729 /* Set the B0-B3 data pairs corresponding to
730 * whether we're going to
731 * set the DPLLs for dual-channel mode or not.
734 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
736 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
738 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
739 * appropriately here, but we need to look more
740 * thoroughly into how panels behave in the two modes.
743 REG_WRITE(LVDS
, lvds
);
747 REG_WRITE(fp_reg
, fp
);
748 REG_WRITE(dpll_reg
, dpll
);
750 /* Wait for the clocks to stabilize. */
753 /* write it again -- the BIOS does, after all */
754 REG_WRITE(dpll_reg
, dpll
);
757 /* Wait for the clocks to stabilize. */
760 REG_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
761 ((adjusted_mode
->crtc_htotal
- 1) << 16));
762 REG_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
763 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
764 REG_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
765 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
766 REG_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
767 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
768 REG_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
769 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
770 REG_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
771 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
772 /* pipesrc and dspsize control the size that is scaled from,
773 * which should always be the user's requested size.
775 REG_WRITE(dspsize_reg
,
776 ((mode
->vdisplay
- 1) << 16) | (mode
->hdisplay
- 1));
777 REG_WRITE(dsppos_reg
, 0);
778 REG_WRITE(pipesrc_reg
,
779 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
780 REG_WRITE(pipeconf_reg
, pipeconf
);
781 REG_READ(pipeconf_reg
);
783 psb_intel_wait_for_vblank(dev
);
785 REG_WRITE(dspcntr_reg
, dspcntr
);
787 /* Flush the plane changes */
789 struct drm_crtc_helper_funcs
*crtc_funcs
=
790 crtc
->helper_private
;
791 crtc_funcs
->mode_set_base(crtc
, x
, y
, old_fb
);
794 psb_intel_wait_for_vblank(dev
);
799 /** Loads the palette/gamma unit for the CRTC with the prepared values */
800 void psb_intel_crtc_load_lut(struct drm_crtc
*crtc
)
802 struct drm_device
*dev
= crtc
->dev
;
803 struct drm_psb_private
*dev_priv
=
804 (struct drm_psb_private
*)dev
->dev_private
;
805 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
806 int palreg
= PALETTE_A
;
809 /* The clocks have to be on to load the palette. */
813 switch (psb_intel_crtc
->pipe
) {
823 DRM_ERROR("Illegal Pipe Number.\n");
827 if (gma_power_begin(dev
, false)) {
828 for (i
= 0; i
< 256; i
++) {
829 REG_WRITE(palreg
+ 4 * i
,
830 ((psb_intel_crtc
->lut_r
[i
] +
831 psb_intel_crtc
->lut_adj
[i
]) << 16) |
832 ((psb_intel_crtc
->lut_g
[i
] +
833 psb_intel_crtc
->lut_adj
[i
]) << 8) |
834 (psb_intel_crtc
->lut_b
[i
] +
835 psb_intel_crtc
->lut_adj
[i
]));
839 for (i
= 0; i
< 256; i
++) {
840 dev_priv
->save_palette_a
[i
] =
841 ((psb_intel_crtc
->lut_r
[i
] +
842 psb_intel_crtc
->lut_adj
[i
]) << 16) |
843 ((psb_intel_crtc
->lut_g
[i
] +
844 psb_intel_crtc
->lut_adj
[i
]) << 8) |
845 (psb_intel_crtc
->lut_b
[i
] +
846 psb_intel_crtc
->lut_adj
[i
]);
853 * Save HW states of giving crtc
855 static void psb_intel_crtc_save(struct drm_crtc
*crtc
)
857 struct drm_device
*dev
= crtc
->dev
;
858 /* struct drm_psb_private *dev_priv =
859 (struct drm_psb_private *)dev->dev_private; */
860 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
861 struct psb_intel_crtc_state
*crtc_state
= psb_intel_crtc
->crtc_state
;
862 int pipeA
= (psb_intel_crtc
->pipe
== 0);
869 DRM_DEBUG("No CRTC state found\n");
873 crtc_state
->saveDSPCNTR
= REG_READ(pipeA
? DSPACNTR
: DSPBCNTR
);
874 crtc_state
->savePIPECONF
= REG_READ(pipeA
? PIPEACONF
: PIPEBCONF
);
875 crtc_state
->savePIPESRC
= REG_READ(pipeA
? PIPEASRC
: PIPEBSRC
);
876 crtc_state
->saveFP0
= REG_READ(pipeA
? FPA0
: FPB0
);
877 crtc_state
->saveFP1
= REG_READ(pipeA
? FPA1
: FPB1
);
878 crtc_state
->saveDPLL
= REG_READ(pipeA
? DPLL_A
: DPLL_B
);
879 crtc_state
->saveHTOTAL
= REG_READ(pipeA
? HTOTAL_A
: HTOTAL_B
);
880 crtc_state
->saveHBLANK
= REG_READ(pipeA
? HBLANK_A
: HBLANK_B
);
881 crtc_state
->saveHSYNC
= REG_READ(pipeA
? HSYNC_A
: HSYNC_B
);
882 crtc_state
->saveVTOTAL
= REG_READ(pipeA
? VTOTAL_A
: VTOTAL_B
);
883 crtc_state
->saveVBLANK
= REG_READ(pipeA
? VBLANK_A
: VBLANK_B
);
884 crtc_state
->saveVSYNC
= REG_READ(pipeA
? VSYNC_A
: VSYNC_B
);
885 crtc_state
->saveDSPSTRIDE
= REG_READ(pipeA
? DSPASTRIDE
: DSPBSTRIDE
);
887 /*NOTE: DSPSIZE DSPPOS only for psb*/
888 crtc_state
->saveDSPSIZE
= REG_READ(pipeA
? DSPASIZE
: DSPBSIZE
);
889 crtc_state
->saveDSPPOS
= REG_READ(pipeA
? DSPAPOS
: DSPBPOS
);
891 crtc_state
->saveDSPBASE
= REG_READ(pipeA
? DSPABASE
: DSPBBASE
);
893 DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
894 crtc_state
->saveDSPCNTR
,
895 crtc_state
->savePIPECONF
,
896 crtc_state
->savePIPESRC
,
899 crtc_state
->saveDPLL
,
900 crtc_state
->saveHTOTAL
,
901 crtc_state
->saveHBLANK
,
902 crtc_state
->saveHSYNC
,
903 crtc_state
->saveVTOTAL
,
904 crtc_state
->saveVBLANK
,
905 crtc_state
->saveVSYNC
,
906 crtc_state
->saveDSPSTRIDE
,
907 crtc_state
->saveDSPSIZE
,
908 crtc_state
->saveDSPPOS
,
909 crtc_state
->saveDSPBASE
912 paletteReg
= pipeA
? PALETTE_A
: PALETTE_B
;
913 for (i
= 0; i
< 256; ++i
)
914 crtc_state
->savePalette
[i
] = REG_READ(paletteReg
+ (i
<< 2));
918 * Restore HW states of giving crtc
920 static void psb_intel_crtc_restore(struct drm_crtc
*crtc
)
922 struct drm_device
*dev
= crtc
->dev
;
923 /* struct drm_psb_private * dev_priv =
924 (struct drm_psb_private *)dev->dev_private; */
925 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
926 struct psb_intel_crtc_state
*crtc_state
= psb_intel_crtc
->crtc_state
;
927 /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */
928 int pipeA
= (psb_intel_crtc
->pipe
== 0);
935 DRM_DEBUG("No crtc state\n");
940 "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
941 REG_READ(pipeA
? DSPACNTR
: DSPBCNTR
),
942 REG_READ(pipeA
? PIPEACONF
: PIPEBCONF
),
943 REG_READ(pipeA
? PIPEASRC
: PIPEBSRC
),
944 REG_READ(pipeA
? FPA0
: FPB0
),
945 REG_READ(pipeA
? FPA1
: FPB1
),
946 REG_READ(pipeA
? DPLL_A
: DPLL_B
),
947 REG_READ(pipeA
? HTOTAL_A
: HTOTAL_B
),
948 REG_READ(pipeA
? HBLANK_A
: HBLANK_B
),
949 REG_READ(pipeA
? HSYNC_A
: HSYNC_B
),
950 REG_READ(pipeA
? VTOTAL_A
: VTOTAL_B
),
951 REG_READ(pipeA
? VBLANK_A
: VBLANK_B
),
952 REG_READ(pipeA
? VSYNC_A
: VSYNC_B
),
953 REG_READ(pipeA
? DSPASTRIDE
: DSPBSTRIDE
),
954 REG_READ(pipeA
? DSPASIZE
: DSPBSIZE
),
955 REG_READ(pipeA
? DSPAPOS
: DSPBPOS
),
956 REG_READ(pipeA
? DSPABASE
: DSPBBASE
)
960 "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
961 crtc_state
->saveDSPCNTR
,
962 crtc_state
->savePIPECONF
,
963 crtc_state
->savePIPESRC
,
966 crtc_state
->saveDPLL
,
967 crtc_state
->saveHTOTAL
,
968 crtc_state
->saveHBLANK
,
969 crtc_state
->saveHSYNC
,
970 crtc_state
->saveVTOTAL
,
971 crtc_state
->saveVBLANK
,
972 crtc_state
->saveVSYNC
,
973 crtc_state
->saveDSPSTRIDE
,
974 crtc_state
->saveDSPSIZE
,
975 crtc_state
->saveDSPPOS
,
976 crtc_state
->saveDSPBASE
980 if (crtc_state
->saveDPLL
& DPLL_VCO_ENABLE
) {
981 REG_WRITE(pipeA
? DPLL_A
: DPLL_B
,
982 crtc_state
->saveDPLL
& ~DPLL_VCO_ENABLE
);
983 REG_READ(pipeA
? DPLL_A
: DPLL_B
);
984 DRM_DEBUG("write dpll: %x\n",
985 REG_READ(pipeA
? DPLL_A
: DPLL_B
));
989 REG_WRITE(pipeA
? FPA0
: FPB0
, crtc_state
->saveFP0
);
990 REG_READ(pipeA
? FPA0
: FPB0
);
992 REG_WRITE(pipeA
? FPA1
: FPB1
, crtc_state
->saveFP1
);
993 REG_READ(pipeA
? FPA1
: FPB1
);
995 REG_WRITE(pipeA
? DPLL_A
: DPLL_B
, crtc_state
->saveDPLL
);
996 REG_READ(pipeA
? DPLL_A
: DPLL_B
);
999 REG_WRITE(pipeA
? HTOTAL_A
: HTOTAL_B
, crtc_state
->saveHTOTAL
);
1000 REG_WRITE(pipeA
? HBLANK_A
: HBLANK_B
, crtc_state
->saveHBLANK
);
1001 REG_WRITE(pipeA
? HSYNC_A
: HSYNC_B
, crtc_state
->saveHSYNC
);
1002 REG_WRITE(pipeA
? VTOTAL_A
: VTOTAL_B
, crtc_state
->saveVTOTAL
);
1003 REG_WRITE(pipeA
? VBLANK_A
: VBLANK_B
, crtc_state
->saveVBLANK
);
1004 REG_WRITE(pipeA
? VSYNC_A
: VSYNC_B
, crtc_state
->saveVSYNC
);
1005 REG_WRITE(pipeA
? DSPASTRIDE
: DSPBSTRIDE
, crtc_state
->saveDSPSTRIDE
);
1007 REG_WRITE(pipeA
? DSPASIZE
: DSPBSIZE
, crtc_state
->saveDSPSIZE
);
1008 REG_WRITE(pipeA
? DSPAPOS
: DSPBPOS
, crtc_state
->saveDSPPOS
);
1010 REG_WRITE(pipeA
? PIPEASRC
: PIPEBSRC
, crtc_state
->savePIPESRC
);
1011 REG_WRITE(pipeA
? DSPABASE
: DSPBBASE
, crtc_state
->saveDSPBASE
);
1012 REG_WRITE(pipeA
? PIPEACONF
: PIPEBCONF
, crtc_state
->savePIPECONF
);
1014 psb_intel_wait_for_vblank(dev
);
1016 REG_WRITE(pipeA
? DSPACNTR
: DSPBCNTR
, crtc_state
->saveDSPCNTR
);
1017 REG_WRITE(pipeA
? DSPABASE
: DSPBBASE
, crtc_state
->saveDSPBASE
);
1019 psb_intel_wait_for_vblank(dev
);
1021 paletteReg
= pipeA
? PALETTE_A
: PALETTE_B
;
1022 for (i
= 0; i
< 256; ++i
)
1023 REG_WRITE(paletteReg
+ (i
<< 2), crtc_state
->savePalette
[i
]);
1026 static int psb_intel_crtc_cursor_set(struct drm_crtc
*crtc
,
1027 struct drm_file
*file_priv
,
1029 uint32_t width
, uint32_t height
)
1031 struct drm_device
*dev
= crtc
->dev
;
1032 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1033 int pipe
= psb_intel_crtc
->pipe
;
1034 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
1035 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
1038 struct gtt_range
*gt
;
1039 struct drm_gem_object
*obj
;
1044 /* if we want to turn of the cursor ignore width and height */
1046 DRM_DEBUG("cursor off\n");
1047 /* turn off the cursor */
1048 temp
= CURSOR_MODE_DISABLE
;
1050 if (gma_power_begin(dev
, false)) {
1051 REG_WRITE(control
, temp
);
1056 /* Unpin the old GEM object */
1057 if (psb_intel_crtc
->cursor_obj
) {
1058 gt
= container_of(psb_intel_crtc
->cursor_obj
,
1059 struct gtt_range
, gem
);
1061 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
1062 psb_intel_crtc
->cursor_obj
= NULL
;
1068 /* Currently we only support 64x64 cursors */
1069 if (width
!= 64 || height
!= 64) {
1070 DRM_ERROR("we currently only support 64x64 cursors\n");
1074 obj
= drm_gem_object_lookup(dev
, file_priv
, handle
);
1078 if (obj
->size
< width
* height
* 4) {
1079 DRM_ERROR("buffer is to small\n");
1083 gt
= container_of(obj
, struct gtt_range
, gem
);
1085 /* Pin the memory into the GTT */
1086 ret
= psb_gtt_pin(gt
);
1088 DRM_ERROR("Can not pin down handle 0x%x\n", handle
);
1093 addr
= gt
->offset
; /* Or resource.start ??? */
1095 psb_intel_crtc
->cursor_addr
= addr
;
1098 /* set the pipe for the cursor */
1099 temp
|= (pipe
<< 28);
1100 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
1102 if (gma_power_begin(dev
, false)) {
1103 REG_WRITE(control
, temp
);
1104 REG_WRITE(base
, addr
);
1108 /* unpin the old bo */
1109 if (psb_intel_crtc
->cursor_obj
&& psb_intel_crtc
->cursor_obj
!= obj
) {
1110 gt
= container_of(psb_intel_crtc
->cursor_obj
,
1111 struct gtt_range
, gem
);
1113 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
1114 psb_intel_crtc
->cursor_obj
= obj
;
1120 static int psb_intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
1122 struct drm_device
*dev
= crtc
->dev
;
1123 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1124 int pipe
= psb_intel_crtc
->pipe
;
1130 temp
|= (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
);
1134 temp
|= (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
);
1138 temp
|= ((x
& CURSOR_POS_MASK
) << CURSOR_X_SHIFT
);
1139 temp
|= ((y
& CURSOR_POS_MASK
) << CURSOR_Y_SHIFT
);
1141 addr
= psb_intel_crtc
->cursor_addr
;
1143 if (gma_power_begin(dev
, false)) {
1144 REG_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
1145 REG_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, addr
);
1151 static void psb_intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
,
1152 u16
*green
, u16
*blue
, uint32_t type
, uint32_t size
)
1154 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1160 for (i
= 0; i
< 256; i
++) {
1161 psb_intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
1162 psb_intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
1163 psb_intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
1166 psb_intel_crtc_load_lut(crtc
);
1169 static int psb_crtc_set_config(struct drm_mode_set
*set
)
1172 struct drm_device
*dev
= set
->crtc
->dev
;
1173 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1175 if (!dev_priv
->rpm_enabled
)
1176 return drm_crtc_helper_set_config(set
);
1178 pm_runtime_forbid(&dev
->pdev
->dev
);
1179 ret
= drm_crtc_helper_set_config(set
);
1180 pm_runtime_allow(&dev
->pdev
->dev
);
1184 /* Returns the clock of the currently programmed mode of the given pipe. */
1185 static int psb_intel_crtc_clock_get(struct drm_device
*dev
,
1186 struct drm_crtc
*crtc
)
1188 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1189 int pipe
= psb_intel_crtc
->pipe
;
1192 struct psb_intel_clock_t clock
;
1194 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1196 if (gma_power_begin(dev
, false)) {
1197 dpll
= REG_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
1198 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
1199 fp
= REG_READ((pipe
== 0) ? FPA0
: FPB0
);
1201 fp
= REG_READ((pipe
== 0) ? FPA1
: FPB1
);
1202 is_lvds
= (pipe
== 1) && (REG_READ(LVDS
) & LVDS_PORT_EN
);
1205 dpll
= (pipe
== 0) ?
1206 dev_priv
->saveDPLL_A
: dev_priv
->saveDPLL_B
;
1208 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
1210 dev_priv
->saveFPA0
:
1214 dev_priv
->saveFPA1
:
1217 is_lvds
= (pipe
== 1) && (dev_priv
->saveLVDS
& LVDS_PORT_EN
);
1220 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
1221 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
1222 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
1227 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
1228 DPLL_FPA01_P1_POST_DIV_SHIFT
);
1231 if ((dpll
& PLL_REF_INPUT_MASK
) ==
1232 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
1233 /* XXX: might not be 66MHz */
1234 i8xx_clock(66000, &clock
);
1236 i8xx_clock(48000, &clock
);
1238 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
1243 DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
1244 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
1246 if (dpll
& PLL_P2_DIVIDE_BY_4
)
1251 i8xx_clock(48000, &clock
);
1254 /* XXX: It would be nice to validate the clocks, but we can't reuse
1255 * i830PllIsValid() because it relies on the xf86_config connector
1256 * configuration being accurate, which it isn't necessarily.
1262 /** Returns the currently programmed mode of the given pipe. */
1263 struct drm_display_mode
*psb_intel_crtc_mode_get(struct drm_device
*dev
,
1264 struct drm_crtc
*crtc
)
1266 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1267 int pipe
= psb_intel_crtc
->pipe
;
1268 struct drm_display_mode
*mode
;
1273 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1275 if (gma_power_begin(dev
, false)) {
1276 htot
= REG_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
1277 hsync
= REG_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
1278 vtot
= REG_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
1279 vsync
= REG_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
1282 htot
= (pipe
== 0) ?
1283 dev_priv
->saveHTOTAL_A
: dev_priv
->saveHTOTAL_B
;
1284 hsync
= (pipe
== 0) ?
1285 dev_priv
->saveHSYNC_A
: dev_priv
->saveHSYNC_B
;
1286 vtot
= (pipe
== 0) ?
1287 dev_priv
->saveVTOTAL_A
: dev_priv
->saveVTOTAL_B
;
1288 vsync
= (pipe
== 0) ?
1289 dev_priv
->saveVSYNC_A
: dev_priv
->saveVSYNC_B
;
1292 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
1296 mode
->clock
= psb_intel_crtc_clock_get(dev
, crtc
);
1297 mode
->hdisplay
= (htot
& 0xffff) + 1;
1298 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
1299 mode
->hsync_start
= (hsync
& 0xffff) + 1;
1300 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
1301 mode
->vdisplay
= (vtot
& 0xffff) + 1;
1302 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
1303 mode
->vsync_start
= (vsync
& 0xffff) + 1;
1304 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
1306 drm_mode_set_name(mode
);
1307 drm_mode_set_crtcinfo(mode
, 0);
1312 static void psb_intel_crtc_destroy(struct drm_crtc
*crtc
)
1314 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1315 struct gtt_range
*gt
;
1317 /* Unpin the old GEM object */
1318 if (psb_intel_crtc
->cursor_obj
) {
1319 gt
= container_of(psb_intel_crtc
->cursor_obj
,
1320 struct gtt_range
, gem
);
1322 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
1323 psb_intel_crtc
->cursor_obj
= NULL
;
1325 kfree(psb_intel_crtc
->crtc_state
);
1326 drm_crtc_cleanup(crtc
);
1327 kfree(psb_intel_crtc
);
1330 static const struct drm_crtc_helper_funcs psb_intel_helper_funcs
= {
1331 .dpms
= psb_intel_crtc_dpms
,
1332 .mode_fixup
= psb_intel_crtc_mode_fixup
,
1333 .mode_set
= psb_intel_crtc_mode_set
,
1334 .mode_set_base
= psb_intel_pipe_set_base
,
1335 .prepare
= psb_intel_crtc_prepare
,
1336 .commit
= psb_intel_crtc_commit
,
1339 const struct drm_crtc_funcs psb_intel_crtc_funcs
= {
1340 .save
= psb_intel_crtc_save
,
1341 .restore
= psb_intel_crtc_restore
,
1342 .cursor_set
= psb_intel_crtc_cursor_set
,
1343 .cursor_move
= psb_intel_crtc_cursor_move
,
1344 .gamma_set
= psb_intel_crtc_gamma_set
,
1345 .set_config
= psb_crtc_set_config
,
1346 .destroy
= psb_intel_crtc_destroy
,
1349 void psb_intel_crtc_init(struct drm_device
*dev
, int pipe
,
1350 struct psb_intel_mode_device
*mode_dev
)
1352 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1353 struct psb_intel_crtc
*psb_intel_crtc
;
1355 uint16_t *r_base
, *g_base
, *b_base
;
1357 PSB_DEBUG_ENTRY("\n");
1359 /* We allocate a extra array of drm_connector pointers
1360 * for fbdev after the crtc */
1362 kzalloc(sizeof(struct psb_intel_crtc
) +
1363 (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)),
1365 if (psb_intel_crtc
== NULL
)
1368 psb_intel_crtc
->crtc_state
=
1369 kzalloc(sizeof(struct psb_intel_crtc_state
), GFP_KERNEL
);
1370 if (!psb_intel_crtc
->crtc_state
) {
1371 DRM_INFO("Crtc state error: No memory\n");
1372 kfree(psb_intel_crtc
);
1376 drm_crtc_init(dev
, &psb_intel_crtc
->base
, &psb_intel_crtc_funcs
);
1378 drm_mode_crtc_set_gamma_size(&psb_intel_crtc
->base
, 256);
1379 psb_intel_crtc
->pipe
= pipe
;
1380 psb_intel_crtc
->plane
= pipe
;
1382 r_base
= psb_intel_crtc
->base
.gamma_store
;
1383 g_base
= r_base
+ 256;
1384 b_base
= g_base
+ 256;
1385 for (i
= 0; i
< 256; i
++) {
1386 psb_intel_crtc
->lut_r
[i
] = i
;
1387 psb_intel_crtc
->lut_g
[i
] = i
;
1388 psb_intel_crtc
->lut_b
[i
] = i
;
1393 psb_intel_crtc
->lut_adj
[i
] = 0;
1396 psb_intel_crtc
->mode_dev
= mode_dev
;
1397 psb_intel_crtc
->cursor_addr
= 0;
1400 drm_crtc_helper_add(&psb_intel_crtc
->base
,
1401 &mrst_helper_funcs
);
1403 drm_crtc_helper_add(&psb_intel_crtc
->base
,
1404 &psb_intel_helper_funcs
);
1406 /* Setup the array of drm_connector pointer array */
1407 psb_intel_crtc
->mode_set
.crtc
= &psb_intel_crtc
->base
;
1408 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
1409 dev_priv
->plane_to_crtc_mapping
[psb_intel_crtc
->plane
] != NULL
);
1410 dev_priv
->plane_to_crtc_mapping
[psb_intel_crtc
->plane
] =
1411 &psb_intel_crtc
->base
;
1412 dev_priv
->pipe_to_crtc_mapping
[psb_intel_crtc
->pipe
] =
1413 &psb_intel_crtc
->base
;
1414 psb_intel_crtc
->mode_set
.connectors
=
1415 (struct drm_connector
**) (psb_intel_crtc
+ 1);
1416 psb_intel_crtc
->mode_set
.num_connectors
= 0;
1419 int psb_intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1420 struct drm_file
*file_priv
)
1422 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
1423 struct drm_psb_get_pipe_from_crtc_id_arg
*pipe_from_crtc_id
= data
;
1424 struct drm_mode_object
*drmmode_obj
;
1425 struct psb_intel_crtc
*crtc
;
1428 DRM_ERROR("called with no initialization\n");
1432 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
1433 DRM_MODE_OBJECT_CRTC
);
1436 DRM_ERROR("no such CRTC id\n");
1440 crtc
= to_psb_intel_crtc(obj_to_crtc(drmmode_obj
));
1441 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
1446 struct drm_crtc
*psb_intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
1448 struct drm_crtc
*crtc
= NULL
;
1450 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1451 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
1452 if (psb_intel_crtc
->pipe
== pipe
)
1458 int psb_intel_connector_clones(struct drm_device
*dev
, int type_mask
)
1461 struct drm_connector
*connector
;
1464 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
1466 struct psb_intel_output
*psb_intel_output
=
1467 to_psb_intel_output(connector
);
1468 if (type_mask
& (1 << psb_intel_output
->type
))
1469 index_mask
|= (1 << entry
);
1476 void psb_intel_modeset_cleanup(struct drm_device
*dev
)
1478 drm_mode_config_cleanup(dev
);
1482 /* current intel driver doesn't take advantage of encoders
1483 always give back the encoder for the connector
1485 struct drm_encoder
*psb_intel_best_encoder(struct drm_connector
*connector
)
1487 struct psb_intel_output
*psb_intel_output
=
1488 to_psb_intel_output(connector
);
1490 return &psb_intel_output
->enc
;