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arm64: dts: marvell: mark the cp110 crypto engine as dma coherent
[linux-2.6/btrfs-unstable.git] / drivers / hwmon / it87.c
blob4dfc7238313ebd393e0e4dc0e17bb4414d1e8b68
1 /*
2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)
9 *
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
12 *
13 * Supports: IT8603E Super I/O chip w/LPC interface
14 * IT8620E Super I/O chip w/LPC interface
15 * IT8622E Super I/O chip w/LPC interface
16 * IT8623E Super I/O chip w/LPC interface
17 * IT8628E Super I/O chip w/LPC interface
18 * IT8705F Super I/O chip w/LPC interface
19 * IT8712F Super I/O chip w/LPC interface
20 * IT8716F Super I/O chip w/LPC interface
21 * IT8718F Super I/O chip w/LPC interface
22 * IT8720F Super I/O chip w/LPC interface
23 * IT8721F Super I/O chip w/LPC interface
24 * IT8726F Super I/O chip w/LPC interface
25 * IT8728F Super I/O chip w/LPC interface
26 * IT8732F Super I/O chip w/LPC interface
27 * IT8758E Super I/O chip w/LPC interface
28 * IT8771E Super I/O chip w/LPC interface
29 * IT8772E Super I/O chip w/LPC interface
30 * IT8781F Super I/O chip w/LPC interface
31 * IT8782F Super I/O chip w/LPC interface
32 * IT8783E/F Super I/O chip w/LPC interface
33 * IT8786E Super I/O chip w/LPC interface
34 * IT8790E Super I/O chip w/LPC interface
35 * IT8792E Super I/O chip w/LPC interface
36 * Sis950 A clone of the IT8705F
37 *
38 * Copyright (C) 2001 Chris Gauthron
39 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
40 *
41 * This program is free software; you can redistribute it and/or modify
42 * it under the terms of the GNU General Public License as published by
43 * the Free Software Foundation; either version 2 of the License, or
44 * (at your option) any later version.
45 *
46 * This program is distributed in the hope that it will be useful,
47 * but WITHOUT ANY WARRANTY; without even the implied warranty of
48 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
49 * GNU General Public License for more details.
50 */
51
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
53
54 #include <linux/bitops.h>
55 #include <linux/module.h>
56 #include <linux/init.h>
57 #include <linux/slab.h>
58 #include <linux/jiffies.h>
59 #include <linux/platform_device.h>
60 #include <linux/hwmon.h>
61 #include <linux/hwmon-sysfs.h>
62 #include <linux/hwmon-vid.h>
63 #include <linux/err.h>
64 #include <linux/mutex.h>
65 #include <linux/sysfs.h>
66 #include <linux/string.h>
67 #include <linux/dmi.h>
68 #include <linux/acpi.h>
69 #include <linux/io.h>
70
71 #define DRVNAME "it87"
72
73 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
74 it8771, it8772, it8781, it8782, it8783, it8786, it8790,
75 it8792, it8603, it8620, it8622, it8628 };
76
77 static unsigned short force_id;
78 module_param(force_id, ushort, 0);
79 MODULE_PARM_DESC(force_id, "Override the detected device ID");
80
81 static struct platform_device *it87_pdev[2];
82
83 #define REG_2E 0x2e /* The register to read/write */
84 #define REG_4E 0x4e /* Secondary register to read/write */
85
86 #define DEV 0x07 /* Register: Logical device select */
87 #define PME 0x04 /* The device with the fan registers in it */
88
89 /* The device with the IT8718F/IT8720F VID value in it */
90 #define GPIO 0x07
91
92 #define DEVID 0x20 /* Register: Device ID */
93 #define DEVREV 0x22 /* Register: Device Revision */
94
95 static inline int superio_inb(int ioreg, int reg)
96 {
97 outb(reg, ioreg);
98 return inb(ioreg + 1);
99 }
100
101 static inline void superio_outb(int ioreg, int reg, int val)
102 {
103 outb(reg, ioreg);
104 outb(val, ioreg + 1);
105 }
106
107 static int superio_inw(int ioreg, int reg)
108 {
109 int val;
110
111 outb(reg++, ioreg);
112 val = inb(ioreg + 1) << 8;
113 outb(reg, ioreg);
114 val |= inb(ioreg + 1);
115 return val;
116 }
117
118 static inline void superio_select(int ioreg, int ldn)
119 {
120 outb(DEV, ioreg);
121 outb(ldn, ioreg + 1);
122 }
123
124 static inline int superio_enter(int ioreg)
125 {
126 /*
127 * Try to reserve ioreg and ioreg + 1 for exclusive access.
128 */
129 if (!request_muxed_region(ioreg, 2, DRVNAME))
130 return -EBUSY;
131
132 outb(0x87, ioreg);
133 outb(0x01, ioreg);
134 outb(0x55, ioreg);
135 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
136 return 0;
137 }
138
139 static inline void superio_exit(int ioreg)
140 {
141 outb(0x02, ioreg);
142 outb(0x02, ioreg + 1);
143 release_region(ioreg, 2);
144 }
145
146 /* Logical device 4 registers */
147 #define IT8712F_DEVID 0x8712
148 #define IT8705F_DEVID 0x8705
149 #define IT8716F_DEVID 0x8716
150 #define IT8718F_DEVID 0x8718
151 #define IT8720F_DEVID 0x8720
152 #define IT8721F_DEVID 0x8721
153 #define IT8726F_DEVID 0x8726
154 #define IT8728F_DEVID 0x8728
155 #define IT8732F_DEVID 0x8732
156 #define IT8792E_DEVID 0x8733
157 #define IT8771E_DEVID 0x8771
158 #define IT8772E_DEVID 0x8772
159 #define IT8781F_DEVID 0x8781
160 #define IT8782F_DEVID 0x8782
161 #define IT8783E_DEVID 0x8783
162 #define IT8786E_DEVID 0x8786
163 #define IT8790E_DEVID 0x8790
164 #define IT8603E_DEVID 0x8603
165 #define IT8620E_DEVID 0x8620
166 #define IT8622E_DEVID 0x8622
167 #define IT8623E_DEVID 0x8623
168 #define IT8628E_DEVID 0x8628
169 #define IT87_ACT_REG 0x30
170 #define IT87_BASE_REG 0x60
171
172 /* Logical device 7 registers (IT8712F and later) */
173 #define IT87_SIO_GPIO1_REG 0x25
174 #define IT87_SIO_GPIO2_REG 0x26
175 #define IT87_SIO_GPIO3_REG 0x27
176 #define IT87_SIO_GPIO4_REG 0x28
177 #define IT87_SIO_GPIO5_REG 0x29
178 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
179 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
180 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
181 #define IT87_SIO_VID_REG 0xfc /* VID value */
182 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
183
184 /* Update battery voltage after every reading if true */
185 static bool update_vbat;
186
187 /* Not all BIOSes properly configure the PWM registers */
188 static bool fix_pwm_polarity;
189
190 /* Many IT87 constants specified below */
191
192 /* Length of ISA address segment */
193 #define IT87_EXTENT 8
194
195 /* Length of ISA address segment for Environmental Controller */
196 #define IT87_EC_EXTENT 2
197
198 /* Offset of EC registers from ISA base address */
199 #define IT87_EC_OFFSET 5
200
201 /* Where are the ISA address/data registers relative to the EC base address */
202 #define IT87_ADDR_REG_OFFSET 0
203 #define IT87_DATA_REG_OFFSET 1
204
205 /*----- The IT87 registers -----*/
206
207 #define IT87_REG_CONFIG 0x00
208
209 #define IT87_REG_ALARM1 0x01
210 #define IT87_REG_ALARM2 0x02
211 #define IT87_REG_ALARM3 0x03
212
213 /*
214 * The IT8718F and IT8720F have the VID value in a different register, in
215 * Super-I/O configuration space.
216 */
217 #define IT87_REG_VID 0x0a
218 /*
219 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
220 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
221 * mode.
222 */
223 #define IT87_REG_FAN_DIV 0x0b
224 #define IT87_REG_FAN_16BIT 0x0c
225
226 /*
227 * Monitors:
228 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
229 * - up to 6 temp (1 to 6)
230 * - up to 6 fan (1 to 6)
231 */
232
233 static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
234 static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
235 static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
236 static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
237 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
238
239 #define IT87_REG_FAN_MAIN_CTRL 0x13
240 #define IT87_REG_FAN_CTL 0x14
241 static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
242 static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
243
244 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
245 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
246
247 #define IT87_REG_TEMP(nr) (0x29 + (nr))
248
249 #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
250 #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
251 #define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
252 #define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
253
254 #define IT87_REG_VIN_ENABLE 0x50
255 #define IT87_REG_TEMP_ENABLE 0x51
256 #define IT87_REG_TEMP_EXTRA 0x55
257 #define IT87_REG_BEEP_ENABLE 0x5c
258
259 #define IT87_REG_CHIPID 0x58
260
261 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
262
263 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
264 #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i))
265
266 #define IT87_REG_TEMP456_ENABLE 0x77
267
268 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
269 #define NUM_VIN_LIMIT 8
270 #define NUM_TEMP 6
271 #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET)
272 #define NUM_TEMP_LIMIT 3
273 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
274 #define NUM_FAN_DIV 3
275 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
276 #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
277
278 struct it87_devices {
279 const char *name;
280 const char * const suffix;
281 u32 features;
282 u8 peci_mask;
283 u8 old_peci_mask;
284 };
285
286 #define FEAT_12MV_ADC BIT(0)
287 #define FEAT_NEWER_AUTOPWM BIT(1)
288 #define FEAT_OLD_AUTOPWM BIT(2)
289 #define FEAT_16BIT_FANS BIT(3)
290 #define FEAT_TEMP_OFFSET BIT(4)
291 #define FEAT_TEMP_PECI BIT(5)
292 #define FEAT_TEMP_OLD_PECI BIT(6)
293 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
294 #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
295 #define FEAT_VID BIT(9) /* Set if chip supports VID */
296 #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
297 #define FEAT_SIX_FANS BIT(11) /* Supports six fans */
298 #define FEAT_10_9MV_ADC BIT(12)
299 #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
300 #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */
301 #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */
302 #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
303 #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
304 #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
305
306 static const struct it87_devices it87_devices[] = {
307 [it87] = {
308 .name = "it87",
309 .suffix = "F",
310 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
311 },
312 [it8712] = {
313 .name = "it8712",
314 .suffix = "F",
315 .features = FEAT_OLD_AUTOPWM | FEAT_VID,
316 /* may need to overwrite */
317 },
318 [it8716] = {
319 .name = "it8716",
320 .suffix = "F",
321 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
322 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2,
323 },
324 [it8718] = {
325 .name = "it8718",
326 .suffix = "F",
327 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
328 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
329 | FEAT_PWM_FREQ2,
330 .old_peci_mask = 0x4,
331 },
332 [it8720] = {
333 .name = "it8720",
334 .suffix = "F",
335 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
336 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
337 | FEAT_PWM_FREQ2,
338 .old_peci_mask = 0x4,
339 },
340 [it8721] = {
341 .name = "it8721",
342 .suffix = "F",
343 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
344 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
345 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
346 | FEAT_PWM_FREQ2,
347 .peci_mask = 0x05,
348 .old_peci_mask = 0x02, /* Actually reports PCH */
349 },
350 [it8728] = {
351 .name = "it8728",
352 .suffix = "F",
353 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
354 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
355 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2,
356 .peci_mask = 0x07,
357 },
358 [it8732] = {
359 .name = "it8732",
360 .suffix = "F",
361 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
362 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
363 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
364 .peci_mask = 0x07,
365 .old_peci_mask = 0x02, /* Actually reports PCH */
366 },
367 [it8771] = {
368 .name = "it8771",
369 .suffix = "E",
370 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
371 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
372 | FEAT_PWM_FREQ2,
373 /* PECI: guesswork */
374 /* 12mV ADC (OHM) */
375 /* 16 bit fans (OHM) */
376 /* three fans, always 16 bit (guesswork) */
377 .peci_mask = 0x07,
378 },
379 [it8772] = {
380 .name = "it8772",
381 .suffix = "E",
382 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
383 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
384 | FEAT_PWM_FREQ2,
385 /* PECI (coreboot) */
386 /* 12mV ADC (HWSensors4, OHM) */
387 /* 16 bit fans (HWSensors4, OHM) */
388 /* three fans, always 16 bit (datasheet) */
389 .peci_mask = 0x07,
390 },
391 [it8781] = {
392 .name = "it8781",
393 .suffix = "F",
394 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
395 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
396 .old_peci_mask = 0x4,
397 },
398 [it8782] = {
399 .name = "it8782",
400 .suffix = "F",
401 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
402 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
403 .old_peci_mask = 0x4,
404 },
405 [it8783] = {
406 .name = "it8783",
407 .suffix = "E/F",
408 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
409 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
410 .old_peci_mask = 0x4,
411 },
412 [it8786] = {
413 .name = "it8786",
414 .suffix = "E",
415 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
416 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
417 | FEAT_PWM_FREQ2,
418 .peci_mask = 0x07,
419 },
420 [it8790] = {
421 .name = "it8790",
422 .suffix = "E",
423 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
424 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
425 | FEAT_PWM_FREQ2,
426 .peci_mask = 0x07,
427 },
428 [it8792] = {
429 .name = "it8792",
430 .suffix = "E",
431 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
432 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
433 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
434 .peci_mask = 0x07,
435 .old_peci_mask = 0x02, /* Actually reports PCH */
436 },
437 [it8603] = {
438 .name = "it8603",
439 .suffix = "E",
440 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
441 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
442 | FEAT_AVCC3 | FEAT_PWM_FREQ2,
443 .peci_mask = 0x07,
444 },
445 [it8620] = {
446 .name = "it8620",
447 .suffix = "E",
448 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
449 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
450 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
451 | FEAT_SIX_TEMP | FEAT_VIN3_5V,
452 .peci_mask = 0x07,
453 },
454 [it8622] = {
455 .name = "it8622",
456 .suffix = "E",
457 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
458 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
459 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
460 | FEAT_AVCC3 | FEAT_VIN3_5V,
461 .peci_mask = 0x07,
462 },
463 [it8628] = {
464 .name = "it8628",
465 .suffix = "E",
466 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
467 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
468 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
469 | FEAT_SIX_TEMP | FEAT_VIN3_5V,
470 .peci_mask = 0x07,
471 },
472 };
473
474 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
475 #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
476 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
477 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
478 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
479 #define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
480 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
481 ((data)->peci_mask & BIT(nr)))
482 #define has_temp_old_peci(data, nr) \
483 (((data)->features & FEAT_TEMP_OLD_PECI) && \
484 ((data)->old_peci_mask & BIT(nr)))
485 #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
486 #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
487 FEAT_SIX_FANS))
488 #define has_vid(data) ((data)->features & FEAT_VID)
489 #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
490 #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
491 #define has_avcc3(data) ((data)->features & FEAT_AVCC3)
492 #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \
493 | FEAT_SIX_PWM))
494 #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
495 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
496 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
497 #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
498
499 struct it87_sio_data {
500 enum chips type;
501 /* Values read from Super-I/O config space */
502 u8 revision;
503 u8 vid_value;
504 u8 beep_pin;
505 u8 internal; /* Internal sensors can be labeled */
506 /* Features skipped based on config or DMI */
507 u16 skip_in;
508 u8 skip_vid;
509 u8 skip_fan;
510 u8 skip_pwm;
511 u8 skip_temp;
512 };
513
514 /*
515 * For each registered chip, we need to keep some data in memory.
516 * The structure is dynamically allocated.
517 */
518 struct it87_data {
519 const struct attribute_group *groups[7];
520 enum chips type;
521 u32 features;
522 u8 peci_mask;
523 u8 old_peci_mask;
524
525 unsigned short addr;
526 const char *name;
527 struct mutex update_lock;
528 char valid; /* !=0 if following fields are valid */
529 unsigned long last_updated; /* In jiffies */
530
531 u16 in_scaled; /* Internal voltage sensors are scaled */
532 u16 in_internal; /* Bitfield, internal sensors (for labels) */
533 u16 has_in; /* Bitfield, voltage sensors enabled */
534 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
535 u8 has_fan; /* Bitfield, fans enabled */
536 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
537 u8 has_temp; /* Bitfield, temp sensors enabled */
538 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
539 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
540 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
541 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
542 bool has_vid; /* True if VID supported */
543 u8 vid; /* Register encoding, combined */
544 u8 vrm;
545 u32 alarms; /* Register encoding, combined */
546 bool has_beep; /* true if beep supported */
547 u8 beeps; /* Register encoding */
548 u8 fan_main_ctrl; /* Register value */
549 u8 fan_ctl; /* Register value */
550
551 /*
552 * The following 3 arrays correspond to the same registers up to
553 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
554 * 7, and we want to preserve settings on mode changes, so we have
555 * to track all values separately.
556 * Starting with the IT8721F, the manual PWM duty cycles are stored
557 * in separate registers (8-bit values), so the separate tracking
558 * is no longer needed, but it is still done to keep the driver
559 * simple.
560 */
561 u8 has_pwm; /* Bitfield, pwm control enabled */
562 u8 pwm_ctrl[NUM_PWM]; /* Register value */
563 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
564 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
565
566 /* Automatic fan speed control registers */
567 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
568 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
569 };
570
571 static int adc_lsb(const struct it87_data *data, int nr)
572 {
573 int lsb;
574
575 if (has_12mv_adc(data))
576 lsb = 120;
577 else if (has_10_9mv_adc(data))
578 lsb = 109;
579 else
580 lsb = 160;
581 if (data->in_scaled & BIT(nr))
582 lsb <<= 1;
583 return lsb;
584 }
585
586 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
587 {
588 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
589 return clamp_val(val, 0, 255);
590 }
591
592 static int in_from_reg(const struct it87_data *data, int nr, int val)
593 {
594 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
595 }
596
597 static inline u8 FAN_TO_REG(long rpm, int div)
598 {
599 if (rpm == 0)
600 return 255;
601 rpm = clamp_val(rpm, 1, 1000000);
602 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
603 }
604
605 static inline u16 FAN16_TO_REG(long rpm)
606 {
607 if (rpm == 0)
608 return 0xffff;
609 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
610 }
611
612 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
613 1350000 / ((val) * (div)))
614 /* The divider is fixed to 2 in 16-bit mode */
615 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
616 1350000 / ((val) * 2))
617
618 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
619 ((val) + 500) / 1000), -128, 127))
620 #define TEMP_FROM_REG(val) ((val) * 1000)
621
622 static u8 pwm_to_reg(const struct it87_data *data, long val)
623 {
624 if (has_newer_autopwm(data))
625 return val;
626 else
627 return val >> 1;
628 }
629
630 static int pwm_from_reg(const struct it87_data *data, u8 reg)
631 {
632 if (has_newer_autopwm(data))
633 return reg;
634 else
635 return (reg & 0x7f) << 1;
636 }
637
638 static int DIV_TO_REG(int val)
639 {
640 int answer = 0;
641
642 while (answer < 7 && (val >>= 1))
643 answer++;
644 return answer;
645 }
646
647 #define DIV_FROM_REG(val) BIT(val)
648
649 /*
650 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
651 * depending on the chip type, to calculate the actual PWM frequency.
652 *
653 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
654 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
655 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
656 * sometimes just one. It is unknown if this is a datasheet error or real,
657 * so this is ignored for now.
658 */
659 static const unsigned int pwm_freq[8] = {
660 48000000,
661 24000000,
662 12000000,
663 8000000,
664 6000000,
665 3000000,
666 1500000,
667 750000,
668 };
669
670 /*
671 * Must be called with data->update_lock held, except during initialization.
672 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
673 * would slow down the IT87 access and should not be necessary.
674 */
675 static int it87_read_value(struct it87_data *data, u8 reg)
676 {
677 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
678 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
679 }
680
681 /*
682 * Must be called with data->update_lock held, except during initialization.
683 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
684 * would slow down the IT87 access and should not be necessary.
685 */
686 static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
687 {
688 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
689 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
690 }
691
692 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
693 {
694 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]);
695 if (has_newer_autopwm(data)) {
696 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
697 data->pwm_duty[nr] = it87_read_value(data,
698 IT87_REG_PWM_DUTY[nr]);
699 } else {
700 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
701 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
702 else /* Manual mode */
703 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
704 }
705
706 if (has_old_autopwm(data)) {
707 int i;
708
709 for (i = 0; i < 5 ; i++)
710 data->auto_temp[nr][i] = it87_read_value(data,
711 IT87_REG_AUTO_TEMP(nr, i));
712 for (i = 0; i < 3 ; i++)
713 data->auto_pwm[nr][i] = it87_read_value(data,
714 IT87_REG_AUTO_PWM(nr, i));
715 } else if (has_newer_autopwm(data)) {
716 int i;
717
718 /*
719 * 0: temperature hysteresis (base + 5)
720 * 1: fan off temperature (base + 0)
721 * 2: fan start temperature (base + 1)
722 * 3: fan max temperature (base + 2)
723 */
724 data->auto_temp[nr][0] =
725 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
726
727 for (i = 0; i < 3 ; i++)
728 data->auto_temp[nr][i + 1] =
729 it87_read_value(data,
730 IT87_REG_AUTO_TEMP(nr, i));
731 /*
732 * 0: start pwm value (base + 3)
733 * 1: pwm slope (base + 4, 1/8th pwm)
734 */
735 data->auto_pwm[nr][0] =
736 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
737 data->auto_pwm[nr][1] =
738 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
739 }
740 }
741
742 static struct it87_data *it87_update_device(struct device *dev)
743 {
744 struct it87_data *data = dev_get_drvdata(dev);
745 int i;
746
747 mutex_lock(&data->update_lock);
748
749 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
750 !data->valid) {
751 if (update_vbat) {
752 /*
753 * Cleared after each update, so reenable. Value
754 * returned by this read will be previous value
755 */
756 it87_write_value(data, IT87_REG_CONFIG,
757 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
758 }
759 for (i = 0; i < NUM_VIN; i++) {
760 if (!(data->has_in & BIT(i)))
761 continue;
762
763 data->in[i][0] =
764 it87_read_value(data, IT87_REG_VIN[i]);
765
766 /* VBAT and AVCC don't have limit registers */
767 if (i >= NUM_VIN_LIMIT)
768 continue;
769
770 data->in[i][1] =
771 it87_read_value(data, IT87_REG_VIN_MIN(i));
772 data->in[i][2] =
773 it87_read_value(data, IT87_REG_VIN_MAX(i));
774 }
775
776 for (i = 0; i < NUM_FAN; i++) {
777 /* Skip disabled fans */
778 if (!(data->has_fan & BIT(i)))
779 continue;
780
781 data->fan[i][1] =
782 it87_read_value(data, IT87_REG_FAN_MIN[i]);
783 data->fan[i][0] = it87_read_value(data,
784 IT87_REG_FAN[i]);
785 /* Add high byte if in 16-bit mode */
786 if (has_16bit_fans(data)) {
787 data->fan[i][0] |= it87_read_value(data,
788 IT87_REG_FANX[i]) << 8;
789 data->fan[i][1] |= it87_read_value(data,
790 IT87_REG_FANX_MIN[i]) << 8;
791 }
792 }
793 for (i = 0; i < NUM_TEMP; i++) {
794 if (!(data->has_temp & BIT(i)))
795 continue;
796 data->temp[i][0] =
797 it87_read_value(data, IT87_REG_TEMP(i));
798
799 if (has_temp_offset(data) && i < NUM_TEMP_OFFSET)
800 data->temp[i][3] =
801 it87_read_value(data,
802 IT87_REG_TEMP_OFFSET[i]);
803
804 if (i >= NUM_TEMP_LIMIT)
805 continue;
806
807 data->temp[i][1] =
808 it87_read_value(data, IT87_REG_TEMP_LOW(i));
809 data->temp[i][2] =
810 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
811 }
812
813 /* Newer chips don't have clock dividers */
814 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
815 i = it87_read_value(data, IT87_REG_FAN_DIV);
816 data->fan_div[0] = i & 0x07;
817 data->fan_div[1] = (i >> 3) & 0x07;
818 data->fan_div[2] = (i & 0x40) ? 3 : 1;
819 }
820
821 data->alarms =
822 it87_read_value(data, IT87_REG_ALARM1) |
823 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
824 (it87_read_value(data, IT87_REG_ALARM3) << 16);
825 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
826
827 data->fan_main_ctrl = it87_read_value(data,
828 IT87_REG_FAN_MAIN_CTRL);
829 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
830 for (i = 0; i < NUM_PWM; i++) {
831 if (!(data->has_pwm & BIT(i)))
832 continue;
833 it87_update_pwm_ctrl(data, i);
834 }
835
836 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
837 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
838 /*
839 * The IT8705F does not have VID capability.
840 * The IT8718F and later don't use IT87_REG_VID for the
841 * same purpose.
842 */
843 if (data->type == it8712 || data->type == it8716) {
844 data->vid = it87_read_value(data, IT87_REG_VID);
845 /*
846 * The older IT8712F revisions had only 5 VID pins,
847 * but we assume it is always safe to read 6 bits.
848 */
849 data->vid &= 0x3f;
850 }
851 data->last_updated = jiffies;
852 data->valid = 1;
853 }
854
855 mutex_unlock(&data->update_lock);
856
857 return data;
858 }
859
860 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
861 char *buf)
862 {
863 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
864 struct it87_data *data = it87_update_device(dev);
865 int index = sattr->index;
866 int nr = sattr->nr;
867
868 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
869 }
870
871 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
872 const char *buf, size_t count)
873 {
874 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
875 struct it87_data *data = dev_get_drvdata(dev);
876 int index = sattr->index;
877 int nr = sattr->nr;
878 unsigned long val;
879
880 if (kstrtoul(buf, 10, &val) < 0)
881 return -EINVAL;
882
883 mutex_lock(&data->update_lock);
884 data->in[nr][index] = in_to_reg(data, nr, val);
885 it87_write_value(data,
886 index == 1 ? IT87_REG_VIN_MIN(nr)
887 : IT87_REG_VIN_MAX(nr),
888 data->in[nr][index]);
889 mutex_unlock(&data->update_lock);
890 return count;
891 }
892
893 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
894 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
895 0, 1);
896 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
897 0, 2);
898
899 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
900 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
901 1, 1);
902 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
903 1, 2);
904
905 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
906 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
907 2, 1);
908 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
909 2, 2);
910
911 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
912 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
913 3, 1);
914 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
915 3, 2);
916
917 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
918 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
919 4, 1);
920 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
921 4, 2);
922
923 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
924 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
925 5, 1);
926 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
927 5, 2);
928
929 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
930 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
931 6, 1);
932 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
933 6, 2);
934
935 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
936 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
937 7, 1);
938 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
939 7, 2);
940
941 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
942 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
943 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
944 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
945 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
946
947 /* Up to 6 temperatures */
948 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
949 char *buf)
950 {
951 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
952 int nr = sattr->nr;
953 int index = sattr->index;
954 struct it87_data *data = it87_update_device(dev);
955
956 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
957 }
958
959 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
960 const char *buf, size_t count)
961 {
962 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
963 int nr = sattr->nr;
964 int index = sattr->index;
965 struct it87_data *data = dev_get_drvdata(dev);
966 long val;
967 u8 reg, regval;
968
969 if (kstrtol(buf, 10, &val) < 0)
970 return -EINVAL;
971
972 mutex_lock(&data->update_lock);
973
974 switch (index) {
975 default:
976 case 1:
977 reg = IT87_REG_TEMP_LOW(nr);
978 break;
979 case 2:
980 reg = IT87_REG_TEMP_HIGH(nr);
981 break;
982 case 3:
983 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
984 if (!(regval & 0x80)) {
985 regval |= 0x80;
986 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
987 }
988 data->valid = 0;
989 reg = IT87_REG_TEMP_OFFSET[nr];
990 break;
991 }
992
993 data->temp[nr][index] = TEMP_TO_REG(val);
994 it87_write_value(data, reg, data->temp[nr][index]);
995 mutex_unlock(&data->update_lock);
996 return count;
997 }
998
999 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1000 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1001 0, 1);
1002 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1003 0, 2);
1004 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1005 set_temp, 0, 3);
1006 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1007 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1008 1, 1);
1009 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1010 1, 2);
1011 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1012 set_temp, 1, 3);
1013 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1014 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1015 2, 1);
1016 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1017 2, 2);
1018 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1019 set_temp, 2, 3);
1020 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1021 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1022 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1023
1024 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1025 char *buf)
1026 {
1027 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1028 int nr = sensor_attr->index;
1029 struct it87_data *data = it87_update_device(dev);
1030 u8 reg = data->sensor; /* In case value is updated while used */
1031 u8 extra = data->extra;
1032
1033 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) ||
1034 (has_temp_old_peci(data, nr) && (extra & 0x80)))
1035 return sprintf(buf, "6\n"); /* Intel PECI */
1036 if (reg & (1 << nr))
1037 return sprintf(buf, "3\n"); /* thermal diode */
1038 if (reg & (8 << nr))
1039 return sprintf(buf, "4\n"); /* thermistor */
1040 return sprintf(buf, "0\n"); /* disabled */
1041 }
1042
1043 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1044 const char *buf, size_t count)
1045 {
1046 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1047 int nr = sensor_attr->index;
1048
1049 struct it87_data *data = dev_get_drvdata(dev);
1050 long val;
1051 u8 reg, extra;
1052
1053 if (kstrtol(buf, 10, &val) < 0)
1054 return -EINVAL;
1055
1056 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1057 reg &= ~(1 << nr);
1058 reg &= ~(8 << nr);
1059 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1060 reg &= 0x3f;
1061 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1062 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1063 extra &= 0x7f;
1064 if (val == 2) { /* backwards compatibility */
1065 dev_warn(dev,
1066 "Sensor type 2 is deprecated, please use 4 instead\n");
1067 val = 4;
1068 }
1069 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1070 if (val == 3)
1071 reg |= 1 << nr;
1072 else if (val == 4)
1073 reg |= 8 << nr;
1074 else if (has_temp_peci(data, nr) && val == 6)
1075 reg |= (nr + 1) << 6;
1076 else if (has_temp_old_peci(data, nr) && val == 6)
1077 extra |= 0x80;
1078 else if (val != 0)
1079 return -EINVAL;
1080
1081 mutex_lock(&data->update_lock);
1082 data->sensor = reg;
1083 data->extra = extra;
1084 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1085 if (has_temp_old_peci(data, nr))
1086 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1087 data->valid = 0; /* Force cache refresh */
1088 mutex_unlock(&data->update_lock);
1089 return count;
1090 }
1091
1092 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1093 set_temp_type, 0);
1094 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1095 set_temp_type, 1);
1096 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1097 set_temp_type, 2);
1098
1099 /* 6 Fans */
1100
1101 static int pwm_mode(const struct it87_data *data, int nr)
1102 {
1103 if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr)))
1104 return 0; /* Full speed */
1105 if (data->pwm_ctrl[nr] & 0x80)
1106 return 2; /* Automatic mode */
1107 if ((data->type == it8603 || nr >= 3) &&
1108 data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1109 return 0; /* Full speed */
1110
1111 return 1; /* Manual mode */
1112 }
1113
1114 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1115 char *buf)
1116 {
1117 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1118 int nr = sattr->nr;
1119 int index = sattr->index;
1120 int speed;
1121 struct it87_data *data = it87_update_device(dev);
1122
1123 speed = has_16bit_fans(data) ?
1124 FAN16_FROM_REG(data->fan[nr][index]) :
1125 FAN_FROM_REG(data->fan[nr][index],
1126 DIV_FROM_REG(data->fan_div[nr]));
1127 return sprintf(buf, "%d\n", speed);
1128 }
1129
1130 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1131 char *buf)
1132 {
1133 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1134 struct it87_data *data = it87_update_device(dev);
1135 int nr = sensor_attr->index;
1136
1137 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1138 }
1139
1140 static ssize_t show_pwm_enable(struct device *dev,
1141 struct device_attribute *attr, char *buf)
1142 {
1143 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1144 struct it87_data *data = it87_update_device(dev);
1145 int nr = sensor_attr->index;
1146
1147 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1148 }
1149
1150 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1151 char *buf)
1152 {
1153 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1154 struct it87_data *data = it87_update_device(dev);
1155 int nr = sensor_attr->index;
1156
1157 return sprintf(buf, "%d\n",
1158 pwm_from_reg(data, data->pwm_duty[nr]));
1159 }
1160
1161 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1162 char *buf)
1163 {
1164 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1165 struct it87_data *data = it87_update_device(dev);
1166 int nr = sensor_attr->index;
1167 unsigned int freq;
1168 int index;
1169
1170 if (has_pwm_freq2(data) && nr == 1)
1171 index = (data->extra >> 4) & 0x07;
1172 else
1173 index = (data->fan_ctl >> 4) & 0x07;
1174
1175 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1176
1177 return sprintf(buf, "%u\n", freq);
1178 }
1179
1180 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1181 const char *buf, size_t count)
1182 {
1183 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1184 int nr = sattr->nr;
1185 int index = sattr->index;
1186
1187 struct it87_data *data = dev_get_drvdata(dev);
1188 long val;
1189 u8 reg;
1190
1191 if (kstrtol(buf, 10, &val) < 0)
1192 return -EINVAL;
1193
1194 mutex_lock(&data->update_lock);
1195
1196 if (has_16bit_fans(data)) {
1197 data->fan[nr][index] = FAN16_TO_REG(val);
1198 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1199 data->fan[nr][index] & 0xff);
1200 it87_write_value(data, IT87_REG_FANX_MIN[nr],
1201 data->fan[nr][index] >> 8);
1202 } else {
1203 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1204 switch (nr) {
1205 case 0:
1206 data->fan_div[nr] = reg & 0x07;
1207 break;
1208 case 1:
1209 data->fan_div[nr] = (reg >> 3) & 0x07;
1210 break;
1211 case 2:
1212 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1213 break;
1214 }
1215 data->fan[nr][index] =
1216 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1217 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1218 data->fan[nr][index]);
1219 }
1220
1221 mutex_unlock(&data->update_lock);
1222 return count;
1223 }
1224
1225 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1226 const char *buf, size_t count)
1227 {
1228 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1229 struct it87_data *data = dev_get_drvdata(dev);
1230 int nr = sensor_attr->index;
1231 unsigned long val;
1232 int min;
1233 u8 old;
1234
1235 if (kstrtoul(buf, 10, &val) < 0)
1236 return -EINVAL;
1237
1238 mutex_lock(&data->update_lock);
1239 old = it87_read_value(data, IT87_REG_FAN_DIV);
1240
1241 /* Save fan min limit */
1242 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1243
1244 switch (nr) {
1245 case 0:
1246 case 1:
1247 data->fan_div[nr] = DIV_TO_REG(val);
1248 break;
1249 case 2:
1250 if (val < 8)
1251 data->fan_div[nr] = 1;
1252 else
1253 data->fan_div[nr] = 3;
1254 }
1255 val = old & 0x80;
1256 val |= (data->fan_div[0] & 0x07);
1257 val |= (data->fan_div[1] & 0x07) << 3;
1258 if (data->fan_div[2] == 3)
1259 val |= 0x1 << 6;
1260 it87_write_value(data, IT87_REG_FAN_DIV, val);
1261
1262 /* Restore fan min limit */
1263 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1264 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
1265
1266 mutex_unlock(&data->update_lock);
1267 return count;
1268 }
1269
1270 /* Returns 0 if OK, -EINVAL otherwise */
1271 static int check_trip_points(struct device *dev, int nr)
1272 {
1273 const struct it87_data *data = dev_get_drvdata(dev);
1274 int i, err = 0;
1275
1276 if (has_old_autopwm(data)) {
1277 for (i = 0; i < 3; i++) {
1278 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1279 err = -EINVAL;
1280 }
1281 for (i = 0; i < 2; i++) {
1282 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1283 err = -EINVAL;
1284 }
1285 } else if (has_newer_autopwm(data)) {
1286 for (i = 1; i < 3; i++) {
1287 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1288 err = -EINVAL;
1289 }
1290 }
1291
1292 if (err) {
1293 dev_err(dev,
1294 "Inconsistent trip points, not switching to automatic mode\n");
1295 dev_err(dev, "Adjust the trip points and try again\n");
1296 }
1297 return err;
1298 }
1299
1300 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1301 const char *buf, size_t count)
1302 {
1303 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1304 struct it87_data *data = dev_get_drvdata(dev);
1305 int nr = sensor_attr->index;
1306 long val;
1307
1308 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1309 return -EINVAL;
1310
1311 /* Check trip points before switching to automatic mode */
1312 if (val == 2) {
1313 if (check_trip_points(dev, nr) < 0)
1314 return -EINVAL;
1315 }
1316
1317 mutex_lock(&data->update_lock);
1318
1319 if (val == 0) {
1320 if (nr < 3 && data->type != it8603) {
1321 int tmp;
1322 /* make sure the fan is on when in on/off mode */
1323 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1324 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1325 /* set on/off mode */
1326 data->fan_main_ctrl &= ~BIT(nr);
1327 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1328 data->fan_main_ctrl);
1329 } else {
1330 u8 ctrl;
1331
1332 /* No on/off mode, set maximum pwm value */
1333 data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1334 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1335 data->pwm_duty[nr]);
1336 /* and set manual mode */
1337 if (has_newer_autopwm(data)) {
1338 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1339 data->pwm_temp_map[nr];
1340 } else {
1341 ctrl = data->pwm_duty[nr];
1342 }
1343 data->pwm_ctrl[nr] = ctrl;
1344 it87_write_value(data, IT87_REG_PWM[nr], ctrl);
1345 }
1346 } else {
1347 u8 ctrl;
1348
1349 if (has_newer_autopwm(data)) {
1350 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1351 data->pwm_temp_map[nr];
1352 if (val != 1)
1353 ctrl |= 0x80;
1354 } else {
1355 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1356 }
1357 data->pwm_ctrl[nr] = ctrl;
1358 it87_write_value(data, IT87_REG_PWM[nr], ctrl);
1359
1360 if (data->type != it8603 && nr < 3) {
1361 /* set SmartGuardian mode */
1362 data->fan_main_ctrl |= BIT(nr);
1363 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1364 data->fan_main_ctrl);
1365 }
1366 }
1367
1368 mutex_unlock(&data->update_lock);
1369 return count;
1370 }
1371
1372 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1373 const char *buf, size_t count)
1374 {
1375 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1376 struct it87_data *data = dev_get_drvdata(dev);
1377 int nr = sensor_attr->index;
1378 long val;
1379
1380 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1381 return -EINVAL;
1382
1383 mutex_lock(&data->update_lock);
1384 it87_update_pwm_ctrl(data, nr);
1385 if (has_newer_autopwm(data)) {
1386 /*
1387 * If we are in automatic mode, the PWM duty cycle register
1388 * is read-only so we can't write the value.
1389 */
1390 if (data->pwm_ctrl[nr] & 0x80) {
1391 mutex_unlock(&data->update_lock);
1392 return -EBUSY;
1393 }
1394 data->pwm_duty[nr] = pwm_to_reg(data, val);
1395 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1396 data->pwm_duty[nr]);
1397 } else {
1398 data->pwm_duty[nr] = pwm_to_reg(data, val);
1399 /*
1400 * If we are in manual mode, write the duty cycle immediately;
1401 * otherwise, just store it for later use.
1402 */
1403 if (!(data->pwm_ctrl[nr] & 0x80)) {
1404 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1405 it87_write_value(data, IT87_REG_PWM[nr],
1406 data->pwm_ctrl[nr]);
1407 }
1408 }
1409 mutex_unlock(&data->update_lock);
1410 return count;
1411 }
1412
1413 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1414 const char *buf, size_t count)
1415 {
1416 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1417 struct it87_data *data = dev_get_drvdata(dev);
1418 int nr = sensor_attr->index;
1419 unsigned long val;
1420 int i;
1421
1422 if (kstrtoul(buf, 10, &val) < 0)
1423 return -EINVAL;
1424
1425 val = clamp_val(val, 0, 1000000);
1426 val *= has_newer_autopwm(data) ? 256 : 128;
1427
1428 /* Search for the nearest available frequency */
1429 for (i = 0; i < 7; i++) {
1430 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1431 break;
1432 }
1433
1434 mutex_lock(&data->update_lock);
1435 if (nr == 0) {
1436 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1437 data->fan_ctl |= i << 4;
1438 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1439 } else {
1440 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1441 data->extra |= i << 4;
1442 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1443 }
1444 mutex_unlock(&data->update_lock);
1445
1446 return count;
1447 }
1448
1449 static ssize_t show_pwm_temp_map(struct device *dev,
1450 struct device_attribute *attr, char *buf)
1451 {
1452 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1453 struct it87_data *data = it87_update_device(dev);
1454 int nr = sensor_attr->index;
1455 int map;
1456
1457 map = data->pwm_temp_map[nr];
1458 if (map >= 3)
1459 map = 0; /* Should never happen */
1460 if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */
1461 map += 3;
1462
1463 return sprintf(buf, "%d\n", (int)BIT(map));
1464 }
1465
1466 static ssize_t set_pwm_temp_map(struct device *dev,
1467 struct device_attribute *attr, const char *buf,
1468 size_t count)
1469 {
1470 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1471 struct it87_data *data = dev_get_drvdata(dev);
1472 int nr = sensor_attr->index;
1473 long val;
1474 u8 reg;
1475
1476 if (kstrtol(buf, 10, &val) < 0)
1477 return -EINVAL;
1478
1479 if (nr >= 3)
1480 val -= 3;
1481
1482 switch (val) {
1483 case BIT(0):
1484 reg = 0x00;
1485 break;
1486 case BIT(1):
1487 reg = 0x01;
1488 break;
1489 case BIT(2):
1490 reg = 0x02;
1491 break;
1492 default:
1493 return -EINVAL;
1494 }
1495
1496 mutex_lock(&data->update_lock);
1497 it87_update_pwm_ctrl(data, nr);
1498 data->pwm_temp_map[nr] = reg;
1499 /*
1500 * If we are in automatic mode, write the temp mapping immediately;
1501 * otherwise, just store it for later use.
1502 */
1503 if (data->pwm_ctrl[nr] & 0x80) {
1504 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) |
1505 data->pwm_temp_map[nr];
1506 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
1507 }
1508 mutex_unlock(&data->update_lock);
1509 return count;
1510 }
1511
1512 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1513 char *buf)
1514 {
1515 struct it87_data *data = it87_update_device(dev);
1516 struct sensor_device_attribute_2 *sensor_attr =
1517 to_sensor_dev_attr_2(attr);
1518 int nr = sensor_attr->nr;
1519 int point = sensor_attr->index;
1520
1521 return sprintf(buf, "%d\n",
1522 pwm_from_reg(data, data->auto_pwm[nr][point]));
1523 }
1524
1525 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1526 const char *buf, size_t count)
1527 {
1528 struct it87_data *data = dev_get_drvdata(dev);
1529 struct sensor_device_attribute_2 *sensor_attr =
1530 to_sensor_dev_attr_2(attr);
1531 int nr = sensor_attr->nr;
1532 int point = sensor_attr->index;
1533 int regaddr;
1534 long val;
1535
1536 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1537 return -EINVAL;
1538
1539 mutex_lock(&data->update_lock);
1540 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1541 if (has_newer_autopwm(data))
1542 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1543 else
1544 regaddr = IT87_REG_AUTO_PWM(nr, point);
1545 it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1546 mutex_unlock(&data->update_lock);
1547 return count;
1548 }
1549
1550 static ssize_t show_auto_pwm_slope(struct device *dev,
1551 struct device_attribute *attr, char *buf)
1552 {
1553 struct it87_data *data = it87_update_device(dev);
1554 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1555 int nr = sensor_attr->index;
1556
1557 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1558 }
1559
1560 static ssize_t set_auto_pwm_slope(struct device *dev,
1561 struct device_attribute *attr,
1562 const char *buf, size_t count)
1563 {
1564 struct it87_data *data = dev_get_drvdata(dev);
1565 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1566 int nr = sensor_attr->index;
1567 unsigned long val;
1568
1569 if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1570 return -EINVAL;
1571
1572 mutex_lock(&data->update_lock);
1573 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1574 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1575 data->auto_pwm[nr][1]);
1576 mutex_unlock(&data->update_lock);
1577 return count;
1578 }
1579
1580 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1581 char *buf)
1582 {
1583 struct it87_data *data = it87_update_device(dev);
1584 struct sensor_device_attribute_2 *sensor_attr =
1585 to_sensor_dev_attr_2(attr);
1586 int nr = sensor_attr->nr;
1587 int point = sensor_attr->index;
1588 int reg;
1589
1590 if (has_old_autopwm(data) || point)
1591 reg = data->auto_temp[nr][point];
1592 else
1593 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1594
1595 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1596 }
1597
1598 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1599 const char *buf, size_t count)
1600 {
1601 struct it87_data *data = dev_get_drvdata(dev);
1602 struct sensor_device_attribute_2 *sensor_attr =
1603 to_sensor_dev_attr_2(attr);
1604 int nr = sensor_attr->nr;
1605 int point = sensor_attr->index;
1606 long val;
1607 int reg;
1608
1609 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1610 return -EINVAL;
1611
1612 mutex_lock(&data->update_lock);
1613 if (has_newer_autopwm(data) && !point) {
1614 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1615 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1616 data->auto_temp[nr][0] = reg;
1617 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1618 } else {
1619 reg = TEMP_TO_REG(val);
1620 data->auto_temp[nr][point] = reg;
1621 if (has_newer_autopwm(data))
1622 point--;
1623 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1624 }
1625 mutex_unlock(&data->update_lock);
1626 return count;
1627 }
1628
1629 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1630 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1631 0, 1);
1632 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1633 set_fan_div, 0);
1634
1635 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1636 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1637 1, 1);
1638 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1639 set_fan_div, 1);
1640
1641 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1642 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1643 2, 1);
1644 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1645 set_fan_div, 2);
1646
1647 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1648 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1649 3, 1);
1650
1651 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1652 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1653 4, 1);
1654
1655 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1656 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1657 5, 1);
1658
1659 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1660 show_pwm_enable, set_pwm_enable, 0);
1661 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1662 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1663 set_pwm_freq, 0);
1664 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
1665 show_pwm_temp_map, set_pwm_temp_map, 0);
1666 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1667 show_auto_pwm, set_auto_pwm, 0, 0);
1668 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1669 show_auto_pwm, set_auto_pwm, 0, 1);
1670 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1671 show_auto_pwm, set_auto_pwm, 0, 2);
1672 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1673 show_auto_pwm, NULL, 0, 3);
1674 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1675 show_auto_temp, set_auto_temp, 0, 1);
1676 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1677 show_auto_temp, set_auto_temp, 0, 0);
1678 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1679 show_auto_temp, set_auto_temp, 0, 2);
1680 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1681 show_auto_temp, set_auto_temp, 0, 3);
1682 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1683 show_auto_temp, set_auto_temp, 0, 4);
1684 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
1685 show_auto_pwm, set_auto_pwm, 0, 0);
1686 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
1687 show_auto_pwm_slope, set_auto_pwm_slope, 0);
1688
1689 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1690 show_pwm_enable, set_pwm_enable, 1);
1691 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1692 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
1693 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
1694 show_pwm_temp_map, set_pwm_temp_map, 1);
1695 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1696 show_auto_pwm, set_auto_pwm, 1, 0);
1697 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1698 show_auto_pwm, set_auto_pwm, 1, 1);
1699 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1700 show_auto_pwm, set_auto_pwm, 1, 2);
1701 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1702 show_auto_pwm, NULL, 1, 3);
1703 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1704 show_auto_temp, set_auto_temp, 1, 1);
1705 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1706 show_auto_temp, set_auto_temp, 1, 0);
1707 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1708 show_auto_temp, set_auto_temp, 1, 2);
1709 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1710 show_auto_temp, set_auto_temp, 1, 3);
1711 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1712 show_auto_temp, set_auto_temp, 1, 4);
1713 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
1714 show_auto_pwm, set_auto_pwm, 1, 0);
1715 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
1716 show_auto_pwm_slope, set_auto_pwm_slope, 1);
1717
1718 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1719 show_pwm_enable, set_pwm_enable, 2);
1720 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
1721 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
1722 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
1723 show_pwm_temp_map, set_pwm_temp_map, 2);
1724 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1725 show_auto_pwm, set_auto_pwm, 2, 0);
1726 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1727 show_auto_pwm, set_auto_pwm, 2, 1);
1728 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1729 show_auto_pwm, set_auto_pwm, 2, 2);
1730 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1731 show_auto_pwm, NULL, 2, 3);
1732 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1733 show_auto_temp, set_auto_temp, 2, 1);
1734 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1735 show_auto_temp, set_auto_temp, 2, 0);
1736 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1737 show_auto_temp, set_auto_temp, 2, 2);
1738 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1739 show_auto_temp, set_auto_temp, 2, 3);
1740 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1741 show_auto_temp, set_auto_temp, 2, 4);
1742 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
1743 show_auto_pwm, set_auto_pwm, 2, 0);
1744 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
1745 show_auto_pwm_slope, set_auto_pwm_slope, 2);
1746
1747 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
1748 show_pwm_enable, set_pwm_enable, 3);
1749 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
1750 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
1751 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
1752 show_pwm_temp_map, set_pwm_temp_map, 3);
1753 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
1754 show_auto_temp, set_auto_temp, 2, 1);
1755 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1756 show_auto_temp, set_auto_temp, 2, 0);
1757 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
1758 show_auto_temp, set_auto_temp, 2, 2);
1759 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
1760 show_auto_temp, set_auto_temp, 2, 3);
1761 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
1762 show_auto_pwm, set_auto_pwm, 3, 0);
1763 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
1764 show_auto_pwm_slope, set_auto_pwm_slope, 3);
1765
1766 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
1767 show_pwm_enable, set_pwm_enable, 4);
1768 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
1769 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
1770 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
1771 show_pwm_temp_map, set_pwm_temp_map, 4);
1772 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
1773 show_auto_temp, set_auto_temp, 2, 1);
1774 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1775 show_auto_temp, set_auto_temp, 2, 0);
1776 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
1777 show_auto_temp, set_auto_temp, 2, 2);
1778 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
1779 show_auto_temp, set_auto_temp, 2, 3);
1780 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
1781 show_auto_pwm, set_auto_pwm, 4, 0);
1782 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
1783 show_auto_pwm_slope, set_auto_pwm_slope, 4);
1784
1785 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
1786 show_pwm_enable, set_pwm_enable, 5);
1787 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
1788 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
1789 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
1790 show_pwm_temp_map, set_pwm_temp_map, 5);
1791 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
1792 show_auto_temp, set_auto_temp, 2, 1);
1793 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1794 show_auto_temp, set_auto_temp, 2, 0);
1795 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
1796 show_auto_temp, set_auto_temp, 2, 2);
1797 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
1798 show_auto_temp, set_auto_temp, 2, 3);
1799 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
1800 show_auto_pwm, set_auto_pwm, 5, 0);
1801 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
1802 show_auto_pwm_slope, set_auto_pwm_slope, 5);
1803
1804 /* Alarms */
1805 static ssize_t alarms_show(struct device *dev, struct device_attribute *attr,
1806 char *buf)
1807 {
1808 struct it87_data *data = it87_update_device(dev);
1809
1810 return sprintf(buf, "%u\n", data->alarms);
1811 }
1812 static DEVICE_ATTR_RO(alarms);
1813
1814 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
1815 char *buf)
1816 {
1817 struct it87_data *data = it87_update_device(dev);
1818 int bitnr = to_sensor_dev_attr(attr)->index;
1819
1820 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1821 }
1822
1823 static ssize_t clear_intrusion(struct device *dev,
1824 struct device_attribute *attr, const char *buf,
1825 size_t count)
1826 {
1827 struct it87_data *data = dev_get_drvdata(dev);
1828 int config;
1829 long val;
1830
1831 if (kstrtol(buf, 10, &val) < 0 || val != 0)
1832 return -EINVAL;
1833
1834 mutex_lock(&data->update_lock);
1835 config = it87_read_value(data, IT87_REG_CONFIG);
1836 if (config < 0) {
1837 count = config;
1838 } else {
1839 config |= BIT(5);
1840 it87_write_value(data, IT87_REG_CONFIG, config);
1841 /* Invalidate cache to force re-read */
1842 data->valid = 0;
1843 }
1844 mutex_unlock(&data->update_lock);
1845
1846 return count;
1847 }
1848
1849 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1850 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1851 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1852 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1853 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1854 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1855 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1856 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1857 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1858 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1859 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1860 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1861 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
1862 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
1863 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1864 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1865 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
1866 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1867 show_alarm, clear_intrusion, 4);
1868
1869 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
1870 char *buf)
1871 {
1872 struct it87_data *data = it87_update_device(dev);
1873 int bitnr = to_sensor_dev_attr(attr)->index;
1874
1875 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1876 }
1877
1878 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
1879 const char *buf, size_t count)
1880 {
1881 int bitnr = to_sensor_dev_attr(attr)->index;
1882 struct it87_data *data = dev_get_drvdata(dev);
1883 long val;
1884
1885 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
1886 return -EINVAL;
1887
1888 mutex_lock(&data->update_lock);
1889 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1890 if (val)
1891 data->beeps |= BIT(bitnr);
1892 else
1893 data->beeps &= ~BIT(bitnr);
1894 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1895 mutex_unlock(&data->update_lock);
1896 return count;
1897 }
1898
1899 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1900 show_beep, set_beep, 1);
1901 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1902 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1903 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1904 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1905 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1906 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1907 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1908 /* fanX_beep writability is set later */
1909 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1910 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1911 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1912 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1913 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
1914 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
1915 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1916 show_beep, set_beep, 2);
1917 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1918 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1919
1920 static ssize_t vrm_show(struct device *dev, struct device_attribute *attr,
1921 char *buf)
1922 {
1923 struct it87_data *data = dev_get_drvdata(dev);
1924
1925 return sprintf(buf, "%u\n", data->vrm);
1926 }
1927
1928 static ssize_t vrm_store(struct device *dev, struct device_attribute *attr,
1929 const char *buf, size_t count)
1930 {
1931 struct it87_data *data = dev_get_drvdata(dev);
1932 unsigned long val;
1933
1934 if (kstrtoul(buf, 10, &val) < 0)
1935 return -EINVAL;
1936
1937 data->vrm = val;
1938
1939 return count;
1940 }
1941 static DEVICE_ATTR_RW(vrm);
1942
1943 static ssize_t cpu0_vid_show(struct device *dev,
1944 struct device_attribute *attr, char *buf)
1945 {
1946 struct it87_data *data = it87_update_device(dev);
1947
1948 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
1949 }
1950 static DEVICE_ATTR_RO(cpu0_vid);
1951
1952 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
1953 char *buf)
1954 {
1955 static const char * const labels[] = {
1956 "+5V",
1957 "5VSB",
1958 "Vbat",
1959 "AVCC",
1960 };
1961 static const char * const labels_it8721[] = {
1962 "+3.3V",
1963 "3VSB",
1964 "Vbat",
1965 "+3.3V",
1966 };
1967 struct it87_data *data = dev_get_drvdata(dev);
1968 int nr = to_sensor_dev_attr(attr)->index;
1969 const char *label;
1970
1971 if (has_vin3_5v(data) && nr == 0)
1972 label = labels[0];
1973 else if (has_12mv_adc(data) || has_10_9mv_adc(data))
1974 label = labels_it8721[nr];
1975 else
1976 label = labels[nr];
1977
1978 return sprintf(buf, "%s\n", label);
1979 }
1980 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1981 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1982 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
1983 /* AVCC3 */
1984 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
1985
1986 static umode_t it87_in_is_visible(struct kobject *kobj,
1987 struct attribute *attr, int index)
1988 {
1989 struct device *dev = container_of(kobj, struct device, kobj);
1990 struct it87_data *data = dev_get_drvdata(dev);
1991 int i = index / 5; /* voltage index */
1992 int a = index % 5; /* attribute index */
1993
1994 if (index >= 40) { /* in8 and higher only have input attributes */
1995 i = index - 40 + 8;
1996 a = 0;
1997 }
1998
1999 if (!(data->has_in & BIT(i)))
2000 return 0;
2001
2002 if (a == 4 && !data->has_beep)
2003 return 0;
2004
2005 return attr->mode;
2006 }
2007
2008 static struct attribute *it87_attributes_in[] = {
2009 &sensor_dev_attr_in0_input.dev_attr.attr,
2010 &sensor_dev_attr_in0_min.dev_attr.attr,
2011 &sensor_dev_attr_in0_max.dev_attr.attr,
2012 &sensor_dev_attr_in0_alarm.dev_attr.attr,
2013 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
2014
2015 &sensor_dev_attr_in1_input.dev_attr.attr,
2016 &sensor_dev_attr_in1_min.dev_attr.attr,
2017 &sensor_dev_attr_in1_max.dev_attr.attr,
2018 &sensor_dev_attr_in1_alarm.dev_attr.attr,
2019 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
2020
2021 &sensor_dev_attr_in2_input.dev_attr.attr,
2022 &sensor_dev_attr_in2_min.dev_attr.attr,
2023 &sensor_dev_attr_in2_max.dev_attr.attr,
2024 &sensor_dev_attr_in2_alarm.dev_attr.attr,
2025 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
2026
2027 &sensor_dev_attr_in3_input.dev_attr.attr,
2028 &sensor_dev_attr_in3_min.dev_attr.attr,
2029 &sensor_dev_attr_in3_max.dev_attr.attr,
2030 &sensor_dev_attr_in3_alarm.dev_attr.attr,
2031 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
2032
2033 &sensor_dev_attr_in4_input.dev_attr.attr,
2034 &sensor_dev_attr_in4_min.dev_attr.attr,
2035 &sensor_dev_attr_in4_max.dev_attr.attr,
2036 &sensor_dev_attr_in4_alarm.dev_attr.attr,
2037 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
2038
2039 &sensor_dev_attr_in5_input.dev_attr.attr,
2040 &sensor_dev_attr_in5_min.dev_attr.attr,
2041 &sensor_dev_attr_in5_max.dev_attr.attr,
2042 &sensor_dev_attr_in5_alarm.dev_attr.attr,
2043 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
2044
2045 &sensor_dev_attr_in6_input.dev_attr.attr,
2046 &sensor_dev_attr_in6_min.dev_attr.attr,
2047 &sensor_dev_attr_in6_max.dev_attr.attr,
2048 &sensor_dev_attr_in6_alarm.dev_attr.attr,
2049 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
2050
2051 &sensor_dev_attr_in7_input.dev_attr.attr,
2052 &sensor_dev_attr_in7_min.dev_attr.attr,
2053 &sensor_dev_attr_in7_max.dev_attr.attr,
2054 &sensor_dev_attr_in7_alarm.dev_attr.attr,
2055 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
2056
2057 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
2058 &sensor_dev_attr_in9_input.dev_attr.attr,
2059 &sensor_dev_attr_in10_input.dev_attr.attr,
2060 &sensor_dev_attr_in11_input.dev_attr.attr,
2061 &sensor_dev_attr_in12_input.dev_attr.attr,
2062 NULL
2063 };
2064
2065 static const struct attribute_group it87_group_in = {
2066 .attrs = it87_attributes_in,
2067 .is_visible = it87_in_is_visible,
2068 };
2069
2070 static umode_t it87_temp_is_visible(struct kobject *kobj,
2071 struct attribute *attr, int index)
2072 {
2073 struct device *dev = container_of(kobj, struct device, kobj);
2074 struct it87_data *data = dev_get_drvdata(dev);
2075 int i = index / 7; /* temperature index */
2076 int a = index % 7; /* attribute index */
2077
2078 if (index >= 21) {
2079 i = index - 21 + 3;
2080 a = 0;
2081 }
2082
2083 if (!(data->has_temp & BIT(i)))
2084 return 0;
2085
2086 if (a == 5 && !has_temp_offset(data))
2087 return 0;
2088
2089 if (a == 6 && !data->has_beep)
2090 return 0;
2091
2092 return attr->mode;
2093 }
2094
2095 static struct attribute *it87_attributes_temp[] = {
2096 &sensor_dev_attr_temp1_input.dev_attr.attr,
2097 &sensor_dev_attr_temp1_max.dev_attr.attr,
2098 &sensor_dev_attr_temp1_min.dev_attr.attr,
2099 &sensor_dev_attr_temp1_type.dev_attr.attr,
2100 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2101 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
2102 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
2103
2104 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
2105 &sensor_dev_attr_temp2_max.dev_attr.attr,
2106 &sensor_dev_attr_temp2_min.dev_attr.attr,
2107 &sensor_dev_attr_temp2_type.dev_attr.attr,
2108 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2109 &sensor_dev_attr_temp2_offset.dev_attr.attr,
2110 &sensor_dev_attr_temp2_beep.dev_attr.attr,
2111
2112 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
2113 &sensor_dev_attr_temp3_max.dev_attr.attr,
2114 &sensor_dev_attr_temp3_min.dev_attr.attr,
2115 &sensor_dev_attr_temp3_type.dev_attr.attr,
2116 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2117 &sensor_dev_attr_temp3_offset.dev_attr.attr,
2118 &sensor_dev_attr_temp3_beep.dev_attr.attr,
2119
2120 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
2121 &sensor_dev_attr_temp5_input.dev_attr.attr,
2122 &sensor_dev_attr_temp6_input.dev_attr.attr,
2123 NULL
2124 };
2125
2126 static const struct attribute_group it87_group_temp = {
2127 .attrs = it87_attributes_temp,
2128 .is_visible = it87_temp_is_visible,
2129 };
2130
2131 static umode_t it87_is_visible(struct kobject *kobj,
2132 struct attribute *attr, int index)
2133 {
2134 struct device *dev = container_of(kobj, struct device, kobj);
2135 struct it87_data *data = dev_get_drvdata(dev);
2136
2137 if ((index == 2 || index == 3) && !data->has_vid)
2138 return 0;
2139
2140 if (index > 3 && !(data->in_internal & BIT(index - 4)))
2141 return 0;
2142
2143 return attr->mode;
2144 }
2145
2146 static struct attribute *it87_attributes[] = {
2147 &dev_attr_alarms.attr,
2148 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2149 &dev_attr_vrm.attr, /* 2 */
2150 &dev_attr_cpu0_vid.attr, /* 3 */
2151 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
2152 &sensor_dev_attr_in7_label.dev_attr.attr,
2153 &sensor_dev_attr_in8_label.dev_attr.attr,
2154 &sensor_dev_attr_in9_label.dev_attr.attr,
2155 NULL
2156 };
2157
2158 static const struct attribute_group it87_group = {
2159 .attrs = it87_attributes,
2160 .is_visible = it87_is_visible,
2161 };
2162
2163 static umode_t it87_fan_is_visible(struct kobject *kobj,
2164 struct attribute *attr, int index)
2165 {
2166 struct device *dev = container_of(kobj, struct device, kobj);
2167 struct it87_data *data = dev_get_drvdata(dev);
2168 int i = index / 5; /* fan index */
2169 int a = index % 5; /* attribute index */
2170
2171 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
2172 i = (index - 15) / 4 + 3;
2173 a = (index - 15) % 4;
2174 }
2175
2176 if (!(data->has_fan & BIT(i)))
2177 return 0;
2178
2179 if (a == 3) { /* beep */
2180 if (!data->has_beep)
2181 return 0;
2182 /* first fan beep attribute is writable */
2183 if (i == __ffs(data->has_fan))
2184 return attr->mode | S_IWUSR;
2185 }
2186
2187 if (a == 4 && has_16bit_fans(data)) /* divisor */
2188 return 0;
2189
2190 return attr->mode;
2191 }
2192
2193 static struct attribute *it87_attributes_fan[] = {
2194 &sensor_dev_attr_fan1_input.dev_attr.attr,
2195 &sensor_dev_attr_fan1_min.dev_attr.attr,
2196 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2197 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
2198 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
2199
2200 &sensor_dev_attr_fan2_input.dev_attr.attr,
2201 &sensor_dev_attr_fan2_min.dev_attr.attr,
2202 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2203 &sensor_dev_attr_fan2_beep.dev_attr.attr,
2204 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
2205
2206 &sensor_dev_attr_fan3_input.dev_attr.attr,
2207 &sensor_dev_attr_fan3_min.dev_attr.attr,
2208 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2209 &sensor_dev_attr_fan3_beep.dev_attr.attr,
2210 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
2211
2212 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
2213 &sensor_dev_attr_fan4_min.dev_attr.attr,
2214 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2215 &sensor_dev_attr_fan4_beep.dev_attr.attr,
2216
2217 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
2218 &sensor_dev_attr_fan5_min.dev_attr.attr,
2219 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2220 &sensor_dev_attr_fan5_beep.dev_attr.attr,
2221
2222 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
2223 &sensor_dev_attr_fan6_min.dev_attr.attr,
2224 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2225 &sensor_dev_attr_fan6_beep.dev_attr.attr,
2226 NULL
2227 };
2228
2229 static const struct attribute_group it87_group_fan = {
2230 .attrs = it87_attributes_fan,
2231 .is_visible = it87_fan_is_visible,
2232 };
2233
2234 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2235 struct attribute *attr, int index)
2236 {
2237 struct device *dev = container_of(kobj, struct device, kobj);
2238 struct it87_data *data = dev_get_drvdata(dev);
2239 int i = index / 4; /* pwm index */
2240 int a = index % 4; /* attribute index */
2241
2242 if (!(data->has_pwm & BIT(i)))
2243 return 0;
2244
2245 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2246 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2247 return attr->mode | S_IWUSR;
2248
2249 /* pwm2_freq is writable if there are two pwm frequency selects */
2250 if (has_pwm_freq2(data) && i == 1 && a == 2)
2251 return attr->mode | S_IWUSR;
2252
2253 return attr->mode;
2254 }
2255
2256 static struct attribute *it87_attributes_pwm[] = {
2257 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2258 &sensor_dev_attr_pwm1.dev_attr.attr,
2259 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2260 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2261
2262 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2263 &sensor_dev_attr_pwm2.dev_attr.attr,
2264 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2265 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2266
2267 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2268 &sensor_dev_attr_pwm3.dev_attr.attr,
2269 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2270 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2271
2272 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2273 &sensor_dev_attr_pwm4.dev_attr.attr,
2274 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2275 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2276
2277 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2278 &sensor_dev_attr_pwm5.dev_attr.attr,
2279 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2280 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2281
2282 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2283 &sensor_dev_attr_pwm6.dev_attr.attr,
2284 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2285 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2286
2287 NULL
2288 };
2289
2290 static const struct attribute_group it87_group_pwm = {
2291 .attrs = it87_attributes_pwm,
2292 .is_visible = it87_pwm_is_visible,
2293 };
2294
2295 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2296 struct attribute *attr, int index)
2297 {
2298 struct device *dev = container_of(kobj, struct device, kobj);
2299 struct it87_data *data = dev_get_drvdata(dev);
2300 int i = index / 11; /* pwm index */
2301 int a = index % 11; /* attribute index */
2302
2303 if (index >= 33) { /* pwm 4..6 */
2304 i = (index - 33) / 6 + 3;
2305 a = (index - 33) % 6 + 4;
2306 }
2307
2308 if (!(data->has_pwm & BIT(i)))
2309 return 0;
2310
2311 if (has_newer_autopwm(data)) {
2312 if (a < 4) /* no auto point pwm */
2313 return 0;
2314 if (a == 8) /* no auto_point4 */
2315 return 0;
2316 }
2317 if (has_old_autopwm(data)) {
2318 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
2319 return 0;
2320 }
2321
2322 return attr->mode;
2323 }
2324
2325 static struct attribute *it87_attributes_auto_pwm[] = {
2326 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2327 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2328 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2329 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2330 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2331 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2332 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2333 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2334 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2335 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2336 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2337
2338 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */
2339 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2340 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2341 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2342 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2343 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2344 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2345 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2346 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2347 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2348 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2349
2350 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */
2351 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2352 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2353 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2354 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2355 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2356 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2357 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2358 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2359 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2360 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2361
2362 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */
2363 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2364 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2365 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2366 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2367 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2368
2369 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2370 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2371 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2372 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2373 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2374 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2375
2376 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2377 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2378 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2379 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2380 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2381 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2382
2383 NULL,
2384 };
2385
2386 static const struct attribute_group it87_group_auto_pwm = {
2387 .attrs = it87_attributes_auto_pwm,
2388 .is_visible = it87_auto_pwm_is_visible,
2389 };
2390
2391 /* SuperIO detection - will change isa_address if a chip is found */
2392 static int __init it87_find(int sioaddr, unsigned short *address,
2393 struct it87_sio_data *sio_data)
2394 {
2395 int err;
2396 u16 chip_type;
2397 const char *board_vendor, *board_name;
2398 const struct it87_devices *config;
2399
2400 err = superio_enter(sioaddr);
2401 if (err)
2402 return err;
2403
2404 err = -ENODEV;
2405 chip_type = force_id ? force_id : superio_inw(sioaddr, DEVID);
2406
2407 switch (chip_type) {
2408 case IT8705F_DEVID:
2409 sio_data->type = it87;
2410 break;
2411 case IT8712F_DEVID:
2412 sio_data->type = it8712;
2413 break;
2414 case IT8716F_DEVID:
2415 case IT8726F_DEVID:
2416 sio_data->type = it8716;
2417 break;
2418 case IT8718F_DEVID:
2419 sio_data->type = it8718;
2420 break;
2421 case IT8720F_DEVID:
2422 sio_data->type = it8720;
2423 break;
2424 case IT8721F_DEVID:
2425 sio_data->type = it8721;
2426 break;
2427 case IT8728F_DEVID:
2428 sio_data->type = it8728;
2429 break;
2430 case IT8732F_DEVID:
2431 sio_data->type = it8732;
2432 break;
2433 case IT8792E_DEVID:
2434 sio_data->type = it8792;
2435 break;
2436 case IT8771E_DEVID:
2437 sio_data->type = it8771;
2438 break;
2439 case IT8772E_DEVID:
2440 sio_data->type = it8772;
2441 break;
2442 case IT8781F_DEVID:
2443 sio_data->type = it8781;
2444 break;
2445 case IT8782F_DEVID:
2446 sio_data->type = it8782;
2447 break;
2448 case IT8783E_DEVID:
2449 sio_data->type = it8783;
2450 break;
2451 case IT8786E_DEVID:
2452 sio_data->type = it8786;
2453 break;
2454 case IT8790E_DEVID:
2455 sio_data->type = it8790;
2456 break;
2457 case IT8603E_DEVID:
2458 case IT8623E_DEVID:
2459 sio_data->type = it8603;
2460 break;
2461 case IT8620E_DEVID:
2462 sio_data->type = it8620;
2463 break;
2464 case IT8622E_DEVID:
2465 sio_data->type = it8622;
2466 break;
2467 case IT8628E_DEVID:
2468 sio_data->type = it8628;
2469 break;
2470 case 0xffff: /* No device at all */
2471 goto exit;
2472 default:
2473 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2474 goto exit;
2475 }
2476
2477 superio_select(sioaddr, PME);
2478 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2479 pr_info("Device not activated, skipping\n");
2480 goto exit;
2481 }
2482
2483 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2484 if (*address == 0) {
2485 pr_info("Base address not set, skipping\n");
2486 goto exit;
2487 }
2488
2489 err = 0;
2490 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2491 pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2492 it87_devices[sio_data->type].suffix,
2493 *address, sio_data->revision);
2494
2495 config = &it87_devices[sio_data->type];
2496
2497 /* in7 (VSB or VCCH5V) is always internal on some chips */
2498 if (has_in7_internal(config))
2499 sio_data->internal |= BIT(1);
2500
2501 /* in8 (Vbat) is always internal */
2502 sio_data->internal |= BIT(2);
2503
2504 /* in9 (AVCC3), always internal if supported */
2505 if (has_avcc3(config))
2506 sio_data->internal |= BIT(3); /* in9 is AVCC */
2507 else
2508 sio_data->skip_in |= BIT(9);
2509
2510 if (!has_five_pwm(config))
2511 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2512 else if (!has_six_pwm(config))
2513 sio_data->skip_pwm |= BIT(5);
2514
2515 if (!has_vid(config))
2516 sio_data->skip_vid = 1;
2517
2518 /* Read GPIO config and VID value from LDN 7 (GPIO) */
2519 if (sio_data->type == it87) {
2520 /* The IT8705F has a different LD number for GPIO */
2521 superio_select(sioaddr, 5);
2522 sio_data->beep_pin = superio_inb(sioaddr,
2523 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2524 } else if (sio_data->type == it8783) {
2525 int reg25, reg27, reg2a, reg2c, regef;
2526
2527 superio_select(sioaddr, GPIO);
2528
2529 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2530 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2531 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2532 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2533 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2534
2535 /* Check if fan3 is there or not */
2536 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2537 sio_data->skip_fan |= BIT(2);
2538 if ((reg25 & BIT(4)) ||
2539 (!(reg2a & BIT(1)) && (regef & BIT(0))))
2540 sio_data->skip_pwm |= BIT(2);
2541
2542 /* Check if fan2 is there or not */
2543 if (reg27 & BIT(7))
2544 sio_data->skip_fan |= BIT(1);
2545 if (reg27 & BIT(3))
2546 sio_data->skip_pwm |= BIT(1);
2547
2548 /* VIN5 */
2549 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2550 sio_data->skip_in |= BIT(5); /* No VIN5 */
2551
2552 /* VIN6 */
2553 if (reg27 & BIT(1))
2554 sio_data->skip_in |= BIT(6); /* No VIN6 */
2555
2556 /*
2557 * VIN7
2558 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2559 */
2560 if (reg27 & BIT(2)) {
2561 /*
2562 * The data sheet is a bit unclear regarding the
2563 * internal voltage divider for VCCH5V. It says
2564 * "This bit enables and switches VIN7 (pin 91) to the
2565 * internal voltage divider for VCCH5V".
2566 * This is different to other chips, where the internal
2567 * voltage divider would connect VIN7 to an internal
2568 * voltage source. Maybe that is the case here as well.
2569 *
2570 * Since we don't know for sure, re-route it if that is
2571 * not the case, and ask the user to report if the
2572 * resulting voltage is sane.
2573 */
2574 if (!(reg2c & BIT(1))) {
2575 reg2c |= BIT(1);
2576 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2577 reg2c);
2578 pr_notice("Routing internal VCCH5V to in7.\n");
2579 }
2580 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2581 pr_notice("Please report if it displays a reasonable voltage.\n");
2582 }
2583
2584 if (reg2c & BIT(0))
2585 sio_data->internal |= BIT(0);
2586 if (reg2c & BIT(1))
2587 sio_data->internal |= BIT(1);
2588
2589 sio_data->beep_pin = superio_inb(sioaddr,
2590 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2591 } else if (sio_data->type == it8603) {
2592 int reg27, reg29;
2593
2594 superio_select(sioaddr, GPIO);
2595
2596 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2597
2598 /* Check if fan3 is there or not */
2599 if (reg27 & BIT(6))
2600 sio_data->skip_pwm |= BIT(2);
2601 if (reg27 & BIT(7))
2602 sio_data->skip_fan |= BIT(2);
2603
2604 /* Check if fan2 is there or not */
2605 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2606 if (reg29 & BIT(1))
2607 sio_data->skip_pwm |= BIT(1);
2608 if (reg29 & BIT(2))
2609 sio_data->skip_fan |= BIT(1);
2610
2611 sio_data->skip_in |= BIT(5); /* No VIN5 */
2612 sio_data->skip_in |= BIT(6); /* No VIN6 */
2613
2614 sio_data->beep_pin = superio_inb(sioaddr,
2615 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2616 } else if (sio_data->type == it8620 || sio_data->type == it8628) {
2617 int reg;
2618
2619 superio_select(sioaddr, GPIO);
2620
2621 /* Check for pwm5 */
2622 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2623 if (reg & BIT(6))
2624 sio_data->skip_pwm |= BIT(4);
2625
2626 /* Check for fan4, fan5 */
2627 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2628 if (!(reg & BIT(5)))
2629 sio_data->skip_fan |= BIT(3);
2630 if (!(reg & BIT(4)))
2631 sio_data->skip_fan |= BIT(4);
2632
2633 /* Check for pwm3, fan3 */
2634 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2635 if (reg & BIT(6))
2636 sio_data->skip_pwm |= BIT(2);
2637 if (reg & BIT(7))
2638 sio_data->skip_fan |= BIT(2);
2639
2640 /* Check for pwm4 */
2641 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
2642 if (reg & BIT(2))
2643 sio_data->skip_pwm |= BIT(3);
2644
2645 /* Check for pwm2, fan2 */
2646 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2647 if (reg & BIT(1))
2648 sio_data->skip_pwm |= BIT(1);
2649 if (reg & BIT(2))
2650 sio_data->skip_fan |= BIT(1);
2651 /* Check for pwm6, fan6 */
2652 if (!(reg & BIT(7))) {
2653 sio_data->skip_pwm |= BIT(5);
2654 sio_data->skip_fan |= BIT(5);
2655 }
2656
2657 /* Check if AVCC is on VIN3 */
2658 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2659 if (reg & BIT(0))
2660 sio_data->internal |= BIT(0);
2661 else
2662 sio_data->skip_in |= BIT(9);
2663
2664 sio_data->beep_pin = superio_inb(sioaddr,
2665 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2666 } else if (sio_data->type == it8622) {
2667 int reg;
2668
2669 superio_select(sioaddr, GPIO);
2670
2671 /* Check for pwm4, fan4 */
2672 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2673 if (reg & BIT(6))
2674 sio_data->skip_fan |= BIT(3);
2675 if (reg & BIT(5))
2676 sio_data->skip_pwm |= BIT(3);
2677
2678 /* Check for pwm3, fan3, pwm5, fan5 */
2679 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2680 if (reg & BIT(6))
2681 sio_data->skip_pwm |= BIT(2);
2682 if (reg & BIT(7))
2683 sio_data->skip_fan |= BIT(2);
2684 if (reg & BIT(3))
2685 sio_data->skip_pwm |= BIT(4);
2686 if (reg & BIT(1))
2687 sio_data->skip_fan |= BIT(4);
2688
2689 /* Check for pwm2, fan2 */
2690 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2691 if (reg & BIT(1))
2692 sio_data->skip_pwm |= BIT(1);
2693 if (reg & BIT(2))
2694 sio_data->skip_fan |= BIT(1);
2695
2696 /* Check for AVCC */
2697 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2698 if (!(reg & BIT(0)))
2699 sio_data->skip_in |= BIT(9);
2700
2701 sio_data->beep_pin = superio_inb(sioaddr,
2702 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2703 } else {
2704 int reg;
2705 bool uart6;
2706
2707 superio_select(sioaddr, GPIO);
2708
2709 /* Check for fan4, fan5 */
2710 if (has_five_fans(config)) {
2711 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2712 switch (sio_data->type) {
2713 case it8718:
2714 if (reg & BIT(5))
2715 sio_data->skip_fan |= BIT(3);
2716 if (reg & BIT(4))
2717 sio_data->skip_fan |= BIT(4);
2718 break;
2719 case it8720:
2720 case it8721:
2721 case it8728:
2722 if (!(reg & BIT(5)))
2723 sio_data->skip_fan |= BIT(3);
2724 if (!(reg & BIT(4)))
2725 sio_data->skip_fan |= BIT(4);
2726 break;
2727 default:
2728 break;
2729 }
2730 }
2731
2732 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2733 if (!sio_data->skip_vid) {
2734 /* We need at least 4 VID pins */
2735 if (reg & 0x0f) {
2736 pr_info("VID is disabled (pins used for GPIO)\n");
2737 sio_data->skip_vid = 1;
2738 }
2739 }
2740
2741 /* Check if fan3 is there or not */
2742 if (reg & BIT(6))
2743 sio_data->skip_pwm |= BIT(2);
2744 if (reg & BIT(7))
2745 sio_data->skip_fan |= BIT(2);
2746
2747 /* Check if fan2 is there or not */
2748 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
2749 if (reg & BIT(1))
2750 sio_data->skip_pwm |= BIT(1);
2751 if (reg & BIT(2))
2752 sio_data->skip_fan |= BIT(1);
2753
2754 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
2755 !(sio_data->skip_vid))
2756 sio_data->vid_value = superio_inb(sioaddr,
2757 IT87_SIO_VID_REG);
2758
2759 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2760
2761 uart6 = sio_data->type == it8782 && (reg & BIT(2));
2762
2763 /*
2764 * The IT8720F has no VIN7 pin, so VCCH should always be
2765 * routed internally to VIN7 with an internal divider.
2766 * Curiously, there still is a configuration bit to control
2767 * this, which means it can be set incorrectly. And even
2768 * more curiously, many boards out there are improperly
2769 * configured, even though the IT8720F datasheet claims
2770 * that the internal routing of VCCH to VIN7 is the default
2771 * setting. So we force the internal routing in this case.
2772 *
2773 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
2774 * If UART6 is enabled, re-route VIN7 to the internal divider
2775 * if that is not already the case.
2776 */
2777 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
2778 reg |= BIT(1);
2779 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
2780 pr_notice("Routing internal VCCH to in7\n");
2781 }
2782 if (reg & BIT(0))
2783 sio_data->internal |= BIT(0);
2784 if (reg & BIT(1))
2785 sio_data->internal |= BIT(1);
2786
2787 /*
2788 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
2789 * While VIN7 can be routed to the internal voltage divider,
2790 * VIN5 and VIN6 are not available if UART6 is enabled.
2791 *
2792 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
2793 * is the temperature source. Since we can not read the
2794 * temperature source here, skip_temp is preliminary.
2795 */
2796 if (uart6) {
2797 sio_data->skip_in |= BIT(5) | BIT(6);
2798 sio_data->skip_temp |= BIT(2);
2799 }
2800
2801 sio_data->beep_pin = superio_inb(sioaddr,
2802 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2803 }
2804 if (sio_data->beep_pin)
2805 pr_info("Beeping is supported\n");
2806
2807 /* Disable specific features based on DMI strings */
2808 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
2809 board_name = dmi_get_system_info(DMI_BOARD_NAME);
2810 if (board_vendor && board_name) {
2811 if (strcmp(board_vendor, "nVIDIA") == 0 &&
2812 strcmp(board_name, "FN68PT") == 0) {
2813 /*
2814 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
2815 * connected to a fan, but to something else. One user
2816 * has reported instant system power-off when changing
2817 * the PWM2 duty cycle, so we disable it.
2818 * I use the board name string as the trigger in case
2819 * the same board is ever used in other systems.
2820 */
2821 pr_info("Disabling pwm2 due to hardware constraints\n");
2822 sio_data->skip_pwm = BIT(1);
2823 }
2824 }
2825
2826 exit:
2827 superio_exit(sioaddr);
2828 return err;
2829 }
2830
2831 /* Called when we have found a new IT87. */
2832 static void it87_init_device(struct platform_device *pdev)
2833 {
2834 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
2835 struct it87_data *data = platform_get_drvdata(pdev);
2836 int tmp, i;
2837 u8 mask;
2838
2839 /*
2840 * For each PWM channel:
2841 * - If it is in automatic mode, setting to manual mode should set
2842 * the fan to full speed by default.
2843 * - If it is in manual mode, we need a mapping to temperature
2844 * channels to use when later setting to automatic mode later.
2845 * Use a 1:1 mapping by default (we are clueless.)
2846 * In both cases, the value can (and should) be changed by the user
2847 * prior to switching to a different mode.
2848 * Note that this is no longer needed for the IT8721F and later, as
2849 * these have separate registers for the temperature mapping and the
2850 * manual duty cycle.
2851 */
2852 for (i = 0; i < NUM_AUTO_PWM; i++) {
2853 data->pwm_temp_map[i] = i;
2854 data->pwm_duty[i] = 0x7f; /* Full speed */
2855 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
2856 }
2857
2858 /*
2859 * Some chips seem to have default value 0xff for all limit
2860 * registers. For low voltage limits it makes no sense and triggers
2861 * alarms, so change to 0 instead. For high temperature limits, it
2862 * means -1 degree C, which surprisingly doesn't trigger an alarm,
2863 * but is still confusing, so change to 127 degrees C.
2864 */
2865 for (i = 0; i < NUM_VIN_LIMIT; i++) {
2866 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
2867 if (tmp == 0xff)
2868 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
2869 }
2870 for (i = 0; i < NUM_TEMP_LIMIT; i++) {
2871 tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
2872 if (tmp == 0xff)
2873 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
2874 }
2875
2876 /*
2877 * Temperature channels are not forcibly enabled, as they can be
2878 * set to two different sensor types and we can't guess which one
2879 * is correct for a given system. These channels can be enabled at
2880 * run-time through the temp{1-3}_type sysfs accessors if needed.
2881 */
2882
2883 /* Check if voltage monitors are reset manually or by some reason */
2884 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
2885 if ((tmp & 0xff) == 0) {
2886 /* Enable all voltage monitors */
2887 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
2888 }
2889
2890 /* Check if tachometers are reset manually or by some reason */
2891 mask = 0x70 & ~(sio_data->skip_fan << 4);
2892 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
2893 if ((data->fan_main_ctrl & mask) == 0) {
2894 /* Enable all fan tachometers */
2895 data->fan_main_ctrl |= mask;
2896 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2897 data->fan_main_ctrl);
2898 }
2899 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
2900
2901 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
2902
2903 /* Set tachometers to 16-bit mode if needed */
2904 if (has_fan16_config(data)) {
2905 if (~tmp & 0x07 & data->has_fan) {
2906 dev_dbg(&pdev->dev,
2907 "Setting fan1-3 to 16-bit mode\n");
2908 it87_write_value(data, IT87_REG_FAN_16BIT,
2909 tmp | 0x07);
2910 }
2911 }
2912
2913 /* Check for additional fans */
2914 if (has_five_fans(data)) {
2915 if (tmp & BIT(4))
2916 data->has_fan |= BIT(3); /* fan4 enabled */
2917 if (tmp & BIT(5))
2918 data->has_fan |= BIT(4); /* fan5 enabled */
2919 if (has_six_fans(data) && (tmp & BIT(2)))
2920 data->has_fan |= BIT(5); /* fan6 enabled */
2921 }
2922
2923 /* Fan input pins may be used for alternative functions */
2924 data->has_fan &= ~sio_data->skip_fan;
2925
2926 /* Check if pwm5, pwm6 are enabled */
2927 if (has_six_pwm(data)) {
2928 /* The following code may be IT8620E specific */
2929 tmp = it87_read_value(data, IT87_REG_FAN_DIV);
2930 if ((tmp & 0xc0) == 0xc0)
2931 sio_data->skip_pwm |= BIT(4);
2932 if (!(tmp & BIT(3)))
2933 sio_data->skip_pwm |= BIT(5);
2934 }
2935
2936 /* Start monitoring */
2937 it87_write_value(data, IT87_REG_CONFIG,
2938 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
2939 | (update_vbat ? 0x41 : 0x01));
2940 }
2941
2942 /* Return 1 if and only if the PWM interface is safe to use */
2943 static int it87_check_pwm(struct device *dev)
2944 {
2945 struct it87_data *data = dev_get_drvdata(dev);
2946 /*
2947 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
2948 * and polarity set to active low is sign that this is the case so we
2949 * disable pwm control to protect the user.
2950 */
2951 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
2952
2953 if ((tmp & 0x87) == 0) {
2954 if (fix_pwm_polarity) {
2955 /*
2956 * The user asks us to attempt a chip reconfiguration.
2957 * This means switching to active high polarity and
2958 * inverting all fan speed values.
2959 */
2960 int i;
2961 u8 pwm[3];
2962
2963 for (i = 0; i < ARRAY_SIZE(pwm); i++)
2964 pwm[i] = it87_read_value(data,
2965 IT87_REG_PWM[i]);
2966
2967 /*
2968 * If any fan is in automatic pwm mode, the polarity
2969 * might be correct, as suspicious as it seems, so we
2970 * better don't change anything (but still disable the
2971 * PWM interface).
2972 */
2973 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
2974 dev_info(dev,
2975 "Reconfiguring PWM to active high polarity\n");
2976 it87_write_value(data, IT87_REG_FAN_CTL,
2977 tmp | 0x87);
2978 for (i = 0; i < 3; i++)
2979 it87_write_value(data,
2980 IT87_REG_PWM[i],
2981 0x7f & ~pwm[i]);
2982 return 1;
2983 }
2984
2985 dev_info(dev,
2986 "PWM configuration is too broken to be fixed\n");
2987 }
2988
2989 dev_info(dev,
2990 "Detected broken BIOS defaults, disabling PWM interface\n");
2991 return 0;
2992 } else if (fix_pwm_polarity) {
2993 dev_info(dev,
2994 "PWM configuration looks sane, won't touch\n");
2995 }
2996
2997 return 1;
2998 }
2999
3000 static int it87_probe(struct platform_device *pdev)
3001 {
3002 struct it87_data *data;
3003 struct resource *res;
3004 struct device *dev = &pdev->dev;
3005 struct it87_sio_data *sio_data = dev_get_platdata(dev);
3006 int enable_pwm_interface;
3007 struct device *hwmon_dev;
3008
3009 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3010 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3011 DRVNAME)) {
3012 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3013 (unsigned long)res->start,
3014 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3015 return -EBUSY;
3016 }
3017
3018 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3019 if (!data)
3020 return -ENOMEM;
3021
3022 data->addr = res->start;
3023 data->type = sio_data->type;
3024 data->features = it87_devices[sio_data->type].features;
3025 data->peci_mask = it87_devices[sio_data->type].peci_mask;
3026 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3027 /*
3028 * IT8705F Datasheet 0.4.1, 3h == Version G.
3029 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3030 * These are the first revisions with 16-bit tachometer support.
3031 */
3032 switch (data->type) {
3033 case it87:
3034 if (sio_data->revision >= 0x03) {
3035 data->features &= ~FEAT_OLD_AUTOPWM;
3036 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3037 }
3038 break;
3039 case it8712:
3040 if (sio_data->revision >= 0x08) {
3041 data->features &= ~FEAT_OLD_AUTOPWM;
3042 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3043 FEAT_FIVE_FANS;
3044 }
3045 break;
3046 default:
3047 break;
3048 }
3049
3050 /* Now, we do the remaining detection. */
3051 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3052 it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3053 return -ENODEV;
3054
3055 platform_set_drvdata(pdev, data);
3056
3057 mutex_init(&data->update_lock);
3058
3059 /* Check PWM configuration */
3060 enable_pwm_interface = it87_check_pwm(dev);
3061
3062 /* Starting with IT8721F, we handle scaling of internal voltages */
3063 if (has_12mv_adc(data)) {
3064 if (sio_data->internal & BIT(0))
3065 data->in_scaled |= BIT(3); /* in3 is AVCC */
3066 if (sio_data->internal & BIT(1))
3067 data->in_scaled |= BIT(7); /* in7 is VSB */
3068 if (sio_data->internal & BIT(2))
3069 data->in_scaled |= BIT(8); /* in8 is Vbat */
3070 if (sio_data->internal & BIT(3))
3071 data->in_scaled |= BIT(9); /* in9 is AVCC */
3072 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3073 sio_data->type == it8783) {
3074 if (sio_data->internal & BIT(0))
3075 data->in_scaled |= BIT(3); /* in3 is VCC5V */
3076 if (sio_data->internal & BIT(1))
3077 data->in_scaled |= BIT(7); /* in7 is VCCH5V */
3078 }
3079
3080 data->has_temp = 0x07;
3081 if (sio_data->skip_temp & BIT(2)) {
3082 if (sio_data->type == it8782 &&
3083 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3084 data->has_temp &= ~BIT(2);
3085 }
3086
3087 data->in_internal = sio_data->internal;
3088 data->has_in = 0x3ff & ~sio_data->skip_in;
3089
3090 if (has_six_temp(data)) {
3091 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3092
3093 /* Check for additional temperature sensors */
3094 if ((reg & 0x03) >= 0x02)
3095 data->has_temp |= BIT(3);
3096 if (((reg >> 2) & 0x03) >= 0x02)
3097 data->has_temp |= BIT(4);
3098 if (((reg >> 4) & 0x03) >= 0x02)
3099 data->has_temp |= BIT(5);
3100
3101 /* Check for additional voltage sensors */
3102 if ((reg & 0x03) == 0x01)
3103 data->has_in |= BIT(10);
3104 if (((reg >> 2) & 0x03) == 0x01)
3105 data->has_in |= BIT(11);
3106 if (((reg >> 4) & 0x03) == 0x01)
3107 data->has_in |= BIT(12);
3108 }
3109
3110 data->has_beep = !!sio_data->beep_pin;
3111
3112 /* Initialize the IT87 chip */
3113 it87_init_device(pdev);
3114
3115 if (!sio_data->skip_vid) {
3116 data->has_vid = true;
3117 data->vrm = vid_which_vrm();
3118 /* VID reading from Super-I/O config space if available */
3119 data->vid = sio_data->vid_value;
3120 }
3121
3122 /* Prepare for sysfs hooks */
3123 data->groups[0] = &it87_group;
3124 data->groups[1] = &it87_group_in;
3125 data->groups[2] = &it87_group_temp;
3126 data->groups[3] = &it87_group_fan;
3127
3128 if (enable_pwm_interface) {
3129 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3130 data->has_pwm &= ~sio_data->skip_pwm;
3131
3132 data->groups[4] = &it87_group_pwm;
3133 if (has_old_autopwm(data) || has_newer_autopwm(data))
3134 data->groups[5] = &it87_group_auto_pwm;
3135 }
3136
3137 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3138 it87_devices[sio_data->type].name,
3139 data, data->groups);
3140 return PTR_ERR_OR_ZERO(hwmon_dev);
3141 }
3142
3143 static struct platform_driver it87_driver = {
3144 .driver = {
3145 .name = DRVNAME,
3146 },
3147 .probe = it87_probe,
3148 };
3149
3150 static int __init it87_device_add(int index, unsigned short address,
3151 const struct it87_sio_data *sio_data)
3152 {
3153 struct platform_device *pdev;
3154 struct resource res = {
3155 .start = address + IT87_EC_OFFSET,
3156 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3157 .name = DRVNAME,
3158 .flags = IORESOURCE_IO,
3159 };
3160 int err;
3161
3162 err = acpi_check_resource_conflict(&res);
3163 if (err)
3164 return err;
3165
3166 pdev = platform_device_alloc(DRVNAME, address);
3167 if (!pdev)
3168 return -ENOMEM;
3169
3170 err = platform_device_add_resources(pdev, &res, 1);
3171 if (err) {
3172 pr_err("Device resource addition failed (%d)\n", err);
3173 goto exit_device_put;
3174 }
3175
3176 err = platform_device_add_data(pdev, sio_data,
3177 sizeof(struct it87_sio_data));
3178 if (err) {
3179 pr_err("Platform data allocation failed\n");
3180 goto exit_device_put;
3181 }
3182
3183 err = platform_device_add(pdev);
3184 if (err) {
3185 pr_err("Device addition failed (%d)\n", err);
3186 goto exit_device_put;
3187 }
3188
3189 it87_pdev[index] = pdev;
3190 return 0;
3191
3192 exit_device_put:
3193 platform_device_put(pdev);
3194 return err;
3195 }
3196
3197 static int __init sm_it87_init(void)
3198 {
3199 int sioaddr[2] = { REG_2E, REG_4E };
3200 struct it87_sio_data sio_data;
3201 unsigned short isa_address[2];
3202 bool found = false;
3203 int i, err;
3204
3205 err = platform_driver_register(&it87_driver);
3206 if (err)
3207 return err;
3208
3209 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3210 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3211 isa_address[i] = 0;
3212 err = it87_find(sioaddr[i], &isa_address[i], &sio_data);
3213 if (err || isa_address[i] == 0)
3214 continue;
3215 /*
3216 * Don't register second chip if its ISA address matches
3217 * the first chip's ISA address.
3218 */
3219 if (i && isa_address[i] == isa_address[0])
3220 break;
3221
3222 err = it87_device_add(i, isa_address[i], &sio_data);
3223 if (err)
3224 goto exit_dev_unregister;
3225
3226 found = true;
3227
3228 /*
3229 * IT8705F may respond on both SIO addresses.
3230 * Stop probing after finding one.
3231 */
3232 if (sio_data.type == it87)
3233 break;
3234 }
3235
3236 if (!found) {
3237 err = -ENODEV;
3238 goto exit_unregister;
3239 }
3240 return 0;
3241
3242 exit_dev_unregister:
3243 /* NULL check handled by platform_device_unregister */
3244 platform_device_unregister(it87_pdev[0]);
3245 exit_unregister:
3246 platform_driver_unregister(&it87_driver);
3247 return err;
3248 }
3249
3250 static void __exit sm_it87_exit(void)
3251 {
3252 /* NULL check handled by platform_device_unregister */
3253 platform_device_unregister(it87_pdev[1]);
3254 platform_device_unregister(it87_pdev[0]);
3255 platform_driver_unregister(&it87_driver);
3256 }
3257
3258 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3259 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3260 module_param(update_vbat, bool, 0);
3261 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3262 module_param(fix_pwm_polarity, bool, 0);
3263 MODULE_PARM_DESC(fix_pwm_polarity,
3264 "Force PWM polarity to active high (DANGEROUS)");
3265 MODULE_LICENSE("GPL");
3266
3267 module_init(sm_it87_init);
3268 module_exit(sm_it87_exit);
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