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Staging: batman-adv: fix function prototype
[linux-2.6/btrfs-unstable.git] / drivers / net / qlcnic / qlcnic_hw.c
blob0c2e1f08f4593af61350bf4bcd4d45452a27f4f4
1 /*
2 * Copyright (C) 2009 - QLogic Corporation.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
22 *
23 */
24
25 #include "qlcnic.h"
26
27 #include <linux/slab.h>
28 #include <net/ip.h>
29
30 #define MASK(n) ((1ULL<<(n))-1)
31 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
32
33 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
34
35 #define CRB_BLK(off) ((off >> 20) & 0x3f)
36 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
37 #define CRB_WINDOW_2M (0x130060)
38 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
39 #define CRB_INDIRECT_2M (0x1e0000UL)
40
41
42 #ifndef readq
43 static inline u64 readq(void __iomem *addr)
44 {
45 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
46 }
47 #endif
48
49 #ifndef writeq
50 static inline void writeq(u64 val, void __iomem *addr)
51 {
52 writel(((u32) (val)), (addr));
53 writel(((u32) (val >> 32)), (addr + 4));
54 }
55 #endif
56
57 static const struct crb_128M_2M_block_map
58 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
59 {{{0, 0, 0, 0} } }, /* 0: PCI */
60 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
61 {1, 0x0110000, 0x0120000, 0x130000},
62 {1, 0x0120000, 0x0122000, 0x124000},
63 {1, 0x0130000, 0x0132000, 0x126000},
64 {1, 0x0140000, 0x0142000, 0x128000},
65 {1, 0x0150000, 0x0152000, 0x12a000},
66 {1, 0x0160000, 0x0170000, 0x110000},
67 {1, 0x0170000, 0x0172000, 0x12e000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {0, 0x0000000, 0x0000000, 0x000000},
72 {0, 0x0000000, 0x0000000, 0x000000},
73 {0, 0x0000000, 0x0000000, 0x000000},
74 {1, 0x01e0000, 0x01e0800, 0x122000},
75 {0, 0x0000000, 0x0000000, 0x000000} } },
76 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
77 {{{0, 0, 0, 0} } }, /* 3: */
78 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
79 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
80 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
81 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
82 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {1, 0x08f0000, 0x08f2000, 0x172000} } },
98 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {1, 0x09f0000, 0x09f2000, 0x176000} } },
114 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
130 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
146 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
147 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
148 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
149 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
150 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
151 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
152 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
153 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
154 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
155 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
156 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
157 {{{0, 0, 0, 0} } }, /* 23: */
158 {{{0, 0, 0, 0} } }, /* 24: */
159 {{{0, 0, 0, 0} } }, /* 25: */
160 {{{0, 0, 0, 0} } }, /* 26: */
161 {{{0, 0, 0, 0} } }, /* 27: */
162 {{{0, 0, 0, 0} } }, /* 28: */
163 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
164 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
165 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
166 {{{0} } }, /* 32: PCI */
167 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
168 {1, 0x2110000, 0x2120000, 0x130000},
169 {1, 0x2120000, 0x2122000, 0x124000},
170 {1, 0x2130000, 0x2132000, 0x126000},
171 {1, 0x2140000, 0x2142000, 0x128000},
172 {1, 0x2150000, 0x2152000, 0x12a000},
173 {1, 0x2160000, 0x2170000, 0x110000},
174 {1, 0x2170000, 0x2172000, 0x12e000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000} } },
183 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
184 {{{0} } }, /* 35: */
185 {{{0} } }, /* 36: */
186 {{{0} } }, /* 37: */
187 {{{0} } }, /* 38: */
188 {{{0} } }, /* 39: */
189 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
190 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
191 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
192 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
193 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
194 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
195 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
196 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
197 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
198 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
199 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
200 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
201 {{{0} } }, /* 52: */
202 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
203 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
204 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
205 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
206 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
207 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
208 {{{0} } }, /* 59: I2C0 */
209 {{{0} } }, /* 60: I2C1 */
210 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
211 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
212 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
213 };
214
215 /*
216 * top 12 bits of crb internal address (hub, agent)
217 */
218 static const unsigned crb_hub_agt[64] = {
219 0,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
223 0,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
240 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
243 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
245 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
246 0,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
248 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
249 0,
250 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
251 0,
252 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
254 0,
255 0,
256 0,
257 0,
258 0,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
260 0,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
265 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
268 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
269 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
270 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
271 0,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
274 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
276 0,
277 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
278 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
279 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
280 0,
281 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
282 0,
283 };
284
285 /* PCI Windowing for DDR regions. */
286
287 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
288
289 int
290 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
291 {
292 int done = 0, timeout = 0;
293
294 while (!done) {
295 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
296 if (done == 1)
297 break;
298 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
299 dev_err(&adapter->pdev->dev,
300 "Failed to acquire sem=%d lock;reg_id=%d\n",
301 sem, id_reg);
302 return -EIO;
303 }
304 msleep(1);
305 }
306
307 if (id_reg)
308 QLCWR32(adapter, id_reg, adapter->portnum);
309
310 return 0;
311 }
312
313 void
314 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
315 {
316 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
317 }
318
319 static int
320 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
321 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
322 {
323 u32 i, producer, consumer;
324 struct qlcnic_cmd_buffer *pbuf;
325 struct cmd_desc_type0 *cmd_desc;
326 struct qlcnic_host_tx_ring *tx_ring;
327
328 i = 0;
329
330 if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
331 return -EIO;
332
333 tx_ring = adapter->tx_ring;
334 __netif_tx_lock_bh(tx_ring->txq);
335
336 producer = tx_ring->producer;
337 consumer = tx_ring->sw_consumer;
338
339 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
340 netif_tx_stop_queue(tx_ring->txq);
341 __netif_tx_unlock_bh(tx_ring->txq);
342 adapter->stats.xmit_off++;
343 return -EBUSY;
344 }
345
346 do {
347 cmd_desc = &cmd_desc_arr[i];
348
349 pbuf = &tx_ring->cmd_buf_arr[producer];
350 pbuf->skb = NULL;
351 pbuf->frag_count = 0;
352
353 memcpy(&tx_ring->desc_head[producer],
354 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
355
356 producer = get_next_index(producer, tx_ring->num_desc);
357 i++;
358
359 } while (i != nr_desc);
360
361 tx_ring->producer = producer;
362
363 qlcnic_update_cmd_producer(adapter, tx_ring);
364
365 __netif_tx_unlock_bh(tx_ring->txq);
366
367 return 0;
368 }
369
370 static int
371 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
372 unsigned op)
373 {
374 struct qlcnic_nic_req req;
375 struct qlcnic_mac_req *mac_req;
376 u64 word;
377
378 memset(&req, 0, sizeof(struct qlcnic_nic_req));
379 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
380
381 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
382 req.req_hdr = cpu_to_le64(word);
383
384 mac_req = (struct qlcnic_mac_req *)&req.words[0];
385 mac_req->op = op;
386 memcpy(mac_req->mac_addr, addr, 6);
387
388 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
389 }
390
391 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
392 {
393 struct list_head *head;
394 struct qlcnic_mac_list_s *cur;
395
396 /* look up if already exists */
397 list_for_each(head, &adapter->mac_list) {
398 cur = list_entry(head, struct qlcnic_mac_list_s, list);
399 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
400 return 0;
401 }
402
403 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
404 if (cur == NULL) {
405 dev_err(&adapter->netdev->dev,
406 "failed to add mac address filter\n");
407 return -ENOMEM;
408 }
409 memcpy(cur->mac_addr, addr, ETH_ALEN);
410 list_add_tail(&cur->list, &adapter->mac_list);
411
412 return qlcnic_sre_macaddr_change(adapter,
413 cur->mac_addr, QLCNIC_MAC_ADD);
414 }
415
416 void qlcnic_set_multi(struct net_device *netdev)
417 {
418 struct qlcnic_adapter *adapter = netdev_priv(netdev);
419 struct netdev_hw_addr *ha;
420 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
421 u32 mode = VPORT_MISS_MODE_DROP;
422
423 if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
424 return;
425
426 qlcnic_nic_add_mac(adapter, adapter->mac_addr);
427 qlcnic_nic_add_mac(adapter, bcast_addr);
428
429 if (netdev->flags & IFF_PROMISC) {
430 mode = VPORT_MISS_MODE_ACCEPT_ALL;
431 goto send_fw_cmd;
432 }
433
434 if ((netdev->flags & IFF_ALLMULTI) ||
435 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
436 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
437 goto send_fw_cmd;
438 }
439
440 if (!netdev_mc_empty(netdev)) {
441 netdev_for_each_mc_addr(ha, netdev) {
442 qlcnic_nic_add_mac(adapter, ha->addr);
443 }
444 }
445
446 send_fw_cmd:
447 qlcnic_nic_set_promisc(adapter, mode);
448 }
449
450 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
451 {
452 struct qlcnic_nic_req req;
453 u64 word;
454
455 memset(&req, 0, sizeof(struct qlcnic_nic_req));
456
457 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
458
459 word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
460 ((u64)adapter->portnum << 16);
461 req.req_hdr = cpu_to_le64(word);
462
463 req.words[0] = cpu_to_le64(mode);
464
465 return qlcnic_send_cmd_descs(adapter,
466 (struct cmd_desc_type0 *)&req, 1);
467 }
468
469 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
470 {
471 struct qlcnic_mac_list_s *cur;
472 struct list_head *head = &adapter->mac_list;
473
474 while (!list_empty(head)) {
475 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
476 qlcnic_sre_macaddr_change(adapter,
477 cur->mac_addr, QLCNIC_MAC_DEL);
478 list_del(&cur->list);
479 kfree(cur);
480 }
481 }
482
483 #define QLCNIC_CONFIG_INTR_COALESCE 3
484
485 /*
486 * Send the interrupt coalescing parameter set by ethtool to the card.
487 */
488 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
489 {
490 struct qlcnic_nic_req req;
491 u64 word[6];
492 int rv, i;
493
494 memset(&req, 0, sizeof(struct qlcnic_nic_req));
495
496 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
497
498 word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
499 req.req_hdr = cpu_to_le64(word[0]);
500
501 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
502 for (i = 0; i < 6; i++)
503 req.words[i] = cpu_to_le64(word[i]);
504
505 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
506 if (rv != 0)
507 dev_err(&adapter->netdev->dev,
508 "Could not send interrupt coalescing parameters\n");
509
510 return rv;
511 }
512
513 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
514 {
515 struct qlcnic_nic_req req;
516 u64 word;
517 int rv;
518
519 if ((adapter->flags & QLCNIC_LRO_ENABLED) == enable)
520 return 0;
521
522 memset(&req, 0, sizeof(struct qlcnic_nic_req));
523
524 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
525
526 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
527 req.req_hdr = cpu_to_le64(word);
528
529 req.words[0] = cpu_to_le64(enable);
530
531 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
532 if (rv != 0)
533 dev_err(&adapter->netdev->dev,
534 "Could not send configure hw lro request\n");
535
536 adapter->flags ^= QLCNIC_LRO_ENABLED;
537
538 return rv;
539 }
540
541 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, int enable)
542 {
543 struct qlcnic_nic_req req;
544 u64 word;
545 int rv;
546
547 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
548 return 0;
549
550 memset(&req, 0, sizeof(struct qlcnic_nic_req));
551
552 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
553
554 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
555 ((u64)adapter->portnum << 16);
556 req.req_hdr = cpu_to_le64(word);
557
558 req.words[0] = cpu_to_le64(enable);
559
560 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
561 if (rv != 0)
562 dev_err(&adapter->netdev->dev,
563 "Could not send configure bridge mode request\n");
564
565 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
566
567 return rv;
568 }
569
570
571 #define RSS_HASHTYPE_IP_TCP 0x3
572
573 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
574 {
575 struct qlcnic_nic_req req;
576 u64 word;
577 int i, rv;
578
579 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
580 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
581 0x255b0ec26d5a56daULL };
582
583
584 memset(&req, 0, sizeof(struct qlcnic_nic_req));
585 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
586
587 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
588 req.req_hdr = cpu_to_le64(word);
589
590 /*
591 * RSS request:
592 * bits 3-0: hash_method
593 * 5-4: hash_type_ipv4
594 * 7-6: hash_type_ipv6
595 * 8: enable
596 * 9: use indirection table
597 * 47-10: reserved
598 * 63-48: indirection table mask
599 */
600 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
601 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
602 ((u64)(enable & 0x1) << 8) |
603 ((0x7ULL) << 48);
604 req.words[0] = cpu_to_le64(word);
605 for (i = 0; i < 5; i++)
606 req.words[i+1] = cpu_to_le64(key[i]);
607
608 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
609 if (rv != 0)
610 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
611
612 return rv;
613 }
614
615 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd)
616 {
617 struct qlcnic_nic_req req;
618 u64 word;
619 int rv;
620
621 memset(&req, 0, sizeof(struct qlcnic_nic_req));
622 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
623
624 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
625 req.req_hdr = cpu_to_le64(word);
626
627 req.words[0] = cpu_to_le64(cmd);
628 req.words[1] = cpu_to_le64(ip);
629
630 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
631 if (rv != 0)
632 dev_err(&adapter->netdev->dev,
633 "could not notify %s IP 0x%x reuqest\n",
634 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
635
636 return rv;
637 }
638
639 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
640 {
641 struct qlcnic_nic_req req;
642 u64 word;
643 int rv;
644
645 memset(&req, 0, sizeof(struct qlcnic_nic_req));
646 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
647
648 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
649 req.req_hdr = cpu_to_le64(word);
650 req.words[0] = cpu_to_le64(enable | (enable << 8));
651
652 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
653 if (rv != 0)
654 dev_err(&adapter->netdev->dev,
655 "could not configure link notification\n");
656
657 return rv;
658 }
659
660 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
661 {
662 struct qlcnic_nic_req req;
663 u64 word;
664 int rv;
665
666 memset(&req, 0, sizeof(struct qlcnic_nic_req));
667 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
668
669 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
670 ((u64)adapter->portnum << 16) |
671 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
672
673 req.req_hdr = cpu_to_le64(word);
674
675 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
676 if (rv != 0)
677 dev_err(&adapter->netdev->dev,
678 "could not cleanup lro flows\n");
679
680 return rv;
681 }
682
683 /*
684 * qlcnic_change_mtu - Change the Maximum Transfer Unit
685 * @returns 0 on success, negative on failure
686 */
687
688 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
689 {
690 struct qlcnic_adapter *adapter = netdev_priv(netdev);
691 int rc = 0;
692
693 if (mtu > P3_MAX_MTU) {
694 dev_err(&adapter->netdev->dev, "mtu > %d bytes unsupported\n",
695 P3_MAX_MTU);
696 return -EINVAL;
697 }
698
699 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
700
701 if (!rc)
702 netdev->mtu = mtu;
703
704 return rc;
705 }
706
707 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u64 *mac)
708 {
709 u32 crbaddr, mac_hi, mac_lo;
710 int pci_func = adapter->ahw.pci_func;
711
712 crbaddr = CRB_MAC_BLOCK_START +
713 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
714
715 mac_lo = QLCRD32(adapter, crbaddr);
716 mac_hi = QLCRD32(adapter, crbaddr+4);
717
718 if (pci_func & 1)
719 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
720 else
721 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
722
723 return 0;
724 }
725
726 /*
727 * Changes the CRB window to the specified window.
728 */
729 /* Returns < 0 if off is not valid,
730 * 1 if window access is needed. 'off' is set to offset from
731 * CRB space in 128M pci map
732 * 0 if no window access is needed. 'off' is set to 2M addr
733 * In: 'off' is offset from base in 128M pci map
734 */
735 static int
736 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
737 ulong off, void __iomem **addr)
738 {
739 const struct crb_128M_2M_sub_block_map *m;
740
741 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
742 return -EINVAL;
743
744 off -= QLCNIC_PCI_CRBSPACE;
745
746 /*
747 * Try direct map
748 */
749 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
750
751 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
752 *addr = adapter->ahw.pci_base0 + m->start_2M +
753 (off - m->start_128M);
754 return 0;
755 }
756
757 /*
758 * Not in direct map, use crb window
759 */
760 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
761 return 1;
762 }
763
764 /*
765 * In: 'off' is offset from CRB space in 128M pci map
766 * Out: 'off' is 2M pci map addr
767 * side effect: lock crb window
768 */
769 static void
770 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
771 {
772 u32 window;
773 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
774
775 off -= QLCNIC_PCI_CRBSPACE;
776
777 window = CRB_HI(off);
778
779 writel(window, addr);
780 if (readl(addr) != window) {
781 if (printk_ratelimit())
782 dev_warn(&adapter->pdev->dev,
783 "failed to set CRB window to %d off 0x%lx\n",
784 window, off);
785 }
786 }
787
788 int
789 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
790 {
791 unsigned long flags;
792 int rv;
793 void __iomem *addr = NULL;
794
795 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
796
797 if (rv == 0) {
798 writel(data, addr);
799 return 0;
800 }
801
802 if (rv > 0) {
803 /* indirect access */
804 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
805 crb_win_lock(adapter);
806 qlcnic_pci_set_crbwindow_2M(adapter, off);
807 writel(data, addr);
808 crb_win_unlock(adapter);
809 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
810 return 0;
811 }
812
813 dev_err(&adapter->pdev->dev,
814 "%s: invalid offset: 0x%016lx\n", __func__, off);
815 dump_stack();
816 return -EIO;
817 }
818
819 u32
820 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
821 {
822 unsigned long flags;
823 int rv;
824 u32 data;
825 void __iomem *addr = NULL;
826
827 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
828
829 if (rv == 0)
830 return readl(addr);
831
832 if (rv > 0) {
833 /* indirect access */
834 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
835 crb_win_lock(adapter);
836 qlcnic_pci_set_crbwindow_2M(adapter, off);
837 data = readl(addr);
838 crb_win_unlock(adapter);
839 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
840 return data;
841 }
842
843 dev_err(&adapter->pdev->dev,
844 "%s: invalid offset: 0x%016lx\n", __func__, off);
845 dump_stack();
846 return -1;
847 }
848
849
850 void __iomem *
851 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
852 {
853 void __iomem *addr = NULL;
854
855 WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
856
857 return addr;
858 }
859
860
861 static int
862 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
863 u64 addr, u32 *start)
864 {
865 u32 window;
866
867 window = OCM_WIN_P3P(addr);
868
869 writel(window, adapter->ahw.ocm_win_crb);
870 /* read back to flush */
871 readl(adapter->ahw.ocm_win_crb);
872
873 *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
874 return 0;
875 }
876
877 static int
878 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
879 u64 *data, int op)
880 {
881 void __iomem *addr;
882 int ret;
883 u32 start;
884
885 mutex_lock(&adapter->ahw.mem_lock);
886
887 ret = qlcnic_pci_set_window_2M(adapter, off, &start);
888 if (ret != 0)
889 goto unlock;
890
891 addr = adapter->ahw.pci_base0 + start;
892
893 if (op == 0) /* read */
894 *data = readq(addr);
895 else /* write */
896 writeq(*data, addr);
897
898 unlock:
899 mutex_unlock(&adapter->ahw.mem_lock);
900
901 return ret;
902 }
903
904 void
905 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
906 {
907 void __iomem *addr = adapter->ahw.pci_base0 +
908 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
909
910 mutex_lock(&adapter->ahw.mem_lock);
911 *data = readq(addr);
912 mutex_unlock(&adapter->ahw.mem_lock);
913 }
914
915 void
916 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
917 {
918 void __iomem *addr = adapter->ahw.pci_base0 +
919 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
920
921 mutex_lock(&adapter->ahw.mem_lock);
922 writeq(data, addr);
923 mutex_unlock(&adapter->ahw.mem_lock);
924 }
925
926 #define MAX_CTL_CHECK 1000
927
928 int
929 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
930 u64 off, u64 data)
931 {
932 int i, j, ret;
933 u32 temp, off8;
934 void __iomem *mem_crb;
935
936 /* Only 64-bit aligned access */
937 if (off & 7)
938 return -EIO;
939
940 /* P3 onward, test agent base for MIU and SIU is same */
941 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
942 QLCNIC_ADDR_QDR_NET_MAX)) {
943 mem_crb = qlcnic_get_ioaddr(adapter,
944 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
945 goto correct;
946 }
947
948 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
949 mem_crb = qlcnic_get_ioaddr(adapter,
950 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
951 goto correct;
952 }
953
954 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
955 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
956
957 return -EIO;
958
959 correct:
960 off8 = off & ~0xf;
961
962 mutex_lock(&adapter->ahw.mem_lock);
963
964 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
965 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
966
967 i = 0;
968 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
969 writel((TA_CTL_START | TA_CTL_ENABLE),
970 (mem_crb + TEST_AGT_CTRL));
971
972 for (j = 0; j < MAX_CTL_CHECK; j++) {
973 temp = readl(mem_crb + TEST_AGT_CTRL);
974 if ((temp & TA_CTL_BUSY) == 0)
975 break;
976 }
977
978 if (j >= MAX_CTL_CHECK) {
979 ret = -EIO;
980 goto done;
981 }
982
983 i = (off & 0xf) ? 0 : 2;
984 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
985 mem_crb + MIU_TEST_AGT_WRDATA(i));
986 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
987 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
988 i = (off & 0xf) ? 2 : 0;
989
990 writel(data & 0xffffffff,
991 mem_crb + MIU_TEST_AGT_WRDATA(i));
992 writel((data >> 32) & 0xffffffff,
993 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
994
995 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
996 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
997 (mem_crb + TEST_AGT_CTRL));
998
999 for (j = 0; j < MAX_CTL_CHECK; j++) {
1000 temp = readl(mem_crb + TEST_AGT_CTRL);
1001 if ((temp & TA_CTL_BUSY) == 0)
1002 break;
1003 }
1004
1005 if (j >= MAX_CTL_CHECK) {
1006 if (printk_ratelimit())
1007 dev_err(&adapter->pdev->dev,
1008 "failed to write through agent\n");
1009 ret = -EIO;
1010 } else
1011 ret = 0;
1012
1013 done:
1014 mutex_unlock(&adapter->ahw.mem_lock);
1015
1016 return ret;
1017 }
1018
1019 int
1020 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1021 u64 off, u64 *data)
1022 {
1023 int j, ret;
1024 u32 temp, off8;
1025 u64 val;
1026 void __iomem *mem_crb;
1027
1028 /* Only 64-bit aligned access */
1029 if (off & 7)
1030 return -EIO;
1031
1032 /* P3 onward, test agent base for MIU and SIU is same */
1033 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1034 QLCNIC_ADDR_QDR_NET_MAX)) {
1035 mem_crb = qlcnic_get_ioaddr(adapter,
1036 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1037 goto correct;
1038 }
1039
1040 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1041 mem_crb = qlcnic_get_ioaddr(adapter,
1042 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1043 goto correct;
1044 }
1045
1046 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1047 return qlcnic_pci_mem_access_direct(adapter,
1048 off, data, 0);
1049 }
1050
1051 return -EIO;
1052
1053 correct:
1054 off8 = off & ~0xf;
1055
1056 mutex_lock(&adapter->ahw.mem_lock);
1057
1058 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1059 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1060 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1061 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1062
1063 for (j = 0; j < MAX_CTL_CHECK; j++) {
1064 temp = readl(mem_crb + TEST_AGT_CTRL);
1065 if ((temp & TA_CTL_BUSY) == 0)
1066 break;
1067 }
1068
1069 if (j >= MAX_CTL_CHECK) {
1070 if (printk_ratelimit())
1071 dev_err(&adapter->pdev->dev,
1072 "failed to read through agent\n");
1073 ret = -EIO;
1074 } else {
1075 off8 = MIU_TEST_AGT_RDDATA_LO;
1076 if (off & 0xf)
1077 off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1078
1079 temp = readl(mem_crb + off8 + 4);
1080 val = (u64)temp << 32;
1081 val |= readl(mem_crb + off8);
1082 *data = val;
1083 ret = 0;
1084 }
1085
1086 mutex_unlock(&adapter->ahw.mem_lock);
1087
1088 return ret;
1089 }
1090
1091 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1092 {
1093 int offset, board_type, magic;
1094 struct pci_dev *pdev = adapter->pdev;
1095
1096 offset = QLCNIC_FW_MAGIC_OFFSET;
1097 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1098 return -EIO;
1099
1100 if (magic != QLCNIC_BDINFO_MAGIC) {
1101 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1102 magic);
1103 return -EIO;
1104 }
1105
1106 offset = QLCNIC_BRDTYPE_OFFSET;
1107 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1108 return -EIO;
1109
1110 adapter->ahw.board_type = board_type;
1111
1112 if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1113 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1114 if ((gpio & 0x8000) == 0)
1115 board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1116 }
1117
1118 switch (board_type) {
1119 case QLCNIC_BRDTYPE_P3_HMEZ:
1120 case QLCNIC_BRDTYPE_P3_XG_LOM:
1121 case QLCNIC_BRDTYPE_P3_10G_CX4:
1122 case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1123 case QLCNIC_BRDTYPE_P3_IMEZ:
1124 case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1125 case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1126 case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1127 case QLCNIC_BRDTYPE_P3_10G_XFP:
1128 case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1129 adapter->ahw.port_type = QLCNIC_XGBE;
1130 break;
1131 case QLCNIC_BRDTYPE_P3_REF_QG:
1132 case QLCNIC_BRDTYPE_P3_4_GB:
1133 case QLCNIC_BRDTYPE_P3_4_GB_MM:
1134 adapter->ahw.port_type = QLCNIC_GBE;
1135 break;
1136 case QLCNIC_BRDTYPE_P3_10G_TP:
1137 adapter->ahw.port_type = (adapter->portnum < 2) ?
1138 QLCNIC_XGBE : QLCNIC_GBE;
1139 break;
1140 default:
1141 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1142 adapter->ahw.port_type = QLCNIC_XGBE;
1143 break;
1144 }
1145
1146 return 0;
1147 }
1148
1149 int
1150 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1151 {
1152 u32 wol_cfg;
1153
1154 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1155 if (wol_cfg & (1UL << adapter->portnum)) {
1156 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1157 if (wol_cfg & (1 << adapter->portnum))
1158 return 1;
1159 }
1160
1161 return 0;
1162 }
1163
1164 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1165 {
1166 struct qlcnic_nic_req req;
1167 int rv;
1168 u64 word;
1169
1170 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1171 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1172
1173 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1174 req.req_hdr = cpu_to_le64(word);
1175
1176 req.words[0] = cpu_to_le64((u64)rate << 32);
1177 req.words[1] = cpu_to_le64(state);
1178
1179 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1180 if (rv)
1181 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1182
1183 return rv;
1184 }
1185
1186 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1187 {
1188 struct qlcnic_nic_req req;
1189 int rv;
1190 u64 word;
1191
1192 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1193 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1194
1195 word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1196 ((u64)adapter->portnum << 16);
1197 req.req_hdr = cpu_to_le64(word);
1198 req.words[0] = cpu_to_le64(flag);
1199
1200 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1201 if (rv)
1202 dev_err(&adapter->pdev->dev,
1203 "%sting loopback mode failed.\n",
1204 flag ? "Set" : "Reset");
1205 return rv;
1206 }
1207
1208 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1209 {
1210 if (qlcnic_set_fw_loopback(adapter, 1))
1211 return -EIO;
1212
1213 if (qlcnic_nic_set_promisc(adapter,
1214 VPORT_MISS_MODE_ACCEPT_ALL)) {
1215 qlcnic_set_fw_loopback(adapter, 0);
1216 return -EIO;
1217 }
1218
1219 msleep(1000);
1220 return 0;
1221 }
1222
1223 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1224 {
1225 int mode = VPORT_MISS_MODE_DROP;
1226 struct net_device *netdev = adapter->netdev;
1227
1228 qlcnic_set_fw_loopback(adapter, 0);
1229
1230 if (netdev->flags & IFF_PROMISC)
1231 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1232 else if (netdev->flags & IFF_ALLMULTI)
1233 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1234
1235 qlcnic_nic_set_promisc(adapter, mode);
1236 }
(deprecated) Btrfs devel tree