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ARM: OMAP2xxx: hwmod/CM: add RNG integration data
[linux-2.6/btrfs-unstable.git] / arch / arm / mach-omap2 / omap_hwmod_2420_data.c
blobe778ff4e18877c0983225724803c01f7d59117fe
1 /*
2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * XXX handle crossbar/shared link difference for L3?
13 * XXX these should be marked initdata for multi-OMAP kernels
14 */
15 #include <plat/omap_hwmod.h>
16 #include <plat/dma.h>
17 #include <plat/serial.h>
18 #include <plat/i2c.h>
19 #include <plat/mcspi.h>
20 #include <plat/dmtimer.h>
21 #include <plat/l3_2xxx.h>
22 #include <plat/l4_2xxx.h>
23 #include <plat/mmc.h>
24
25 #include "omap_hwmod_common_data.h"
26
27 #include "cm-regbits-24xx.h"
28 #include "prm-regbits-24xx.h"
29 #include "wd_timer.h"
30
31 /*
32 * OMAP2420 hardware module integration data
33 *
34 * All of the data in this section should be autogeneratable from the
35 * TI hardware database or other technical documentation. Data that
36 * is driver-specific or driver-kernel integration-specific belongs
37 * elsewhere.
38 */
39
40 /*
41 * IP blocks
42 */
43
44 /* IVA1 (IVA1) */
45 static struct omap_hwmod_class iva1_hwmod_class = {
46 .name = "iva1",
47 };
48
49 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
50 { .name = "iva", .rst_shift = 8 },
51 };
52
53 static struct omap_hwmod omap2420_iva_hwmod = {
54 .name = "iva",
55 .class = &iva1_hwmod_class,
56 .clkdm_name = "iva1_clkdm",
57 .rst_lines = omap2420_iva_resets,
58 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
59 .main_clk = "iva1_ifck",
60 };
61
62 /* DSP */
63 static struct omap_hwmod_class dsp_hwmod_class = {
64 .name = "dsp",
65 };
66
67 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
68 { .name = "logic", .rst_shift = 0 },
69 { .name = "mmu", .rst_shift = 1 },
70 };
71
72 static struct omap_hwmod omap2420_dsp_hwmod = {
73 .name = "dsp",
74 .class = &dsp_hwmod_class,
75 .clkdm_name = "dsp_clkdm",
76 .rst_lines = omap2420_dsp_resets,
77 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
78 .main_clk = "dsp_fck",
79 };
80
81 /* I2C common */
82 static struct omap_hwmod_class_sysconfig i2c_sysc = {
83 .rev_offs = 0x00,
84 .sysc_offs = 0x20,
85 .syss_offs = 0x10,
86 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
87 .sysc_fields = &omap_hwmod_sysc_type1,
88 };
89
90 static struct omap_hwmod_class i2c_class = {
91 .name = "i2c",
92 .sysc = &i2c_sysc,
93 .rev = OMAP_I2C_IP_VERSION_1,
94 .reset = &omap_i2c_reset,
95 };
96
97 static struct omap_i2c_dev_attr i2c_dev_attr = {
98 .flags = OMAP_I2C_FLAG_NO_FIFO |
99 OMAP_I2C_FLAG_SIMPLE_CLOCK |
100 OMAP_I2C_FLAG_16BIT_DATA_REG |
101 OMAP_I2C_FLAG_BUS_SHIFT_2,
102 };
103
104 /* I2C1 */
105 static struct omap_hwmod omap2420_i2c1_hwmod = {
106 .name = "i2c1",
107 .mpu_irqs = omap2_i2c1_mpu_irqs,
108 .sdma_reqs = omap2_i2c1_sdma_reqs,
109 .main_clk = "i2c1_fck",
110 .prcm = {
111 .omap2 = {
112 .module_offs = CORE_MOD,
113 .prcm_reg_id = 1,
114 .module_bit = OMAP2420_EN_I2C1_SHIFT,
115 .idlest_reg_id = 1,
116 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
117 },
118 },
119 .class = &i2c_class,
120 .dev_attr = &i2c_dev_attr,
121 .flags = HWMOD_16BIT_REG,
122 };
123
124 /* I2C2 */
125 static struct omap_hwmod omap2420_i2c2_hwmod = {
126 .name = "i2c2",
127 .mpu_irqs = omap2_i2c2_mpu_irqs,
128 .sdma_reqs = omap2_i2c2_sdma_reqs,
129 .main_clk = "i2c2_fck",
130 .prcm = {
131 .omap2 = {
132 .module_offs = CORE_MOD,
133 .prcm_reg_id = 1,
134 .module_bit = OMAP2420_EN_I2C2_SHIFT,
135 .idlest_reg_id = 1,
136 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
137 },
138 },
139 .class = &i2c_class,
140 .dev_attr = &i2c_dev_attr,
141 .flags = HWMOD_16BIT_REG,
142 };
143
144 /* dma attributes */
145 static struct omap_dma_dev_attr dma_dev_attr = {
146 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
147 IS_CSSA_32 | IS_CDSA_32,
148 .lch_count = 32,
149 };
150
151 static struct omap_hwmod omap2420_dma_system_hwmod = {
152 .name = "dma",
153 .class = &omap2xxx_dma_hwmod_class,
154 .mpu_irqs = omap2_dma_system_irqs,
155 .main_clk = "core_l3_ck",
156 .dev_attr = &dma_dev_attr,
157 .flags = HWMOD_NO_IDLEST,
158 };
159
160 /* mailbox */
161 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
162 { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
163 { .name = "iva", .irq = 34 + OMAP_INTC_START, },
164 { .irq = -1 },
165 };
166
167 static struct omap_hwmod omap2420_mailbox_hwmod = {
168 .name = "mailbox",
169 .class = &omap2xxx_mailbox_hwmod_class,
170 .mpu_irqs = omap2420_mailbox_irqs,
171 .main_clk = "mailboxes_ick",
172 .prcm = {
173 .omap2 = {
174 .prcm_reg_id = 1,
175 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
176 .module_offs = CORE_MOD,
177 .idlest_reg_id = 1,
178 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
179 },
180 },
181 };
182
183 /*
184 * 'mcbsp' class
185 * multi channel buffered serial port controller
186 */
187
188 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
189 .name = "mcbsp",
190 };
191
192 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
193 { .role = "pad_fck", .clk = "mcbsp_clks" },
194 { .role = "prcm_fck", .clk = "func_96m_ck" },
195 };
196
197 /* mcbsp1 */
198 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
199 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
200 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
201 { .irq = -1 },
202 };
203
204 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
205 .name = "mcbsp1",
206 .class = &omap2420_mcbsp_hwmod_class,
207 .mpu_irqs = omap2420_mcbsp1_irqs,
208 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
209 .main_clk = "mcbsp1_fck",
210 .prcm = {
211 .omap2 = {
212 .prcm_reg_id = 1,
213 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
214 .module_offs = CORE_MOD,
215 .idlest_reg_id = 1,
216 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
217 },
218 },
219 .opt_clks = mcbsp_opt_clks,
220 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
221 };
222
223 /* mcbsp2 */
224 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
225 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
226 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
227 { .irq = -1 },
228 };
229
230 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
231 .name = "mcbsp2",
232 .class = &omap2420_mcbsp_hwmod_class,
233 .mpu_irqs = omap2420_mcbsp2_irqs,
234 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
235 .main_clk = "mcbsp2_fck",
236 .prcm = {
237 .omap2 = {
238 .prcm_reg_id = 1,
239 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
240 .module_offs = CORE_MOD,
241 .idlest_reg_id = 1,
242 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
243 },
244 },
245 .opt_clks = mcbsp_opt_clks,
246 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
247 };
248
249 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
250 .rev_offs = 0x3c,
251 .sysc_offs = 0x64,
252 .syss_offs = 0x68,
253 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
254 .sysc_fields = &omap_hwmod_sysc_type1,
255 };
256
257 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
258 .name = "msdi",
259 .sysc = &omap2420_msdi_sysc,
260 .reset = &omap_msdi_reset,
261 };
262
263 /* msdi1 */
264 static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
265 { .irq = 83 + OMAP_INTC_START, },
266 { .irq = -1 },
267 };
268
269 static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
270 { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
271 { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
272 { .dma_req = -1 }
273 };
274
275 static struct omap_hwmod omap2420_msdi1_hwmod = {
276 .name = "msdi1",
277 .class = &omap2420_msdi_hwmod_class,
278 .mpu_irqs = omap2420_msdi1_irqs,
279 .sdma_reqs = omap2420_msdi1_sdma_reqs,
280 .main_clk = "mmc_fck",
281 .prcm = {
282 .omap2 = {
283 .prcm_reg_id = 1,
284 .module_bit = OMAP2420_EN_MMC_SHIFT,
285 .module_offs = CORE_MOD,
286 .idlest_reg_id = 1,
287 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
288 },
289 },
290 .flags = HWMOD_16BIT_REG,
291 };
292
293 /* HDQ1W/1-wire */
294 static struct omap_hwmod omap2420_hdq1w_hwmod = {
295 .name = "hdq1w",
296 .mpu_irqs = omap2_hdq1w_mpu_irqs,
297 .main_clk = "hdq_fck",
298 .prcm = {
299 .omap2 = {
300 .module_offs = CORE_MOD,
301 .prcm_reg_id = 1,
302 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
303 .idlest_reg_id = 1,
304 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
305 },
306 },
307 .class = &omap2_hdq1w_class,
308 };
309
310 /*
311 * interfaces
312 */
313
314 /* L4 CORE -> I2C1 interface */
315 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
316 .master = &omap2xxx_l4_core_hwmod,
317 .slave = &omap2420_i2c1_hwmod,
318 .clk = "i2c1_ick",
319 .addr = omap2_i2c1_addr_space,
320 .user = OCP_USER_MPU | OCP_USER_SDMA,
321 };
322
323 /* L4 CORE -> I2C2 interface */
324 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
325 .master = &omap2xxx_l4_core_hwmod,
326 .slave = &omap2420_i2c2_hwmod,
327 .clk = "i2c2_ick",
328 .addr = omap2_i2c2_addr_space,
329 .user = OCP_USER_MPU | OCP_USER_SDMA,
330 };
331
332 /* IVA <- L3 interface */
333 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
334 .master = &omap2xxx_l3_main_hwmod,
335 .slave = &omap2420_iva_hwmod,
336 .clk = "core_l3_ck",
337 .user = OCP_USER_MPU | OCP_USER_SDMA,
338 };
339
340 /* DSP <- L3 interface */
341 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
342 .master = &omap2xxx_l3_main_hwmod,
343 .slave = &omap2420_dsp_hwmod,
344 .clk = "dsp_ick",
345 .user = OCP_USER_MPU | OCP_USER_SDMA,
346 };
347
348 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
349 {
350 .pa_start = 0x48028000,
351 .pa_end = 0x48028000 + SZ_1K - 1,
352 .flags = ADDR_TYPE_RT
353 },
354 { }
355 };
356
357 /* l4_wkup -> timer1 */
358 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
359 .master = &omap2xxx_l4_wkup_hwmod,
360 .slave = &omap2xxx_timer1_hwmod,
361 .clk = "gpt1_ick",
362 .addr = omap2420_timer1_addrs,
363 .user = OCP_USER_MPU | OCP_USER_SDMA,
364 };
365
366 /* l4_wkup -> wd_timer2 */
367 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
368 {
369 .pa_start = 0x48022000,
370 .pa_end = 0x4802207f,
371 .flags = ADDR_TYPE_RT
372 },
373 { }
374 };
375
376 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
377 .master = &omap2xxx_l4_wkup_hwmod,
378 .slave = &omap2xxx_wd_timer2_hwmod,
379 .clk = "mpu_wdt_ick",
380 .addr = omap2420_wd_timer2_addrs,
381 .user = OCP_USER_MPU | OCP_USER_SDMA,
382 };
383
384 /* l4_wkup -> gpio1 */
385 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
386 {
387 .pa_start = 0x48018000,
388 .pa_end = 0x480181ff,
389 .flags = ADDR_TYPE_RT
390 },
391 { }
392 };
393
394 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
395 .master = &omap2xxx_l4_wkup_hwmod,
396 .slave = &omap2xxx_gpio1_hwmod,
397 .clk = "gpios_ick",
398 .addr = omap2420_gpio1_addr_space,
399 .user = OCP_USER_MPU | OCP_USER_SDMA,
400 };
401
402 /* l4_wkup -> gpio2 */
403 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
404 {
405 .pa_start = 0x4801a000,
406 .pa_end = 0x4801a1ff,
407 .flags = ADDR_TYPE_RT
408 },
409 { }
410 };
411
412 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
413 .master = &omap2xxx_l4_wkup_hwmod,
414 .slave = &omap2xxx_gpio2_hwmod,
415 .clk = "gpios_ick",
416 .addr = omap2420_gpio2_addr_space,
417 .user = OCP_USER_MPU | OCP_USER_SDMA,
418 };
419
420 /* l4_wkup -> gpio3 */
421 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
422 {
423 .pa_start = 0x4801c000,
424 .pa_end = 0x4801c1ff,
425 .flags = ADDR_TYPE_RT
426 },
427 { }
428 };
429
430 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
431 .master = &omap2xxx_l4_wkup_hwmod,
432 .slave = &omap2xxx_gpio3_hwmod,
433 .clk = "gpios_ick",
434 .addr = omap2420_gpio3_addr_space,
435 .user = OCP_USER_MPU | OCP_USER_SDMA,
436 };
437
438 /* l4_wkup -> gpio4 */
439 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
440 {
441 .pa_start = 0x4801e000,
442 .pa_end = 0x4801e1ff,
443 .flags = ADDR_TYPE_RT
444 },
445 { }
446 };
447
448 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
449 .master = &omap2xxx_l4_wkup_hwmod,
450 .slave = &omap2xxx_gpio4_hwmod,
451 .clk = "gpios_ick",
452 .addr = omap2420_gpio4_addr_space,
453 .user = OCP_USER_MPU | OCP_USER_SDMA,
454 };
455
456 /* dma_system -> L3 */
457 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
458 .master = &omap2420_dma_system_hwmod,
459 .slave = &omap2xxx_l3_main_hwmod,
460 .clk = "core_l3_ck",
461 .user = OCP_USER_MPU | OCP_USER_SDMA,
462 };
463
464 /* l4_core -> dma_system */
465 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
466 .master = &omap2xxx_l4_core_hwmod,
467 .slave = &omap2420_dma_system_hwmod,
468 .clk = "sdma_ick",
469 .addr = omap2_dma_system_addrs,
470 .user = OCP_USER_MPU | OCP_USER_SDMA,
471 };
472
473 /* l4_core -> mailbox */
474 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
475 .master = &omap2xxx_l4_core_hwmod,
476 .slave = &omap2420_mailbox_hwmod,
477 .addr = omap2_mailbox_addrs,
478 .user = OCP_USER_MPU | OCP_USER_SDMA,
479 };
480
481 /* l4_core -> mcbsp1 */
482 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
483 .master = &omap2xxx_l4_core_hwmod,
484 .slave = &omap2420_mcbsp1_hwmod,
485 .clk = "mcbsp1_ick",
486 .addr = omap2_mcbsp1_addrs,
487 .user = OCP_USER_MPU | OCP_USER_SDMA,
488 };
489
490 /* l4_core -> mcbsp2 */
491 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
492 .master = &omap2xxx_l4_core_hwmod,
493 .slave = &omap2420_mcbsp2_hwmod,
494 .clk = "mcbsp2_ick",
495 .addr = omap2xxx_mcbsp2_addrs,
496 .user = OCP_USER_MPU | OCP_USER_SDMA,
497 };
498
499 static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
500 {
501 .pa_start = 0x4809c000,
502 .pa_end = 0x4809c000 + SZ_128 - 1,
503 .flags = ADDR_TYPE_RT,
504 },
505 { }
506 };
507
508 /* l4_core -> msdi1 */
509 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
510 .master = &omap2xxx_l4_core_hwmod,
511 .slave = &omap2420_msdi1_hwmod,
512 .clk = "mmc_ick",
513 .addr = omap2420_msdi1_addrs,
514 .user = OCP_USER_MPU | OCP_USER_SDMA,
515 };
516
517 /* l4_core -> hdq1w interface */
518 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
519 .master = &omap2xxx_l4_core_hwmod,
520 .slave = &omap2420_hdq1w_hwmod,
521 .clk = "hdq_ick",
522 .addr = omap2_hdq1w_addr_space,
523 .user = OCP_USER_MPU | OCP_USER_SDMA,
524 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
525 };
526
527
528 /* l4_wkup -> 32ksync_counter */
529 static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
530 {
531 .pa_start = 0x48004000,
532 .pa_end = 0x4800401f,
533 .flags = ADDR_TYPE_RT
534 },
535 { }
536 };
537
538 static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
539 {
540 .pa_start = 0x6800a000,
541 .pa_end = 0x6800afff,
542 .flags = ADDR_TYPE_RT
543 },
544 { }
545 };
546
547 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
548 .master = &omap2xxx_l4_wkup_hwmod,
549 .slave = &omap2xxx_counter_32k_hwmod,
550 .clk = "sync_32k_ick",
551 .addr = omap2420_counter_32k_addrs,
552 .user = OCP_USER_MPU | OCP_USER_SDMA,
553 };
554
555 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
556 .master = &omap2xxx_l3_main_hwmod,
557 .slave = &omap2xxx_gpmc_hwmod,
558 .clk = "core_l3_ck",
559 .addr = omap2420_gpmc_addrs,
560 .user = OCP_USER_MPU | OCP_USER_SDMA,
561 };
562
563 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
564 &omap2xxx_l3_main__l4_core,
565 &omap2xxx_mpu__l3_main,
566 &omap2xxx_dss__l3,
567 &omap2xxx_l4_core__mcspi1,
568 &omap2xxx_l4_core__mcspi2,
569 &omap2xxx_l4_core__l4_wkup,
570 &omap2_l4_core__uart1,
571 &omap2_l4_core__uart2,
572 &omap2_l4_core__uart3,
573 &omap2420_l4_core__i2c1,
574 &omap2420_l4_core__i2c2,
575 &omap2420_l3__iva,
576 &omap2420_l3__dsp,
577 &omap2420_l4_wkup__timer1,
578 &omap2xxx_l4_core__timer2,
579 &omap2xxx_l4_core__timer3,
580 &omap2xxx_l4_core__timer4,
581 &omap2xxx_l4_core__timer5,
582 &omap2xxx_l4_core__timer6,
583 &omap2xxx_l4_core__timer7,
584 &omap2xxx_l4_core__timer8,
585 &omap2xxx_l4_core__timer9,
586 &omap2xxx_l4_core__timer10,
587 &omap2xxx_l4_core__timer11,
588 &omap2xxx_l4_core__timer12,
589 &omap2420_l4_wkup__wd_timer2,
590 &omap2xxx_l4_core__dss,
591 &omap2xxx_l4_core__dss_dispc,
592 &omap2xxx_l4_core__dss_rfbi,
593 &omap2xxx_l4_core__dss_venc,
594 &omap2420_l4_wkup__gpio1,
595 &omap2420_l4_wkup__gpio2,
596 &omap2420_l4_wkup__gpio3,
597 &omap2420_l4_wkup__gpio4,
598 &omap2420_dma_system__l3,
599 &omap2420_l4_core__dma_system,
600 &omap2420_l4_core__mailbox,
601 &omap2420_l4_core__mcbsp1,
602 &omap2420_l4_core__mcbsp2,
603 &omap2420_l4_core__msdi1,
604 &omap2xxx_l4_core__rng,
605 &omap2420_l4_core__hdq1w,
606 &omap2420_l4_wkup__counter_32k,
607 &omap2420_l3__gpmc,
608 NULL,
609 };
610
611 int __init omap2420_hwmod_init(void)
612 {
613 omap_hwmod_init();
614 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
615 }
(deprecated) Btrfs devel tree