arch/x86/pci/intel_mid_pci.c

   1 /*
   2  * Intel MID PCI support
   3  *   Copyright (c) 2008 Intel Corporation
   4  *     Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Moorestown has an interesting PCI implementation:
   7  *   - configuration space is memory mapped (as defined by MCFG)
   8  *   - Lincroft devices also have a real, type 1 configuration space
   9  *   - Early Lincroft silicon has a type 1 access bug that will cause
  10  *     a hang if non-existent devices are accessed
  11  *   - some devices have the "fixed BAR" capability, which means
  12  *     they can't be relocated or modified; check for that during
  13  *     BAR sizing
  14  *
  15  * So, we use the MCFG space for all reads and writes, but also send
  16  * Lincroft writes to type 1 space.  But only read/write if the device
  17  * actually exists, otherwise return all 1s for reads and bit bucket
  18  * the writes.
  19  */
  20
  21 #include <linux/sched.h>
  22 #include <linux/pci.h>
  23 #include <linux/ioport.h>
  24 #include <linux/init.h>
  25 #include <linux/dmi.h>
  26 #include <linux/acpi.h>
  27 #include <linux/io.h>
  28 #include <linux/smp.h>
  29
  30 #include <asm/segment.h>
  31 #include <asm/pci_x86.h>
  32 #include <asm/hw_irq.h>
  33 #include <asm/io_apic.h>
  34 #include <asm/intel-mid.h>
  35
  36 #define PCIE_CAP_OFFSET 0x100
  37
  38 /* Quirks for the listed devices */
  39 #define PCI_DEVICE_ID_INTEL_MRFL_MMC    0x1190
  40 #define PCI_DEVICE_ID_INTEL_MRFL_HSU    0x1191
  41
  42 /* Fixed BAR fields */
  43 #define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
  44 #define PCI_FIXED_BAR_0_SIZE    0x04
  45 #define PCI_FIXED_BAR_1_SIZE    0x08
  46 #define PCI_FIXED_BAR_2_SIZE    0x0c
  47 #define PCI_FIXED_BAR_3_SIZE    0x10
  48 #define PCI_FIXED_BAR_4_SIZE    0x14
  49 #define PCI_FIXED_BAR_5_SIZE    0x1c
  50
  51 static int pci_soc_mode;
  52
  53 /**
  54  * fixed_bar_cap - return the offset of the fixed BAR cap if found
  55  * @bus: PCI bus
  56  * @devfn: device in question
  57  *
  58  * Look for the fixed BAR cap on @bus and @devfn, returning its offset
  59  * if found or 0 otherwise.
  60  */
  61 static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
  62 {
  63         int pos;
  64         u32 pcie_cap = 0, cap_data;
  65
  66         pos = PCIE_CAP_OFFSET;
  67
  68         if (!raw_pci_ext_ops)
  69                 return 0;
  70
  71         while (pos) {
  72                 if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
  73                                           devfn, pos, 4, &pcie_cap))
  74                         return 0;
  75
  76                 if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
  77                         PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
  78                         break;
  79
  80                 if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
  81                         raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
  82                                               devfn, pos + 4, 4, &cap_data);
  83                         if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
  84                                 return pos;
  85                 }
  86
  87                 pos = PCI_EXT_CAP_NEXT(pcie_cap);
  88         }
  89
  90         return 0;
  91 }
  92
  93 static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
  94                                    int reg, int len, u32 val, int offset)
  95 {
  96         u32 size;
  97         unsigned int domain, busnum;
  98         int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
  99
 100         domain = pci_domain_nr(bus);
 101         busnum = bus->number;
 102
 103         if (val == ~0 && len == 4) {
 104                 unsigned long decode;
 105
 106                 raw_pci_ext_ops->read(domain, busnum, devfn,
 107                                offset + 8 + (bar * 4), 4, &size);
 108
 109                 /* Turn the size into a decode pattern for the sizing code */
 110                 if (size) {
 111                         decode = size - 1;
 112                         decode |= decode >> 1;
 113                         decode |= decode >> 2;
 114                         decode |= decode >> 4;
 115                         decode |= decode >> 8;
 116                         decode |= decode >> 16;
 117                         decode++;
 118                         decode = ~(decode - 1);
 119                 } else {
 120                         decode = 0;
 121                 }
 122
 123                 /*
 124                  * If val is all ones, the core code is trying to size the reg,
 125                  * so update the mmconfig space with the real size.
 126                  *
 127                  * Note: this assumes the fixed size we got is a power of two.
 128                  */
 129                 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
 130                                        decode);
 131         }
 132
 133         /* This is some other kind of BAR write, so just do it. */
 134         return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
 135 }
 136
 137 /**
 138  * type1_access_ok - check whether to use type 1
 139  * @bus: bus number
 140  * @devfn: device & function in question
 141  *
 142  * If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
 143  * all, the we can go ahead with any reads & writes.  If it's on a Lincroft,
 144  * but doesn't exist, avoid the access altogether to keep the chip from
 145  * hanging.
 146  */
 147 static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
 148 {
 149         /*
 150          * This is a workaround for A0 LNC bug where PCI status register does
 151          * not have new CAP bit set. can not be written by SW either.
 152          *
 153          * PCI header type in real LNC indicates a single function device, this
 154          * will prevent probing other devices under the same function in PCI
 155          * shim. Therefore, use the header type in shim instead.
 156          */
 157         if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
 158                 return false;
 159         if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
 160                                 || devfn == PCI_DEVFN(0, 0)
 161                                 || devfn == PCI_DEVFN(3, 0)))
 162                 return true;
 163         return false; /* Langwell on others */
 164 }
 165
 166 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
 167                     int size, u32 *value)
 168 {
 169         if (type1_access_ok(bus->number, devfn, where))
 170                 return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
 171                                         devfn, where, size, value);
 172         return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
 173                               devfn, where, size, value);
 174 }
 175
 176 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
 177                      int size, u32 value)
 178 {
 179         int offset;
 180
 181         /*
 182          * On MRST, there is no PCI ROM BAR, this will cause a subsequent read
 183          * to ROM BAR return 0 then being ignored.
 184          */
 185         if (where == PCI_ROM_ADDRESS)
 186                 return 0;
 187
 188         /*
 189          * Devices with fixed BARs need special handling:
 190          *   - BAR sizing code will save, write ~0, read size, restore
 191          *   - so writes to fixed BARs need special handling
 192          *   - other writes to fixed BAR devices should go through mmconfig
 193          */
 194         offset = fixed_bar_cap(bus, devfn);
 195         if (offset &&
 196             (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
 197                 return pci_device_update_fixed(bus, devfn, where, size, value,
 198                                                offset);
 199         }
 200
 201         /*
 202          * On Moorestown update both real & mmconfig space
 203          * Note: early Lincroft silicon can't handle type 1 accesses to
 204          *       non-existent devices, so just eat the write in that case.
 205          */
 206         if (type1_access_ok(bus->number, devfn, where))
 207                 return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
 208                                               devfn, where, size, value);
 209         return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
 210                                where, size, value);
 211 }
 212
 213 static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 214 {
 215         struct irq_alloc_info info;
 216         int polarity;
 217         int ret;
 218
 219         if (dev->irq_managed && dev->irq > 0)
 220                 return 0;
 221
 222         switch (intel_mid_identify_cpu()) {
 223         case INTEL_MID_CPU_CHIP_TANGIER:
 224                 polarity = IOAPIC_POL_HIGH;
 225
 226                 /* Special treatment for IRQ0 */
 227                 if (dev->irq == 0) {
 228                         /*
 229                          * Skip HS UART common registers device since it has
 230                          * IRQ0 assigned and not used by the kernel.
 231                          */
 232                         if (dev->device == PCI_DEVICE_ID_INTEL_MRFL_HSU)
 233                                 return -EBUSY;
 234                         /*
 235                          * TNG has IRQ0 assigned to eMMC controller. But there
 236                          * are also other devices with bogus PCI configuration
 237                          * that have IRQ0 assigned. This check ensures that
 238                          * eMMC gets it. The rest of devices still could be
 239                          * enabled without interrupt line being allocated.
 240                          */
 241                         if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC)
 242                                 return 0;
 243                 }
 244                 break;
 245         default:
 246                 polarity = IOAPIC_POL_LOW;
 247                 break;
 248         }
 249
 250         ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity);
 251
 252         /*
 253          * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
 254          * IOAPIC RTE entries, so we just enable RTE for the device.
 255          */
 256         ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info);
 257         if (ret < 0)
 258                 return ret;
 259
 260         dev->irq_managed = 1;
 261
 262         return 0;
 263 }
 264
 265 static void intel_mid_pci_irq_disable(struct pci_dev *dev)
 266 {
 267         if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed &&
 268             dev->irq > 0) {
 269                 mp_unmap_irq(dev->irq);
 270                 dev->irq_managed = 0;
 271         }
 272 }
 273
 274 static struct pci_ops intel_mid_pci_ops = {
 275         .read = pci_read,
 276         .write = pci_write,
 277 };
 278
 279 /**
 280  * intel_mid_pci_init - installs intel_mid_pci_ops
 281  *
 282  * Moorestown has an interesting PCI implementation (see above).
 283  * Called when the early platform detection installs it.
 284  */
 285 int __init intel_mid_pci_init(void)
 286 {
 287         pr_info("Intel MID platform detected, using MID PCI ops\n");
 288         pci_mmcfg_late_init();
 289         pcibios_enable_irq = intel_mid_pci_irq_enable;
 290         pcibios_disable_irq = intel_mid_pci_irq_disable;
 291         pci_root_ops = intel_mid_pci_ops;
 292         pci_soc_mode = 1;
 293         /* Continue with standard init */
 294         return 1;
 295 }
 296
 297 /*
 298  * Langwell devices are not true PCI devices; they are not subject to 10 ms
 299  * d3 to d0 delay required by PCI spec.
 300  */
 301 static void pci_d3delay_fixup(struct pci_dev *dev)
 302 {
 303         /*
 304          * PCI fixups are effectively decided compile time. If we have a dual
 305          * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.
 306          */
 307         if (!pci_soc_mode)
 308                 return;
 309         /*
 310          * True PCI devices in Lincroft should allow type 1 access, the rest
 311          * are Langwell fake PCI devices.
 312          */
 313         if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
 314                 return;
 315         dev->d3_delay = 0;
 316 }
 317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
 318
 319 static void mid_power_off_one_device(struct pci_dev *dev)
 320 {
 321         u16 pmcsr;
 322
 323         /*
 324          * Update current state first, otherwise PCI core enforces PCI_D0 in
 325          * pci_set_power_state() for devices which status was PCI_UNKNOWN.
 326          */
 327         pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
 328         dev->current_state = (pci_power_t __force)(pmcsr & PCI_PM_CTRL_STATE_MASK);
 329
 330         pci_set_power_state(dev, PCI_D3hot);
 331 }
 332
 333 static void mid_power_off_devices(struct pci_dev *dev)
 334 {
 335         int id;
 336
 337         if (!pci_soc_mode)
 338                 return;
 339
 340         id = intel_mid_pwr_get_lss_id(dev);
 341         if (id < 0)
 342                 return;
 343
 344         /*
 345          * This sets only PMCSR bits. The actual power off will happen in
 346          * arch/x86/platform/intel-mid/pwr.c.
 347          */
 348         mid_power_off_one_device(dev);
 349 }
 350
 351 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, mid_power_off_devices);
 352
 353 /*
 354  * Langwell devices reside at fixed offsets, don't try to move them.
 355  */
 356 static void pci_fixed_bar_fixup(struct pci_dev *dev)
 357 {
 358         unsigned long offset;
 359         u32 size;
 360         int i;
 361
 362         if (!pci_soc_mode)
 363                 return;
 364
 365         /* Must have extended configuration space */
 366         if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
 367                 return;
 368
 369         /* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
 370         offset = fixed_bar_cap(dev->bus, dev->devfn);
 371         if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
 372             PCI_DEVFN(2, 2) == dev->devfn)
 373                 return;
 374
 375         for (i = 0; i < PCI_ROM_RESOURCE; i++) {
 376                 pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
 377                 dev->resource[i].end = dev->resource[i].start + size - 1;
 378                 dev->resource[i].flags |= IORESOURCE_PCI_FIXED;
 379         }
 380 }
 381 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);