2 * Support PCI/PCIe on PowerNV platforms
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
22 #include <linux/irq.h>
24 #include <linux/msi.h>
25 #include <linux/memblock.h>
26 #include <linux/iommu.h>
27 #include <linux/rculist.h>
28 #include <linux/sizes.h>
30 #include <asm/sections.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/machdep.h>
35 #include <asm/msi_bitmap.h>
36 #include <asm/ppc-pci.h>
38 #include <asm/iommu.h>
41 #include <asm/debug.h>
42 #include <asm/firmware.h>
43 #include <asm/pnv-pci.h>
44 #include <asm/mmzone.h>
46 #include <misc/cxl-base.h>
51 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
52 #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8)
54 #define POWERNV_IOMMU_DEFAULT_LEVELS 1
55 #define POWERNV_IOMMU_MAX_LEVELS 5
57 static void pnv_pci_ioda2_table_free_pages(struct iommu_table
*tbl
);
59 static void pe_level_printk(const struct pnv_ioda_pe
*pe
, const char *level
,
71 if (pe
->flags
& PNV_IODA_PE_DEV
)
72 strlcpy(pfix
, dev_name(&pe
->pdev
->dev
), sizeof(pfix
));
73 else if (pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
))
74 sprintf(pfix
, "%04x:%02x ",
75 pci_domain_nr(pe
->pbus
), pe
->pbus
->number
);
77 else if (pe
->flags
& PNV_IODA_PE_VF
)
78 sprintf(pfix
, "%04x:%02x:%2x.%d",
79 pci_domain_nr(pe
->parent_dev
->bus
),
80 (pe
->rid
& 0xff00) >> 8,
81 PCI_SLOT(pe
->rid
), PCI_FUNC(pe
->rid
));
82 #endif /* CONFIG_PCI_IOV*/
84 printk("%spci %s: [PE# %.3d] %pV",
85 level
, pfix
, pe
->pe_number
, &vaf
);
90 #define pe_err(pe, fmt, ...) \
91 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
92 #define pe_warn(pe, fmt, ...) \
93 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
94 #define pe_info(pe, fmt, ...) \
95 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
97 static bool pnv_iommu_bypass_disabled __read_mostly
;
99 static int __init
iommu_setup(char *str
)
105 if (!strncmp(str
, "nobypass", 8)) {
106 pnv_iommu_bypass_disabled
= true;
107 pr_info("PowerNV: IOMMU bypass window disabled.\n");
110 str
+= strcspn(str
, ",");
117 early_param("iommu", iommu_setup
);
120 * stdcix is only supposed to be used in hypervisor real mode as per
121 * the architecture spec
123 static inline void __raw_rm_writeq(u64 val
, volatile void __iomem
*paddr
)
125 __asm__
__volatile__("stdcix %0,0,%1"
126 : : "r" (val
), "r" (paddr
) : "memory");
129 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags
)
131 return ((flags
& (IORESOURCE_MEM_64
| IORESOURCE_PREFETCH
)) ==
132 (IORESOURCE_MEM_64
| IORESOURCE_PREFETCH
));
135 static void pnv_ioda_reserve_pe(struct pnv_phb
*phb
, int pe_no
)
137 if (!(pe_no
>= 0 && pe_no
< phb
->ioda
.total_pe
)) {
138 pr_warn("%s: Invalid PE %d on PHB#%x\n",
139 __func__
, pe_no
, phb
->hose
->global_number
);
143 if (test_and_set_bit(pe_no
, phb
->ioda
.pe_alloc
)) {
144 pr_warn("%s: PE %d was assigned on PHB#%x\n",
145 __func__
, pe_no
, phb
->hose
->global_number
);
149 phb
->ioda
.pe_array
[pe_no
].phb
= phb
;
150 phb
->ioda
.pe_array
[pe_no
].pe_number
= pe_no
;
153 static int pnv_ioda_alloc_pe(struct pnv_phb
*phb
)
158 pe
= find_next_zero_bit(phb
->ioda
.pe_alloc
,
159 phb
->ioda
.total_pe
, 0);
160 if (pe
>= phb
->ioda
.total_pe
)
161 return IODA_INVALID_PE
;
162 } while(test_and_set_bit(pe
, phb
->ioda
.pe_alloc
));
164 phb
->ioda
.pe_array
[pe
].phb
= phb
;
165 phb
->ioda
.pe_array
[pe
].pe_number
= pe
;
169 static void pnv_ioda_free_pe(struct pnv_phb
*phb
, int pe
)
171 WARN_ON(phb
->ioda
.pe_array
[pe
].pdev
);
173 memset(&phb
->ioda
.pe_array
[pe
], 0, sizeof(struct pnv_ioda_pe
));
174 clear_bit(pe
, phb
->ioda
.pe_alloc
);
177 /* The default M64 BAR is shared by all PEs */
178 static int pnv_ioda2_init_m64(struct pnv_phb
*phb
)
184 /* Configure the default M64 BAR */
185 rc
= opal_pci_set_phb_mem_window(phb
->opal_id
,
186 OPAL_M64_WINDOW_TYPE
,
187 phb
->ioda
.m64_bar_idx
,
191 if (rc
!= OPAL_SUCCESS
) {
192 desc
= "configuring";
196 /* Enable the default M64 BAR */
197 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
198 OPAL_M64_WINDOW_TYPE
,
199 phb
->ioda
.m64_bar_idx
,
200 OPAL_ENABLE_M64_SPLIT
);
201 if (rc
!= OPAL_SUCCESS
) {
206 /* Mark the M64 BAR assigned */
207 set_bit(phb
->ioda
.m64_bar_idx
, &phb
->ioda
.m64_bar_alloc
);
210 * Strip off the segment used by the reserved PE, which is
211 * expected to be 0 or last one of PE capabicity.
213 r
= &phb
->hose
->mem_resources
[1];
214 if (phb
->ioda
.reserved_pe
== 0)
215 r
->start
+= phb
->ioda
.m64_segsize
;
216 else if (phb
->ioda
.reserved_pe
== (phb
->ioda
.total_pe
- 1))
217 r
->end
-= phb
->ioda
.m64_segsize
;
219 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n",
220 phb
->ioda
.reserved_pe
);
225 pr_warn(" Failure %lld %s M64 BAR#%d\n",
226 rc
, desc
, phb
->ioda
.m64_bar_idx
);
227 opal_pci_phb_mmio_enable(phb
->opal_id
,
228 OPAL_M64_WINDOW_TYPE
,
229 phb
->ioda
.m64_bar_idx
,
234 static void pnv_ioda2_reserve_m64_pe(struct pnv_phb
*phb
)
236 resource_size_t sgsz
= phb
->ioda
.m64_segsize
;
237 struct pci_dev
*pdev
;
242 * Root bus always has full M64 range and root port has
243 * M64 range used in reality. So we're checking root port
244 * instead of root bus.
246 list_for_each_entry(pdev
, &phb
->hose
->bus
->devices
, bus_list
) {
247 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
248 r
= &pdev
->resource
[PCI_BRIDGE_RESOURCES
+ i
];
250 !pnv_pci_is_mem_pref_64(r
->flags
))
253 base
= (r
->start
- phb
->ioda
.m64_base
) / sgsz
;
254 for (step
= 0; step
< resource_size(r
) / sgsz
; step
++)
255 pnv_ioda_reserve_pe(phb
, base
+ step
);
260 static int pnv_ioda2_pick_m64_pe(struct pnv_phb
*phb
,
261 struct pci_bus
*bus
, int all
)
263 resource_size_t segsz
= phb
->ioda
.m64_segsize
;
264 struct pci_dev
*pdev
;
266 struct pnv_ioda_pe
*master_pe
, *pe
;
267 unsigned long size
, *pe_alloc
;
271 /* Root bus shouldn't use M64 */
272 if (pci_is_root_bus(bus
))
273 return IODA_INVALID_PE
;
275 /* We support only one M64 window on each bus */
277 pci_bus_for_each_resource(bus
, r
, i
) {
278 if (r
&& r
->parent
&&
279 pnv_pci_is_mem_pref_64(r
->flags
)) {
285 /* No M64 window found ? */
287 return IODA_INVALID_PE
;
289 /* Allocate bitmap */
290 size
= _ALIGN_UP(phb
->ioda
.total_pe
/ 8, sizeof(unsigned long));
291 pe_alloc
= kzalloc(size
, GFP_KERNEL
);
293 pr_warn("%s: Out of memory !\n",
295 return IODA_INVALID_PE
;
299 * Figure out reserved PE numbers by the PE
302 start
= (r
->start
- phb
->ioda
.m64_base
) / segsz
;
303 for (i
= 0; i
< resource_size(r
) / segsz
; i
++)
304 set_bit(start
+ i
, pe_alloc
);
310 * If the PE doesn't cover all subordinate buses,
311 * we need subtract from reserved PEs for children.
313 list_for_each_entry(pdev
, &bus
->devices
, bus_list
) {
314 if (!pdev
->subordinate
)
317 pci_bus_for_each_resource(pdev
->subordinate
, r
, i
) {
318 if (!r
|| !r
->parent
||
319 !pnv_pci_is_mem_pref_64(r
->flags
))
322 start
= (r
->start
- phb
->ioda
.m64_base
) / segsz
;
323 for (j
= 0; j
< resource_size(r
) / segsz
; j
++)
324 clear_bit(start
+ j
, pe_alloc
);
329 * the current bus might not own M64 window and that's all
330 * contributed by its child buses. For the case, we needn't
331 * pick M64 dependent PE#.
333 if (bitmap_empty(pe_alloc
, phb
->ioda
.total_pe
)) {
335 return IODA_INVALID_PE
;
339 * Figure out the master PE and put all slave PEs to master
340 * PE's list to form compound PE.
345 while ((i
= find_next_bit(pe_alloc
, phb
->ioda
.total_pe
, i
+ 1)) <
346 phb
->ioda
.total_pe
) {
347 pe
= &phb
->ioda
.pe_array
[i
];
350 pe
->flags
|= PNV_IODA_PE_MASTER
;
351 INIT_LIST_HEAD(&pe
->slaves
);
354 pe
->flags
|= PNV_IODA_PE_SLAVE
;
355 pe
->master
= master_pe
;
356 list_add_tail(&pe
->list
, &master_pe
->slaves
);
361 return master_pe
->pe_number
;
364 static void __init
pnv_ioda_parse_m64_window(struct pnv_phb
*phb
)
366 struct pci_controller
*hose
= phb
->hose
;
367 struct device_node
*dn
= hose
->dn
;
368 struct resource
*res
;
372 /* FIXME: Support M64 for P7IOC */
373 if (phb
->type
!= PNV_PHB_IODA2
) {
374 pr_info(" Not support M64 window\n");
378 if (!firmware_has_feature(FW_FEATURE_OPALv3
)) {
379 pr_info(" Firmware too old to support M64 window\n");
383 r
= of_get_property(dn
, "ibm,opal-m64-window", NULL
);
385 pr_info(" No <ibm,opal-m64-window> on %s\n",
390 res
= &hose
->mem_resources
[1];
391 res
->start
= of_translate_address(dn
, r
+ 2);
392 res
->end
= res
->start
+ of_read_number(r
+ 4, 2) - 1;
393 res
->flags
= (IORESOURCE_MEM
| IORESOURCE_MEM_64
| IORESOURCE_PREFETCH
);
394 pci_addr
= of_read_number(r
, 2);
395 hose
->mem_offset
[1] = res
->start
- pci_addr
;
397 phb
->ioda
.m64_size
= resource_size(res
);
398 phb
->ioda
.m64_segsize
= phb
->ioda
.m64_size
/ phb
->ioda
.total_pe
;
399 phb
->ioda
.m64_base
= pci_addr
;
401 pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
402 res
->start
, res
->end
, pci_addr
);
404 /* Use last M64 BAR to cover M64 window */
405 phb
->ioda
.m64_bar_idx
= 15;
406 phb
->init_m64
= pnv_ioda2_init_m64
;
407 phb
->reserve_m64_pe
= pnv_ioda2_reserve_m64_pe
;
408 phb
->pick_m64_pe
= pnv_ioda2_pick_m64_pe
;
411 static void pnv_ioda_freeze_pe(struct pnv_phb
*phb
, int pe_no
)
413 struct pnv_ioda_pe
*pe
= &phb
->ioda
.pe_array
[pe_no
];
414 struct pnv_ioda_pe
*slave
;
417 /* Fetch master PE */
418 if (pe
->flags
& PNV_IODA_PE_SLAVE
) {
420 if (WARN_ON(!pe
|| !(pe
->flags
& PNV_IODA_PE_MASTER
)))
423 pe_no
= pe
->pe_number
;
426 /* Freeze master PE */
427 rc
= opal_pci_eeh_freeze_set(phb
->opal_id
,
429 OPAL_EEH_ACTION_SET_FREEZE_ALL
);
430 if (rc
!= OPAL_SUCCESS
) {
431 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
432 __func__
, rc
, phb
->hose
->global_number
, pe_no
);
436 /* Freeze slave PEs */
437 if (!(pe
->flags
& PNV_IODA_PE_MASTER
))
440 list_for_each_entry(slave
, &pe
->slaves
, list
) {
441 rc
= opal_pci_eeh_freeze_set(phb
->opal_id
,
443 OPAL_EEH_ACTION_SET_FREEZE_ALL
);
444 if (rc
!= OPAL_SUCCESS
)
445 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
446 __func__
, rc
, phb
->hose
->global_number
,
451 static int pnv_ioda_unfreeze_pe(struct pnv_phb
*phb
, int pe_no
, int opt
)
453 struct pnv_ioda_pe
*pe
, *slave
;
457 pe
= &phb
->ioda
.pe_array
[pe_no
];
458 if (pe
->flags
& PNV_IODA_PE_SLAVE
) {
460 WARN_ON(!pe
|| !(pe
->flags
& PNV_IODA_PE_MASTER
));
461 pe_no
= pe
->pe_number
;
464 /* Clear frozen state for master PE */
465 rc
= opal_pci_eeh_freeze_clear(phb
->opal_id
, pe_no
, opt
);
466 if (rc
!= OPAL_SUCCESS
) {
467 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
468 __func__
, rc
, opt
, phb
->hose
->global_number
, pe_no
);
472 if (!(pe
->flags
& PNV_IODA_PE_MASTER
))
475 /* Clear frozen state for slave PEs */
476 list_for_each_entry(slave
, &pe
->slaves
, list
) {
477 rc
= opal_pci_eeh_freeze_clear(phb
->opal_id
,
480 if (rc
!= OPAL_SUCCESS
) {
481 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
482 __func__
, rc
, opt
, phb
->hose
->global_number
,
491 static int pnv_ioda_get_pe_state(struct pnv_phb
*phb
, int pe_no
)
493 struct pnv_ioda_pe
*slave
, *pe
;
498 /* Sanity check on PE number */
499 if (pe_no
< 0 || pe_no
>= phb
->ioda
.total_pe
)
500 return OPAL_EEH_STOPPED_PERM_UNAVAIL
;
503 * Fetch the master PE and the PE instance might be
504 * not initialized yet.
506 pe
= &phb
->ioda
.pe_array
[pe_no
];
507 if (pe
->flags
& PNV_IODA_PE_SLAVE
) {
509 WARN_ON(!pe
|| !(pe
->flags
& PNV_IODA_PE_MASTER
));
510 pe_no
= pe
->pe_number
;
513 /* Check the master PE */
514 rc
= opal_pci_eeh_freeze_status(phb
->opal_id
, pe_no
,
515 &state
, &pcierr
, NULL
);
516 if (rc
!= OPAL_SUCCESS
) {
517 pr_warn("%s: Failure %lld getting "
518 "PHB#%x-PE#%x state\n",
520 phb
->hose
->global_number
, pe_no
);
521 return OPAL_EEH_STOPPED_TEMP_UNAVAIL
;
524 /* Check the slave PE */
525 if (!(pe
->flags
& PNV_IODA_PE_MASTER
))
528 list_for_each_entry(slave
, &pe
->slaves
, list
) {
529 rc
= opal_pci_eeh_freeze_status(phb
->opal_id
,
534 if (rc
!= OPAL_SUCCESS
) {
535 pr_warn("%s: Failure %lld getting "
536 "PHB#%x-PE#%x state\n",
538 phb
->hose
->global_number
, slave
->pe_number
);
539 return OPAL_EEH_STOPPED_TEMP_UNAVAIL
;
543 * Override the result based on the ascending
553 /* Currently those 2 are only used when MSIs are enabled, this will change
554 * but in the meantime, we need to protect them to avoid warnings
556 #ifdef CONFIG_PCI_MSI
557 static struct pnv_ioda_pe
*pnv_ioda_get_pe(struct pci_dev
*dev
)
559 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
560 struct pnv_phb
*phb
= hose
->private_data
;
561 struct pci_dn
*pdn
= pci_get_pdn(dev
);
565 if (pdn
->pe_number
== IODA_INVALID_PE
)
567 return &phb
->ioda
.pe_array
[pdn
->pe_number
];
569 #endif /* CONFIG_PCI_MSI */
571 static int pnv_ioda_set_one_peltv(struct pnv_phb
*phb
,
572 struct pnv_ioda_pe
*parent
,
573 struct pnv_ioda_pe
*child
,
576 const char *desc
= is_add
? "adding" : "removing";
577 uint8_t op
= is_add
? OPAL_ADD_PE_TO_DOMAIN
:
578 OPAL_REMOVE_PE_FROM_DOMAIN
;
579 struct pnv_ioda_pe
*slave
;
582 /* Parent PE affects child PE */
583 rc
= opal_pci_set_peltv(phb
->opal_id
, parent
->pe_number
,
584 child
->pe_number
, op
);
585 if (rc
!= OPAL_SUCCESS
) {
586 pe_warn(child
, "OPAL error %ld %s to parent PELTV\n",
591 if (!(child
->flags
& PNV_IODA_PE_MASTER
))
594 /* Compound case: parent PE affects slave PEs */
595 list_for_each_entry(slave
, &child
->slaves
, list
) {
596 rc
= opal_pci_set_peltv(phb
->opal_id
, parent
->pe_number
,
597 slave
->pe_number
, op
);
598 if (rc
!= OPAL_SUCCESS
) {
599 pe_warn(slave
, "OPAL error %ld %s to parent PELTV\n",
608 static int pnv_ioda_set_peltv(struct pnv_phb
*phb
,
609 struct pnv_ioda_pe
*pe
,
612 struct pnv_ioda_pe
*slave
;
613 struct pci_dev
*pdev
= NULL
;
617 * Clear PE frozen state. If it's master PE, we need
618 * clear slave PE frozen state as well.
621 opal_pci_eeh_freeze_clear(phb
->opal_id
, pe
->pe_number
,
622 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
623 if (pe
->flags
& PNV_IODA_PE_MASTER
) {
624 list_for_each_entry(slave
, &pe
->slaves
, list
)
625 opal_pci_eeh_freeze_clear(phb
->opal_id
,
627 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
632 * Associate PE in PELT. We need add the PE into the
633 * corresponding PELT-V as well. Otherwise, the error
634 * originated from the PE might contribute to other
637 ret
= pnv_ioda_set_one_peltv(phb
, pe
, pe
, is_add
);
641 /* For compound PEs, any one affects all of them */
642 if (pe
->flags
& PNV_IODA_PE_MASTER
) {
643 list_for_each_entry(slave
, &pe
->slaves
, list
) {
644 ret
= pnv_ioda_set_one_peltv(phb
, slave
, pe
, is_add
);
650 if (pe
->flags
& (PNV_IODA_PE_BUS_ALL
| PNV_IODA_PE_BUS
))
651 pdev
= pe
->pbus
->self
;
652 else if (pe
->flags
& PNV_IODA_PE_DEV
)
653 pdev
= pe
->pdev
->bus
->self
;
654 #ifdef CONFIG_PCI_IOV
655 else if (pe
->flags
& PNV_IODA_PE_VF
)
656 pdev
= pe
->parent_dev
->bus
->self
;
657 #endif /* CONFIG_PCI_IOV */
659 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
660 struct pnv_ioda_pe
*parent
;
662 if (pdn
&& pdn
->pe_number
!= IODA_INVALID_PE
) {
663 parent
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
664 ret
= pnv_ioda_set_one_peltv(phb
, parent
, pe
, is_add
);
669 pdev
= pdev
->bus
->self
;
675 #ifdef CONFIG_PCI_IOV
676 static int pnv_ioda_deconfigure_pe(struct pnv_phb
*phb
, struct pnv_ioda_pe
*pe
)
678 struct pci_dev
*parent
;
679 uint8_t bcomp
, dcomp
, fcomp
;
683 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
687 dcomp
= OPAL_IGNORE_RID_DEVICE_NUMBER
;
688 fcomp
= OPAL_IGNORE_RID_FUNCTION_NUMBER
;
689 parent
= pe
->pbus
->self
;
690 if (pe
->flags
& PNV_IODA_PE_BUS_ALL
)
691 count
= pe
->pbus
->busn_res
.end
- pe
->pbus
->busn_res
.start
+ 1;
696 case 1: bcomp
= OpalPciBusAll
; break;
697 case 2: bcomp
= OpalPciBus7Bits
; break;
698 case 4: bcomp
= OpalPciBus6Bits
; break;
699 case 8: bcomp
= OpalPciBus5Bits
; break;
700 case 16: bcomp
= OpalPciBus4Bits
; break;
701 case 32: bcomp
= OpalPciBus3Bits
; break;
703 dev_err(&pe
->pbus
->dev
, "Number of subordinate buses %d unsupported\n",
705 /* Do an exact match only */
706 bcomp
= OpalPciBusAll
;
708 rid_end
= pe
->rid
+ (count
<< 8);
710 if (pe
->flags
& PNV_IODA_PE_VF
)
711 parent
= pe
->parent_dev
;
713 parent
= pe
->pdev
->bus
->self
;
714 bcomp
= OpalPciBusAll
;
715 dcomp
= OPAL_COMPARE_RID_DEVICE_NUMBER
;
716 fcomp
= OPAL_COMPARE_RID_FUNCTION_NUMBER
;
717 rid_end
= pe
->rid
+ 1;
720 /* Clear the reverse map */
721 for (rid
= pe
->rid
; rid
< rid_end
; rid
++)
722 phb
->ioda
.pe_rmap
[rid
] = 0;
724 /* Release from all parents PELT-V */
726 struct pci_dn
*pdn
= pci_get_pdn(parent
);
727 if (pdn
&& pdn
->pe_number
!= IODA_INVALID_PE
) {
728 rc
= opal_pci_set_peltv(phb
->opal_id
, pdn
->pe_number
,
729 pe
->pe_number
, OPAL_REMOVE_PE_FROM_DOMAIN
);
730 /* XXX What to do in case of error ? */
732 parent
= parent
->bus
->self
;
735 opal_pci_eeh_freeze_set(phb
->opal_id
, pe
->pe_number
,
736 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
738 /* Disassociate PE in PELT */
739 rc
= opal_pci_set_peltv(phb
->opal_id
, pe
->pe_number
,
740 pe
->pe_number
, OPAL_REMOVE_PE_FROM_DOMAIN
);
742 pe_warn(pe
, "OPAL error %ld remove self from PELTV\n", rc
);
743 rc
= opal_pci_set_pe(phb
->opal_id
, pe
->pe_number
, pe
->rid
,
744 bcomp
, dcomp
, fcomp
, OPAL_UNMAP_PE
);
746 pe_err(pe
, "OPAL error %ld trying to setup PELT table\n", rc
);
750 pe
->parent_dev
= NULL
;
754 #endif /* CONFIG_PCI_IOV */
756 static int pnv_ioda_configure_pe(struct pnv_phb
*phb
, struct pnv_ioda_pe
*pe
)
758 struct pci_dev
*parent
;
759 uint8_t bcomp
, dcomp
, fcomp
;
760 long rc
, rid_end
, rid
;
762 /* Bus validation ? */
766 dcomp
= OPAL_IGNORE_RID_DEVICE_NUMBER
;
767 fcomp
= OPAL_IGNORE_RID_FUNCTION_NUMBER
;
768 parent
= pe
->pbus
->self
;
769 if (pe
->flags
& PNV_IODA_PE_BUS_ALL
)
770 count
= pe
->pbus
->busn_res
.end
- pe
->pbus
->busn_res
.start
+ 1;
775 case 1: bcomp
= OpalPciBusAll
; break;
776 case 2: bcomp
= OpalPciBus7Bits
; break;
777 case 4: bcomp
= OpalPciBus6Bits
; break;
778 case 8: bcomp
= OpalPciBus5Bits
; break;
779 case 16: bcomp
= OpalPciBus4Bits
; break;
780 case 32: bcomp
= OpalPciBus3Bits
; break;
782 dev_err(&pe
->pbus
->dev
, "Number of subordinate buses %d unsupported\n",
784 /* Do an exact match only */
785 bcomp
= OpalPciBusAll
;
787 rid_end
= pe
->rid
+ (count
<< 8);
789 #ifdef CONFIG_PCI_IOV
790 if (pe
->flags
& PNV_IODA_PE_VF
)
791 parent
= pe
->parent_dev
;
793 #endif /* CONFIG_PCI_IOV */
794 parent
= pe
->pdev
->bus
->self
;
795 bcomp
= OpalPciBusAll
;
796 dcomp
= OPAL_COMPARE_RID_DEVICE_NUMBER
;
797 fcomp
= OPAL_COMPARE_RID_FUNCTION_NUMBER
;
798 rid_end
= pe
->rid
+ 1;
802 * Associate PE in PELT. We need add the PE into the
803 * corresponding PELT-V as well. Otherwise, the error
804 * originated from the PE might contribute to other
807 rc
= opal_pci_set_pe(phb
->opal_id
, pe
->pe_number
, pe
->rid
,
808 bcomp
, dcomp
, fcomp
, OPAL_MAP_PE
);
810 pe_err(pe
, "OPAL error %ld trying to setup PELT table\n", rc
);
814 /* Configure PELTV */
815 pnv_ioda_set_peltv(phb
, pe
, true);
817 /* Setup reverse map */
818 for (rid
= pe
->rid
; rid
< rid_end
; rid
++)
819 phb
->ioda
.pe_rmap
[rid
] = pe
->pe_number
;
821 /* Setup one MVTs on IODA1 */
822 if (phb
->type
!= PNV_PHB_IODA1
) {
827 pe
->mve_number
= pe
->pe_number
;
828 rc
= opal_pci_set_mve(phb
->opal_id
, pe
->mve_number
, pe
->pe_number
);
829 if (rc
!= OPAL_SUCCESS
) {
830 pe_err(pe
, "OPAL error %ld setting up MVE %d\n",
834 rc
= opal_pci_set_mve_enable(phb
->opal_id
,
835 pe
->mve_number
, OPAL_ENABLE_MVE
);
837 pe_err(pe
, "OPAL error %ld enabling MVE %d\n",
847 static void pnv_ioda_link_pe_by_weight(struct pnv_phb
*phb
,
848 struct pnv_ioda_pe
*pe
)
850 struct pnv_ioda_pe
*lpe
;
852 list_for_each_entry(lpe
, &phb
->ioda
.pe_dma_list
, dma_link
) {
853 if (lpe
->dma_weight
< pe
->dma_weight
) {
854 list_add_tail(&pe
->dma_link
, &lpe
->dma_link
);
858 list_add_tail(&pe
->dma_link
, &phb
->ioda
.pe_dma_list
);
861 static unsigned int pnv_ioda_dma_weight(struct pci_dev
*dev
)
863 /* This is quite simplistic. The "base" weight of a device
864 * is 10. 0 means no DMA is to be accounted for it.
867 /* If it's a bridge, no DMA */
868 if (dev
->hdr_type
!= PCI_HEADER_TYPE_NORMAL
)
871 /* Reduce the weight of slow USB controllers */
872 if (dev
->class == PCI_CLASS_SERIAL_USB_UHCI
||
873 dev
->class == PCI_CLASS_SERIAL_USB_OHCI
||
874 dev
->class == PCI_CLASS_SERIAL_USB_EHCI
)
877 /* Increase the weight of RAID (includes Obsidian) */
878 if ((dev
->class >> 8) == PCI_CLASS_STORAGE_RAID
)
885 #ifdef CONFIG_PCI_IOV
886 static int pnv_pci_vf_resource_shift(struct pci_dev
*dev
, int offset
)
888 struct pci_dn
*pdn
= pci_get_pdn(dev
);
890 struct resource
*res
, res2
;
891 resource_size_t size
;
898 * "offset" is in VFs. The M64 windows are sized so that when they
899 * are segmented, each segment is the same size as the IOV BAR.
900 * Each segment is in a separate PE, and the high order bits of the
901 * address are the PE number. Therefore, each VF's BAR is in a
902 * separate PE, and changing the IOV BAR start address changes the
903 * range of PEs the VFs are in.
905 num_vfs
= pdn
->num_vfs
;
906 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
907 res
= &dev
->resource
[i
+ PCI_IOV_RESOURCES
];
908 if (!res
->flags
|| !res
->parent
)
911 if (!pnv_pci_is_mem_pref_64(res
->flags
))
915 * The actual IOV BAR range is determined by the start address
916 * and the actual size for num_vfs VFs BAR. This check is to
917 * make sure that after shifting, the range will not overlap
918 * with another device.
920 size
= pci_iov_resource_size(dev
, i
+ PCI_IOV_RESOURCES
);
921 res2
.flags
= res
->flags
;
922 res2
.start
= res
->start
+ (size
* offset
);
923 res2
.end
= res2
.start
+ (size
* num_vfs
) - 1;
925 if (res2
.end
> res
->end
) {
926 dev_err(&dev
->dev
, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
927 i
, &res2
, res
, num_vfs
, offset
);
933 * After doing so, there would be a "hole" in the /proc/iomem when
934 * offset is a positive value. It looks like the device return some
935 * mmio back to the system, which actually no one could use it.
937 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
938 res
= &dev
->resource
[i
+ PCI_IOV_RESOURCES
];
939 if (!res
->flags
|| !res
->parent
)
942 if (!pnv_pci_is_mem_pref_64(res
->flags
))
945 size
= pci_iov_resource_size(dev
, i
+ PCI_IOV_RESOURCES
);
947 res
->start
+= size
* offset
;
949 dev_info(&dev
->dev
, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n",
950 i
, &res2
, res
, num_vfs
, offset
);
951 pci_update_resource(dev
, i
+ PCI_IOV_RESOURCES
);
955 #endif /* CONFIG_PCI_IOV */
958 static struct pnv_ioda_pe
*pnv_ioda_setup_dev_PE(struct pci_dev
*dev
)
960 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
961 struct pnv_phb
*phb
= hose
->private_data
;
962 struct pci_dn
*pdn
= pci_get_pdn(dev
);
963 struct pnv_ioda_pe
*pe
;
967 pr_err("%s: Device tree node not associated properly\n",
971 if (pdn
->pe_number
!= IODA_INVALID_PE
)
974 /* PE#0 has been pre-set */
975 if (dev
->bus
->number
== 0)
978 pe_num
= pnv_ioda_alloc_pe(phb
);
979 if (pe_num
== IODA_INVALID_PE
) {
980 pr_warning("%s: Not enough PE# available, disabling device\n",
985 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
986 * pointer in the PE data structure, both should be destroyed at the
987 * same time. However, this needs to be looked at more closely again
988 * once we actually start removing things (Hotplug, SR-IOV, ...)
990 * At some point we want to remove the PDN completely anyways
992 pe
= &phb
->ioda
.pe_array
[pe_num
];
995 pdn
->pe_number
= pe_num
;
1000 pe
->rid
= dev
->bus
->number
<< 8 | pdn
->devfn
;
1002 pe_info(pe
, "Associated device to PE\n");
1004 if (pnv_ioda_configure_pe(phb
, pe
)) {
1005 /* XXX What do we do here ? */
1007 pnv_ioda_free_pe(phb
, pe_num
);
1008 pdn
->pe_number
= IODA_INVALID_PE
;
1014 /* Assign a DMA weight to the device */
1015 pe
->dma_weight
= pnv_ioda_dma_weight(dev
);
1016 if (pe
->dma_weight
!= 0) {
1017 phb
->ioda
.dma_weight
+= pe
->dma_weight
;
1018 phb
->ioda
.dma_pe_count
++;
1022 pnv_ioda_link_pe_by_weight(phb
, pe
);
1026 #endif /* Useful for SRIOV case */
1028 static void pnv_ioda_setup_same_PE(struct pci_bus
*bus
, struct pnv_ioda_pe
*pe
)
1030 struct pci_dev
*dev
;
1032 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1033 struct pci_dn
*pdn
= pci_get_pdn(dev
);
1036 pr_warn("%s: No device node associated with device !\n",
1040 pdn
->pe_number
= pe
->pe_number
;
1041 pe
->dma_weight
+= pnv_ioda_dma_weight(dev
);
1042 if ((pe
->flags
& PNV_IODA_PE_BUS_ALL
) && dev
->subordinate
)
1043 pnv_ioda_setup_same_PE(dev
->subordinate
, pe
);
1048 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1049 * single PCI bus. Another one that contains the primary PCI bus and its
1050 * subordinate PCI devices and buses. The second type of PE is normally
1051 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1053 static void pnv_ioda_setup_bus_PE(struct pci_bus
*bus
, int all
)
1055 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1056 struct pnv_phb
*phb
= hose
->private_data
;
1057 struct pnv_ioda_pe
*pe
;
1058 int pe_num
= IODA_INVALID_PE
;
1060 /* Check if PE is determined by M64 */
1061 if (phb
->pick_m64_pe
)
1062 pe_num
= phb
->pick_m64_pe(phb
, bus
, all
);
1064 /* The PE number isn't pinned by M64 */
1065 if (pe_num
== IODA_INVALID_PE
)
1066 pe_num
= pnv_ioda_alloc_pe(phb
);
1068 if (pe_num
== IODA_INVALID_PE
) {
1069 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1070 __func__
, pci_domain_nr(bus
), bus
->number
);
1074 pe
= &phb
->ioda
.pe_array
[pe_num
];
1075 pe
->flags
|= (all
? PNV_IODA_PE_BUS_ALL
: PNV_IODA_PE_BUS
);
1079 pe
->mve_number
= -1;
1080 pe
->rid
= bus
->busn_res
.start
<< 8;
1084 pe_info(pe
, "Secondary bus %d..%d associated with PE#%d\n",
1085 bus
->busn_res
.start
, bus
->busn_res
.end
, pe_num
);
1087 pe_info(pe
, "Secondary bus %d associated with PE#%d\n",
1088 bus
->busn_res
.start
, pe_num
);
1090 if (pnv_ioda_configure_pe(phb
, pe
)) {
1091 /* XXX What do we do here ? */
1093 pnv_ioda_free_pe(phb
, pe_num
);
1098 /* Associate it with all child devices */
1099 pnv_ioda_setup_same_PE(bus
, pe
);
1101 /* Put PE to the list */
1102 list_add_tail(&pe
->list
, &phb
->ioda
.pe_list
);
1104 /* Account for one DMA PE if at least one DMA capable device exist
1107 if (pe
->dma_weight
!= 0) {
1108 phb
->ioda
.dma_weight
+= pe
->dma_weight
;
1109 phb
->ioda
.dma_pe_count
++;
1113 pnv_ioda_link_pe_by_weight(phb
, pe
);
1116 static void pnv_ioda_setup_PEs(struct pci_bus
*bus
)
1118 struct pci_dev
*dev
;
1120 pnv_ioda_setup_bus_PE(bus
, 0);
1122 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1123 if (dev
->subordinate
) {
1124 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_PCI_BRIDGE
)
1125 pnv_ioda_setup_bus_PE(dev
->subordinate
, 1);
1127 pnv_ioda_setup_PEs(dev
->subordinate
);
1133 * Configure PEs so that the downstream PCI buses and devices
1134 * could have their associated PE#. Unfortunately, we didn't
1135 * figure out the way to identify the PLX bridge yet. So we
1136 * simply put the PCI bus and the subordinate behind the root
1137 * port to PE# here. The game rule here is expected to be changed
1138 * as soon as we can detected PLX bridge correctly.
1140 static void pnv_pci_ioda_setup_PEs(void)
1142 struct pci_controller
*hose
, *tmp
;
1143 struct pnv_phb
*phb
;
1145 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1146 phb
= hose
->private_data
;
1148 /* M64 layout might affect PE allocation */
1149 if (phb
->reserve_m64_pe
)
1150 phb
->reserve_m64_pe(phb
);
1152 pnv_ioda_setup_PEs(hose
->bus
);
1156 #ifdef CONFIG_PCI_IOV
1157 static int pnv_pci_vf_release_m64(struct pci_dev
*pdev
)
1159 struct pci_bus
*bus
;
1160 struct pci_controller
*hose
;
1161 struct pnv_phb
*phb
;
1166 hose
= pci_bus_to_host(bus
);
1167 phb
= hose
->private_data
;
1168 pdn
= pci_get_pdn(pdev
);
1170 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++)
1171 for (j
= 0; j
< M64_PER_IOV
; j
++) {
1172 if (pdn
->m64_wins
[i
][j
] == IODA_INVALID_M64
)
1174 opal_pci_phb_mmio_enable(phb
->opal_id
,
1175 OPAL_M64_WINDOW_TYPE
, pdn
->m64_wins
[i
][j
], 0);
1176 clear_bit(pdn
->m64_wins
[i
][j
], &phb
->ioda
.m64_bar_alloc
);
1177 pdn
->m64_wins
[i
][j
] = IODA_INVALID_M64
;
1183 static int pnv_pci_vf_assign_m64(struct pci_dev
*pdev
, u16 num_vfs
)
1185 struct pci_bus
*bus
;
1186 struct pci_controller
*hose
;
1187 struct pnv_phb
*phb
;
1190 struct resource
*res
;
1194 resource_size_t size
, start
;
1200 hose
= pci_bus_to_host(bus
);
1201 phb
= hose
->private_data
;
1202 pdn
= pci_get_pdn(pdev
);
1203 total_vfs
= pci_sriov_get_totalvfs(pdev
);
1205 /* Initialize the m64_wins to IODA_INVALID_M64 */
1206 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++)
1207 for (j
= 0; j
< M64_PER_IOV
; j
++)
1208 pdn
->m64_wins
[i
][j
] = IODA_INVALID_M64
;
1210 if (pdn
->m64_per_iov
== M64_PER_IOV
) {
1211 vf_groups
= (num_vfs
<= M64_PER_IOV
) ? num_vfs
: M64_PER_IOV
;
1212 vf_per_group
= (num_vfs
<= M64_PER_IOV
)? 1:
1213 roundup_pow_of_two(num_vfs
) / pdn
->m64_per_iov
;
1219 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
1220 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
1221 if (!res
->flags
|| !res
->parent
)
1224 if (!pnv_pci_is_mem_pref_64(res
->flags
))
1227 for (j
= 0; j
< vf_groups
; j
++) {
1229 win
= find_next_zero_bit(&phb
->ioda
.m64_bar_alloc
,
1230 phb
->ioda
.m64_bar_idx
+ 1, 0);
1232 if (win
>= phb
->ioda
.m64_bar_idx
+ 1)
1234 } while (test_and_set_bit(win
, &phb
->ioda
.m64_bar_alloc
));
1236 pdn
->m64_wins
[i
][j
] = win
;
1238 if (pdn
->m64_per_iov
== M64_PER_IOV
) {
1239 size
= pci_iov_resource_size(pdev
,
1240 PCI_IOV_RESOURCES
+ i
);
1241 size
= size
* vf_per_group
;
1242 start
= res
->start
+ size
* j
;
1244 size
= resource_size(res
);
1248 /* Map the M64 here */
1249 if (pdn
->m64_per_iov
== M64_PER_IOV
) {
1250 pe_num
= pdn
->offset
+ j
;
1251 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
1252 pe_num
, OPAL_M64_WINDOW_TYPE
,
1253 pdn
->m64_wins
[i
][j
], 0);
1256 rc
= opal_pci_set_phb_mem_window(phb
->opal_id
,
1257 OPAL_M64_WINDOW_TYPE
,
1258 pdn
->m64_wins
[i
][j
],
1264 if (rc
!= OPAL_SUCCESS
) {
1265 dev_err(&pdev
->dev
, "Failed to map M64 window #%d: %lld\n",
1270 if (pdn
->m64_per_iov
== M64_PER_IOV
)
1271 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
1272 OPAL_M64_WINDOW_TYPE
, pdn
->m64_wins
[i
][j
], 2);
1274 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
1275 OPAL_M64_WINDOW_TYPE
, pdn
->m64_wins
[i
][j
], 1);
1277 if (rc
!= OPAL_SUCCESS
) {
1278 dev_err(&pdev
->dev
, "Failed to enable M64 window #%d: %llx\n",
1287 pnv_pci_vf_release_m64(pdev
);
1291 static long pnv_pci_ioda2_unset_window(struct iommu_table_group
*table_group
,
1293 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe
*pe
, bool enable
);
1295 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev
*dev
, struct pnv_ioda_pe
*pe
)
1297 struct iommu_table
*tbl
;
1300 tbl
= pe
->table_group
.tables
[0];
1301 rc
= pnv_pci_ioda2_unset_window(&pe
->table_group
, 0);
1303 pe_warn(pe
, "OPAL error %ld release DMA window\n", rc
);
1305 pnv_pci_ioda2_set_bypass(pe
, false);
1306 if (pe
->table_group
.group
) {
1307 iommu_group_put(pe
->table_group
.group
);
1308 BUG_ON(pe
->table_group
.group
);
1310 pnv_pci_ioda2_table_free_pages(tbl
);
1311 iommu_free_table(tbl
, of_node_full_name(dev
->dev
.of_node
));
1314 static void pnv_ioda_release_vf_PE(struct pci_dev
*pdev
, u16 num_vfs
)
1316 struct pci_bus
*bus
;
1317 struct pci_controller
*hose
;
1318 struct pnv_phb
*phb
;
1319 struct pnv_ioda_pe
*pe
, *pe_n
;
1325 hose
= pci_bus_to_host(bus
);
1326 phb
= hose
->private_data
;
1327 pdn
= pci_get_pdn(pdev
);
1329 if (!pdev
->is_physfn
)
1332 if (pdn
->m64_per_iov
== M64_PER_IOV
&& num_vfs
> M64_PER_IOV
) {
1337 vf_per_group
= roundup_pow_of_two(num_vfs
) / pdn
->m64_per_iov
;
1339 for (vf_group
= 0; vf_group
< M64_PER_IOV
; vf_group
++)
1340 for (vf_index
= vf_group
* vf_per_group
;
1341 vf_index
< (vf_group
+ 1) * vf_per_group
&&
1344 for (vf_index1
= vf_group
* vf_per_group
;
1345 vf_index1
< (vf_group
+ 1) * vf_per_group
&&
1346 vf_index1
< num_vfs
;
1349 rc
= opal_pci_set_peltv(phb
->opal_id
,
1350 pdn
->offset
+ vf_index
,
1351 pdn
->offset
+ vf_index1
,
1352 OPAL_REMOVE_PE_FROM_DOMAIN
);
1355 dev_warn(&pdev
->dev
, "%s: Failed to unlink same group PE#%d(%lld)\n",
1357 pdn
->offset
+ vf_index1
, rc
);
1361 list_for_each_entry_safe(pe
, pe_n
, &phb
->ioda
.pe_list
, list
) {
1362 if (pe
->parent_dev
!= pdev
)
1365 pnv_pci_ioda2_release_dma_pe(pdev
, pe
);
1367 /* Remove from list */
1368 mutex_lock(&phb
->ioda
.pe_list_mutex
);
1369 list_del(&pe
->list
);
1370 mutex_unlock(&phb
->ioda
.pe_list_mutex
);
1372 pnv_ioda_deconfigure_pe(phb
, pe
);
1374 pnv_ioda_free_pe(phb
, pe
->pe_number
);
1378 void pnv_pci_sriov_disable(struct pci_dev
*pdev
)
1380 struct pci_bus
*bus
;
1381 struct pci_controller
*hose
;
1382 struct pnv_phb
*phb
;
1384 struct pci_sriov
*iov
;
1388 hose
= pci_bus_to_host(bus
);
1389 phb
= hose
->private_data
;
1390 pdn
= pci_get_pdn(pdev
);
1392 num_vfs
= pdn
->num_vfs
;
1394 /* Release VF PEs */
1395 pnv_ioda_release_vf_PE(pdev
, num_vfs
);
1397 if (phb
->type
== PNV_PHB_IODA2
) {
1398 if (pdn
->m64_per_iov
== 1)
1399 pnv_pci_vf_resource_shift(pdev
, -pdn
->offset
);
1401 /* Release M64 windows */
1402 pnv_pci_vf_release_m64(pdev
);
1404 /* Release PE numbers */
1405 bitmap_clear(phb
->ioda
.pe_alloc
, pdn
->offset
, num_vfs
);
1410 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb
*phb
,
1411 struct pnv_ioda_pe
*pe
);
1412 static void pnv_ioda_setup_vf_PE(struct pci_dev
*pdev
, u16 num_vfs
)
1414 struct pci_bus
*bus
;
1415 struct pci_controller
*hose
;
1416 struct pnv_phb
*phb
;
1417 struct pnv_ioda_pe
*pe
;
1424 hose
= pci_bus_to_host(bus
);
1425 phb
= hose
->private_data
;
1426 pdn
= pci_get_pdn(pdev
);
1428 if (!pdev
->is_physfn
)
1431 /* Reserve PE for each VF */
1432 for (vf_index
= 0; vf_index
< num_vfs
; vf_index
++) {
1433 pe_num
= pdn
->offset
+ vf_index
;
1435 pe
= &phb
->ioda
.pe_array
[pe_num
];
1436 pe
->pe_number
= pe_num
;
1438 pe
->flags
= PNV_IODA_PE_VF
;
1440 pe
->parent_dev
= pdev
;
1442 pe
->mve_number
= -1;
1443 pe
->rid
= (pci_iov_virtfn_bus(pdev
, vf_index
) << 8) |
1444 pci_iov_virtfn_devfn(pdev
, vf_index
);
1446 pe_info(pe
, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1447 hose
->global_number
, pdev
->bus
->number
,
1448 PCI_SLOT(pci_iov_virtfn_devfn(pdev
, vf_index
)),
1449 PCI_FUNC(pci_iov_virtfn_devfn(pdev
, vf_index
)), pe_num
);
1451 if (pnv_ioda_configure_pe(phb
, pe
)) {
1452 /* XXX What do we do here ? */
1454 pnv_ioda_free_pe(phb
, pe_num
);
1459 /* Put PE to the list */
1460 mutex_lock(&phb
->ioda
.pe_list_mutex
);
1461 list_add_tail(&pe
->list
, &phb
->ioda
.pe_list
);
1462 mutex_unlock(&phb
->ioda
.pe_list_mutex
);
1464 pnv_pci_ioda2_setup_dma_pe(phb
, pe
);
1467 if (pdn
->m64_per_iov
== M64_PER_IOV
&& num_vfs
> M64_PER_IOV
) {
1472 vf_per_group
= roundup_pow_of_two(num_vfs
) / pdn
->m64_per_iov
;
1474 for (vf_group
= 0; vf_group
< M64_PER_IOV
; vf_group
++) {
1475 for (vf_index
= vf_group
* vf_per_group
;
1476 vf_index
< (vf_group
+ 1) * vf_per_group
&&
1479 for (vf_index1
= vf_group
* vf_per_group
;
1480 vf_index1
< (vf_group
+ 1) * vf_per_group
&&
1481 vf_index1
< num_vfs
;
1484 rc
= opal_pci_set_peltv(phb
->opal_id
,
1485 pdn
->offset
+ vf_index
,
1486 pdn
->offset
+ vf_index1
,
1487 OPAL_ADD_PE_TO_DOMAIN
);
1490 dev_warn(&pdev
->dev
, "%s: Failed to link same group PE#%d(%lld)\n",
1492 pdn
->offset
+ vf_index1
, rc
);
1499 int pnv_pci_sriov_enable(struct pci_dev
*pdev
, u16 num_vfs
)
1501 struct pci_bus
*bus
;
1502 struct pci_controller
*hose
;
1503 struct pnv_phb
*phb
;
1508 hose
= pci_bus_to_host(bus
);
1509 phb
= hose
->private_data
;
1510 pdn
= pci_get_pdn(pdev
);
1512 if (phb
->type
== PNV_PHB_IODA2
) {
1513 /* Calculate available PE for required VFs */
1514 mutex_lock(&phb
->ioda
.pe_alloc_mutex
);
1515 pdn
->offset
= bitmap_find_next_zero_area(
1516 phb
->ioda
.pe_alloc
, phb
->ioda
.total_pe
,
1518 if (pdn
->offset
>= phb
->ioda
.total_pe
) {
1519 mutex_unlock(&phb
->ioda
.pe_alloc_mutex
);
1520 dev_info(&pdev
->dev
, "Failed to enable VF%d\n", num_vfs
);
1524 bitmap_set(phb
->ioda
.pe_alloc
, pdn
->offset
, num_vfs
);
1525 pdn
->num_vfs
= num_vfs
;
1526 mutex_unlock(&phb
->ioda
.pe_alloc_mutex
);
1528 /* Assign M64 window accordingly */
1529 ret
= pnv_pci_vf_assign_m64(pdev
, num_vfs
);
1531 dev_info(&pdev
->dev
, "Not enough M64 window resources\n");
1536 * When using one M64 BAR to map one IOV BAR, we need to shift
1537 * the IOV BAR according to the PE# allocated to the VFs.
1538 * Otherwise, the PE# for the VF will conflict with others.
1540 if (pdn
->m64_per_iov
== 1) {
1541 ret
= pnv_pci_vf_resource_shift(pdev
, pdn
->offset
);
1548 pnv_ioda_setup_vf_PE(pdev
, num_vfs
);
1553 bitmap_clear(phb
->ioda
.pe_alloc
, pdn
->offset
, num_vfs
);
1559 int pcibios_sriov_disable(struct pci_dev
*pdev
)
1561 pnv_pci_sriov_disable(pdev
);
1563 /* Release PCI data */
1564 remove_dev_pci_data(pdev
);
1568 int pcibios_sriov_enable(struct pci_dev
*pdev
, u16 num_vfs
)
1570 /* Allocate PCI data */
1571 add_dev_pci_data(pdev
);
1573 pnv_pci_sriov_enable(pdev
, num_vfs
);
1576 #endif /* CONFIG_PCI_IOV */
1578 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb
*phb
, struct pci_dev
*pdev
)
1580 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
1581 struct pnv_ioda_pe
*pe
;
1584 * The function can be called while the PE#
1585 * hasn't been assigned. Do nothing for the
1588 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
1591 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
1592 WARN_ON(get_dma_ops(&pdev
->dev
) != &dma_iommu_ops
);
1593 set_iommu_table_base(&pdev
->dev
, pe
->table_group
.tables
[0]);
1595 * Note: iommu_add_device() will fail here as
1596 * for physical PE: the device is already added by now;
1597 * for virtual PE: sysfs entries are not ready yet and
1598 * tce_iommu_bus_notifier will add the device to a group later.
1602 static int pnv_pci_ioda_dma_set_mask(struct pci_dev
*pdev
, u64 dma_mask
)
1604 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
1605 struct pnv_phb
*phb
= hose
->private_data
;
1606 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
1607 struct pnv_ioda_pe
*pe
;
1609 bool bypass
= false;
1611 if (WARN_ON(!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
))
1614 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
1615 if (pe
->tce_bypass_enabled
) {
1616 top
= pe
->tce_bypass_base
+ memblock_end_of_DRAM() - 1;
1617 bypass
= (dma_mask
>= top
);
1621 dev_info(&pdev
->dev
, "Using 64-bit DMA iommu bypass\n");
1622 set_dma_ops(&pdev
->dev
, &dma_direct_ops
);
1624 dev_info(&pdev
->dev
, "Using 32-bit DMA via iommu\n");
1625 set_dma_ops(&pdev
->dev
, &dma_iommu_ops
);
1627 *pdev
->dev
.dma_mask
= dma_mask
;
1631 static u64
pnv_pci_ioda_dma_get_required_mask(struct pnv_phb
*phb
,
1632 struct pci_dev
*pdev
)
1634 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
1635 struct pnv_ioda_pe
*pe
;
1638 if (WARN_ON(!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
))
1641 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
1642 if (!pe
->tce_bypass_enabled
)
1643 return __dma_get_required_mask(&pdev
->dev
);
1646 end
= pe
->tce_bypass_base
+ memblock_end_of_DRAM();
1647 mask
= 1ULL << (fls64(end
) - 1);
1653 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe
*pe
,
1654 struct pci_bus
*bus
)
1656 struct pci_dev
*dev
;
1658 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1659 set_iommu_table_base(&dev
->dev
, pe
->table_group
.tables
[0]);
1660 set_dma_offset(&dev
->dev
, pe
->tce_bypass_base
);
1661 iommu_add_device(&dev
->dev
);
1663 if ((pe
->flags
& PNV_IODA_PE_BUS_ALL
) && dev
->subordinate
)
1664 pnv_ioda_setup_bus_dma(pe
, dev
->subordinate
);
1668 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table
*tbl
,
1669 unsigned long index
, unsigned long npages
, bool rm
)
1671 struct iommu_table_group_link
*tgl
= list_first_entry_or_null(
1672 &tbl
->it_group_list
, struct iommu_table_group_link
,
1674 struct pnv_ioda_pe
*pe
= container_of(tgl
->table_group
,
1675 struct pnv_ioda_pe
, table_group
);
1676 __be64 __iomem
*invalidate
= rm
?
1677 (__be64 __iomem
*)pe
->phb
->ioda
.tce_inval_reg_phys
:
1678 pe
->phb
->ioda
.tce_inval_reg
;
1679 unsigned long start
, end
, inc
;
1680 const unsigned shift
= tbl
->it_page_shift
;
1682 start
= __pa(((__be64
*)tbl
->it_base
) + index
- tbl
->it_offset
);
1683 end
= __pa(((__be64
*)tbl
->it_base
) + index
- tbl
->it_offset
+
1686 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1687 if (tbl
->it_busno
) {
1690 inc
= 128ull << shift
;
1691 start
|= tbl
->it_busno
;
1692 end
|= tbl
->it_busno
;
1693 } else if (tbl
->it_type
& TCE_PCI_SWINV_PAIR
) {
1694 /* p7ioc-style invalidation, 2 TCEs per write */
1695 start
|= (1ull << 63);
1696 end
|= (1ull << 63);
1699 /* Default (older HW) */
1703 end
|= inc
- 1; /* round up end to be different than start */
1705 mb(); /* Ensure above stores are visible */
1706 while (start
<= end
) {
1708 __raw_rm_writeq(cpu_to_be64(start
), invalidate
);
1710 __raw_writeq(cpu_to_be64(start
), invalidate
);
1715 * The iommu layer will do another mb() for us on build()
1716 * and we don't care on free()
1720 static int pnv_ioda1_tce_build(struct iommu_table
*tbl
, long index
,
1721 long npages
, unsigned long uaddr
,
1722 enum dma_data_direction direction
,
1723 struct dma_attrs
*attrs
)
1725 int ret
= pnv_tce_build(tbl
, index
, npages
, uaddr
, direction
,
1728 if (!ret
&& (tbl
->it_type
& TCE_PCI_SWINV_CREATE
))
1729 pnv_pci_ioda1_tce_invalidate(tbl
, index
, npages
, false);
1734 #ifdef CONFIG_IOMMU_API
1735 static int pnv_ioda1_tce_xchg(struct iommu_table
*tbl
, long index
,
1736 unsigned long *hpa
, enum dma_data_direction
*direction
)
1738 long ret
= pnv_tce_xchg(tbl
, index
, hpa
, direction
);
1740 if (!ret
&& (tbl
->it_type
&
1741 (TCE_PCI_SWINV_CREATE
| TCE_PCI_SWINV_FREE
)))
1742 pnv_pci_ioda1_tce_invalidate(tbl
, index
, 1, false);
1748 static void pnv_ioda1_tce_free(struct iommu_table
*tbl
, long index
,
1751 pnv_tce_free(tbl
, index
, npages
);
1753 if (tbl
->it_type
& TCE_PCI_SWINV_FREE
)
1754 pnv_pci_ioda1_tce_invalidate(tbl
, index
, npages
, false);
1757 static struct iommu_table_ops pnv_ioda1_iommu_ops
= {
1758 .set
= pnv_ioda1_tce_build
,
1759 #ifdef CONFIG_IOMMU_API
1760 .exchange
= pnv_ioda1_tce_xchg
,
1762 .clear
= pnv_ioda1_tce_free
,
1766 static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe
*pe
)
1768 /* 01xb - invalidate TCEs that match the specified PE# */
1769 unsigned long val
= (0x4ull
<< 60) | (pe
->pe_number
& 0xFF);
1770 struct pnv_phb
*phb
= pe
->phb
;
1772 if (!phb
->ioda
.tce_inval_reg
)
1775 mb(); /* Ensure above stores are visible */
1776 __raw_writeq(cpu_to_be64(val
), phb
->ioda
.tce_inval_reg
);
1779 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number
, bool rm
,
1780 __be64 __iomem
*invalidate
, unsigned shift
,
1781 unsigned long index
, unsigned long npages
)
1783 unsigned long start
, end
, inc
;
1785 /* We'll invalidate DMA address in PE scope */
1786 start
= 0x2ull
<< 60;
1787 start
|= (pe_number
& 0xFF);
1790 /* Figure out the start, end and step */
1791 start
|= (index
<< shift
);
1792 end
|= ((index
+ npages
- 1) << shift
);
1793 inc
= (0x1ull
<< shift
);
1796 while (start
<= end
) {
1798 __raw_rm_writeq(cpu_to_be64(start
), invalidate
);
1800 __raw_writeq(cpu_to_be64(start
), invalidate
);
1805 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table
*tbl
,
1806 unsigned long index
, unsigned long npages
, bool rm
)
1808 struct iommu_table_group_link
*tgl
;
1810 list_for_each_entry_rcu(tgl
, &tbl
->it_group_list
, next
) {
1811 struct pnv_ioda_pe
*pe
= container_of(tgl
->table_group
,
1812 struct pnv_ioda_pe
, table_group
);
1813 __be64 __iomem
*invalidate
= rm
?
1814 (__be64 __iomem
*)pe
->phb
->ioda
.tce_inval_reg_phys
:
1815 pe
->phb
->ioda
.tce_inval_reg
;
1817 pnv_pci_ioda2_do_tce_invalidate(pe
->pe_number
, rm
,
1818 invalidate
, tbl
->it_page_shift
,
1823 static int pnv_ioda2_tce_build(struct iommu_table
*tbl
, long index
,
1824 long npages
, unsigned long uaddr
,
1825 enum dma_data_direction direction
,
1826 struct dma_attrs
*attrs
)
1828 int ret
= pnv_tce_build(tbl
, index
, npages
, uaddr
, direction
,
1831 if (!ret
&& (tbl
->it_type
& TCE_PCI_SWINV_CREATE
))
1832 pnv_pci_ioda2_tce_invalidate(tbl
, index
, npages
, false);
1837 #ifdef CONFIG_IOMMU_API
1838 static int pnv_ioda2_tce_xchg(struct iommu_table
*tbl
, long index
,
1839 unsigned long *hpa
, enum dma_data_direction
*direction
)
1841 long ret
= pnv_tce_xchg(tbl
, index
, hpa
, direction
);
1843 if (!ret
&& (tbl
->it_type
&
1844 (TCE_PCI_SWINV_CREATE
| TCE_PCI_SWINV_FREE
)))
1845 pnv_pci_ioda2_tce_invalidate(tbl
, index
, 1, false);
1851 static void pnv_ioda2_tce_free(struct iommu_table
*tbl
, long index
,
1854 pnv_tce_free(tbl
, index
, npages
);
1856 if (tbl
->it_type
& TCE_PCI_SWINV_FREE
)
1857 pnv_pci_ioda2_tce_invalidate(tbl
, index
, npages
, false);
1860 static void pnv_ioda2_table_free(struct iommu_table
*tbl
)
1862 pnv_pci_ioda2_table_free_pages(tbl
);
1863 iommu_free_table(tbl
, "pnv");
1866 static struct iommu_table_ops pnv_ioda2_iommu_ops
= {
1867 .set
= pnv_ioda2_tce_build
,
1868 #ifdef CONFIG_IOMMU_API
1869 .exchange
= pnv_ioda2_tce_xchg
,
1871 .clear
= pnv_ioda2_tce_free
,
1873 .free
= pnv_ioda2_table_free
,
1876 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb
*phb
,
1877 struct pnv_ioda_pe
*pe
, unsigned int base
,
1881 struct page
*tce_mem
= NULL
;
1882 struct iommu_table
*tbl
;
1887 /* XXX FIXME: Handle 64-bit only DMA devices */
1888 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1889 /* XXX FIXME: Allocate multi-level tables on PHB3 */
1891 /* We shouldn't already have a 32-bit DMA associated */
1892 if (WARN_ON(pe
->tce32_seg
>= 0))
1895 tbl
= pnv_pci_table_alloc(phb
->hose
->node
);
1896 iommu_register_group(&pe
->table_group
, phb
->hose
->global_number
,
1898 pnv_pci_link_table_and_group(phb
->hose
->node
, 0, tbl
, &pe
->table_group
);
1900 /* Grab a 32-bit TCE table */
1901 pe
->tce32_seg
= base
;
1902 pe_info(pe
, " Setting up 32-bit TCE table at %08x..%08x\n",
1903 (base
<< 28), ((base
+ segs
) << 28) - 1);
1905 /* XXX Currently, we allocate one big contiguous table for the
1906 * TCEs. We only really need one chunk per 256M of TCE space
1907 * (ie per segment) but that's an optimization for later, it
1908 * requires some added smarts with our get/put_tce implementation
1910 tce_mem
= alloc_pages_node(phb
->hose
->node
, GFP_KERNEL
,
1911 get_order(TCE32_TABLE_SIZE
* segs
));
1913 pe_err(pe
, " Failed to allocate a 32-bit TCE memory\n");
1916 addr
= page_address(tce_mem
);
1917 memset(addr
, 0, TCE32_TABLE_SIZE
* segs
);
1920 for (i
= 0; i
< segs
; i
++) {
1921 rc
= opal_pci_map_pe_dma_window(phb
->opal_id
,
1924 __pa(addr
) + TCE32_TABLE_SIZE
* i
,
1925 TCE32_TABLE_SIZE
, 0x1000);
1927 pe_err(pe
, " Failed to configure 32-bit TCE table,"
1933 /* Setup linux iommu table */
1934 pnv_pci_setup_iommu_table(tbl
, addr
, TCE32_TABLE_SIZE
* segs
,
1935 base
<< 28, IOMMU_PAGE_SHIFT_4K
);
1937 /* OPAL variant of P7IOC SW invalidated TCEs */
1938 if (phb
->ioda
.tce_inval_reg
)
1939 tbl
->it_type
|= (TCE_PCI_SWINV_CREATE
|
1940 TCE_PCI_SWINV_FREE
|
1941 TCE_PCI_SWINV_PAIR
);
1943 tbl
->it_ops
= &pnv_ioda1_iommu_ops
;
1944 pe
->table_group
.tce32_start
= tbl
->it_offset
<< tbl
->it_page_shift
;
1945 pe
->table_group
.tce32_size
= tbl
->it_size
<< tbl
->it_page_shift
;
1946 iommu_init_table(tbl
, phb
->hose
->node
);
1948 if (pe
->flags
& PNV_IODA_PE_DEV
) {
1950 * Setting table base here only for carrying iommu_group
1951 * further down to let iommu_add_device() do the job.
1952 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
1954 set_iommu_table_base(&pe
->pdev
->dev
, tbl
);
1955 iommu_add_device(&pe
->pdev
->dev
);
1956 } else if (pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
))
1957 pnv_ioda_setup_bus_dma(pe
, pe
->pbus
);
1961 /* XXX Failure: Try to fallback to 64-bit only ? */
1962 if (pe
->tce32_seg
>= 0)
1965 __free_pages(tce_mem
, get_order(TCE32_TABLE_SIZE
* segs
));
1967 pnv_pci_unlink_table_and_group(tbl
, &pe
->table_group
);
1968 iommu_free_table(tbl
, "pnv");
1972 static long pnv_pci_ioda2_set_window(struct iommu_table_group
*table_group
,
1973 int num
, struct iommu_table
*tbl
)
1975 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
1977 struct pnv_phb
*phb
= pe
->phb
;
1979 const unsigned long size
= tbl
->it_indirect_levels
?
1980 tbl
->it_level_size
: tbl
->it_size
;
1981 const __u64 start_addr
= tbl
->it_offset
<< tbl
->it_page_shift
;
1982 const __u64 win_size
= tbl
->it_size
<< tbl
->it_page_shift
;
1984 pe_info(pe
, "Setting up window#%d %llx..%llx pg=%x\n", num
,
1985 start_addr
, start_addr
+ win_size
- 1,
1986 IOMMU_PAGE_SIZE(tbl
));
1989 * Map TCE table through TVT. The TVE index is the PE number
1990 * shifted by 1 bit for 32-bits DMA space.
1992 rc
= opal_pci_map_pe_dma_window(phb
->opal_id
,
1994 (pe
->pe_number
<< 1) + num
,
1995 tbl
->it_indirect_levels
+ 1,
1998 IOMMU_PAGE_SIZE(tbl
));
2000 pe_err(pe
, "Failed to configure TCE table, err %ld\n", rc
);
2004 pnv_pci_link_table_and_group(phb
->hose
->node
, num
,
2005 tbl
, &pe
->table_group
);
2006 pnv_pci_ioda2_tce_invalidate_entire(pe
);
2011 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe
*pe
, bool enable
)
2013 uint16_t window_id
= (pe
->pe_number
<< 1 ) + 1;
2016 pe_info(pe
, "%sabling 64-bit DMA bypass\n", enable
? "En" : "Dis");
2018 phys_addr_t top
= memblock_end_of_DRAM();
2020 top
= roundup_pow_of_two(top
);
2021 rc
= opal_pci_map_pe_dma_window_real(pe
->phb
->opal_id
,
2024 pe
->tce_bypass_base
,
2027 rc
= opal_pci_map_pe_dma_window_real(pe
->phb
->opal_id
,
2030 pe
->tce_bypass_base
,
2034 pe_err(pe
, "OPAL error %lld configuring bypass window\n", rc
);
2036 pe
->tce_bypass_enabled
= enable
;
2039 static long pnv_pci_ioda2_table_alloc_pages(int nid
, __u64 bus_offset
,
2040 __u32 page_shift
, __u64 window_size
, __u32 levels
,
2041 struct iommu_table
*tbl
);
2043 static long pnv_pci_ioda2_create_table(struct iommu_table_group
*table_group
,
2044 int num
, __u32 page_shift
, __u64 window_size
, __u32 levels
,
2045 struct iommu_table
**ptbl
)
2047 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2049 int nid
= pe
->phb
->hose
->node
;
2050 __u64 bus_offset
= num
? pe
->tce_bypass_base
: table_group
->tce32_start
;
2052 struct iommu_table
*tbl
;
2054 tbl
= pnv_pci_table_alloc(nid
);
2058 ret
= pnv_pci_ioda2_table_alloc_pages(nid
,
2059 bus_offset
, page_shift
, window_size
,
2062 iommu_free_table(tbl
, "pnv");
2066 tbl
->it_ops
= &pnv_ioda2_iommu_ops
;
2067 if (pe
->phb
->ioda
.tce_inval_reg
)
2068 tbl
->it_type
|= (TCE_PCI_SWINV_CREATE
| TCE_PCI_SWINV_FREE
);
2075 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe
*pe
)
2077 struct iommu_table
*tbl
= NULL
;
2080 rc
= pnv_pci_ioda2_create_table(&pe
->table_group
, 0,
2081 IOMMU_PAGE_SHIFT_4K
,
2082 pe
->table_group
.tce32_size
,
2083 POWERNV_IOMMU_DEFAULT_LEVELS
, &tbl
);
2085 pe_err(pe
, "Failed to create 32-bit TCE table, err %ld",
2090 iommu_init_table(tbl
, pe
->phb
->hose
->node
);
2092 rc
= pnv_pci_ioda2_set_window(&pe
->table_group
, 0, tbl
);
2094 pe_err(pe
, "Failed to configure 32-bit TCE table, err %ld\n",
2096 pnv_ioda2_table_free(tbl
);
2100 if (!pnv_iommu_bypass_disabled
)
2101 pnv_pci_ioda2_set_bypass(pe
, true);
2103 /* OPAL variant of PHB3 invalidated TCEs */
2104 if (pe
->phb
->ioda
.tce_inval_reg
)
2105 tbl
->it_type
|= (TCE_PCI_SWINV_CREATE
| TCE_PCI_SWINV_FREE
);
2108 * Setting table base here only for carrying iommu_group
2109 * further down to let iommu_add_device() do the job.
2110 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2112 if (pe
->flags
& PNV_IODA_PE_DEV
)
2113 set_iommu_table_base(&pe
->pdev
->dev
, tbl
);
2118 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2119 static long pnv_pci_ioda2_unset_window(struct iommu_table_group
*table_group
,
2122 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2124 struct pnv_phb
*phb
= pe
->phb
;
2127 pe_info(pe
, "Removing DMA window #%d\n", num
);
2129 ret
= opal_pci_map_pe_dma_window(phb
->opal_id
, pe
->pe_number
,
2130 (pe
->pe_number
<< 1) + num
,
2131 0/* levels */, 0/* table address */,
2132 0/* table size */, 0/* page size */);
2134 pe_warn(pe
, "Unmapping failed, ret = %ld\n", ret
);
2136 pnv_pci_ioda2_tce_invalidate_entire(pe
);
2138 pnv_pci_unlink_table_and_group(table_group
->tables
[num
], table_group
);
2144 #ifdef CONFIG_IOMMU_API
2145 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift
,
2146 __u64 window_size
, __u32 levels
)
2148 unsigned long bytes
= 0;
2149 const unsigned window_shift
= ilog2(window_size
);
2150 unsigned entries_shift
= window_shift
- page_shift
;
2151 unsigned table_shift
= entries_shift
+ 3;
2152 unsigned long tce_table_size
= max(0x1000UL
, 1UL << table_shift
);
2153 unsigned long direct_table_size
;
2155 if (!levels
|| (levels
> POWERNV_IOMMU_MAX_LEVELS
) ||
2156 (window_size
> memory_hotplug_max()) ||
2157 !is_power_of_2(window_size
))
2160 /* Calculate a direct table size from window_size and levels */
2161 entries_shift
= (entries_shift
+ levels
- 1) / levels
;
2162 table_shift
= entries_shift
+ 3;
2163 table_shift
= max_t(unsigned, table_shift
, PAGE_SHIFT
);
2164 direct_table_size
= 1UL << table_shift
;
2166 for ( ; levels
; --levels
) {
2167 bytes
+= _ALIGN_UP(tce_table_size
, direct_table_size
);
2169 tce_table_size
/= direct_table_size
;
2170 tce_table_size
<<= 3;
2171 tce_table_size
= _ALIGN_UP(tce_table_size
, direct_table_size
);
2177 static void pnv_ioda2_take_ownership(struct iommu_table_group
*table_group
)
2179 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2181 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2182 struct iommu_table
*tbl
= pe
->table_group
.tables
[0];
2184 pnv_pci_ioda2_set_bypass(pe
, false);
2185 pnv_pci_ioda2_unset_window(&pe
->table_group
, 0);
2186 pnv_ioda2_table_free(tbl
);
2189 static void pnv_ioda2_release_ownership(struct iommu_table_group
*table_group
)
2191 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2194 pnv_pci_ioda2_setup_default_config(pe
);
2197 static struct iommu_table_group_ops pnv_pci_ioda2_ops
= {
2198 .get_table_size
= pnv_pci_ioda2_get_table_size
,
2199 .create_table
= pnv_pci_ioda2_create_table
,
2200 .set_window
= pnv_pci_ioda2_set_window
,
2201 .unset_window
= pnv_pci_ioda2_unset_window
,
2202 .take_ownership
= pnv_ioda2_take_ownership
,
2203 .release_ownership
= pnv_ioda2_release_ownership
,
2207 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb
*phb
)
2209 const __be64
*swinvp
;
2211 /* OPAL variant of PHB3 invalidated TCEs */
2212 swinvp
= of_get_property(phb
->hose
->dn
, "ibm,opal-tce-kill", NULL
);
2216 phb
->ioda
.tce_inval_reg_phys
= be64_to_cpup(swinvp
);
2217 phb
->ioda
.tce_inval_reg
= ioremap(phb
->ioda
.tce_inval_reg_phys
, 8);
2220 static __be64
*pnv_pci_ioda2_table_do_alloc_pages(int nid
, unsigned shift
,
2221 unsigned levels
, unsigned long limit
,
2222 unsigned long *current_offset
)
2224 struct page
*tce_mem
= NULL
;
2226 unsigned order
= max_t(unsigned, shift
, PAGE_SHIFT
) - PAGE_SHIFT
;
2227 unsigned long allocated
= 1UL << (order
+ PAGE_SHIFT
);
2228 unsigned entries
= 1UL << (shift
- 3);
2231 tce_mem
= alloc_pages_node(nid
, GFP_KERNEL
, order
);
2233 pr_err("Failed to allocate a TCE memory, order=%d\n", order
);
2236 addr
= page_address(tce_mem
);
2237 memset(addr
, 0, allocated
);
2241 *current_offset
+= allocated
;
2245 for (i
= 0; i
< entries
; ++i
) {
2246 tmp
= pnv_pci_ioda2_table_do_alloc_pages(nid
, shift
,
2247 levels
, limit
, current_offset
);
2251 addr
[i
] = cpu_to_be64(__pa(tmp
) |
2252 TCE_PCI_READ
| TCE_PCI_WRITE
);
2254 if (*current_offset
>= limit
)
2261 static void pnv_pci_ioda2_table_do_free_pages(__be64
*addr
,
2262 unsigned long size
, unsigned level
);
2264 static long pnv_pci_ioda2_table_alloc_pages(int nid
, __u64 bus_offset
,
2265 __u32 page_shift
, __u64 window_size
, __u32 levels
,
2266 struct iommu_table
*tbl
)
2269 unsigned long offset
= 0, level_shift
;
2270 const unsigned window_shift
= ilog2(window_size
);
2271 unsigned entries_shift
= window_shift
- page_shift
;
2272 unsigned table_shift
= max_t(unsigned, entries_shift
+ 3, PAGE_SHIFT
);
2273 const unsigned long tce_table_size
= 1UL << table_shift
;
2275 if (!levels
|| (levels
> POWERNV_IOMMU_MAX_LEVELS
))
2278 if ((window_size
> memory_hotplug_max()) || !is_power_of_2(window_size
))
2281 /* Adjust direct table size from window_size and levels */
2282 entries_shift
= (entries_shift
+ levels
- 1) / levels
;
2283 level_shift
= entries_shift
+ 3;
2284 level_shift
= max_t(unsigned, level_shift
, PAGE_SHIFT
);
2286 /* Allocate TCE table */
2287 addr
= pnv_pci_ioda2_table_do_alloc_pages(nid
, level_shift
,
2288 levels
, tce_table_size
, &offset
);
2290 /* addr==NULL means that the first level allocation failed */
2295 * First level was allocated but some lower level failed as
2296 * we did not allocate as much as we wanted,
2297 * release partially allocated table.
2299 if (offset
< tce_table_size
) {
2300 pnv_pci_ioda2_table_do_free_pages(addr
,
2301 1ULL << (level_shift
- 3), levels
- 1);
2305 /* Setup linux iommu table */
2306 pnv_pci_setup_iommu_table(tbl
, addr
, tce_table_size
, bus_offset
,
2308 tbl
->it_level_size
= 1ULL << (level_shift
- 3);
2309 tbl
->it_indirect_levels
= levels
- 1;
2310 tbl
->it_allocated_size
= offset
;
2312 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2313 window_size
, tce_table_size
, bus_offset
);
2318 static void pnv_pci_ioda2_table_do_free_pages(__be64
*addr
,
2319 unsigned long size
, unsigned level
)
2321 const unsigned long addr_ul
= (unsigned long) addr
&
2322 ~(TCE_PCI_READ
| TCE_PCI_WRITE
);
2326 u64
*tmp
= (u64
*) addr_ul
;
2328 for (i
= 0; i
< size
; ++i
) {
2329 unsigned long hpa
= be64_to_cpu(tmp
[i
]);
2331 if (!(hpa
& (TCE_PCI_READ
| TCE_PCI_WRITE
)))
2334 pnv_pci_ioda2_table_do_free_pages(__va(hpa
), size
,
2339 free_pages(addr_ul
, get_order(size
<< 3));
2342 static void pnv_pci_ioda2_table_free_pages(struct iommu_table
*tbl
)
2344 const unsigned long size
= tbl
->it_indirect_levels
?
2345 tbl
->it_level_size
: tbl
->it_size
;
2350 pnv_pci_ioda2_table_do_free_pages((__be64
*)tbl
->it_base
, size
,
2351 tbl
->it_indirect_levels
);
2354 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb
*phb
,
2355 struct pnv_ioda_pe
*pe
)
2359 /* We shouldn't already have a 32-bit DMA associated */
2360 if (WARN_ON(pe
->tce32_seg
>= 0))
2363 /* TVE #1 is selected by PCI address bit 59 */
2364 pe
->tce_bypass_base
= 1ull << 59;
2366 iommu_register_group(&pe
->table_group
, phb
->hose
->global_number
,
2369 /* The PE will reserve all possible 32-bits space */
2371 pe_info(pe
, "Setting up 32-bit TCE table at 0..%08x\n",
2372 phb
->ioda
.m32_pci_base
);
2374 /* Setup linux iommu table */
2375 pe
->table_group
.tce32_start
= 0;
2376 pe
->table_group
.tce32_size
= phb
->ioda
.m32_pci_base
;
2377 pe
->table_group
.max_dynamic_windows_supported
=
2378 IOMMU_TABLE_GROUP_MAX_TABLES
;
2379 pe
->table_group
.max_levels
= POWERNV_IOMMU_MAX_LEVELS
;
2380 pe
->table_group
.pgsizes
= SZ_4K
| SZ_64K
| SZ_16M
;
2381 #ifdef CONFIG_IOMMU_API
2382 pe
->table_group
.ops
= &pnv_pci_ioda2_ops
;
2385 rc
= pnv_pci_ioda2_setup_default_config(pe
);
2387 if (pe
->tce32_seg
>= 0)
2392 if (pe
->flags
& PNV_IODA_PE_DEV
)
2393 iommu_add_device(&pe
->pdev
->dev
);
2394 else if (pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
))
2395 pnv_ioda_setup_bus_dma(pe
, pe
->pbus
);
2398 static void pnv_ioda_setup_dma(struct pnv_phb
*phb
)
2400 struct pci_controller
*hose
= phb
->hose
;
2401 unsigned int residual
, remaining
, segs
, tw
, base
;
2402 struct pnv_ioda_pe
*pe
;
2404 /* If we have more PE# than segments available, hand out one
2405 * per PE until we run out and let the rest fail. If not,
2406 * then we assign at least one segment per PE, plus more based
2407 * on the amount of devices under that PE
2409 if (phb
->ioda
.dma_pe_count
> phb
->ioda
.tce32_count
)
2412 residual
= phb
->ioda
.tce32_count
-
2413 phb
->ioda
.dma_pe_count
;
2415 pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
2416 hose
->global_number
, phb
->ioda
.tce32_count
);
2417 pr_info("PCI: %d PE# for a total weight of %d\n",
2418 phb
->ioda
.dma_pe_count
, phb
->ioda
.dma_weight
);
2420 pnv_pci_ioda_setup_opal_tce_kill(phb
);
2422 /* Walk our PE list and configure their DMA segments, hand them
2423 * out one base segment plus any residual segments based on
2426 remaining
= phb
->ioda
.tce32_count
;
2427 tw
= phb
->ioda
.dma_weight
;
2429 list_for_each_entry(pe
, &phb
->ioda
.pe_dma_list
, dma_link
) {
2430 if (!pe
->dma_weight
)
2433 pe_warn(pe
, "No DMA32 resources available\n");
2438 segs
+= ((pe
->dma_weight
* residual
) + (tw
/ 2)) / tw
;
2439 if (segs
> remaining
)
2444 * For IODA2 compliant PHB3, we needn't care about the weight.
2445 * The all available 32-bits DMA space will be assigned to
2448 if (phb
->type
== PNV_PHB_IODA1
) {
2449 pe_info(pe
, "DMA weight %d, assigned %d DMA32 segments\n",
2450 pe
->dma_weight
, segs
);
2451 pnv_pci_ioda_setup_dma_pe(phb
, pe
, base
, segs
);
2453 pe_info(pe
, "Assign DMA32 space\n");
2455 pnv_pci_ioda2_setup_dma_pe(phb
, pe
);
2463 #ifdef CONFIG_PCI_MSI
2464 static void pnv_ioda2_msi_eoi(struct irq_data
*d
)
2466 unsigned int hw_irq
= (unsigned int)irqd_to_hwirq(d
);
2467 struct irq_chip
*chip
= irq_data_get_irq_chip(d
);
2468 struct pnv_phb
*phb
= container_of(chip
, struct pnv_phb
,
2472 rc
= opal_pci_msi_eoi(phb
->opal_id
, hw_irq
);
2479 static void set_msi_irq_chip(struct pnv_phb
*phb
, unsigned int virq
)
2481 struct irq_data
*idata
;
2482 struct irq_chip
*ichip
;
2484 if (phb
->type
!= PNV_PHB_IODA2
)
2487 if (!phb
->ioda
.irq_chip_init
) {
2489 * First time we setup an MSI IRQ, we need to setup the
2490 * corresponding IRQ chip to route correctly.
2492 idata
= irq_get_irq_data(virq
);
2493 ichip
= irq_data_get_irq_chip(idata
);
2494 phb
->ioda
.irq_chip_init
= 1;
2495 phb
->ioda
.irq_chip
= *ichip
;
2496 phb
->ioda
.irq_chip
.irq_eoi
= pnv_ioda2_msi_eoi
;
2498 irq_set_chip(virq
, &phb
->ioda
.irq_chip
);
2501 #ifdef CONFIG_CXL_BASE
2503 struct device_node
*pnv_pci_get_phb_node(struct pci_dev
*dev
)
2505 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
2507 return of_node_get(hose
->dn
);
2509 EXPORT_SYMBOL(pnv_pci_get_phb_node
);
2511 int pnv_phb_to_cxl_mode(struct pci_dev
*dev
, uint64_t mode
)
2513 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
2514 struct pnv_phb
*phb
= hose
->private_data
;
2515 struct pnv_ioda_pe
*pe
;
2518 pe
= pnv_ioda_get_pe(dev
);
2522 pe_info(pe
, "Switching PHB to CXL\n");
2524 rc
= opal_pci_set_phb_cxl_mode(phb
->opal_id
, mode
, pe
->pe_number
);
2526 dev_err(&dev
->dev
, "opal_pci_set_phb_cxl_mode failed: %i\n", rc
);
2530 EXPORT_SYMBOL(pnv_phb_to_cxl_mode
);
2532 /* Find PHB for cxl dev and allocate MSI hwirqs?
2533 * Returns the absolute hardware IRQ number
2535 int pnv_cxl_alloc_hwirqs(struct pci_dev
*dev
, int num
)
2537 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
2538 struct pnv_phb
*phb
= hose
->private_data
;
2539 int hwirq
= msi_bitmap_alloc_hwirqs(&phb
->msi_bmp
, num
);
2542 dev_warn(&dev
->dev
, "Failed to find a free MSI\n");
2546 return phb
->msi_base
+ hwirq
;
2548 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs
);
2550 void pnv_cxl_release_hwirqs(struct pci_dev
*dev
, int hwirq
, int num
)
2552 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
2553 struct pnv_phb
*phb
= hose
->private_data
;
2555 msi_bitmap_free_hwirqs(&phb
->msi_bmp
, hwirq
- phb
->msi_base
, num
);
2557 EXPORT_SYMBOL(pnv_cxl_release_hwirqs
);
2559 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges
*irqs
,
2560 struct pci_dev
*dev
)
2562 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
2563 struct pnv_phb
*phb
= hose
->private_data
;
2566 for (i
= 1; i
< CXL_IRQ_RANGES
; i
++) {
2567 if (!irqs
->range
[i
])
2569 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
2572 hwirq
= irqs
->offset
[i
] - phb
->msi_base
;
2573 msi_bitmap_free_hwirqs(&phb
->msi_bmp
, hwirq
,
2577 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges
);
2579 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges
*irqs
,
2580 struct pci_dev
*dev
, int num
)
2582 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
2583 struct pnv_phb
*phb
= hose
->private_data
;
2586 memset(irqs
, 0, sizeof(struct cxl_irq_ranges
));
2588 /* 0 is reserved for the multiplexed PSL DSI interrupt */
2589 for (i
= 1; i
< CXL_IRQ_RANGES
&& num
; i
++) {
2592 hwirq
= msi_bitmap_alloc_hwirqs(&phb
->msi_bmp
, try);
2600 irqs
->offset
[i
] = phb
->msi_base
+ hwirq
;
2601 irqs
->range
[i
] = try;
2602 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
2603 i
, irqs
->offset
[i
], irqs
->range
[i
]);
2611 pnv_cxl_release_hwirq_ranges(irqs
, dev
);
2614 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges
);
2616 int pnv_cxl_get_irq_count(struct pci_dev
*dev
)
2618 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
2619 struct pnv_phb
*phb
= hose
->private_data
;
2621 return phb
->msi_bmp
.irq_count
;
2623 EXPORT_SYMBOL(pnv_cxl_get_irq_count
);
2625 int pnv_cxl_ioda_msi_setup(struct pci_dev
*dev
, unsigned int hwirq
,
2628 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
2629 struct pnv_phb
*phb
= hose
->private_data
;
2630 unsigned int xive_num
= hwirq
- phb
->msi_base
;
2631 struct pnv_ioda_pe
*pe
;
2634 if (!(pe
= pnv_ioda_get_pe(dev
)))
2637 /* Assign XIVE to PE */
2638 rc
= opal_pci_set_xive_pe(phb
->opal_id
, pe
->pe_number
, xive_num
);
2640 pe_warn(pe
, "%s: OPAL error %d setting msi_base 0x%x "
2641 "hwirq 0x%x XIVE 0x%x PE\n",
2642 pci_name(dev
), rc
, phb
->msi_base
, hwirq
, xive_num
);
2645 set_msi_irq_chip(phb
, virq
);
2649 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup
);
2652 static int pnv_pci_ioda_msi_setup(struct pnv_phb
*phb
, struct pci_dev
*dev
,
2653 unsigned int hwirq
, unsigned int virq
,
2654 unsigned int is_64
, struct msi_msg
*msg
)
2656 struct pnv_ioda_pe
*pe
= pnv_ioda_get_pe(dev
);
2657 unsigned int xive_num
= hwirq
- phb
->msi_base
;
2661 /* No PE assigned ? bail out ... no MSI for you ! */
2665 /* Check if we have an MVE */
2666 if (pe
->mve_number
< 0)
2669 /* Force 32-bit MSI on some broken devices */
2670 if (dev
->no_64bit_msi
)
2673 /* Assign XIVE to PE */
2674 rc
= opal_pci_set_xive_pe(phb
->opal_id
, pe
->pe_number
, xive_num
);
2676 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2677 pci_name(dev
), rc
, xive_num
);
2684 rc
= opal_get_msi_64(phb
->opal_id
, pe
->mve_number
, xive_num
, 1,
2687 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2691 msg
->address_hi
= be64_to_cpu(addr64
) >> 32;
2692 msg
->address_lo
= be64_to_cpu(addr64
) & 0xfffffffful
;
2696 rc
= opal_get_msi_32(phb
->opal_id
, pe
->mve_number
, xive_num
, 1,
2699 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2703 msg
->address_hi
= 0;
2704 msg
->address_lo
= be32_to_cpu(addr32
);
2706 msg
->data
= be32_to_cpu(data
);
2708 set_msi_irq_chip(phb
, virq
);
2710 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2711 " address=%x_%08x data=%x PE# %d\n",
2712 pci_name(dev
), is_64
? "64" : "32", hwirq
, xive_num
,
2713 msg
->address_hi
, msg
->address_lo
, data
, pe
->pe_number
);
2718 static void pnv_pci_init_ioda_msis(struct pnv_phb
*phb
)
2721 const __be32
*prop
= of_get_property(phb
->hose
->dn
,
2722 "ibm,opal-msi-ranges", NULL
);
2725 prop
= of_get_property(phb
->hose
->dn
, "msi-ranges", NULL
);
2730 phb
->msi_base
= be32_to_cpup(prop
);
2731 count
= be32_to_cpup(prop
+ 1);
2732 if (msi_bitmap_alloc(&phb
->msi_bmp
, count
, phb
->hose
->dn
)) {
2733 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2734 phb
->hose
->global_number
);
2738 phb
->msi_setup
= pnv_pci_ioda_msi_setup
;
2739 phb
->msi32_support
= 1;
2740 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2741 count
, phb
->msi_base
);
2744 static void pnv_pci_init_ioda_msis(struct pnv_phb
*phb
) { }
2745 #endif /* CONFIG_PCI_MSI */
2747 #ifdef CONFIG_PCI_IOV
2748 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev
*pdev
)
2750 struct pci_controller
*hose
;
2751 struct pnv_phb
*phb
;
2752 struct resource
*res
;
2754 resource_size_t size
;
2758 if (!pdev
->is_physfn
|| pdev
->is_added
)
2761 hose
= pci_bus_to_host(pdev
->bus
);
2762 phb
= hose
->private_data
;
2764 pdn
= pci_get_pdn(pdev
);
2765 pdn
->vfs_expanded
= 0;
2767 total_vfs
= pci_sriov_get_totalvfs(pdev
);
2768 pdn
->m64_per_iov
= 1;
2769 mul
= phb
->ioda
.total_pe
;
2771 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
2772 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
2773 if (!res
->flags
|| res
->parent
)
2775 if (!pnv_pci_is_mem_pref_64(res
->flags
)) {
2776 dev_warn(&pdev
->dev
, " non M64 VF BAR%d: %pR\n",
2781 size
= pci_iov_resource_size(pdev
, i
+ PCI_IOV_RESOURCES
);
2783 /* bigger than 64M */
2784 if (size
> (1 << 26)) {
2785 dev_info(&pdev
->dev
, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n",
2787 pdn
->m64_per_iov
= M64_PER_IOV
;
2788 mul
= roundup_pow_of_two(total_vfs
);
2793 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
2794 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
2795 if (!res
->flags
|| res
->parent
)
2797 if (!pnv_pci_is_mem_pref_64(res
->flags
)) {
2798 dev_warn(&pdev
->dev
, "Skipping expanding VF BAR%d: %pR\n",
2803 dev_dbg(&pdev
->dev
, " Fixing VF BAR%d: %pR to\n", i
, res
);
2804 size
= pci_iov_resource_size(pdev
, i
+ PCI_IOV_RESOURCES
);
2805 res
->end
= res
->start
+ size
* mul
- 1;
2806 dev_dbg(&pdev
->dev
, " %pR\n", res
);
2807 dev_info(&pdev
->dev
, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2810 pdn
->vfs_expanded
= mul
;
2812 #endif /* CONFIG_PCI_IOV */
2815 * This function is supposed to be called on basis of PE from top
2816 * to bottom style. So the the I/O or MMIO segment assigned to
2817 * parent PE could be overrided by its child PEs if necessary.
2819 static void pnv_ioda_setup_pe_seg(struct pci_controller
*hose
,
2820 struct pnv_ioda_pe
*pe
)
2822 struct pnv_phb
*phb
= hose
->private_data
;
2823 struct pci_bus_region region
;
2824 struct resource
*res
;
2829 * NOTE: We only care PCI bus based PE for now. For PCI
2830 * device based PE, for example SRIOV sensitive VF should
2831 * be figured out later.
2833 BUG_ON(!(pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
)));
2835 pci_bus_for_each_resource(pe
->pbus
, res
, i
) {
2836 if (!res
|| !res
->flags
||
2837 res
->start
> res
->end
)
2840 if (res
->flags
& IORESOURCE_IO
) {
2841 region
.start
= res
->start
- phb
->ioda
.io_pci_base
;
2842 region
.end
= res
->end
- phb
->ioda
.io_pci_base
;
2843 index
= region
.start
/ phb
->ioda
.io_segsize
;
2845 while (index
< phb
->ioda
.total_pe
&&
2846 region
.start
<= region
.end
) {
2847 phb
->ioda
.io_segmap
[index
] = pe
->pe_number
;
2848 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
2849 pe
->pe_number
, OPAL_IO_WINDOW_TYPE
, 0, index
);
2850 if (rc
!= OPAL_SUCCESS
) {
2851 pr_err("%s: OPAL error %d when mapping IO "
2852 "segment #%d to PE#%d\n",
2853 __func__
, rc
, index
, pe
->pe_number
);
2857 region
.start
+= phb
->ioda
.io_segsize
;
2860 } else if ((res
->flags
& IORESOURCE_MEM
) &&
2861 !pnv_pci_is_mem_pref_64(res
->flags
)) {
2862 region
.start
= res
->start
-
2863 hose
->mem_offset
[0] -
2864 phb
->ioda
.m32_pci_base
;
2865 region
.end
= res
->end
-
2866 hose
->mem_offset
[0] -
2867 phb
->ioda
.m32_pci_base
;
2868 index
= region
.start
/ phb
->ioda
.m32_segsize
;
2870 while (index
< phb
->ioda
.total_pe
&&
2871 region
.start
<= region
.end
) {
2872 phb
->ioda
.m32_segmap
[index
] = pe
->pe_number
;
2873 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
2874 pe
->pe_number
, OPAL_M32_WINDOW_TYPE
, 0, index
);
2875 if (rc
!= OPAL_SUCCESS
) {
2876 pr_err("%s: OPAL error %d when mapping M32 "
2877 "segment#%d to PE#%d",
2878 __func__
, rc
, index
, pe
->pe_number
);
2882 region
.start
+= phb
->ioda
.m32_segsize
;
2889 static void pnv_pci_ioda_setup_seg(void)
2891 struct pci_controller
*tmp
, *hose
;
2892 struct pnv_phb
*phb
;
2893 struct pnv_ioda_pe
*pe
;
2895 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
2896 phb
= hose
->private_data
;
2897 list_for_each_entry(pe
, &phb
->ioda
.pe_list
, list
) {
2898 pnv_ioda_setup_pe_seg(hose
, pe
);
2903 static void pnv_pci_ioda_setup_DMA(void)
2905 struct pci_controller
*hose
, *tmp
;
2906 struct pnv_phb
*phb
;
2908 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
2909 pnv_ioda_setup_dma(hose
->private_data
);
2911 /* Mark the PHB initialization done */
2912 phb
= hose
->private_data
;
2913 phb
->initialized
= 1;
2917 static void pnv_pci_ioda_create_dbgfs(void)
2919 #ifdef CONFIG_DEBUG_FS
2920 struct pci_controller
*hose
, *tmp
;
2921 struct pnv_phb
*phb
;
2924 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
2925 phb
= hose
->private_data
;
2927 sprintf(name
, "PCI%04x", hose
->global_number
);
2928 phb
->dbgfs
= debugfs_create_dir(name
, powerpc_debugfs_root
);
2930 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
2931 __func__
, hose
->global_number
);
2933 #endif /* CONFIG_DEBUG_FS */
2936 static void pnv_pci_ioda_fixup(void)
2938 pnv_pci_ioda_setup_PEs();
2939 pnv_pci_ioda_setup_seg();
2940 pnv_pci_ioda_setup_DMA();
2942 pnv_pci_ioda_create_dbgfs();
2946 eeh_addr_cache_build();
2951 * Returns the alignment for I/O or memory windows for P2P
2952 * bridges. That actually depends on how PEs are segmented.
2953 * For now, we return I/O or M32 segment size for PE sensitive
2954 * P2P bridges. Otherwise, the default values (4KiB for I/O,
2955 * 1MiB for memory) will be returned.
2957 * The current PCI bus might be put into one PE, which was
2958 * create against the parent PCI bridge. For that case, we
2959 * needn't enlarge the alignment so that we can save some
2962 static resource_size_t
pnv_pci_window_alignment(struct pci_bus
*bus
,
2965 struct pci_dev
*bridge
;
2966 struct pci_controller
*hose
= pci_bus_to_host(bus
);
2967 struct pnv_phb
*phb
= hose
->private_data
;
2968 int num_pci_bridges
= 0;
2972 if (pci_pcie_type(bridge
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
2974 if (num_pci_bridges
>= 2)
2978 bridge
= bridge
->bus
->self
;
2981 /* We fail back to M32 if M64 isn't supported */
2982 if (phb
->ioda
.m64_segsize
&&
2983 pnv_pci_is_mem_pref_64(type
))
2984 return phb
->ioda
.m64_segsize
;
2985 if (type
& IORESOURCE_MEM
)
2986 return phb
->ioda
.m32_segsize
;
2988 return phb
->ioda
.io_segsize
;
2991 #ifdef CONFIG_PCI_IOV
2992 static resource_size_t
pnv_pci_iov_resource_alignment(struct pci_dev
*pdev
,
2995 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
2996 resource_size_t align
, iov_align
;
2998 iov_align
= resource_size(&pdev
->resource
[resno
]);
3002 align
= pci_iov_resource_size(pdev
, resno
);
3003 if (pdn
->vfs_expanded
)
3004 return pdn
->vfs_expanded
* align
;
3008 #endif /* CONFIG_PCI_IOV */
3010 /* Prevent enabling devices for which we couldn't properly
3013 static bool pnv_pci_enable_device_hook(struct pci_dev
*dev
)
3015 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
3016 struct pnv_phb
*phb
= hose
->private_data
;
3019 /* The function is probably called while the PEs have
3020 * not be created yet. For example, resource reassignment
3021 * during PCI probe period. We just skip the check if
3024 if (!phb
->initialized
)
3027 pdn
= pci_get_pdn(dev
);
3028 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
3034 static u32
pnv_ioda_bdfn_to_pe(struct pnv_phb
*phb
, struct pci_bus
*bus
,
3037 return phb
->ioda
.pe_rmap
[(bus
->number
<< 8) | devfn
];
3040 static void pnv_pci_ioda_shutdown(struct pci_controller
*hose
)
3042 struct pnv_phb
*phb
= hose
->private_data
;
3044 opal_pci_reset(phb
->opal_id
, OPAL_RESET_PCI_IODA_TABLE
,
3048 static const struct pci_controller_ops pnv_pci_ioda_controller_ops
= {
3049 .dma_dev_setup
= pnv_pci_dma_dev_setup
,
3050 #ifdef CONFIG_PCI_MSI
3051 .setup_msi_irqs
= pnv_setup_msi_irqs
,
3052 .teardown_msi_irqs
= pnv_teardown_msi_irqs
,
3054 .enable_device_hook
= pnv_pci_enable_device_hook
,
3055 .window_alignment
= pnv_pci_window_alignment
,
3056 .reset_secondary_bus
= pnv_pci_reset_secondary_bus
,
3057 .dma_set_mask
= pnv_pci_ioda_dma_set_mask
,
3058 .shutdown
= pnv_pci_ioda_shutdown
,
3061 static void __init
pnv_pci_init_ioda_phb(struct device_node
*np
,
3062 u64 hub_id
, int ioda_type
)
3064 struct pci_controller
*hose
;
3065 struct pnv_phb
*phb
;
3066 unsigned long size
, m32map_off
, pemap_off
, iomap_off
= 0;
3067 const __be64
*prop64
;
3068 const __be32
*prop32
;
3074 pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type
, np
->full_name
);
3076 prop64
= of_get_property(np
, "ibm,opal-phbid", NULL
);
3078 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3081 phb_id
= be64_to_cpup(prop64
);
3082 pr_debug(" PHB-ID : 0x%016llx\n", phb_id
);
3084 phb
= memblock_virt_alloc(sizeof(struct pnv_phb
), 0);
3086 /* Allocate PCI controller */
3087 phb
->hose
= hose
= pcibios_alloc_controller(np
);
3089 pr_err(" Can't allocate PCI controller for %s\n",
3091 memblock_free(__pa(phb
), sizeof(struct pnv_phb
));
3095 spin_lock_init(&phb
->lock
);
3096 prop32
= of_get_property(np
, "bus-range", &len
);
3097 if (prop32
&& len
== 8) {
3098 hose
->first_busno
= be32_to_cpu(prop32
[0]);
3099 hose
->last_busno
= be32_to_cpu(prop32
[1]);
3101 pr_warn(" Broken <bus-range> on %s\n", np
->full_name
);
3102 hose
->first_busno
= 0;
3103 hose
->last_busno
= 0xff;
3105 hose
->private_data
= phb
;
3106 phb
->hub_id
= hub_id
;
3107 phb
->opal_id
= phb_id
;
3108 phb
->type
= ioda_type
;
3109 mutex_init(&phb
->ioda
.pe_alloc_mutex
);
3111 /* Detect specific models for error handling */
3112 if (of_device_is_compatible(np
, "ibm,p7ioc-pciex"))
3113 phb
->model
= PNV_PHB_MODEL_P7IOC
;
3114 else if (of_device_is_compatible(np
, "ibm,power8-pciex"))
3115 phb
->model
= PNV_PHB_MODEL_PHB3
;
3117 phb
->model
= PNV_PHB_MODEL_UNKNOWN
;
3119 /* Parse 32-bit and IO ranges (if any) */
3120 pci_process_bridge_OF_ranges(hose
, np
, !hose
->global_number
);
3123 phb
->regs
= of_iomap(np
, 0);
3124 if (phb
->regs
== NULL
)
3125 pr_err(" Failed to map registers !\n");
3127 /* Initialize more IODA stuff */
3128 phb
->ioda
.total_pe
= 1;
3129 prop32
= of_get_property(np
, "ibm,opal-num-pes", NULL
);
3131 phb
->ioda
.total_pe
= be32_to_cpup(prop32
);
3132 prop32
= of_get_property(np
, "ibm,opal-reserved-pe", NULL
);
3134 phb
->ioda
.reserved_pe
= be32_to_cpup(prop32
);
3136 /* Parse 64-bit MMIO range */
3137 pnv_ioda_parse_m64_window(phb
);
3139 phb
->ioda
.m32_size
= resource_size(&hose
->mem_resources
[0]);
3140 /* FW Has already off top 64k of M32 space (MSI space) */
3141 phb
->ioda
.m32_size
+= 0x10000;
3143 phb
->ioda
.m32_segsize
= phb
->ioda
.m32_size
/ phb
->ioda
.total_pe
;
3144 phb
->ioda
.m32_pci_base
= hose
->mem_resources
[0].start
- hose
->mem_offset
[0];
3145 phb
->ioda
.io_size
= hose
->pci_io_size
;
3146 phb
->ioda
.io_segsize
= phb
->ioda
.io_size
/ phb
->ioda
.total_pe
;
3147 phb
->ioda
.io_pci_base
= 0; /* XXX calculate this ? */
3149 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3150 size
= _ALIGN_UP(phb
->ioda
.total_pe
/ 8, sizeof(unsigned long));
3152 size
+= phb
->ioda
.total_pe
* sizeof(phb
->ioda
.m32_segmap
[0]);
3153 if (phb
->type
== PNV_PHB_IODA1
) {
3155 size
+= phb
->ioda
.total_pe
* sizeof(phb
->ioda
.io_segmap
[0]);
3158 size
+= phb
->ioda
.total_pe
* sizeof(struct pnv_ioda_pe
);
3159 aux
= memblock_virt_alloc(size
, 0);
3160 phb
->ioda
.pe_alloc
= aux
;
3161 phb
->ioda
.m32_segmap
= aux
+ m32map_off
;
3162 if (phb
->type
== PNV_PHB_IODA1
)
3163 phb
->ioda
.io_segmap
= aux
+ iomap_off
;
3164 phb
->ioda
.pe_array
= aux
+ pemap_off
;
3165 set_bit(phb
->ioda
.reserved_pe
, phb
->ioda
.pe_alloc
);
3167 INIT_LIST_HEAD(&phb
->ioda
.pe_dma_list
);
3168 INIT_LIST_HEAD(&phb
->ioda
.pe_list
);
3169 mutex_init(&phb
->ioda
.pe_list_mutex
);
3171 /* Calculate how many 32-bit TCE segments we have */
3172 phb
->ioda
.tce32_count
= phb
->ioda
.m32_pci_base
>> 28;
3174 #if 0 /* We should really do that ... */
3175 rc
= opal_pci_set_phb_mem_window(opal
->phb_id
,
3178 starting_real_address
,
3179 starting_pci_address
,
3183 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3184 phb
->ioda
.total_pe
, phb
->ioda
.reserved_pe
,
3185 phb
->ioda
.m32_size
, phb
->ioda
.m32_segsize
);
3186 if (phb
->ioda
.m64_size
)
3187 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3188 phb
->ioda
.m64_size
, phb
->ioda
.m64_segsize
);
3189 if (phb
->ioda
.io_size
)
3190 pr_info(" IO: 0x%x [segment=0x%x]\n",
3191 phb
->ioda
.io_size
, phb
->ioda
.io_segsize
);
3194 phb
->hose
->ops
= &pnv_pci_ops
;
3195 phb
->get_pe_state
= pnv_ioda_get_pe_state
;
3196 phb
->freeze_pe
= pnv_ioda_freeze_pe
;
3197 phb
->unfreeze_pe
= pnv_ioda_unfreeze_pe
;
3199 /* Setup RID -> PE mapping function */
3200 phb
->bdfn_to_pe
= pnv_ioda_bdfn_to_pe
;
3203 phb
->dma_dev_setup
= pnv_pci_ioda_dma_dev_setup
;
3204 phb
->dma_get_required_mask
= pnv_pci_ioda_dma_get_required_mask
;
3206 /* Setup MSI support */
3207 pnv_pci_init_ioda_msis(phb
);
3210 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3211 * to let the PCI core do resource assignment. It's supposed
3212 * that the PCI core will do correct I/O and MMIO alignment
3213 * for the P2P bridge bars so that each PCI bus (excluding
3214 * the child P2P bridges) can form individual PE.
3216 ppc_md
.pcibios_fixup
= pnv_pci_ioda_fixup
;
3217 hose
->controller_ops
= pnv_pci_ioda_controller_ops
;
3219 #ifdef CONFIG_PCI_IOV
3220 ppc_md
.pcibios_fixup_sriov
= pnv_pci_ioda_fixup_iov_resources
;
3221 ppc_md
.pcibios_iov_resource_alignment
= pnv_pci_iov_resource_alignment
;
3224 pci_add_flags(PCI_REASSIGN_ALL_RSRC
);
3226 /* Reset IODA tables to a clean state */
3227 rc
= opal_pci_reset(phb_id
, OPAL_RESET_PCI_IODA_TABLE
, OPAL_ASSERT_RESET
);
3229 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc
);
3231 /* If we're running in kdump kerenl, the previous kerenl never
3232 * shutdown PCI devices correctly. We already got IODA table
3233 * cleaned out. So we have to issue PHB reset to stop all PCI
3234 * transactions from previous kerenl.
3236 if (is_kdump_kernel()) {
3237 pr_info(" Issue PHB reset ...\n");
3238 pnv_eeh_phb_reset(hose
, EEH_RESET_FUNDAMENTAL
);
3239 pnv_eeh_phb_reset(hose
, EEH_RESET_DEACTIVATE
);
3242 /* Remove M64 resource if we can't configure it successfully */
3243 if (!phb
->init_m64
|| phb
->init_m64(phb
))
3244 hose
->mem_resources
[1].flags
= 0;
3247 void __init
pnv_pci_init_ioda2_phb(struct device_node
*np
)
3249 pnv_pci_init_ioda_phb(np
, 0, PNV_PHB_IODA2
);
3252 void __init
pnv_pci_init_ioda_hub(struct device_node
*np
)
3254 struct device_node
*phbn
;
3255 const __be64
*prop64
;
3258 pr_info("Probing IODA IO-Hub %s\n", np
->full_name
);
3260 prop64
= of_get_property(np
, "ibm,opal-hubid", NULL
);
3262 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3265 hub_id
= be64_to_cpup(prop64
);
3266 pr_devel(" HUB-ID : 0x%016llx\n", hub_id
);
3268 /* Count child PHBs */
3269 for_each_child_of_node(np
, phbn
) {
3270 /* Look for IODA1 PHBs */
3271 if (of_device_is_compatible(phbn
, "ibm,ioda-phb"))
3272 pnv_pci_init_ioda_phb(phbn
, hub_id
, PNV_PHB_IODA1
);