arch/arm/mach-imx/mach-imx6q.c

   1 /*
   2  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/clocksource.h>
  17 #include <linux/cpu.h>
  18 #include <linux/delay.h>
  19 #include <linux/export.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/irqchip.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/opp.h>
  29 #include <linux/phy.h>
  30 #include <linux/regmap.h>
  31 #include <linux/micrel_phy.h>
  32 #include <linux/mfd/syscon.h>
  33 #include <asm/hardware/cache-l2x0.h>
  34 #include <asm/mach/arch.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/system_misc.h>
  37
  38 #include "common.h"
  39 #include "cpuidle.h"
  40 #include "hardware.h"
  41
  42 static u32 chip_revision;
  43
  44 int imx6q_revision(void)
  45 {
  46         return chip_revision;
  47 }
  48
  49 static void __init imx6q_init_revision(void)
  50 {
  51         u32 rev = imx_anatop_get_digprog();
  52
  53         switch (rev & 0xff) {
  54         case 0:
  55                 chip_revision = IMX_CHIP_REVISION_1_0;
  56                 break;
  57         case 1:
  58                 chip_revision = IMX_CHIP_REVISION_1_1;
  59                 break;
  60         case 2:
  61                 chip_revision = IMX_CHIP_REVISION_1_2;
  62                 break;
  63         default:
  64                 chip_revision = IMX_CHIP_REVISION_UNKNOWN;
  65         }
  66
  67         mxc_set_cpu_type(rev >> 16 & 0xff);
  68 }
  69
  70 static void imx6q_restart(char mode, const char *cmd)
  71 {
  72         struct device_node *np;
  73         void __iomem *wdog_base;
  74
  75         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
  76         wdog_base = of_iomap(np, 0);
  77         if (!wdog_base)
  78                 goto soft;
  79
  80         imx_src_prepare_restart();
  81
  82         /* enable wdog */
  83         writew_relaxed(1 << 2, wdog_base);
  84         /* write twice to ensure the request will not get ignored */
  85         writew_relaxed(1 << 2, wdog_base);
  86
  87         /* wait for reset to assert ... */
  88         mdelay(500);
  89
  90         pr_err("Watchdog reset failed to assert reset\n");
  91
  92         /* delay to allow the serial port to show the message */
  93         mdelay(50);
  94
  95 soft:
  96         /* we'll take a jump through zero as a poor second */
  97         soft_restart(0);
  98 }
  99
 100 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
 101 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 102 {
 103         if (IS_BUILTIN(CONFIG_PHYLIB)) {
 104                 /* min rx data delay */
 105                 phy_write(phydev, 0x0b, 0x8105);
 106                 phy_write(phydev, 0x0c, 0x0000);
 107
 108                 /* max rx/tx clock delay, min rx/tx control delay */
 109                 phy_write(phydev, 0x0b, 0x8104);
 110                 phy_write(phydev, 0x0c, 0xf0f0);
 111                 phy_write(phydev, 0x0b, 0x104);
 112         }
 113
 114         return 0;
 115 }
 116
 117 static void __init imx6q_sabrelite_cko1_setup(void)
 118 {
 119         struct clk *cko1_sel, *ahb, *cko1;
 120         unsigned long rate;
 121
 122         cko1_sel = clk_get_sys(NULL, "cko1_sel");
 123         ahb = clk_get_sys(NULL, "ahb");
 124         cko1 = clk_get_sys(NULL, "cko1");
 125         if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
 126                 pr_err("cko1 setup failed!\n");
 127                 goto put_clk;
 128         }
 129         clk_set_parent(cko1_sel, ahb);
 130         rate = clk_round_rate(cko1, 16000000);
 131         clk_set_rate(cko1, rate);
 132 put_clk:
 133         if (!IS_ERR(cko1_sel))
 134                 clk_put(cko1_sel);
 135         if (!IS_ERR(ahb))
 136                 clk_put(ahb);
 137         if (!IS_ERR(cko1))
 138                 clk_put(cko1);
 139 }
 140
 141 static void __init imx6q_sabrelite_init(void)
 142 {
 143         if (IS_BUILTIN(CONFIG_PHYLIB))
 144                 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
 145                                 ksz9021rn_phy_fixup);
 146         imx6q_sabrelite_cko1_setup();
 147 }
 148
 149 static void __init imx6q_sabresd_cko1_setup(void)
 150 {
 151         struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
 152         unsigned long rate;
 153
 154         cko1_sel = clk_get_sys(NULL, "cko1_sel");
 155         pll4 = clk_get_sys(NULL, "pll4_audio");
 156         pll4_post = clk_get_sys(NULL, "pll4_post_div");
 157         cko1 = clk_get_sys(NULL, "cko1");
 158         if (IS_ERR(cko1_sel) || IS_ERR(pll4)
 159                         || IS_ERR(pll4_post) || IS_ERR(cko1)) {
 160                 pr_err("cko1 setup failed!\n");
 161                 goto put_clk;
 162         }
 163         /*
 164          * Setting pll4 at 768MHz (24MHz * 32)
 165          * So its child clock can get 24MHz easily
 166          */
 167         clk_set_rate(pll4, 768000000);
 168
 169         clk_set_parent(cko1_sel, pll4_post);
 170         rate = clk_round_rate(cko1, 24000000);
 171         clk_set_rate(cko1, rate);
 172 put_clk:
 173         if (!IS_ERR(cko1_sel))
 174                 clk_put(cko1_sel);
 175         if (!IS_ERR(pll4_post))
 176                 clk_put(pll4_post);
 177         if (!IS_ERR(pll4))
 178                 clk_put(pll4);
 179         if (!IS_ERR(cko1))
 180                 clk_put(cko1);
 181 }
 182
 183 static void __init imx6q_sabresd_init(void)
 184 {
 185         imx6q_sabresd_cko1_setup();
 186 }
 187
 188 static void __init imx6q_1588_init(void)
 189 {
 190         struct regmap *gpr;
 191
 192         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 193         if (!IS_ERR(gpr))
 194                 regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
 195         else
 196                 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
 197
 198 }
 199 static void __init imx6q_usb_init(void)
 200 {
 201         imx_anatop_usb_chrg_detect_disable();
 202 }
 203
 204 static void __init imx6q_init_machine(void)
 205 {
 206         if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
 207                 imx6q_sabrelite_init();
 208         else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
 209                         of_machine_is_compatible("fsl,imx6dl-sabresd"))
 210                 imx6q_sabresd_init();
 211
 212         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 213
 214         imx_anatop_init();
 215         imx6q_pm_init();
 216         imx6q_usb_init();
 217         imx6q_1588_init();
 218 }
 219
 220 #define OCOTP_CFG3                      0x440
 221 #define OCOTP_CFG3_SPEED_SHIFT          16
 222 #define OCOTP_CFG3_SPEED_1P2GHZ         0x3
 223
 224 static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
 225 {
 226         struct device_node *np;
 227         void __iomem *base;
 228         u32 val;
 229
 230         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
 231         if (!np) {
 232                 pr_warn("failed to find ocotp node\n");
 233                 return;
 234         }
 235
 236         base = of_iomap(np, 0);
 237         if (!base) {
 238                 pr_warn("failed to map ocotp\n");
 239                 goto put_node;
 240         }
 241
 242         val = readl_relaxed(base + OCOTP_CFG3);
 243         val >>= OCOTP_CFG3_SPEED_SHIFT;
 244         if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
 245                 if (opp_disable(cpu_dev, 1200000000))
 246                         pr_warn("failed to disable 1.2 GHz OPP\n");
 247
 248 put_node:
 249         of_node_put(np);
 250 }
 251
 252 static void __init imx6q_opp_init(struct device *cpu_dev)
 253 {
 254         struct device_node *np;
 255
 256         np = of_find_node_by_path("/cpus/cpu@0");
 257         if (!np) {
 258                 pr_warn("failed to find cpu0 node\n");
 259                 return;
 260         }
 261
 262         cpu_dev->of_node = np;
 263         if (of_init_opp_table(cpu_dev)) {
 264                 pr_warn("failed to init OPP table\n");
 265                 goto put_node;
 266         }
 267
 268         imx6q_opp_check_1p2ghz(cpu_dev);
 269
 270 put_node:
 271         of_node_put(np);
 272 }
 273
 274 static struct platform_device imx6q_cpufreq_pdev = {
 275         .name = "imx6q-cpufreq",
 276 };
 277
 278 static void __init imx6q_init_late(void)
 279 {
 280         /*
 281          * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
 282          * to run cpuidle on them.
 283          */
 284         if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
 285                 imx6q_cpuidle_init();
 286
 287         if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
 288                 imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
 289                 platform_device_register(&imx6q_cpufreq_pdev);
 290         }
 291 }
 292
 293 static void __init imx6q_map_io(void)
 294 {
 295         debug_ll_io_init();
 296         imx_scu_map_io();
 297 }
 298
 299 #ifdef CONFIG_CACHE_L2X0
 300 static void __init imx6q_init_l2cache(void)
 301 {
 302         void __iomem *l2x0_base;
 303         struct device_node *np;
 304         unsigned int val;
 305
 306         np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
 307         if (!np)
 308                 goto out;
 309
 310         l2x0_base = of_iomap(np, 0);
 311         if (!l2x0_base) {
 312                 of_node_put(np);
 313                 goto out;
 314         }
 315
 316         /* Configure the L2 PREFETCH and POWER registers */
 317         val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
 318         val |= 0x70800000;
 319         writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
 320         val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
 321         writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
 322
 323         iounmap(l2x0_base);
 324         of_node_put(np);
 325
 326 out:
 327         l2x0_of_init(0, ~0UL);
 328 }
 329 #else
 330 static inline void imx6q_init_l2cache(void) {}
 331 #endif
 332
 333 static void __init imx6q_init_irq(void)
 334 {
 335         imx6q_init_revision();
 336         imx6q_init_l2cache();
 337         imx_src_init();
 338         imx_gpc_init();
 339         irqchip_init();
 340 }
 341
 342 static void __init imx6q_timer_init(void)
 343 {
 344         of_clk_init(NULL);
 345         clocksource_of_init();
 346         imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
 347                               imx6q_revision());
 348 }
 349
 350 static const char *imx6q_dt_compat[] __initdata = {
 351         "fsl,imx6dl",
 352         "fsl,imx6q",
 353         NULL,
 354 };
 355
 356 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
 357         .smp            = smp_ops(imx_smp_ops),
 358         .map_io         = imx6q_map_io,
 359         .init_irq       = imx6q_init_irq,
 360         .init_time      = imx6q_timer_init,
 361         .init_machine   = imx6q_init_machine,
 362         .init_late      = imx6q_init_late,
 363         .dt_compat      = imx6q_dt_compat,
 364         .restart        = imx6q_restart,
 365 MACHINE_END