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drm/i915: Remove more ilk rc6 remnants
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / i915 / intel_pm.c
blob32ff034a0875d2921031f101cd6ac5e1dd2966d5
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <linux/cpufreq.h>
29 #include "i915_drv.h"
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33
34 /**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51 #define INTEL_RC6_ENABLE (1<<0)
52 #define INTEL_RC6p_ENABLE (1<<1)
53 #define INTEL_RC6pp_ENABLE (1<<2)
54
55 static void gen9_init_clock_gating(struct drm_device *dev)
56 {
57 struct drm_i915_private *dev_priv = dev->dev_private;
58
59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62 }
63
64 static void skl_init_clock_gating(struct drm_device *dev)
65 {
66 struct drm_i915_private *dev_priv = dev->dev_private;
67
68 gen9_init_clock_gating(dev);
69
70 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
71 /*
72 * WaDisableSDEUnitClockGating:skl
73 * WaSetGAPSunitClckGateDisable:skl
74 */
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
78
79 /* WaDisableVFUnitClockGating:skl */
80 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
81 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
82 }
83
84 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
85 /* WaDisableHDCInvalidation:skl */
86 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
87 BDW_DISABLE_HDC_INVALIDATION);
88
89 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
90 I915_WRITE(FF_SLICE_CS_CHICKEN2,
91 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
92 }
93
94 if (INTEL_REVID(dev) <= SKL_REVID_E0)
95 /* WaDisableLSQCROPERFforOCL:skl */
96 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
97 GEN8_LQSC_RO_PERF_DIS);
98 }
99
100 static void bxt_init_clock_gating(struct drm_device *dev)
101 {
102 struct drm_i915_private *dev_priv = dev->dev_private;
103
104 gen9_init_clock_gating(dev);
105
106 /*
107 * FIXME:
108 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
109 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
110 */
111 /* WaDisableSDEUnitClockGating:bxt */
112 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
113 GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
114 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
115
116 /* FIXME: apply on A0 only */
117 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
118 }
119
120 static void i915_pineview_get_mem_freq(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 u32 tmp;
124
125 tmp = I915_READ(CLKCFG);
126
127 switch (tmp & CLKCFG_FSB_MASK) {
128 case CLKCFG_FSB_533:
129 dev_priv->fsb_freq = 533; /* 133*4 */
130 break;
131 case CLKCFG_FSB_800:
132 dev_priv->fsb_freq = 800; /* 200*4 */
133 break;
134 case CLKCFG_FSB_667:
135 dev_priv->fsb_freq = 667; /* 167*4 */
136 break;
137 case CLKCFG_FSB_400:
138 dev_priv->fsb_freq = 400; /* 100*4 */
139 break;
140 }
141
142 switch (tmp & CLKCFG_MEM_MASK) {
143 case CLKCFG_MEM_533:
144 dev_priv->mem_freq = 533;
145 break;
146 case CLKCFG_MEM_667:
147 dev_priv->mem_freq = 667;
148 break;
149 case CLKCFG_MEM_800:
150 dev_priv->mem_freq = 800;
151 break;
152 }
153
154 /* detect pineview DDR3 setting */
155 tmp = I915_READ(CSHRDDR3CTL);
156 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
157 }
158
159 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
160 {
161 struct drm_i915_private *dev_priv = dev->dev_private;
162 u16 ddrpll, csipll;
163
164 ddrpll = I915_READ16(DDRMPLL1);
165 csipll = I915_READ16(CSIPLL0);
166
167 switch (ddrpll & 0xff) {
168 case 0xc:
169 dev_priv->mem_freq = 800;
170 break;
171 case 0x10:
172 dev_priv->mem_freq = 1066;
173 break;
174 case 0x14:
175 dev_priv->mem_freq = 1333;
176 break;
177 case 0x18:
178 dev_priv->mem_freq = 1600;
179 break;
180 default:
181 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
182 ddrpll & 0xff);
183 dev_priv->mem_freq = 0;
184 break;
185 }
186
187 dev_priv->ips.r_t = dev_priv->mem_freq;
188
189 switch (csipll & 0x3ff) {
190 case 0x00c:
191 dev_priv->fsb_freq = 3200;
192 break;
193 case 0x00e:
194 dev_priv->fsb_freq = 3733;
195 break;
196 case 0x010:
197 dev_priv->fsb_freq = 4266;
198 break;
199 case 0x012:
200 dev_priv->fsb_freq = 4800;
201 break;
202 case 0x014:
203 dev_priv->fsb_freq = 5333;
204 break;
205 case 0x016:
206 dev_priv->fsb_freq = 5866;
207 break;
208 case 0x018:
209 dev_priv->fsb_freq = 6400;
210 break;
211 default:
212 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
213 csipll & 0x3ff);
214 dev_priv->fsb_freq = 0;
215 break;
216 }
217
218 if (dev_priv->fsb_freq == 3200) {
219 dev_priv->ips.c_m = 0;
220 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
221 dev_priv->ips.c_m = 1;
222 } else {
223 dev_priv->ips.c_m = 2;
224 }
225 }
226
227 static const struct cxsr_latency cxsr_latency_table[] = {
228 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
229 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
230 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
231 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
232 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
233
234 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
235 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
236 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
237 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
238 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
239
240 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
241 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
242 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
243 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
244 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
245
246 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
247 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
248 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
249 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
250 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
251
252 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
253 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
254 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
255 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
256 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
257
258 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
259 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
260 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
261 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
262 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
263 };
264
265 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
266 int is_ddr3,
267 int fsb,
268 int mem)
269 {
270 const struct cxsr_latency *latency;
271 int i;
272
273 if (fsb == 0 || mem == 0)
274 return NULL;
275
276 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
277 latency = &cxsr_latency_table[i];
278 if (is_desktop == latency->is_desktop &&
279 is_ddr3 == latency->is_ddr3 &&
280 fsb == latency->fsb_freq && mem == latency->mem_freq)
281 return latency;
282 }
283
284 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
285
286 return NULL;
287 }
288
289 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
290 {
291 u32 val;
292
293 mutex_lock(&dev_priv->rps.hw_lock);
294
295 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
296 if (enable)
297 val &= ~FORCE_DDR_HIGH_FREQ;
298 else
299 val |= FORCE_DDR_HIGH_FREQ;
300 val &= ~FORCE_DDR_LOW_FREQ;
301 val |= FORCE_DDR_FREQ_REQ_ACK;
302 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
303
304 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
305 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
306 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
307
308 mutex_unlock(&dev_priv->rps.hw_lock);
309 }
310
311 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
312 {
313 u32 val;
314
315 mutex_lock(&dev_priv->rps.hw_lock);
316
317 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
318 if (enable)
319 val |= DSP_MAXFIFO_PM5_ENABLE;
320 else
321 val &= ~DSP_MAXFIFO_PM5_ENABLE;
322 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
323
324 mutex_unlock(&dev_priv->rps.hw_lock);
325 }
326
327 #define FW_WM(value, plane) \
328 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
329
330 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
331 {
332 struct drm_device *dev = dev_priv->dev;
333 u32 val;
334
335 if (IS_VALLEYVIEW(dev)) {
336 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
337 if (IS_CHERRYVIEW(dev))
338 chv_set_memory_pm5(dev_priv, enable);
339 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
340 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
341 } else if (IS_PINEVIEW(dev)) {
342 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
343 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
344 I915_WRITE(DSPFW3, val);
345 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
346 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
347 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
348 I915_WRITE(FW_BLC_SELF, val);
349 } else if (IS_I915GM(dev)) {
350 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
351 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
352 I915_WRITE(INSTPM, val);
353 } else {
354 return;
355 }
356
357 DRM_DEBUG_KMS("memory self-refresh is %s\n",
358 enable ? "enabled" : "disabled");
359 }
360
361
362 /*
363 * Latency for FIFO fetches is dependent on several factors:
364 * - memory configuration (speed, channels)
365 * - chipset
366 * - current MCH state
367 * It can be fairly high in some situations, so here we assume a fairly
368 * pessimal value. It's a tradeoff between extra memory fetches (if we
369 * set this value too high, the FIFO will fetch frequently to stay full)
370 * and power consumption (set it too low to save power and we might see
371 * FIFO underruns and display "flicker").
372 *
373 * A value of 5us seems to be a good balance; safe for very low end
374 * platforms but not overly aggressive on lower latency configs.
375 */
376 static const int pessimal_latency_ns = 5000;
377
378 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
379 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
380
381 static int vlv_get_fifo_size(struct drm_device *dev,
382 enum pipe pipe, int plane)
383 {
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 int sprite0_start, sprite1_start, size;
386
387 switch (pipe) {
388 uint32_t dsparb, dsparb2, dsparb3;
389 case PIPE_A:
390 dsparb = I915_READ(DSPARB);
391 dsparb2 = I915_READ(DSPARB2);
392 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
393 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
394 break;
395 case PIPE_B:
396 dsparb = I915_READ(DSPARB);
397 dsparb2 = I915_READ(DSPARB2);
398 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
399 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
400 break;
401 case PIPE_C:
402 dsparb2 = I915_READ(DSPARB2);
403 dsparb3 = I915_READ(DSPARB3);
404 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
405 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
406 break;
407 default:
408 return 0;
409 }
410
411 switch (plane) {
412 case 0:
413 size = sprite0_start;
414 break;
415 case 1:
416 size = sprite1_start - sprite0_start;
417 break;
418 case 2:
419 size = 512 - 1 - sprite1_start;
420 break;
421 default:
422 return 0;
423 }
424
425 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
426 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
427 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
428 size);
429
430 return size;
431 }
432
433 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
434 {
435 struct drm_i915_private *dev_priv = dev->dev_private;
436 uint32_t dsparb = I915_READ(DSPARB);
437 int size;
438
439 size = dsparb & 0x7f;
440 if (plane)
441 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
442
443 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
444 plane ? "B" : "A", size);
445
446 return size;
447 }
448
449 static int i830_get_fifo_size(struct drm_device *dev, int plane)
450 {
451 struct drm_i915_private *dev_priv = dev->dev_private;
452 uint32_t dsparb = I915_READ(DSPARB);
453 int size;
454
455 size = dsparb & 0x1ff;
456 if (plane)
457 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
458 size >>= 1; /* Convert to cachelines */
459
460 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
461 plane ? "B" : "A", size);
462
463 return size;
464 }
465
466 static int i845_get_fifo_size(struct drm_device *dev, int plane)
467 {
468 struct drm_i915_private *dev_priv = dev->dev_private;
469 uint32_t dsparb = I915_READ(DSPARB);
470 int size;
471
472 size = dsparb & 0x7f;
473 size >>= 2; /* Convert to cachelines */
474
475 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
476 plane ? "B" : "A",
477 size);
478
479 return size;
480 }
481
482 /* Pineview has different values for various configs */
483 static const struct intel_watermark_params pineview_display_wm = {
484 .fifo_size = PINEVIEW_DISPLAY_FIFO,
485 .max_wm = PINEVIEW_MAX_WM,
486 .default_wm = PINEVIEW_DFT_WM,
487 .guard_size = PINEVIEW_GUARD_WM,
488 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
489 };
490 static const struct intel_watermark_params pineview_display_hplloff_wm = {
491 .fifo_size = PINEVIEW_DISPLAY_FIFO,
492 .max_wm = PINEVIEW_MAX_WM,
493 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
494 .guard_size = PINEVIEW_GUARD_WM,
495 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
496 };
497 static const struct intel_watermark_params pineview_cursor_wm = {
498 .fifo_size = PINEVIEW_CURSOR_FIFO,
499 .max_wm = PINEVIEW_CURSOR_MAX_WM,
500 .default_wm = PINEVIEW_CURSOR_DFT_WM,
501 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
502 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
503 };
504 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
505 .fifo_size = PINEVIEW_CURSOR_FIFO,
506 .max_wm = PINEVIEW_CURSOR_MAX_WM,
507 .default_wm = PINEVIEW_CURSOR_DFT_WM,
508 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
509 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
510 };
511 static const struct intel_watermark_params g4x_wm_info = {
512 .fifo_size = G4X_FIFO_SIZE,
513 .max_wm = G4X_MAX_WM,
514 .default_wm = G4X_MAX_WM,
515 .guard_size = 2,
516 .cacheline_size = G4X_FIFO_LINE_SIZE,
517 };
518 static const struct intel_watermark_params g4x_cursor_wm_info = {
519 .fifo_size = I965_CURSOR_FIFO,
520 .max_wm = I965_CURSOR_MAX_WM,
521 .default_wm = I965_CURSOR_DFT_WM,
522 .guard_size = 2,
523 .cacheline_size = G4X_FIFO_LINE_SIZE,
524 };
525 static const struct intel_watermark_params valleyview_wm_info = {
526 .fifo_size = VALLEYVIEW_FIFO_SIZE,
527 .max_wm = VALLEYVIEW_MAX_WM,
528 .default_wm = VALLEYVIEW_MAX_WM,
529 .guard_size = 2,
530 .cacheline_size = G4X_FIFO_LINE_SIZE,
531 };
532 static const struct intel_watermark_params valleyview_cursor_wm_info = {
533 .fifo_size = I965_CURSOR_FIFO,
534 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
535 .default_wm = I965_CURSOR_DFT_WM,
536 .guard_size = 2,
537 .cacheline_size = G4X_FIFO_LINE_SIZE,
538 };
539 static const struct intel_watermark_params i965_cursor_wm_info = {
540 .fifo_size = I965_CURSOR_FIFO,
541 .max_wm = I965_CURSOR_MAX_WM,
542 .default_wm = I965_CURSOR_DFT_WM,
543 .guard_size = 2,
544 .cacheline_size = I915_FIFO_LINE_SIZE,
545 };
546 static const struct intel_watermark_params i945_wm_info = {
547 .fifo_size = I945_FIFO_SIZE,
548 .max_wm = I915_MAX_WM,
549 .default_wm = 1,
550 .guard_size = 2,
551 .cacheline_size = I915_FIFO_LINE_SIZE,
552 };
553 static const struct intel_watermark_params i915_wm_info = {
554 .fifo_size = I915_FIFO_SIZE,
555 .max_wm = I915_MAX_WM,
556 .default_wm = 1,
557 .guard_size = 2,
558 .cacheline_size = I915_FIFO_LINE_SIZE,
559 };
560 static const struct intel_watermark_params i830_a_wm_info = {
561 .fifo_size = I855GM_FIFO_SIZE,
562 .max_wm = I915_MAX_WM,
563 .default_wm = 1,
564 .guard_size = 2,
565 .cacheline_size = I830_FIFO_LINE_SIZE,
566 };
567 static const struct intel_watermark_params i830_bc_wm_info = {
568 .fifo_size = I855GM_FIFO_SIZE,
569 .max_wm = I915_MAX_WM/2,
570 .default_wm = 1,
571 .guard_size = 2,
572 .cacheline_size = I830_FIFO_LINE_SIZE,
573 };
574 static const struct intel_watermark_params i845_wm_info = {
575 .fifo_size = I830_FIFO_SIZE,
576 .max_wm = I915_MAX_WM,
577 .default_wm = 1,
578 .guard_size = 2,
579 .cacheline_size = I830_FIFO_LINE_SIZE,
580 };
581
582 /**
583 * intel_calculate_wm - calculate watermark level
584 * @clock_in_khz: pixel clock
585 * @wm: chip FIFO params
586 * @pixel_size: display pixel size
587 * @latency_ns: memory latency for the platform
588 *
589 * Calculate the watermark level (the level at which the display plane will
590 * start fetching from memory again). Each chip has a different display
591 * FIFO size and allocation, so the caller needs to figure that out and pass
592 * in the correct intel_watermark_params structure.
593 *
594 * As the pixel clock runs, the FIFO will be drained at a rate that depends
595 * on the pixel size. When it reaches the watermark level, it'll start
596 * fetching FIFO line sized based chunks from memory until the FIFO fills
597 * past the watermark point. If the FIFO drains completely, a FIFO underrun
598 * will occur, and a display engine hang could result.
599 */
600 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
601 const struct intel_watermark_params *wm,
602 int fifo_size,
603 int pixel_size,
604 unsigned long latency_ns)
605 {
606 long entries_required, wm_size;
607
608 /*
609 * Note: we need to make sure we don't overflow for various clock &
610 * latency values.
611 * clocks go from a few thousand to several hundred thousand.
612 * latency is usually a few thousand
613 */
614 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
615 1000;
616 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
617
618 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
619
620 wm_size = fifo_size - (entries_required + wm->guard_size);
621
622 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
623
624 /* Don't promote wm_size to unsigned... */
625 if (wm_size > (long)wm->max_wm)
626 wm_size = wm->max_wm;
627 if (wm_size <= 0)
628 wm_size = wm->default_wm;
629
630 /*
631 * Bspec seems to indicate that the value shouldn't be lower than
632 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
633 * Lets go for 8 which is the burst size since certain platforms
634 * already use a hardcoded 8 (which is what the spec says should be
635 * done).
636 */
637 if (wm_size <= 8)
638 wm_size = 8;
639
640 return wm_size;
641 }
642
643 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
644 {
645 struct drm_crtc *crtc, *enabled = NULL;
646
647 for_each_crtc(dev, crtc) {
648 if (intel_crtc_active(crtc)) {
649 if (enabled)
650 return NULL;
651 enabled = crtc;
652 }
653 }
654
655 return enabled;
656 }
657
658 static void pineview_update_wm(struct drm_crtc *unused_crtc)
659 {
660 struct drm_device *dev = unused_crtc->dev;
661 struct drm_i915_private *dev_priv = dev->dev_private;
662 struct drm_crtc *crtc;
663 const struct cxsr_latency *latency;
664 u32 reg;
665 unsigned long wm;
666
667 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
668 dev_priv->fsb_freq, dev_priv->mem_freq);
669 if (!latency) {
670 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
671 intel_set_memory_cxsr(dev_priv, false);
672 return;
673 }
674
675 crtc = single_enabled_crtc(dev);
676 if (crtc) {
677 const struct drm_display_mode *adjusted_mode;
678 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
679 int clock;
680
681 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
682 clock = adjusted_mode->crtc_clock;
683
684 /* Display SR */
685 wm = intel_calculate_wm(clock, &pineview_display_wm,
686 pineview_display_wm.fifo_size,
687 pixel_size, latency->display_sr);
688 reg = I915_READ(DSPFW1);
689 reg &= ~DSPFW_SR_MASK;
690 reg |= FW_WM(wm, SR);
691 I915_WRITE(DSPFW1, reg);
692 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
693
694 /* cursor SR */
695 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
696 pineview_display_wm.fifo_size,
697 pixel_size, latency->cursor_sr);
698 reg = I915_READ(DSPFW3);
699 reg &= ~DSPFW_CURSOR_SR_MASK;
700 reg |= FW_WM(wm, CURSOR_SR);
701 I915_WRITE(DSPFW3, reg);
702
703 /* Display HPLL off SR */
704 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
705 pineview_display_hplloff_wm.fifo_size,
706 pixel_size, latency->display_hpll_disable);
707 reg = I915_READ(DSPFW3);
708 reg &= ~DSPFW_HPLL_SR_MASK;
709 reg |= FW_WM(wm, HPLL_SR);
710 I915_WRITE(DSPFW3, reg);
711
712 /* cursor HPLL off SR */
713 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
714 pineview_display_hplloff_wm.fifo_size,
715 pixel_size, latency->cursor_hpll_disable);
716 reg = I915_READ(DSPFW3);
717 reg &= ~DSPFW_HPLL_CURSOR_MASK;
718 reg |= FW_WM(wm, HPLL_CURSOR);
719 I915_WRITE(DSPFW3, reg);
720 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
721
722 intel_set_memory_cxsr(dev_priv, true);
723 } else {
724 intel_set_memory_cxsr(dev_priv, false);
725 }
726 }
727
728 static bool g4x_compute_wm0(struct drm_device *dev,
729 int plane,
730 const struct intel_watermark_params *display,
731 int display_latency_ns,
732 const struct intel_watermark_params *cursor,
733 int cursor_latency_ns,
734 int *plane_wm,
735 int *cursor_wm)
736 {
737 struct drm_crtc *crtc;
738 const struct drm_display_mode *adjusted_mode;
739 int htotal, hdisplay, clock, pixel_size;
740 int line_time_us, line_count;
741 int entries, tlb_miss;
742
743 crtc = intel_get_crtc_for_plane(dev, plane);
744 if (!intel_crtc_active(crtc)) {
745 *cursor_wm = cursor->guard_size;
746 *plane_wm = display->guard_size;
747 return false;
748 }
749
750 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
751 clock = adjusted_mode->crtc_clock;
752 htotal = adjusted_mode->crtc_htotal;
753 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
754 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
755
756 /* Use the small buffer method to calculate plane watermark */
757 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
758 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
759 if (tlb_miss > 0)
760 entries += tlb_miss;
761 entries = DIV_ROUND_UP(entries, display->cacheline_size);
762 *plane_wm = entries + display->guard_size;
763 if (*plane_wm > (int)display->max_wm)
764 *plane_wm = display->max_wm;
765
766 /* Use the large buffer method to calculate cursor watermark */
767 line_time_us = max(htotal * 1000 / clock, 1);
768 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
769 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
770 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
771 if (tlb_miss > 0)
772 entries += tlb_miss;
773 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
774 *cursor_wm = entries + cursor->guard_size;
775 if (*cursor_wm > (int)cursor->max_wm)
776 *cursor_wm = (int)cursor->max_wm;
777
778 return true;
779 }
780
781 /*
782 * Check the wm result.
783 *
784 * If any calculated watermark values is larger than the maximum value that
785 * can be programmed into the associated watermark register, that watermark
786 * must be disabled.
787 */
788 static bool g4x_check_srwm(struct drm_device *dev,
789 int display_wm, int cursor_wm,
790 const struct intel_watermark_params *display,
791 const struct intel_watermark_params *cursor)
792 {
793 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
794 display_wm, cursor_wm);
795
796 if (display_wm > display->max_wm) {
797 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
798 display_wm, display->max_wm);
799 return false;
800 }
801
802 if (cursor_wm > cursor->max_wm) {
803 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
804 cursor_wm, cursor->max_wm);
805 return false;
806 }
807
808 if (!(display_wm || cursor_wm)) {
809 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
810 return false;
811 }
812
813 return true;
814 }
815
816 static bool g4x_compute_srwm(struct drm_device *dev,
817 int plane,
818 int latency_ns,
819 const struct intel_watermark_params *display,
820 const struct intel_watermark_params *cursor,
821 int *display_wm, int *cursor_wm)
822 {
823 struct drm_crtc *crtc;
824 const struct drm_display_mode *adjusted_mode;
825 int hdisplay, htotal, pixel_size, clock;
826 unsigned long line_time_us;
827 int line_count, line_size;
828 int small, large;
829 int entries;
830
831 if (!latency_ns) {
832 *display_wm = *cursor_wm = 0;
833 return false;
834 }
835
836 crtc = intel_get_crtc_for_plane(dev, plane);
837 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
838 clock = adjusted_mode->crtc_clock;
839 htotal = adjusted_mode->crtc_htotal;
840 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
841 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
842
843 line_time_us = max(htotal * 1000 / clock, 1);
844 line_count = (latency_ns / line_time_us + 1000) / 1000;
845 line_size = hdisplay * pixel_size;
846
847 /* Use the minimum of the small and large buffer method for primary */
848 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
849 large = line_count * line_size;
850
851 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
852 *display_wm = entries + display->guard_size;
853
854 /* calculate the self-refresh watermark for display cursor */
855 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
856 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
857 *cursor_wm = entries + cursor->guard_size;
858
859 return g4x_check_srwm(dev,
860 *display_wm, *cursor_wm,
861 display, cursor);
862 }
863
864 #define FW_WM_VLV(value, plane) \
865 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
866
867 static void vlv_write_wm_values(struct intel_crtc *crtc,
868 const struct vlv_wm_values *wm)
869 {
870 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
871 enum pipe pipe = crtc->pipe;
872
873 I915_WRITE(VLV_DDL(pipe),
874 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
875 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
876 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
877 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
878
879 I915_WRITE(DSPFW1,
880 FW_WM(wm->sr.plane, SR) |
881 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
882 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
883 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
884 I915_WRITE(DSPFW2,
885 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
886 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
887 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
888 I915_WRITE(DSPFW3,
889 FW_WM(wm->sr.cursor, CURSOR_SR));
890
891 if (IS_CHERRYVIEW(dev_priv)) {
892 I915_WRITE(DSPFW7_CHV,
893 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
894 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
895 I915_WRITE(DSPFW8_CHV,
896 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
897 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
898 I915_WRITE(DSPFW9_CHV,
899 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
900 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
901 I915_WRITE(DSPHOWM,
902 FW_WM(wm->sr.plane >> 9, SR_HI) |
903 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
904 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
905 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
906 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
907 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
908 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
909 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
910 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
911 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
912 } else {
913 I915_WRITE(DSPFW7,
914 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
915 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
916 I915_WRITE(DSPHOWM,
917 FW_WM(wm->sr.plane >> 9, SR_HI) |
918 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
919 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
920 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
921 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
922 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
923 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
924 }
925
926 POSTING_READ(DSPFW1);
927
928 dev_priv->wm.vlv = *wm;
929 }
930
931 #undef FW_WM_VLV
932
933 static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
934 struct drm_plane *plane)
935 {
936 struct drm_device *dev = crtc->dev;
937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
938 int entries, prec_mult, drain_latency, pixel_size;
939 int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
940 const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
941
942 /*
943 * FIXME the plane might have an fb
944 * but be invisible (eg. due to clipping)
945 */
946 if (!intel_crtc->active || !plane->state->fb)
947 return 0;
948
949 if (WARN(clock == 0, "Pixel clock is zero!\n"))
950 return 0;
951
952 pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
953
954 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
955 return 0;
956
957 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
958
959 prec_mult = high_precision;
960 drain_latency = 64 * prec_mult * 4 / entries;
961
962 if (drain_latency > DRAIN_LATENCY_MASK) {
963 prec_mult /= 2;
964 drain_latency = 64 * prec_mult * 4 / entries;
965 }
966
967 if (drain_latency > DRAIN_LATENCY_MASK)
968 drain_latency = DRAIN_LATENCY_MASK;
969
970 return drain_latency | (prec_mult == high_precision ?
971 DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
972 }
973
974 static int vlv_compute_wm(struct intel_crtc *crtc,
975 struct intel_plane *plane,
976 int fifo_size)
977 {
978 int clock, entries, pixel_size;
979
980 /*
981 * FIXME the plane might have an fb
982 * but be invisible (eg. due to clipping)
983 */
984 if (!crtc->active || !plane->base.state->fb)
985 return 0;
986
987 pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
988 clock = crtc->config->base.adjusted_mode.crtc_clock;
989
990 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
991
992 /*
993 * Set up the watermark such that we don't start issuing memory
994 * requests until we are within PND's max deadline value (256us).
995 * Idea being to be idle as long as possible while still taking
996 * advatange of PND's deadline scheduling. The limit of 8
997 * cachelines (used when the FIFO will anyway drain in less time
998 * than 256us) should match what we would be done if trickle
999 * feed were enabled.
1000 */
1001 return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
1002 }
1003
1004 static bool vlv_compute_sr_wm(struct drm_device *dev,
1005 struct vlv_wm_values *wm)
1006 {
1007 struct drm_i915_private *dev_priv = to_i915(dev);
1008 struct drm_crtc *crtc;
1009 enum pipe pipe = INVALID_PIPE;
1010 int num_planes = 0;
1011 int fifo_size = 0;
1012 struct intel_plane *plane;
1013
1014 wm->sr.cursor = wm->sr.plane = 0;
1015
1016 crtc = single_enabled_crtc(dev);
1017 /* maxfifo not supported on pipe C */
1018 if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
1019 pipe = to_intel_crtc(crtc)->pipe;
1020 num_planes = !!wm->pipe[pipe].primary +
1021 !!wm->pipe[pipe].sprite[0] +
1022 !!wm->pipe[pipe].sprite[1];
1023 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1024 }
1025
1026 if (fifo_size == 0 || num_planes > 1)
1027 return false;
1028
1029 wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
1030 to_intel_plane(crtc->cursor), 0x3f);
1031
1032 list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
1033 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1034 continue;
1035
1036 if (plane->pipe != pipe)
1037 continue;
1038
1039 wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
1040 plane, fifo_size);
1041 if (wm->sr.plane != 0)
1042 break;
1043 }
1044
1045 return true;
1046 }
1047
1048 static void valleyview_update_wm(struct drm_crtc *crtc)
1049 {
1050 struct drm_device *dev = crtc->dev;
1051 struct drm_i915_private *dev_priv = dev->dev_private;
1052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1053 enum pipe pipe = intel_crtc->pipe;
1054 bool cxsr_enabled;
1055 struct vlv_wm_values wm = dev_priv->wm.vlv;
1056
1057 wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
1058 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
1059 to_intel_plane(crtc->primary),
1060 vlv_get_fifo_size(dev, pipe, 0));
1061
1062 wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
1063 wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
1064 to_intel_plane(crtc->cursor),
1065 0x3f);
1066
1067 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1068
1069 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1070 return;
1071
1072 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1073 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1074 wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1075 wm.sr.plane, wm.sr.cursor);
1076
1077 /*
1078 * FIXME DDR DVFS introduces massive memory latencies which
1079 * are not known to system agent so any deadline specified
1080 * by the display may not be respected. To support DDR DVFS
1081 * the watermark code needs to be rewritten to essentially
1082 * bypass deadline mechanism and rely solely on the
1083 * watermarks. For now disable DDR DVFS.
1084 */
1085 if (IS_CHERRYVIEW(dev_priv))
1086 chv_set_memory_dvfs(dev_priv, false);
1087
1088 if (!cxsr_enabled)
1089 intel_set_memory_cxsr(dev_priv, false);
1090
1091 vlv_write_wm_values(intel_crtc, &wm);
1092
1093 if (cxsr_enabled)
1094 intel_set_memory_cxsr(dev_priv, true);
1095 }
1096
1097 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1098 struct drm_crtc *crtc,
1099 uint32_t sprite_width,
1100 uint32_t sprite_height,
1101 int pixel_size,
1102 bool enabled, bool scaled)
1103 {
1104 struct drm_device *dev = crtc->dev;
1105 struct drm_i915_private *dev_priv = dev->dev_private;
1106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1107 enum pipe pipe = intel_crtc->pipe;
1108 int sprite = to_intel_plane(plane)->plane;
1109 bool cxsr_enabled;
1110 struct vlv_wm_values wm = dev_priv->wm.vlv;
1111
1112 if (enabled) {
1113 wm.ddl[pipe].sprite[sprite] =
1114 vlv_compute_drain_latency(crtc, plane);
1115
1116 wm.pipe[pipe].sprite[sprite] =
1117 vlv_compute_wm(intel_crtc,
1118 to_intel_plane(plane),
1119 vlv_get_fifo_size(dev, pipe, sprite+1));
1120 } else {
1121 wm.ddl[pipe].sprite[sprite] = 0;
1122 wm.pipe[pipe].sprite[sprite] = 0;
1123 }
1124
1125 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1126
1127 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1128 return;
1129
1130 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
1131 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1132 sprite_name(pipe, sprite),
1133 wm.pipe[pipe].sprite[sprite],
1134 wm.sr.plane, wm.sr.cursor);
1135
1136 if (!cxsr_enabled)
1137 intel_set_memory_cxsr(dev_priv, false);
1138
1139 vlv_write_wm_values(intel_crtc, &wm);
1140
1141 if (cxsr_enabled)
1142 intel_set_memory_cxsr(dev_priv, true);
1143 }
1144
1145 #define single_plane_enabled(mask) is_power_of_2(mask)
1146
1147 static void g4x_update_wm(struct drm_crtc *crtc)
1148 {
1149 struct drm_device *dev = crtc->dev;
1150 static const int sr_latency_ns = 12000;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1153 int plane_sr, cursor_sr;
1154 unsigned int enabled = 0;
1155 bool cxsr_enabled;
1156
1157 if (g4x_compute_wm0(dev, PIPE_A,
1158 &g4x_wm_info, pessimal_latency_ns,
1159 &g4x_cursor_wm_info, pessimal_latency_ns,
1160 &planea_wm, &cursora_wm))
1161 enabled |= 1 << PIPE_A;
1162
1163 if (g4x_compute_wm0(dev, PIPE_B,
1164 &g4x_wm_info, pessimal_latency_ns,
1165 &g4x_cursor_wm_info, pessimal_latency_ns,
1166 &planeb_wm, &cursorb_wm))
1167 enabled |= 1 << PIPE_B;
1168
1169 if (single_plane_enabled(enabled) &&
1170 g4x_compute_srwm(dev, ffs(enabled) - 1,
1171 sr_latency_ns,
1172 &g4x_wm_info,
1173 &g4x_cursor_wm_info,
1174 &plane_sr, &cursor_sr)) {
1175 cxsr_enabled = true;
1176 } else {
1177 cxsr_enabled = false;
1178 intel_set_memory_cxsr(dev_priv, false);
1179 plane_sr = cursor_sr = 0;
1180 }
1181
1182 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1183 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1184 planea_wm, cursora_wm,
1185 planeb_wm, cursorb_wm,
1186 plane_sr, cursor_sr);
1187
1188 I915_WRITE(DSPFW1,
1189 FW_WM(plane_sr, SR) |
1190 FW_WM(cursorb_wm, CURSORB) |
1191 FW_WM(planeb_wm, PLANEB) |
1192 FW_WM(planea_wm, PLANEA));
1193 I915_WRITE(DSPFW2,
1194 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1195 FW_WM(cursora_wm, CURSORA));
1196 /* HPLL off in SR has some issues on G4x... disable it */
1197 I915_WRITE(DSPFW3,
1198 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1199 FW_WM(cursor_sr, CURSOR_SR));
1200
1201 if (cxsr_enabled)
1202 intel_set_memory_cxsr(dev_priv, true);
1203 }
1204
1205 static void i965_update_wm(struct drm_crtc *unused_crtc)
1206 {
1207 struct drm_device *dev = unused_crtc->dev;
1208 struct drm_i915_private *dev_priv = dev->dev_private;
1209 struct drm_crtc *crtc;
1210 int srwm = 1;
1211 int cursor_sr = 16;
1212 bool cxsr_enabled;
1213
1214 /* Calc sr entries for one plane configs */
1215 crtc = single_enabled_crtc(dev);
1216 if (crtc) {
1217 /* self-refresh has much higher latency */
1218 static const int sr_latency_ns = 12000;
1219 const struct drm_display_mode *adjusted_mode =
1220 &to_intel_crtc(crtc)->config->base.adjusted_mode;
1221 int clock = adjusted_mode->crtc_clock;
1222 int htotal = adjusted_mode->crtc_htotal;
1223 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1224 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1225 unsigned long line_time_us;
1226 int entries;
1227
1228 line_time_us = max(htotal * 1000 / clock, 1);
1229
1230 /* Use ns/us then divide to preserve precision */
1231 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1232 pixel_size * hdisplay;
1233 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1234 srwm = I965_FIFO_SIZE - entries;
1235 if (srwm < 0)
1236 srwm = 1;
1237 srwm &= 0x1ff;
1238 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1239 entries, srwm);
1240
1241 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1242 pixel_size * crtc->cursor->state->crtc_w;
1243 entries = DIV_ROUND_UP(entries,
1244 i965_cursor_wm_info.cacheline_size);
1245 cursor_sr = i965_cursor_wm_info.fifo_size -
1246 (entries + i965_cursor_wm_info.guard_size);
1247
1248 if (cursor_sr > i965_cursor_wm_info.max_wm)
1249 cursor_sr = i965_cursor_wm_info.max_wm;
1250
1251 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1252 "cursor %d\n", srwm, cursor_sr);
1253
1254 cxsr_enabled = true;
1255 } else {
1256 cxsr_enabled = false;
1257 /* Turn off self refresh if both pipes are enabled */
1258 intel_set_memory_cxsr(dev_priv, false);
1259 }
1260
1261 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1262 srwm);
1263
1264 /* 965 has limitations... */
1265 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1266 FW_WM(8, CURSORB) |
1267 FW_WM(8, PLANEB) |
1268 FW_WM(8, PLANEA));
1269 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1270 FW_WM(8, PLANEC_OLD));
1271 /* update cursor SR watermark */
1272 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1273
1274 if (cxsr_enabled)
1275 intel_set_memory_cxsr(dev_priv, true);
1276 }
1277
1278 #undef FW_WM
1279
1280 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1281 {
1282 struct drm_device *dev = unused_crtc->dev;
1283 struct drm_i915_private *dev_priv = dev->dev_private;
1284 const struct intel_watermark_params *wm_info;
1285 uint32_t fwater_lo;
1286 uint32_t fwater_hi;
1287 int cwm, srwm = 1;
1288 int fifo_size;
1289 int planea_wm, planeb_wm;
1290 struct drm_crtc *crtc, *enabled = NULL;
1291
1292 if (IS_I945GM(dev))
1293 wm_info = &i945_wm_info;
1294 else if (!IS_GEN2(dev))
1295 wm_info = &i915_wm_info;
1296 else
1297 wm_info = &i830_a_wm_info;
1298
1299 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1300 crtc = intel_get_crtc_for_plane(dev, 0);
1301 if (intel_crtc_active(crtc)) {
1302 const struct drm_display_mode *adjusted_mode;
1303 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1304 if (IS_GEN2(dev))
1305 cpp = 4;
1306
1307 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1308 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1309 wm_info, fifo_size, cpp,
1310 pessimal_latency_ns);
1311 enabled = crtc;
1312 } else {
1313 planea_wm = fifo_size - wm_info->guard_size;
1314 if (planea_wm > (long)wm_info->max_wm)
1315 planea_wm = wm_info->max_wm;
1316 }
1317
1318 if (IS_GEN2(dev))
1319 wm_info = &i830_bc_wm_info;
1320
1321 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1322 crtc = intel_get_crtc_for_plane(dev, 1);
1323 if (intel_crtc_active(crtc)) {
1324 const struct drm_display_mode *adjusted_mode;
1325 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1326 if (IS_GEN2(dev))
1327 cpp = 4;
1328
1329 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1330 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1331 wm_info, fifo_size, cpp,
1332 pessimal_latency_ns);
1333 if (enabled == NULL)
1334 enabled = crtc;
1335 else
1336 enabled = NULL;
1337 } else {
1338 planeb_wm = fifo_size - wm_info->guard_size;
1339 if (planeb_wm > (long)wm_info->max_wm)
1340 planeb_wm = wm_info->max_wm;
1341 }
1342
1343 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1344
1345 if (IS_I915GM(dev) && enabled) {
1346 struct drm_i915_gem_object *obj;
1347
1348 obj = intel_fb_obj(enabled->primary->state->fb);
1349
1350 /* self-refresh seems busted with untiled */
1351 if (obj->tiling_mode == I915_TILING_NONE)
1352 enabled = NULL;
1353 }
1354
1355 /*
1356 * Overlay gets an aggressive default since video jitter is bad.
1357 */
1358 cwm = 2;
1359
1360 /* Play safe and disable self-refresh before adjusting watermarks. */
1361 intel_set_memory_cxsr(dev_priv, false);
1362
1363 /* Calc sr entries for one plane configs */
1364 if (HAS_FW_BLC(dev) && enabled) {
1365 /* self-refresh has much higher latency */
1366 static const int sr_latency_ns = 6000;
1367 const struct drm_display_mode *adjusted_mode =
1368 &to_intel_crtc(enabled)->config->base.adjusted_mode;
1369 int clock = adjusted_mode->crtc_clock;
1370 int htotal = adjusted_mode->crtc_htotal;
1371 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1372 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1373 unsigned long line_time_us;
1374 int entries;
1375
1376 line_time_us = max(htotal * 1000 / clock, 1);
1377
1378 /* Use ns/us then divide to preserve precision */
1379 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1380 pixel_size * hdisplay;
1381 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1382 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1383 srwm = wm_info->fifo_size - entries;
1384 if (srwm < 0)
1385 srwm = 1;
1386
1387 if (IS_I945G(dev) || IS_I945GM(dev))
1388 I915_WRITE(FW_BLC_SELF,
1389 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1390 else if (IS_I915GM(dev))
1391 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1392 }
1393
1394 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1395 planea_wm, planeb_wm, cwm, srwm);
1396
1397 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1398 fwater_hi = (cwm & 0x1f);
1399
1400 /* Set request length to 8 cachelines per fetch */
1401 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1402 fwater_hi = fwater_hi | (1 << 8);
1403
1404 I915_WRITE(FW_BLC, fwater_lo);
1405 I915_WRITE(FW_BLC2, fwater_hi);
1406
1407 if (enabled)
1408 intel_set_memory_cxsr(dev_priv, true);
1409 }
1410
1411 static void i845_update_wm(struct drm_crtc *unused_crtc)
1412 {
1413 struct drm_device *dev = unused_crtc->dev;
1414 struct drm_i915_private *dev_priv = dev->dev_private;
1415 struct drm_crtc *crtc;
1416 const struct drm_display_mode *adjusted_mode;
1417 uint32_t fwater_lo;
1418 int planea_wm;
1419
1420 crtc = single_enabled_crtc(dev);
1421 if (crtc == NULL)
1422 return;
1423
1424 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1425 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1426 &i845_wm_info,
1427 dev_priv->display.get_fifo_size(dev, 0),
1428 4, pessimal_latency_ns);
1429 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1430 fwater_lo |= (3<<8) | planea_wm;
1431
1432 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1433
1434 I915_WRITE(FW_BLC, fwater_lo);
1435 }
1436
1437 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1438 {
1439 uint32_t pixel_rate;
1440
1441 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1442
1443 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1444 * adjust the pixel_rate here. */
1445
1446 if (pipe_config->pch_pfit.enabled) {
1447 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1448 uint32_t pfit_size = pipe_config->pch_pfit.size;
1449
1450 pipe_w = pipe_config->pipe_src_w;
1451 pipe_h = pipe_config->pipe_src_h;
1452
1453 pfit_w = (pfit_size >> 16) & 0xFFFF;
1454 pfit_h = pfit_size & 0xFFFF;
1455 if (pipe_w < pfit_w)
1456 pipe_w = pfit_w;
1457 if (pipe_h < pfit_h)
1458 pipe_h = pfit_h;
1459
1460 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1461 pfit_w * pfit_h);
1462 }
1463
1464 return pixel_rate;
1465 }
1466
1467 /* latency must be in 0.1us units. */
1468 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1469 uint32_t latency)
1470 {
1471 uint64_t ret;
1472
1473 if (WARN(latency == 0, "Latency value missing\n"))
1474 return UINT_MAX;
1475
1476 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1477 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1478
1479 return ret;
1480 }
1481
1482 /* latency must be in 0.1us units. */
1483 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1484 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1485 uint32_t latency)
1486 {
1487 uint32_t ret;
1488
1489 if (WARN(latency == 0, "Latency value missing\n"))
1490 return UINT_MAX;
1491
1492 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1493 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1494 ret = DIV_ROUND_UP(ret, 64) + 2;
1495 return ret;
1496 }
1497
1498 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1499 uint8_t bytes_per_pixel)
1500 {
1501 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1502 }
1503
1504 struct skl_pipe_wm_parameters {
1505 bool active;
1506 uint32_t pipe_htotal;
1507 uint32_t pixel_rate; /* in KHz */
1508 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1509 struct intel_plane_wm_parameters cursor;
1510 };
1511
1512 struct ilk_pipe_wm_parameters {
1513 bool active;
1514 uint32_t pipe_htotal;
1515 uint32_t pixel_rate;
1516 struct intel_plane_wm_parameters pri;
1517 struct intel_plane_wm_parameters spr;
1518 struct intel_plane_wm_parameters cur;
1519 };
1520
1521 struct ilk_wm_maximums {
1522 uint16_t pri;
1523 uint16_t spr;
1524 uint16_t cur;
1525 uint16_t fbc;
1526 };
1527
1528 /* used in computing the new watermarks state */
1529 struct intel_wm_config {
1530 unsigned int num_pipes_active;
1531 bool sprites_enabled;
1532 bool sprites_scaled;
1533 };
1534
1535 /*
1536 * For both WM_PIPE and WM_LP.
1537 * mem_value must be in 0.1us units.
1538 */
1539 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1540 uint32_t mem_value,
1541 bool is_lp)
1542 {
1543 uint32_t method1, method2;
1544
1545 if (!params->active || !params->pri.enabled)
1546 return 0;
1547
1548 method1 = ilk_wm_method1(params->pixel_rate,
1549 params->pri.bytes_per_pixel,
1550 mem_value);
1551
1552 if (!is_lp)
1553 return method1;
1554
1555 method2 = ilk_wm_method2(params->pixel_rate,
1556 params->pipe_htotal,
1557 params->pri.horiz_pixels,
1558 params->pri.bytes_per_pixel,
1559 mem_value);
1560
1561 return min(method1, method2);
1562 }
1563
1564 /*
1565 * For both WM_PIPE and WM_LP.
1566 * mem_value must be in 0.1us units.
1567 */
1568 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1569 uint32_t mem_value)
1570 {
1571 uint32_t method1, method2;
1572
1573 if (!params->active || !params->spr.enabled)
1574 return 0;
1575
1576 method1 = ilk_wm_method1(params->pixel_rate,
1577 params->spr.bytes_per_pixel,
1578 mem_value);
1579 method2 = ilk_wm_method2(params->pixel_rate,
1580 params->pipe_htotal,
1581 params->spr.horiz_pixels,
1582 params->spr.bytes_per_pixel,
1583 mem_value);
1584 return min(method1, method2);
1585 }
1586
1587 /*
1588 * For both WM_PIPE and WM_LP.
1589 * mem_value must be in 0.1us units.
1590 */
1591 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1592 uint32_t mem_value)
1593 {
1594 if (!params->active || !params->cur.enabled)
1595 return 0;
1596
1597 return ilk_wm_method2(params->pixel_rate,
1598 params->pipe_htotal,
1599 params->cur.horiz_pixels,
1600 params->cur.bytes_per_pixel,
1601 mem_value);
1602 }
1603
1604 /* Only for WM_LP. */
1605 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1606 uint32_t pri_val)
1607 {
1608 if (!params->active || !params->pri.enabled)
1609 return 0;
1610
1611 return ilk_wm_fbc(pri_val,
1612 params->pri.horiz_pixels,
1613 params->pri.bytes_per_pixel);
1614 }
1615
1616 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1617 {
1618 if (INTEL_INFO(dev)->gen >= 8)
1619 return 3072;
1620 else if (INTEL_INFO(dev)->gen >= 7)
1621 return 768;
1622 else
1623 return 512;
1624 }
1625
1626 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1627 int level, bool is_sprite)
1628 {
1629 if (INTEL_INFO(dev)->gen >= 8)
1630 /* BDW primary/sprite plane watermarks */
1631 return level == 0 ? 255 : 2047;
1632 else if (INTEL_INFO(dev)->gen >= 7)
1633 /* IVB/HSW primary/sprite plane watermarks */
1634 return level == 0 ? 127 : 1023;
1635 else if (!is_sprite)
1636 /* ILK/SNB primary plane watermarks */
1637 return level == 0 ? 127 : 511;
1638 else
1639 /* ILK/SNB sprite plane watermarks */
1640 return level == 0 ? 63 : 255;
1641 }
1642
1643 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1644 int level)
1645 {
1646 if (INTEL_INFO(dev)->gen >= 7)
1647 return level == 0 ? 63 : 255;
1648 else
1649 return level == 0 ? 31 : 63;
1650 }
1651
1652 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1653 {
1654 if (INTEL_INFO(dev)->gen >= 8)
1655 return 31;
1656 else
1657 return 15;
1658 }
1659
1660 /* Calculate the maximum primary/sprite plane watermark */
1661 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1662 int level,
1663 const struct intel_wm_config *config,
1664 enum intel_ddb_partitioning ddb_partitioning,
1665 bool is_sprite)
1666 {
1667 unsigned int fifo_size = ilk_display_fifo_size(dev);
1668
1669 /* if sprites aren't enabled, sprites get nothing */
1670 if (is_sprite && !config->sprites_enabled)
1671 return 0;
1672
1673 /* HSW allows LP1+ watermarks even with multiple pipes */
1674 if (level == 0 || config->num_pipes_active > 1) {
1675 fifo_size /= INTEL_INFO(dev)->num_pipes;
1676
1677 /*
1678 * For some reason the non self refresh
1679 * FIFO size is only half of the self
1680 * refresh FIFO size on ILK/SNB.
1681 */
1682 if (INTEL_INFO(dev)->gen <= 6)
1683 fifo_size /= 2;
1684 }
1685
1686 if (config->sprites_enabled) {
1687 /* level 0 is always calculated with 1:1 split */
1688 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1689 if (is_sprite)
1690 fifo_size *= 5;
1691 fifo_size /= 6;
1692 } else {
1693 fifo_size /= 2;
1694 }
1695 }
1696
1697 /* clamp to max that the registers can hold */
1698 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1699 }
1700
1701 /* Calculate the maximum cursor plane watermark */
1702 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1703 int level,
1704 const struct intel_wm_config *config)
1705 {
1706 /* HSW LP1+ watermarks w/ multiple pipes */
1707 if (level > 0 && config->num_pipes_active > 1)
1708 return 64;
1709
1710 /* otherwise just report max that registers can hold */
1711 return ilk_cursor_wm_reg_max(dev, level);
1712 }
1713
1714 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1715 int level,
1716 const struct intel_wm_config *config,
1717 enum intel_ddb_partitioning ddb_partitioning,
1718 struct ilk_wm_maximums *max)
1719 {
1720 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1721 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1722 max->cur = ilk_cursor_wm_max(dev, level, config);
1723 max->fbc = ilk_fbc_wm_reg_max(dev);
1724 }
1725
1726 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1727 int level,
1728 struct ilk_wm_maximums *max)
1729 {
1730 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1731 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1732 max->cur = ilk_cursor_wm_reg_max(dev, level);
1733 max->fbc = ilk_fbc_wm_reg_max(dev);
1734 }
1735
1736 static bool ilk_validate_wm_level(int level,
1737 const struct ilk_wm_maximums *max,
1738 struct intel_wm_level *result)
1739 {
1740 bool ret;
1741
1742 /* already determined to be invalid? */
1743 if (!result->enable)
1744 return false;
1745
1746 result->enable = result->pri_val <= max->pri &&
1747 result->spr_val <= max->spr &&
1748 result->cur_val <= max->cur;
1749
1750 ret = result->enable;
1751
1752 /*
1753 * HACK until we can pre-compute everything,
1754 * and thus fail gracefully if LP0 watermarks
1755 * are exceeded...
1756 */
1757 if (level == 0 && !result->enable) {
1758 if (result->pri_val > max->pri)
1759 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1760 level, result->pri_val, max->pri);
1761 if (result->spr_val > max->spr)
1762 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1763 level, result->spr_val, max->spr);
1764 if (result->cur_val > max->cur)
1765 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1766 level, result->cur_val, max->cur);
1767
1768 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1769 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1770 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1771 result->enable = true;
1772 }
1773
1774 return ret;
1775 }
1776
1777 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1778 int level,
1779 const struct ilk_pipe_wm_parameters *p,
1780 struct intel_wm_level *result)
1781 {
1782 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1783 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1784 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1785
1786 /* WM1+ latency values stored in 0.5us units */
1787 if (level > 0) {
1788 pri_latency *= 5;
1789 spr_latency *= 5;
1790 cur_latency *= 5;
1791 }
1792
1793 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1794 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1795 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1796 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1797 result->enable = true;
1798 }
1799
1800 static uint32_t
1801 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1802 {
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1805 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
1806 u32 linetime, ips_linetime;
1807
1808 if (!intel_crtc->active)
1809 return 0;
1810
1811 /* The WM are computed with base on how long it takes to fill a single
1812 * row at the given clock rate, multiplied by 8.
1813 * */
1814 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1815 mode->crtc_clock);
1816 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1817 dev_priv->cdclk_freq);
1818
1819 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1820 PIPE_WM_LINETIME_TIME(linetime);
1821 }
1822
1823 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
1824 {
1825 struct drm_i915_private *dev_priv = dev->dev_private;
1826
1827 if (IS_GEN9(dev)) {
1828 uint32_t val;
1829 int ret, i;
1830 int level, max_level = ilk_wm_max_level(dev);
1831
1832 /* read the first set of memory latencies[0:3] */
1833 val = 0; /* data0 to be programmed to 0 for first set */
1834 mutex_lock(&dev_priv->rps.hw_lock);
1835 ret = sandybridge_pcode_read(dev_priv,
1836 GEN9_PCODE_READ_MEM_LATENCY,
1837 &val);
1838 mutex_unlock(&dev_priv->rps.hw_lock);
1839
1840 if (ret) {
1841 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1842 return;
1843 }
1844
1845 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1846 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1847 GEN9_MEM_LATENCY_LEVEL_MASK;
1848 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1849 GEN9_MEM_LATENCY_LEVEL_MASK;
1850 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1851 GEN9_MEM_LATENCY_LEVEL_MASK;
1852
1853 /* read the second set of memory latencies[4:7] */
1854 val = 1; /* data0 to be programmed to 1 for second set */
1855 mutex_lock(&dev_priv->rps.hw_lock);
1856 ret = sandybridge_pcode_read(dev_priv,
1857 GEN9_PCODE_READ_MEM_LATENCY,
1858 &val);
1859 mutex_unlock(&dev_priv->rps.hw_lock);
1860 if (ret) {
1861 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1862 return;
1863 }
1864
1865 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1866 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1867 GEN9_MEM_LATENCY_LEVEL_MASK;
1868 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1869 GEN9_MEM_LATENCY_LEVEL_MASK;
1870 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1871 GEN9_MEM_LATENCY_LEVEL_MASK;
1872
1873 /*
1874 * WaWmMemoryReadLatency:skl
1875 *
1876 * punit doesn't take into account the read latency so we need
1877 * to add 2us to the various latency levels we retrieve from
1878 * the punit.
1879 * - W0 is a bit special in that it's the only level that
1880 * can't be disabled if we want to have display working, so
1881 * we always add 2us there.
1882 * - For levels >=1, punit returns 0us latency when they are
1883 * disabled, so we respect that and don't add 2us then
1884 *
1885 * Additionally, if a level n (n > 1) has a 0us latency, all
1886 * levels m (m >= n) need to be disabled. We make sure to
1887 * sanitize the values out of the punit to satisfy this
1888 * requirement.
1889 */
1890 wm[0] += 2;
1891 for (level = 1; level <= max_level; level++)
1892 if (wm[level] != 0)
1893 wm[level] += 2;
1894 else {
1895 for (i = level + 1; i <= max_level; i++)
1896 wm[i] = 0;
1897
1898 break;
1899 }
1900 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1901 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1902
1903 wm[0] = (sskpd >> 56) & 0xFF;
1904 if (wm[0] == 0)
1905 wm[0] = sskpd & 0xF;
1906 wm[1] = (sskpd >> 4) & 0xFF;
1907 wm[2] = (sskpd >> 12) & 0xFF;
1908 wm[3] = (sskpd >> 20) & 0x1FF;
1909 wm[4] = (sskpd >> 32) & 0x1FF;
1910 } else if (INTEL_INFO(dev)->gen >= 6) {
1911 uint32_t sskpd = I915_READ(MCH_SSKPD);
1912
1913 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1914 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1915 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1916 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
1917 } else if (INTEL_INFO(dev)->gen >= 5) {
1918 uint32_t mltr = I915_READ(MLTR_ILK);
1919
1920 /* ILK primary LP0 latency is 700 ns */
1921 wm[0] = 7;
1922 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1923 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
1924 }
1925 }
1926
1927 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1928 {
1929 /* ILK sprite LP0 latency is 1300 ns */
1930 if (INTEL_INFO(dev)->gen == 5)
1931 wm[0] = 13;
1932 }
1933
1934 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1935 {
1936 /* ILK cursor LP0 latency is 1300 ns */
1937 if (INTEL_INFO(dev)->gen == 5)
1938 wm[0] = 13;
1939
1940 /* WaDoubleCursorLP3Latency:ivb */
1941 if (IS_IVYBRIDGE(dev))
1942 wm[3] *= 2;
1943 }
1944
1945 int ilk_wm_max_level(const struct drm_device *dev)
1946 {
1947 /* how many WM levels are we expecting */
1948 if (INTEL_INFO(dev)->gen >= 9)
1949 return 7;
1950 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1951 return 4;
1952 else if (INTEL_INFO(dev)->gen >= 6)
1953 return 3;
1954 else
1955 return 2;
1956 }
1957
1958 static void intel_print_wm_latency(struct drm_device *dev,
1959 const char *name,
1960 const uint16_t wm[8])
1961 {
1962 int level, max_level = ilk_wm_max_level(dev);
1963
1964 for (level = 0; level <= max_level; level++) {
1965 unsigned int latency = wm[level];
1966
1967 if (latency == 0) {
1968 DRM_ERROR("%s WM%d latency not provided\n",
1969 name, level);
1970 continue;
1971 }
1972
1973 /*
1974 * - latencies are in us on gen9.
1975 * - before then, WM1+ latency values are in 0.5us units
1976 */
1977 if (IS_GEN9(dev))
1978 latency *= 10;
1979 else if (level > 0)
1980 latency *= 5;
1981
1982 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1983 name, level, wm[level],
1984 latency / 10, latency % 10);
1985 }
1986 }
1987
1988 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1989 uint16_t wm[5], uint16_t min)
1990 {
1991 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1992
1993 if (wm[0] >= min)
1994 return false;
1995
1996 wm[0] = max(wm[0], min);
1997 for (level = 1; level <= max_level; level++)
1998 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
1999
2000 return true;
2001 }
2002
2003 static void snb_wm_latency_quirk(struct drm_device *dev)
2004 {
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006 bool changed;
2007
2008 /*
2009 * The BIOS provided WM memory latency values are often
2010 * inadequate for high resolution displays. Adjust them.
2011 */
2012 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2013 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2014 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2015
2016 if (!changed)
2017 return;
2018
2019 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2020 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2021 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2022 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2023 }
2024
2025 static void ilk_setup_wm_latency(struct drm_device *dev)
2026 {
2027 struct drm_i915_private *dev_priv = dev->dev_private;
2028
2029 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2030
2031 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2032 sizeof(dev_priv->wm.pri_latency));
2033 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2034 sizeof(dev_priv->wm.pri_latency));
2035
2036 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2037 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2038
2039 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2040 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2041 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2042
2043 if (IS_GEN6(dev))
2044 snb_wm_latency_quirk(dev);
2045 }
2046
2047 static void skl_setup_wm_latency(struct drm_device *dev)
2048 {
2049 struct drm_i915_private *dev_priv = dev->dev_private;
2050
2051 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2052 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2053 }
2054
2055 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2056 struct ilk_pipe_wm_parameters *p)
2057 {
2058 struct drm_device *dev = crtc->dev;
2059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2060 enum pipe pipe = intel_crtc->pipe;
2061 struct drm_plane *plane;
2062
2063 if (!intel_crtc->active)
2064 return;
2065
2066 p->active = true;
2067 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2068 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
2069
2070 if (crtc->primary->state->fb)
2071 p->pri.bytes_per_pixel =
2072 crtc->primary->state->fb->bits_per_pixel / 8;
2073 else
2074 p->pri.bytes_per_pixel = 4;
2075
2076 p->cur.bytes_per_pixel = 4;
2077 /*
2078 * TODO: for now, assume primary and cursor planes are always enabled.
2079 * Setting them to false makes the screen flicker.
2080 */
2081 p->pri.enabled = true;
2082 p->cur.enabled = true;
2083
2084 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
2085 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
2086
2087 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2088 struct intel_plane *intel_plane = to_intel_plane(plane);
2089
2090 if (intel_plane->pipe == pipe) {
2091 p->spr = intel_plane->wm;
2092 break;
2093 }
2094 }
2095 }
2096
2097 static void ilk_compute_wm_config(struct drm_device *dev,
2098 struct intel_wm_config *config)
2099 {
2100 struct intel_crtc *intel_crtc;
2101
2102 /* Compute the currently _active_ config */
2103 for_each_intel_crtc(dev, intel_crtc) {
2104 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2105
2106 if (!wm->pipe_enabled)
2107 continue;
2108
2109 config->sprites_enabled |= wm->sprites_enabled;
2110 config->sprites_scaled |= wm->sprites_scaled;
2111 config->num_pipes_active++;
2112 }
2113 }
2114
2115 /* Compute new watermarks for the pipe */
2116 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2117 const struct ilk_pipe_wm_parameters *params,
2118 struct intel_pipe_wm *pipe_wm)
2119 {
2120 struct drm_device *dev = crtc->dev;
2121 const struct drm_i915_private *dev_priv = dev->dev_private;
2122 int level, max_level = ilk_wm_max_level(dev);
2123 /* LP0 watermark maximums depend on this pipe alone */
2124 struct intel_wm_config config = {
2125 .num_pipes_active = 1,
2126 .sprites_enabled = params->spr.enabled,
2127 .sprites_scaled = params->spr.scaled,
2128 };
2129 struct ilk_wm_maximums max;
2130
2131 pipe_wm->pipe_enabled = params->active;
2132 pipe_wm->sprites_enabled = params->spr.enabled;
2133 pipe_wm->sprites_scaled = params->spr.scaled;
2134
2135 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2136 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2137 max_level = 1;
2138
2139 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2140 if (params->spr.scaled)
2141 max_level = 0;
2142
2143 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2144
2145 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2146 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2147
2148 /* LP0 watermarks always use 1/2 DDB partitioning */
2149 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2150
2151 /* At least LP0 must be valid */
2152 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2153 return false;
2154
2155 ilk_compute_wm_reg_maximums(dev, 1, &max);
2156
2157 for (level = 1; level <= max_level; level++) {
2158 struct intel_wm_level wm = {};
2159
2160 ilk_compute_wm_level(dev_priv, level, params, &wm);
2161
2162 /*
2163 * Disable any watermark level that exceeds the
2164 * register maximums since such watermarks are
2165 * always invalid.
2166 */
2167 if (!ilk_validate_wm_level(level, &max, &wm))
2168 break;
2169
2170 pipe_wm->wm[level] = wm;
2171 }
2172
2173 return true;
2174 }
2175
2176 /*
2177 * Merge the watermarks from all active pipes for a specific level.
2178 */
2179 static void ilk_merge_wm_level(struct drm_device *dev,
2180 int level,
2181 struct intel_wm_level *ret_wm)
2182 {
2183 const struct intel_crtc *intel_crtc;
2184
2185 ret_wm->enable = true;
2186
2187 for_each_intel_crtc(dev, intel_crtc) {
2188 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2189 const struct intel_wm_level *wm = &active->wm[level];
2190
2191 if (!active->pipe_enabled)
2192 continue;
2193
2194 /*
2195 * The watermark values may have been used in the past,
2196 * so we must maintain them in the registers for some
2197 * time even if the level is now disabled.
2198 */
2199 if (!wm->enable)
2200 ret_wm->enable = false;
2201
2202 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2203 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2204 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2205 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2206 }
2207 }
2208
2209 /*
2210 * Merge all low power watermarks for all active pipes.
2211 */
2212 static void ilk_wm_merge(struct drm_device *dev,
2213 const struct intel_wm_config *config,
2214 const struct ilk_wm_maximums *max,
2215 struct intel_pipe_wm *merged)
2216 {
2217 int level, max_level = ilk_wm_max_level(dev);
2218 int last_enabled_level = max_level;
2219
2220 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2221 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2222 config->num_pipes_active > 1)
2223 return;
2224
2225 /* ILK: FBC WM must be disabled always */
2226 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2227
2228 /* merge each WM1+ level */
2229 for (level = 1; level <= max_level; level++) {
2230 struct intel_wm_level *wm = &merged->wm[level];
2231
2232 ilk_merge_wm_level(dev, level, wm);
2233
2234 if (level > last_enabled_level)
2235 wm->enable = false;
2236 else if (!ilk_validate_wm_level(level, max, wm))
2237 /* make sure all following levels get disabled */
2238 last_enabled_level = level - 1;
2239
2240 /*
2241 * The spec says it is preferred to disable
2242 * FBC WMs instead of disabling a WM level.
2243 */
2244 if (wm->fbc_val > max->fbc) {
2245 if (wm->enable)
2246 merged->fbc_wm_enabled = false;
2247 wm->fbc_val = 0;
2248 }
2249 }
2250
2251 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2252 /*
2253 * FIXME this is racy. FBC might get enabled later.
2254 * What we should check here is whether FBC can be
2255 * enabled sometime later.
2256 */
2257 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2258 for (level = 2; level <= max_level; level++) {
2259 struct intel_wm_level *wm = &merged->wm[level];
2260
2261 wm->enable = false;
2262 }
2263 }
2264 }
2265
2266 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2267 {
2268 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2269 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2270 }
2271
2272 /* The value we need to program into the WM_LPx latency field */
2273 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2274 {
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276
2277 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2278 return 2 * level;
2279 else
2280 return dev_priv->wm.pri_latency[level];
2281 }
2282
2283 static void ilk_compute_wm_results(struct drm_device *dev,
2284 const struct intel_pipe_wm *merged,
2285 enum intel_ddb_partitioning partitioning,
2286 struct ilk_wm_values *results)
2287 {
2288 struct intel_crtc *intel_crtc;
2289 int level, wm_lp;
2290
2291 results->enable_fbc_wm = merged->fbc_wm_enabled;
2292 results->partitioning = partitioning;
2293
2294 /* LP1+ register values */
2295 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2296 const struct intel_wm_level *r;
2297
2298 level = ilk_wm_lp_to_level(wm_lp, merged);
2299
2300 r = &merged->wm[level];
2301
2302 /*
2303 * Maintain the watermark values even if the level is
2304 * disabled. Doing otherwise could cause underruns.
2305 */
2306 results->wm_lp[wm_lp - 1] =
2307 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2308 (r->pri_val << WM1_LP_SR_SHIFT) |
2309 r->cur_val;
2310
2311 if (r->enable)
2312 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2313
2314 if (INTEL_INFO(dev)->gen >= 8)
2315 results->wm_lp[wm_lp - 1] |=
2316 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2317 else
2318 results->wm_lp[wm_lp - 1] |=
2319 r->fbc_val << WM1_LP_FBC_SHIFT;
2320
2321 /*
2322 * Always set WM1S_LP_EN when spr_val != 0, even if the
2323 * level is disabled. Doing otherwise could cause underruns.
2324 */
2325 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2326 WARN_ON(wm_lp != 1);
2327 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2328 } else
2329 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2330 }
2331
2332 /* LP0 register values */
2333 for_each_intel_crtc(dev, intel_crtc) {
2334 enum pipe pipe = intel_crtc->pipe;
2335 const struct intel_wm_level *r =
2336 &intel_crtc->wm.active.wm[0];
2337
2338 if (WARN_ON(!r->enable))
2339 continue;
2340
2341 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2342
2343 results->wm_pipe[pipe] =
2344 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2345 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2346 r->cur_val;
2347 }
2348 }
2349
2350 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2351 * case both are at the same level. Prefer r1 in case they're the same. */
2352 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2353 struct intel_pipe_wm *r1,
2354 struct intel_pipe_wm *r2)
2355 {
2356 int level, max_level = ilk_wm_max_level(dev);
2357 int level1 = 0, level2 = 0;
2358
2359 for (level = 1; level <= max_level; level++) {
2360 if (r1->wm[level].enable)
2361 level1 = level;
2362 if (r2->wm[level].enable)
2363 level2 = level;
2364 }
2365
2366 if (level1 == level2) {
2367 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2368 return r2;
2369 else
2370 return r1;
2371 } else if (level1 > level2) {
2372 return r1;
2373 } else {
2374 return r2;
2375 }
2376 }
2377
2378 /* dirty bits used to track which watermarks need changes */
2379 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2380 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2381 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2382 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2383 #define WM_DIRTY_FBC (1 << 24)
2384 #define WM_DIRTY_DDB (1 << 25)
2385
2386 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2387 const struct ilk_wm_values *old,
2388 const struct ilk_wm_values *new)
2389 {
2390 unsigned int dirty = 0;
2391 enum pipe pipe;
2392 int wm_lp;
2393
2394 for_each_pipe(dev_priv, pipe) {
2395 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2396 dirty |= WM_DIRTY_LINETIME(pipe);
2397 /* Must disable LP1+ watermarks too */
2398 dirty |= WM_DIRTY_LP_ALL;
2399 }
2400
2401 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2402 dirty |= WM_DIRTY_PIPE(pipe);
2403 /* Must disable LP1+ watermarks too */
2404 dirty |= WM_DIRTY_LP_ALL;
2405 }
2406 }
2407
2408 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2409 dirty |= WM_DIRTY_FBC;
2410 /* Must disable LP1+ watermarks too */
2411 dirty |= WM_DIRTY_LP_ALL;
2412 }
2413
2414 if (old->partitioning != new->partitioning) {
2415 dirty |= WM_DIRTY_DDB;
2416 /* Must disable LP1+ watermarks too */
2417 dirty |= WM_DIRTY_LP_ALL;
2418 }
2419
2420 /* LP1+ watermarks already deemed dirty, no need to continue */
2421 if (dirty & WM_DIRTY_LP_ALL)
2422 return dirty;
2423
2424 /* Find the lowest numbered LP1+ watermark in need of an update... */
2425 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2426 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2427 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2428 break;
2429 }
2430
2431 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2432 for (; wm_lp <= 3; wm_lp++)
2433 dirty |= WM_DIRTY_LP(wm_lp);
2434
2435 return dirty;
2436 }
2437
2438 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2439 unsigned int dirty)
2440 {
2441 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2442 bool changed = false;
2443
2444 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2445 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2446 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2447 changed = true;
2448 }
2449 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2450 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2451 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2452 changed = true;
2453 }
2454 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2455 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2456 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2457 changed = true;
2458 }
2459
2460 /*
2461 * Don't touch WM1S_LP_EN here.
2462 * Doing so could cause underruns.
2463 */
2464
2465 return changed;
2466 }
2467
2468 /*
2469 * The spec says we shouldn't write when we don't need, because every write
2470 * causes WMs to be re-evaluated, expending some power.
2471 */
2472 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2473 struct ilk_wm_values *results)
2474 {
2475 struct drm_device *dev = dev_priv->dev;
2476 struct ilk_wm_values *previous = &dev_priv->wm.hw;
2477 unsigned int dirty;
2478 uint32_t val;
2479
2480 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2481 if (!dirty)
2482 return;
2483
2484 _ilk_disable_lp_wm(dev_priv, dirty);
2485
2486 if (dirty & WM_DIRTY_PIPE(PIPE_A))
2487 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2488 if (dirty & WM_DIRTY_PIPE(PIPE_B))
2489 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2490 if (dirty & WM_DIRTY_PIPE(PIPE_C))
2491 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2492
2493 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2494 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2495 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2496 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2497 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2498 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2499
2500 if (dirty & WM_DIRTY_DDB) {
2501 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2502 val = I915_READ(WM_MISC);
2503 if (results->partitioning == INTEL_DDB_PART_1_2)
2504 val &= ~WM_MISC_DATA_PARTITION_5_6;
2505 else
2506 val |= WM_MISC_DATA_PARTITION_5_6;
2507 I915_WRITE(WM_MISC, val);
2508 } else {
2509 val = I915_READ(DISP_ARB_CTL2);
2510 if (results->partitioning == INTEL_DDB_PART_1_2)
2511 val &= ~DISP_DATA_PARTITION_5_6;
2512 else
2513 val |= DISP_DATA_PARTITION_5_6;
2514 I915_WRITE(DISP_ARB_CTL2, val);
2515 }
2516 }
2517
2518 if (dirty & WM_DIRTY_FBC) {
2519 val = I915_READ(DISP_ARB_CTL);
2520 if (results->enable_fbc_wm)
2521 val &= ~DISP_FBC_WM_DIS;
2522 else
2523 val |= DISP_FBC_WM_DIS;
2524 I915_WRITE(DISP_ARB_CTL, val);
2525 }
2526
2527 if (dirty & WM_DIRTY_LP(1) &&
2528 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2529 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2530
2531 if (INTEL_INFO(dev)->gen >= 7) {
2532 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2533 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2534 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2535 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2536 }
2537
2538 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2539 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2540 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2541 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2542 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2543 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2544
2545 dev_priv->wm.hw = *results;
2546 }
2547
2548 static bool ilk_disable_lp_wm(struct drm_device *dev)
2549 {
2550 struct drm_i915_private *dev_priv = dev->dev_private;
2551
2552 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2553 }
2554
2555 /*
2556 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2557 * different active planes.
2558 */
2559
2560 #define SKL_DDB_SIZE 896 /* in blocks */
2561 #define BXT_DDB_SIZE 512
2562
2563 static void
2564 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2565 struct drm_crtc *for_crtc,
2566 const struct intel_wm_config *config,
2567 const struct skl_pipe_wm_parameters *params,
2568 struct skl_ddb_entry *alloc /* out */)
2569 {
2570 struct drm_crtc *crtc;
2571 unsigned int pipe_size, ddb_size;
2572 int nth_active_pipe;
2573
2574 if (!params->active) {
2575 alloc->start = 0;
2576 alloc->end = 0;
2577 return;
2578 }
2579
2580 if (IS_BROXTON(dev))
2581 ddb_size = BXT_DDB_SIZE;
2582 else
2583 ddb_size = SKL_DDB_SIZE;
2584
2585 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2586
2587 nth_active_pipe = 0;
2588 for_each_crtc(dev, crtc) {
2589 if (!to_intel_crtc(crtc)->active)
2590 continue;
2591
2592 if (crtc == for_crtc)
2593 break;
2594
2595 nth_active_pipe++;
2596 }
2597
2598 pipe_size = ddb_size / config->num_pipes_active;
2599 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2600 alloc->end = alloc->start + pipe_size;
2601 }
2602
2603 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2604 {
2605 if (config->num_pipes_active == 1)
2606 return 32;
2607
2608 return 8;
2609 }
2610
2611 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2612 {
2613 entry->start = reg & 0x3ff;
2614 entry->end = (reg >> 16) & 0x3ff;
2615 if (entry->end)
2616 entry->end += 1;
2617 }
2618
2619 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2620 struct skl_ddb_allocation *ddb /* out */)
2621 {
2622 enum pipe pipe;
2623 int plane;
2624 u32 val;
2625
2626 for_each_pipe(dev_priv, pipe) {
2627 for_each_plane(dev_priv, pipe, plane) {
2628 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2629 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2630 val);
2631 }
2632
2633 val = I915_READ(CUR_BUF_CFG(pipe));
2634 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2635 }
2636 }
2637
2638 static unsigned int
2639 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2640 {
2641
2642 /* for planar format */
2643 if (p->y_bytes_per_pixel) {
2644 if (y) /* y-plane data rate */
2645 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2646 else /* uv-plane data rate */
2647 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2648 }
2649
2650 /* for packed formats */
2651 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2652 }
2653
2654 /*
2655 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2656 * a 8192x4096@32bpp framebuffer:
2657 * 3 * 4096 * 8192 * 4 < 2^32
2658 */
2659 static unsigned int
2660 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2661 const struct skl_pipe_wm_parameters *params)
2662 {
2663 unsigned int total_data_rate = 0;
2664 int plane;
2665
2666 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2667 const struct intel_plane_wm_parameters *p;
2668
2669 p = &params->plane[plane];
2670 if (!p->enabled)
2671 continue;
2672
2673 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2674 if (p->y_bytes_per_pixel) {
2675 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2676 }
2677 }
2678
2679 return total_data_rate;
2680 }
2681
2682 static void
2683 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2684 const struct intel_wm_config *config,
2685 const struct skl_pipe_wm_parameters *params,
2686 struct skl_ddb_allocation *ddb /* out */)
2687 {
2688 struct drm_device *dev = crtc->dev;
2689 struct drm_i915_private *dev_priv = dev->dev_private;
2690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2691 enum pipe pipe = intel_crtc->pipe;
2692 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2693 uint16_t alloc_size, start, cursor_blocks;
2694 uint16_t minimum[I915_MAX_PLANES];
2695 uint16_t y_minimum[I915_MAX_PLANES];
2696 unsigned int total_data_rate;
2697 int plane;
2698
2699 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2700 alloc_size = skl_ddb_entry_size(alloc);
2701 if (alloc_size == 0) {
2702 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2703 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2704 return;
2705 }
2706
2707 cursor_blocks = skl_cursor_allocation(config);
2708 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2709 ddb->cursor[pipe].end = alloc->end;
2710
2711 alloc_size -= cursor_blocks;
2712 alloc->end -= cursor_blocks;
2713
2714 /* 1. Allocate the mininum required blocks for each active plane */
2715 for_each_plane(dev_priv, pipe, plane) {
2716 const struct intel_plane_wm_parameters *p;
2717
2718 p = &params->plane[plane];
2719 if (!p->enabled)
2720 continue;
2721
2722 minimum[plane] = 8;
2723 alloc_size -= minimum[plane];
2724 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2725 alloc_size -= y_minimum[plane];
2726 }
2727
2728 /*
2729 * 2. Distribute the remaining space in proportion to the amount of
2730 * data each plane needs to fetch from memory.
2731 *
2732 * FIXME: we may not allocate every single block here.
2733 */
2734 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2735
2736 start = alloc->start;
2737 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2738 const struct intel_plane_wm_parameters *p;
2739 unsigned int data_rate, y_data_rate;
2740 uint16_t plane_blocks, y_plane_blocks = 0;
2741
2742 p = &params->plane[plane];
2743 if (!p->enabled)
2744 continue;
2745
2746 data_rate = skl_plane_relative_data_rate(p, 0);
2747
2748 /*
2749 * allocation for (packed formats) or (uv-plane part of planar format):
2750 * promote the expression to 64 bits to avoid overflowing, the
2751 * result is < available as data_rate / total_data_rate < 1
2752 */
2753 plane_blocks = minimum[plane];
2754 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2755 total_data_rate);
2756
2757 ddb->plane[pipe][plane].start = start;
2758 ddb->plane[pipe][plane].end = start + plane_blocks;
2759
2760 start += plane_blocks;
2761
2762 /*
2763 * allocation for y_plane part of planar format:
2764 */
2765 if (p->y_bytes_per_pixel) {
2766 y_data_rate = skl_plane_relative_data_rate(p, 1);
2767 y_plane_blocks = y_minimum[plane];
2768 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2769 total_data_rate);
2770
2771 ddb->y_plane[pipe][plane].start = start;
2772 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
2773
2774 start += y_plane_blocks;
2775 }
2776
2777 }
2778
2779 }
2780
2781 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2782 {
2783 /* TODO: Take into account the scalers once we support them */
2784 return config->base.adjusted_mode.crtc_clock;
2785 }
2786
2787 /*
2788 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2789 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2790 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2791 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2792 */
2793 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2794 uint32_t latency)
2795 {
2796 uint32_t wm_intermediate_val, ret;
2797
2798 if (latency == 0)
2799 return UINT_MAX;
2800
2801 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2802 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2803
2804 return ret;
2805 }
2806
2807 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2808 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2809 uint64_t tiling, uint32_t latency)
2810 {
2811 uint32_t ret;
2812 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2813 uint32_t wm_intermediate_val;
2814
2815 if (latency == 0)
2816 return UINT_MAX;
2817
2818 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
2819
2820 if (tiling == I915_FORMAT_MOD_Y_TILED ||
2821 tiling == I915_FORMAT_MOD_Yf_TILED) {
2822 plane_bytes_per_line *= 4;
2823 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2824 plane_blocks_per_line /= 4;
2825 } else {
2826 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2827 }
2828
2829 wm_intermediate_val = latency * pixel_rate;
2830 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
2831 plane_blocks_per_line;
2832
2833 return ret;
2834 }
2835
2836 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2837 const struct intel_crtc *intel_crtc)
2838 {
2839 struct drm_device *dev = intel_crtc->base.dev;
2840 struct drm_i915_private *dev_priv = dev->dev_private;
2841 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2842 enum pipe pipe = intel_crtc->pipe;
2843
2844 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2845 sizeof(new_ddb->plane[pipe])))
2846 return true;
2847
2848 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2849 sizeof(new_ddb->cursor[pipe])))
2850 return true;
2851
2852 return false;
2853 }
2854
2855 static void skl_compute_wm_global_parameters(struct drm_device *dev,
2856 struct intel_wm_config *config)
2857 {
2858 struct drm_crtc *crtc;
2859 struct drm_plane *plane;
2860
2861 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2862 config->num_pipes_active += to_intel_crtc(crtc)->active;
2863
2864 /* FIXME: I don't think we need those two global parameters on SKL */
2865 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2866 struct intel_plane *intel_plane = to_intel_plane(plane);
2867
2868 config->sprites_enabled |= intel_plane->wm.enabled;
2869 config->sprites_scaled |= intel_plane->wm.scaled;
2870 }
2871 }
2872
2873 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2874 struct skl_pipe_wm_parameters *p)
2875 {
2876 struct drm_device *dev = crtc->dev;
2877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2878 enum pipe pipe = intel_crtc->pipe;
2879 struct drm_plane *plane;
2880 struct drm_framebuffer *fb;
2881 int i = 1; /* Index for sprite planes start */
2882
2883 p->active = intel_crtc->active;
2884 if (p->active) {
2885 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2886 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2887
2888 fb = crtc->primary->state->fb;
2889 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
2890 if (fb) {
2891 p->plane[0].enabled = true;
2892 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
2893 drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
2894 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
2895 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
2896 p->plane[0].tiling = fb->modifier[0];
2897 } else {
2898 p->plane[0].enabled = false;
2899 p->plane[0].bytes_per_pixel = 0;
2900 p->plane[0].y_bytes_per_pixel = 0;
2901 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
2902 }
2903 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2904 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
2905 p->plane[0].rotation = crtc->primary->state->rotation;
2906
2907 fb = crtc->cursor->state->fb;
2908 p->cursor.y_bytes_per_pixel = 0;
2909 if (fb) {
2910 p->cursor.enabled = true;
2911 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
2912 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
2913 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
2914 } else {
2915 p->cursor.enabled = false;
2916 p->cursor.bytes_per_pixel = 0;
2917 p->cursor.horiz_pixels = 64;
2918 p->cursor.vert_pixels = 64;
2919 }
2920 }
2921
2922 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2923 struct intel_plane *intel_plane = to_intel_plane(plane);
2924
2925 if (intel_plane->pipe == pipe &&
2926 plane->type == DRM_PLANE_TYPE_OVERLAY)
2927 p->plane[i++] = intel_plane->wm;
2928 }
2929 }
2930
2931 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
2932 struct skl_pipe_wm_parameters *p,
2933 struct intel_plane_wm_parameters *p_params,
2934 uint16_t ddb_allocation,
2935 int level,
2936 uint16_t *out_blocks, /* out */
2937 uint8_t *out_lines /* out */)
2938 {
2939 uint32_t latency = dev_priv->wm.skl_latency[level];
2940 uint32_t method1, method2;
2941 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2942 uint32_t res_blocks, res_lines;
2943 uint32_t selected_result;
2944 uint8_t bytes_per_pixel;
2945
2946 if (latency == 0 || !p->active || !p_params->enabled)
2947 return false;
2948
2949 bytes_per_pixel = p_params->y_bytes_per_pixel ?
2950 p_params->y_bytes_per_pixel :
2951 p_params->bytes_per_pixel;
2952 method1 = skl_wm_method1(p->pixel_rate,
2953 bytes_per_pixel,
2954 latency);
2955 method2 = skl_wm_method2(p->pixel_rate,
2956 p->pipe_htotal,
2957 p_params->horiz_pixels,
2958 bytes_per_pixel,
2959 p_params->tiling,
2960 latency);
2961
2962 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
2963 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2964
2965 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2966 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
2967 uint32_t min_scanlines = 4;
2968 uint32_t y_tile_minimum;
2969 if (intel_rotation_90_or_270(p_params->rotation)) {
2970 switch (p_params->bytes_per_pixel) {
2971 case 1:
2972 min_scanlines = 16;
2973 break;
2974 case 2:
2975 min_scanlines = 8;
2976 break;
2977 case 8:
2978 WARN(1, "Unsupported pixel depth for rotation");
2979 }
2980 }
2981 y_tile_minimum = plane_blocks_per_line * min_scanlines;
2982 selected_result = max(method2, y_tile_minimum);
2983 } else {
2984 if ((ddb_allocation / plane_blocks_per_line) >= 1)
2985 selected_result = min(method1, method2);
2986 else
2987 selected_result = method1;
2988 }
2989
2990 res_blocks = selected_result + 1;
2991 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
2992
2993 if (level >= 1 && level <= 7) {
2994 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2995 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
2996 res_lines += 4;
2997 else
2998 res_blocks++;
2999 }
3000
3001 if (res_blocks >= ddb_allocation || res_lines > 31)
3002 return false;
3003
3004 *out_blocks = res_blocks;
3005 *out_lines = res_lines;
3006
3007 return true;
3008 }
3009
3010 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3011 struct skl_ddb_allocation *ddb,
3012 struct skl_pipe_wm_parameters *p,
3013 enum pipe pipe,
3014 int level,
3015 int num_planes,
3016 struct skl_wm_level *result)
3017 {
3018 uint16_t ddb_blocks;
3019 int i;
3020
3021 for (i = 0; i < num_planes; i++) {
3022 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3023
3024 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3025 p, &p->plane[i],
3026 ddb_blocks,
3027 level,
3028 &result->plane_res_b[i],
3029 &result->plane_res_l[i]);
3030 }
3031
3032 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
3033 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3034 ddb_blocks, level,
3035 &result->cursor_res_b,
3036 &result->cursor_res_l);
3037 }
3038
3039 static uint32_t
3040 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3041 {
3042 if (!to_intel_crtc(crtc)->active)
3043 return 0;
3044
3045 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3046
3047 }
3048
3049 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3050 struct skl_pipe_wm_parameters *params,
3051 struct skl_wm_level *trans_wm /* out */)
3052 {
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3054 int i;
3055
3056 if (!params->active)
3057 return;
3058
3059 /* Until we know more, just disable transition WMs */
3060 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3061 trans_wm->plane_en[i] = false;
3062 trans_wm->cursor_en = false;
3063 }
3064
3065 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3066 struct skl_ddb_allocation *ddb,
3067 struct skl_pipe_wm_parameters *params,
3068 struct skl_pipe_wm *pipe_wm)
3069 {
3070 struct drm_device *dev = crtc->dev;
3071 const struct drm_i915_private *dev_priv = dev->dev_private;
3072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3073 int level, max_level = ilk_wm_max_level(dev);
3074
3075 for (level = 0; level <= max_level; level++) {
3076 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3077 level, intel_num_planes(intel_crtc),
3078 &pipe_wm->wm[level]);
3079 }
3080 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3081
3082 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3083 }
3084
3085 static void skl_compute_wm_results(struct drm_device *dev,
3086 struct skl_pipe_wm_parameters *p,
3087 struct skl_pipe_wm *p_wm,
3088 struct skl_wm_values *r,
3089 struct intel_crtc *intel_crtc)
3090 {
3091 int level, max_level = ilk_wm_max_level(dev);
3092 enum pipe pipe = intel_crtc->pipe;
3093 uint32_t temp;
3094 int i;
3095
3096 for (level = 0; level <= max_level; level++) {
3097 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3098 temp = 0;
3099
3100 temp |= p_wm->wm[level].plane_res_l[i] <<
3101 PLANE_WM_LINES_SHIFT;
3102 temp |= p_wm->wm[level].plane_res_b[i];
3103 if (p_wm->wm[level].plane_en[i])
3104 temp |= PLANE_WM_EN;
3105
3106 r->plane[pipe][i][level] = temp;
3107 }
3108
3109 temp = 0;
3110
3111 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3112 temp |= p_wm->wm[level].cursor_res_b;
3113
3114 if (p_wm->wm[level].cursor_en)
3115 temp |= PLANE_WM_EN;
3116
3117 r->cursor[pipe][level] = temp;
3118
3119 }
3120
3121 /* transition WMs */
3122 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3123 temp = 0;
3124 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3125 temp |= p_wm->trans_wm.plane_res_b[i];
3126 if (p_wm->trans_wm.plane_en[i])
3127 temp |= PLANE_WM_EN;
3128
3129 r->plane_trans[pipe][i] = temp;
3130 }
3131
3132 temp = 0;
3133 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3134 temp |= p_wm->trans_wm.cursor_res_b;
3135 if (p_wm->trans_wm.cursor_en)
3136 temp |= PLANE_WM_EN;
3137
3138 r->cursor_trans[pipe] = temp;
3139
3140 r->wm_linetime[pipe] = p_wm->linetime;
3141 }
3142
3143 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3144 const struct skl_ddb_entry *entry)
3145 {
3146 if (entry->end)
3147 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3148 else
3149 I915_WRITE(reg, 0);
3150 }
3151
3152 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3153 const struct skl_wm_values *new)
3154 {
3155 struct drm_device *dev = dev_priv->dev;
3156 struct intel_crtc *crtc;
3157
3158 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3159 int i, level, max_level = ilk_wm_max_level(dev);
3160 enum pipe pipe = crtc->pipe;
3161
3162 if (!new->dirty[pipe])
3163 continue;
3164
3165 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3166
3167 for (level = 0; level <= max_level; level++) {
3168 for (i = 0; i < intel_num_planes(crtc); i++)
3169 I915_WRITE(PLANE_WM(pipe, i, level),
3170 new->plane[pipe][i][level]);
3171 I915_WRITE(CUR_WM(pipe, level),
3172 new->cursor[pipe][level]);
3173 }
3174 for (i = 0; i < intel_num_planes(crtc); i++)
3175 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3176 new->plane_trans[pipe][i]);
3177 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3178
3179 for (i = 0; i < intel_num_planes(crtc); i++) {
3180 skl_ddb_entry_write(dev_priv,
3181 PLANE_BUF_CFG(pipe, i),
3182 &new->ddb.plane[pipe][i]);
3183 skl_ddb_entry_write(dev_priv,
3184 PLANE_NV12_BUF_CFG(pipe, i),
3185 &new->ddb.y_plane[pipe][i]);
3186 }
3187
3188 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3189 &new->ddb.cursor[pipe]);
3190 }
3191 }
3192
3193 /*
3194 * When setting up a new DDB allocation arrangement, we need to correctly
3195 * sequence the times at which the new allocations for the pipes are taken into
3196 * account or we'll have pipes fetching from space previously allocated to
3197 * another pipe.
3198 *
3199 * Roughly the sequence looks like:
3200 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3201 * overlapping with a previous light-up pipe (another way to put it is:
3202 * pipes with their new allocation strickly included into their old ones).
3203 * 2. re-allocate the other pipes that get their allocation reduced
3204 * 3. allocate the pipes having their allocation increased
3205 *
3206 * Steps 1. and 2. are here to take care of the following case:
3207 * - Initially DDB looks like this:
3208 * | B | C |
3209 * - enable pipe A.
3210 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3211 * allocation
3212 * | A | B | C |
3213 *
3214 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3215 */
3216
3217 static void
3218 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3219 {
3220 int plane;
3221
3222 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3223
3224 for_each_plane(dev_priv, pipe, plane) {
3225 I915_WRITE(PLANE_SURF(pipe, plane),
3226 I915_READ(PLANE_SURF(pipe, plane)));
3227 }
3228 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3229 }
3230
3231 static bool
3232 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3233 const struct skl_ddb_allocation *new,
3234 enum pipe pipe)
3235 {
3236 uint16_t old_size, new_size;
3237
3238 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3239 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3240
3241 return old_size != new_size &&
3242 new->pipe[pipe].start >= old->pipe[pipe].start &&
3243 new->pipe[pipe].end <= old->pipe[pipe].end;
3244 }
3245
3246 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3247 struct skl_wm_values *new_values)
3248 {
3249 struct drm_device *dev = dev_priv->dev;
3250 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3251 bool reallocated[I915_MAX_PIPES] = {};
3252 struct intel_crtc *crtc;
3253 enum pipe pipe;
3254
3255 new_ddb = &new_values->ddb;
3256 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3257
3258 /*
3259 * First pass: flush the pipes with the new allocation contained into
3260 * the old space.
3261 *
3262 * We'll wait for the vblank on those pipes to ensure we can safely
3263 * re-allocate the freed space without this pipe fetching from it.
3264 */
3265 for_each_intel_crtc(dev, crtc) {
3266 if (!crtc->active)
3267 continue;
3268
3269 pipe = crtc->pipe;
3270
3271 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3272 continue;
3273
3274 skl_wm_flush_pipe(dev_priv, pipe, 1);
3275 intel_wait_for_vblank(dev, pipe);
3276
3277 reallocated[pipe] = true;
3278 }
3279
3280
3281 /*
3282 * Second pass: flush the pipes that are having their allocation
3283 * reduced, but overlapping with a previous allocation.
3284 *
3285 * Here as well we need to wait for the vblank to make sure the freed
3286 * space is not used anymore.
3287 */
3288 for_each_intel_crtc(dev, crtc) {
3289 if (!crtc->active)
3290 continue;
3291
3292 pipe = crtc->pipe;
3293
3294 if (reallocated[pipe])
3295 continue;
3296
3297 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3298 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3299 skl_wm_flush_pipe(dev_priv, pipe, 2);
3300 intel_wait_for_vblank(dev, pipe);
3301 reallocated[pipe] = true;
3302 }
3303 }
3304
3305 /*
3306 * Third pass: flush the pipes that got more space allocated.
3307 *
3308 * We don't need to actively wait for the update here, next vblank
3309 * will just get more DDB space with the correct WM values.
3310 */
3311 for_each_intel_crtc(dev, crtc) {
3312 if (!crtc->active)
3313 continue;
3314
3315 pipe = crtc->pipe;
3316
3317 /*
3318 * At this point, only the pipes more space than before are
3319 * left to re-allocate.
3320 */
3321 if (reallocated[pipe])
3322 continue;
3323
3324 skl_wm_flush_pipe(dev_priv, pipe, 3);
3325 }
3326 }
3327
3328 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3329 struct skl_pipe_wm_parameters *params,
3330 struct intel_wm_config *config,
3331 struct skl_ddb_allocation *ddb, /* out */
3332 struct skl_pipe_wm *pipe_wm /* out */)
3333 {
3334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3335
3336 skl_compute_wm_pipe_parameters(crtc, params);
3337 skl_allocate_pipe_ddb(crtc, config, params, ddb);
3338 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3339
3340 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3341 return false;
3342
3343 intel_crtc->wm.skl_active = *pipe_wm;
3344
3345 return true;
3346 }
3347
3348 static void skl_update_other_pipe_wm(struct drm_device *dev,
3349 struct drm_crtc *crtc,
3350 struct intel_wm_config *config,
3351 struct skl_wm_values *r)
3352 {
3353 struct intel_crtc *intel_crtc;
3354 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3355
3356 /*
3357 * If the WM update hasn't changed the allocation for this_crtc (the
3358 * crtc we are currently computing the new WM values for), other
3359 * enabled crtcs will keep the same allocation and we don't need to
3360 * recompute anything for them.
3361 */
3362 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3363 return;
3364
3365 /*
3366 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3367 * other active pipes need new DDB allocation and WM values.
3368 */
3369 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3370 base.head) {
3371 struct skl_pipe_wm_parameters params = {};
3372 struct skl_pipe_wm pipe_wm = {};
3373 bool wm_changed;
3374
3375 if (this_crtc->pipe == intel_crtc->pipe)
3376 continue;
3377
3378 if (!intel_crtc->active)
3379 continue;
3380
3381 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3382 &params, config,
3383 &r->ddb, &pipe_wm);
3384
3385 /*
3386 * If we end up re-computing the other pipe WM values, it's
3387 * because it was really needed, so we expect the WM values to
3388 * be different.
3389 */
3390 WARN_ON(!wm_changed);
3391
3392 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3393 r->dirty[intel_crtc->pipe] = true;
3394 }
3395 }
3396
3397 static void skl_update_wm(struct drm_crtc *crtc)
3398 {
3399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3400 struct drm_device *dev = crtc->dev;
3401 struct drm_i915_private *dev_priv = dev->dev_private;
3402 struct skl_pipe_wm_parameters params = {};
3403 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3404 struct skl_pipe_wm pipe_wm = {};
3405 struct intel_wm_config config = {};
3406
3407 memset(results, 0, sizeof(*results));
3408
3409 skl_compute_wm_global_parameters(dev, &config);
3410
3411 if (!skl_update_pipe_wm(crtc, &params, &config,
3412 &results->ddb, &pipe_wm))
3413 return;
3414
3415 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3416 results->dirty[intel_crtc->pipe] = true;
3417
3418 skl_update_other_pipe_wm(dev, crtc, &config, results);
3419 skl_write_wm_values(dev_priv, results);
3420 skl_flush_wm_values(dev_priv, results);
3421
3422 /* store the new configuration */
3423 dev_priv->wm.skl_hw = *results;
3424 }
3425
3426 static void
3427 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3428 uint32_t sprite_width, uint32_t sprite_height,
3429 int pixel_size, bool enabled, bool scaled)
3430 {
3431 struct intel_plane *intel_plane = to_intel_plane(plane);
3432 struct drm_framebuffer *fb = plane->state->fb;
3433
3434 intel_plane->wm.enabled = enabled;
3435 intel_plane->wm.scaled = scaled;
3436 intel_plane->wm.horiz_pixels = sprite_width;
3437 intel_plane->wm.vert_pixels = sprite_height;
3438 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3439
3440 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3441 intel_plane->wm.bytes_per_pixel =
3442 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3443 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3444 intel_plane->wm.y_bytes_per_pixel =
3445 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3446 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3447
3448 /*
3449 * Framebuffer can be NULL on plane disable, but it does not
3450 * matter for watermarks if we assume no tiling in that case.
3451 */
3452 if (fb)
3453 intel_plane->wm.tiling = fb->modifier[0];
3454 intel_plane->wm.rotation = plane->state->rotation;
3455
3456 skl_update_wm(crtc);
3457 }
3458
3459 static void ilk_update_wm(struct drm_crtc *crtc)
3460 {
3461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3462 struct drm_device *dev = crtc->dev;
3463 struct drm_i915_private *dev_priv = dev->dev_private;
3464 struct ilk_wm_maximums max;
3465 struct ilk_pipe_wm_parameters params = {};
3466 struct ilk_wm_values results = {};
3467 enum intel_ddb_partitioning partitioning;
3468 struct intel_pipe_wm pipe_wm = {};
3469 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3470 struct intel_wm_config config = {};
3471
3472 ilk_compute_wm_parameters(crtc, &params);
3473
3474 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3475
3476 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3477 return;
3478
3479 intel_crtc->wm.active = pipe_wm;
3480
3481 ilk_compute_wm_config(dev, &config);
3482
3483 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3484 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3485
3486 /* 5/6 split only in single pipe config on IVB+ */
3487 if (INTEL_INFO(dev)->gen >= 7 &&
3488 config.num_pipes_active == 1 && config.sprites_enabled) {
3489 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3490 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3491
3492 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3493 } else {
3494 best_lp_wm = &lp_wm_1_2;
3495 }
3496
3497 partitioning = (best_lp_wm == &lp_wm_1_2) ?
3498 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3499
3500 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3501
3502 ilk_write_wm_values(dev_priv, &results);
3503 }
3504
3505 static void
3506 ilk_update_sprite_wm(struct drm_plane *plane,
3507 struct drm_crtc *crtc,
3508 uint32_t sprite_width, uint32_t sprite_height,
3509 int pixel_size, bool enabled, bool scaled)
3510 {
3511 struct drm_device *dev = plane->dev;
3512 struct intel_plane *intel_plane = to_intel_plane(plane);
3513
3514 intel_plane->wm.enabled = enabled;
3515 intel_plane->wm.scaled = scaled;
3516 intel_plane->wm.horiz_pixels = sprite_width;
3517 intel_plane->wm.vert_pixels = sprite_width;
3518 intel_plane->wm.bytes_per_pixel = pixel_size;
3519
3520 /*
3521 * IVB workaround: must disable low power watermarks for at least
3522 * one frame before enabling scaling. LP watermarks can be re-enabled
3523 * when scaling is disabled.
3524 *
3525 * WaCxSRDisabledForSpriteScaling:ivb
3526 */
3527 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3528 intel_wait_for_vblank(dev, intel_plane->pipe);
3529
3530 ilk_update_wm(crtc);
3531 }
3532
3533 static void skl_pipe_wm_active_state(uint32_t val,
3534 struct skl_pipe_wm *active,
3535 bool is_transwm,
3536 bool is_cursor,
3537 int i,
3538 int level)
3539 {
3540 bool is_enabled = (val & PLANE_WM_EN) != 0;
3541
3542 if (!is_transwm) {
3543 if (!is_cursor) {
3544 active->wm[level].plane_en[i] = is_enabled;
3545 active->wm[level].plane_res_b[i] =
3546 val & PLANE_WM_BLOCKS_MASK;
3547 active->wm[level].plane_res_l[i] =
3548 (val >> PLANE_WM_LINES_SHIFT) &
3549 PLANE_WM_LINES_MASK;
3550 } else {
3551 active->wm[level].cursor_en = is_enabled;
3552 active->wm[level].cursor_res_b =
3553 val & PLANE_WM_BLOCKS_MASK;
3554 active->wm[level].cursor_res_l =
3555 (val >> PLANE_WM_LINES_SHIFT) &
3556 PLANE_WM_LINES_MASK;
3557 }
3558 } else {
3559 if (!is_cursor) {
3560 active->trans_wm.plane_en[i] = is_enabled;
3561 active->trans_wm.plane_res_b[i] =
3562 val & PLANE_WM_BLOCKS_MASK;
3563 active->trans_wm.plane_res_l[i] =
3564 (val >> PLANE_WM_LINES_SHIFT) &
3565 PLANE_WM_LINES_MASK;
3566 } else {
3567 active->trans_wm.cursor_en = is_enabled;
3568 active->trans_wm.cursor_res_b =
3569 val & PLANE_WM_BLOCKS_MASK;
3570 active->trans_wm.cursor_res_l =
3571 (val >> PLANE_WM_LINES_SHIFT) &
3572 PLANE_WM_LINES_MASK;
3573 }
3574 }
3575 }
3576
3577 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3578 {
3579 struct drm_device *dev = crtc->dev;
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3583 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3584 enum pipe pipe = intel_crtc->pipe;
3585 int level, i, max_level;
3586 uint32_t temp;
3587
3588 max_level = ilk_wm_max_level(dev);
3589
3590 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3591
3592 for (level = 0; level <= max_level; level++) {
3593 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3594 hw->plane[pipe][i][level] =
3595 I915_READ(PLANE_WM(pipe, i, level));
3596 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3597 }
3598
3599 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3600 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3601 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3602
3603 if (!intel_crtc->active)
3604 return;
3605
3606 hw->dirty[pipe] = true;
3607
3608 active->linetime = hw->wm_linetime[pipe];
3609
3610 for (level = 0; level <= max_level; level++) {
3611 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3612 temp = hw->plane[pipe][i][level];
3613 skl_pipe_wm_active_state(temp, active, false,
3614 false, i, level);
3615 }
3616 temp = hw->cursor[pipe][level];
3617 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3618 }
3619
3620 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3621 temp = hw->plane_trans[pipe][i];
3622 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3623 }
3624
3625 temp = hw->cursor_trans[pipe];
3626 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3627 }
3628
3629 void skl_wm_get_hw_state(struct drm_device *dev)
3630 {
3631 struct drm_i915_private *dev_priv = dev->dev_private;
3632 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3633 struct drm_crtc *crtc;
3634
3635 skl_ddb_get_hw_state(dev_priv, ddb);
3636 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3637 skl_pipe_wm_get_hw_state(crtc);
3638 }
3639
3640 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3641 {
3642 struct drm_device *dev = crtc->dev;
3643 struct drm_i915_private *dev_priv = dev->dev_private;
3644 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3646 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3647 enum pipe pipe = intel_crtc->pipe;
3648 static const unsigned int wm0_pipe_reg[] = {
3649 [PIPE_A] = WM0_PIPEA_ILK,
3650 [PIPE_B] = WM0_PIPEB_ILK,
3651 [PIPE_C] = WM0_PIPEC_IVB,
3652 };
3653
3654 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3655 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3656 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3657
3658 active->pipe_enabled = intel_crtc->active;
3659
3660 if (active->pipe_enabled) {
3661 u32 tmp = hw->wm_pipe[pipe];
3662
3663 /*
3664 * For active pipes LP0 watermark is marked as
3665 * enabled, and LP1+ watermaks as disabled since
3666 * we can't really reverse compute them in case
3667 * multiple pipes are active.
3668 */
3669 active->wm[0].enable = true;
3670 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3671 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3672 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3673 active->linetime = hw->wm_linetime[pipe];
3674 } else {
3675 int level, max_level = ilk_wm_max_level(dev);
3676
3677 /*
3678 * For inactive pipes, all watermark levels
3679 * should be marked as enabled but zeroed,
3680 * which is what we'd compute them to.
3681 */
3682 for (level = 0; level <= max_level; level++)
3683 active->wm[level].enable = true;
3684 }
3685 }
3686
3687 void ilk_wm_get_hw_state(struct drm_device *dev)
3688 {
3689 struct drm_i915_private *dev_priv = dev->dev_private;
3690 struct ilk_wm_values *hw = &dev_priv->wm.hw;
3691 struct drm_crtc *crtc;
3692
3693 for_each_crtc(dev, crtc)
3694 ilk_pipe_wm_get_hw_state(crtc);
3695
3696 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3697 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3698 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3699
3700 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3701 if (INTEL_INFO(dev)->gen >= 7) {
3702 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3703 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3704 }
3705
3706 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3707 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3708 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3709 else if (IS_IVYBRIDGE(dev))
3710 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3711 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3712
3713 hw->enable_fbc_wm =
3714 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3715 }
3716
3717 /**
3718 * intel_update_watermarks - update FIFO watermark values based on current modes
3719 *
3720 * Calculate watermark values for the various WM regs based on current mode
3721 * and plane configuration.
3722 *
3723 * There are several cases to deal with here:
3724 * - normal (i.e. non-self-refresh)
3725 * - self-refresh (SR) mode
3726 * - lines are large relative to FIFO size (buffer can hold up to 2)
3727 * - lines are small relative to FIFO size (buffer can hold more than 2
3728 * lines), so need to account for TLB latency
3729 *
3730 * The normal calculation is:
3731 * watermark = dotclock * bytes per pixel * latency
3732 * where latency is platform & configuration dependent (we assume pessimal
3733 * values here).
3734 *
3735 * The SR calculation is:
3736 * watermark = (trunc(latency/line time)+1) * surface width *
3737 * bytes per pixel
3738 * where
3739 * line time = htotal / dotclock
3740 * surface width = hdisplay for normal plane and 64 for cursor
3741 * and latency is assumed to be high, as above.
3742 *
3743 * The final value programmed to the register should always be rounded up,
3744 * and include an extra 2 entries to account for clock crossings.
3745 *
3746 * We don't use the sprite, so we can ignore that. And on Crestline we have
3747 * to set the non-SR watermarks to 8.
3748 */
3749 void intel_update_watermarks(struct drm_crtc *crtc)
3750 {
3751 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3752
3753 if (dev_priv->display.update_wm)
3754 dev_priv->display.update_wm(crtc);
3755 }
3756
3757 void intel_update_sprite_watermarks(struct drm_plane *plane,
3758 struct drm_crtc *crtc,
3759 uint32_t sprite_width,
3760 uint32_t sprite_height,
3761 int pixel_size,
3762 bool enabled, bool scaled)
3763 {
3764 struct drm_i915_private *dev_priv = plane->dev->dev_private;
3765
3766 if (dev_priv->display.update_sprite_wm)
3767 dev_priv->display.update_sprite_wm(plane, crtc,
3768 sprite_width, sprite_height,
3769 pixel_size, enabled, scaled);
3770 }
3771
3772 /**
3773 * Lock protecting IPS related data structures
3774 */
3775 DEFINE_SPINLOCK(mchdev_lock);
3776
3777 /* Global for IPS driver to get at the current i915 device. Protected by
3778 * mchdev_lock. */
3779 static struct drm_i915_private *i915_mch_dev;
3780
3781 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3782 {
3783 struct drm_i915_private *dev_priv = dev->dev_private;
3784 u16 rgvswctl;
3785
3786 assert_spin_locked(&mchdev_lock);
3787
3788 rgvswctl = I915_READ16(MEMSWCTL);
3789 if (rgvswctl & MEMCTL_CMD_STS) {
3790 DRM_DEBUG("gpu busy, RCS change rejected\n");
3791 return false; /* still busy with another command */
3792 }
3793
3794 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3795 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3796 I915_WRITE16(MEMSWCTL, rgvswctl);
3797 POSTING_READ16(MEMSWCTL);
3798
3799 rgvswctl |= MEMCTL_CMD_STS;
3800 I915_WRITE16(MEMSWCTL, rgvswctl);
3801
3802 return true;
3803 }
3804
3805 static void ironlake_enable_drps(struct drm_device *dev)
3806 {
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3808 u32 rgvmodectl = I915_READ(MEMMODECTL);
3809 u8 fmax, fmin, fstart, vstart;
3810
3811 spin_lock_irq(&mchdev_lock);
3812
3813 /* Enable temp reporting */
3814 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3815 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3816
3817 /* 100ms RC evaluation intervals */
3818 I915_WRITE(RCUPEI, 100000);
3819 I915_WRITE(RCDNEI, 100000);
3820
3821 /* Set max/min thresholds to 90ms and 80ms respectively */
3822 I915_WRITE(RCBMAXAVG, 90000);
3823 I915_WRITE(RCBMINAVG, 80000);
3824
3825 I915_WRITE(MEMIHYST, 1);
3826
3827 /* Set up min, max, and cur for interrupt handling */
3828 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3829 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3830 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3831 MEMMODE_FSTART_SHIFT;
3832
3833 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3834 PXVFREQ_PX_SHIFT;
3835
3836 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3837 dev_priv->ips.fstart = fstart;
3838
3839 dev_priv->ips.max_delay = fstart;
3840 dev_priv->ips.min_delay = fmin;
3841 dev_priv->ips.cur_delay = fstart;
3842
3843 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3844 fmax, fmin, fstart);
3845
3846 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3847
3848 /*
3849 * Interrupts will be enabled in ironlake_irq_postinstall
3850 */
3851
3852 I915_WRITE(VIDSTART, vstart);
3853 POSTING_READ(VIDSTART);
3854
3855 rgvmodectl |= MEMMODE_SWMODE_EN;
3856 I915_WRITE(MEMMODECTL, rgvmodectl);
3857
3858 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3859 DRM_ERROR("stuck trying to change perf mode\n");
3860 mdelay(1);
3861
3862 ironlake_set_drps(dev, fstart);
3863
3864 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3865 I915_READ(0x112e0);
3866 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3867 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3868 dev_priv->ips.last_time2 = ktime_get_raw_ns();
3869
3870 spin_unlock_irq(&mchdev_lock);
3871 }
3872
3873 static void ironlake_disable_drps(struct drm_device *dev)
3874 {
3875 struct drm_i915_private *dev_priv = dev->dev_private;
3876 u16 rgvswctl;
3877
3878 spin_lock_irq(&mchdev_lock);
3879
3880 rgvswctl = I915_READ16(MEMSWCTL);
3881
3882 /* Ack interrupts, disable EFC interrupt */
3883 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3884 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3885 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3886 I915_WRITE(DEIIR, DE_PCU_EVENT);
3887 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3888
3889 /* Go back to the starting frequency */
3890 ironlake_set_drps(dev, dev_priv->ips.fstart);
3891 mdelay(1);
3892 rgvswctl |= MEMCTL_CMD_STS;
3893 I915_WRITE(MEMSWCTL, rgvswctl);
3894 mdelay(1);
3895
3896 spin_unlock_irq(&mchdev_lock);
3897 }
3898
3899 /* There's a funny hw issue where the hw returns all 0 when reading from
3900 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3901 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3902 * all limits and the gpu stuck at whatever frequency it is at atm).
3903 */
3904 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3905 {
3906 u32 limits;
3907
3908 /* Only set the down limit when we've reached the lowest level to avoid
3909 * getting more interrupts, otherwise leave this clear. This prevents a
3910 * race in the hw when coming out of rc6: There's a tiny window where
3911 * the hw runs at the minimal clock before selecting the desired
3912 * frequency, if the down threshold expires in that window we will not
3913 * receive a down interrupt. */
3914 if (IS_GEN9(dev_priv->dev)) {
3915 limits = (dev_priv->rps.max_freq_softlimit) << 23;
3916 if (val <= dev_priv->rps.min_freq_softlimit)
3917 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
3918 } else {
3919 limits = dev_priv->rps.max_freq_softlimit << 24;
3920 if (val <= dev_priv->rps.min_freq_softlimit)
3921 limits |= dev_priv->rps.min_freq_softlimit << 16;
3922 }
3923
3924 return limits;
3925 }
3926
3927 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3928 {
3929 int new_power;
3930 u32 threshold_up = 0, threshold_down = 0; /* in % */
3931 u32 ei_up = 0, ei_down = 0;
3932
3933 new_power = dev_priv->rps.power;
3934 switch (dev_priv->rps.power) {
3935 case LOW_POWER:
3936 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3937 new_power = BETWEEN;
3938 break;
3939
3940 case BETWEEN:
3941 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3942 new_power = LOW_POWER;
3943 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3944 new_power = HIGH_POWER;
3945 break;
3946
3947 case HIGH_POWER:
3948 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3949 new_power = BETWEEN;
3950 break;
3951 }
3952 /* Max/min bins are special */
3953 if (val <= dev_priv->rps.min_freq_softlimit)
3954 new_power = LOW_POWER;
3955 if (val >= dev_priv->rps.max_freq_softlimit)
3956 new_power = HIGH_POWER;
3957 if (new_power == dev_priv->rps.power)
3958 return;
3959
3960 /* Note the units here are not exactly 1us, but 1280ns. */
3961 switch (new_power) {
3962 case LOW_POWER:
3963 /* Upclock if more than 95% busy over 16ms */
3964 ei_up = 16000;
3965 threshold_up = 95;
3966
3967 /* Downclock if less than 85% busy over 32ms */
3968 ei_down = 32000;
3969 threshold_down = 85;
3970 break;
3971
3972 case BETWEEN:
3973 /* Upclock if more than 90% busy over 13ms */
3974 ei_up = 13000;
3975 threshold_up = 90;
3976
3977 /* Downclock if less than 75% busy over 32ms */
3978 ei_down = 32000;
3979 threshold_down = 75;
3980 break;
3981
3982 case HIGH_POWER:
3983 /* Upclock if more than 85% busy over 10ms */
3984 ei_up = 10000;
3985 threshold_up = 85;
3986
3987 /* Downclock if less than 60% busy over 32ms */
3988 ei_down = 32000;
3989 threshold_down = 60;
3990 break;
3991 }
3992
3993 I915_WRITE(GEN6_RP_UP_EI,
3994 GT_INTERVAL_FROM_US(dev_priv, ei_up));
3995 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3996 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
3997
3998 I915_WRITE(GEN6_RP_DOWN_EI,
3999 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4000 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4001 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4002
4003 I915_WRITE(GEN6_RP_CONTROL,
4004 GEN6_RP_MEDIA_TURBO |
4005 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4006 GEN6_RP_MEDIA_IS_GFX |
4007 GEN6_RP_ENABLE |
4008 GEN6_RP_UP_BUSY_AVG |
4009 GEN6_RP_DOWN_IDLE_AVG);
4010
4011 dev_priv->rps.power = new_power;
4012 dev_priv->rps.up_threshold = threshold_up;
4013 dev_priv->rps.down_threshold = threshold_down;
4014 dev_priv->rps.last_adj = 0;
4015 }
4016
4017 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4018 {
4019 u32 mask = 0;
4020
4021 if (val > dev_priv->rps.min_freq_softlimit)
4022 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4023 if (val < dev_priv->rps.max_freq_softlimit)
4024 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4025
4026 mask &= dev_priv->pm_rps_events;
4027
4028 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4029 }
4030
4031 /* gen6_set_rps is called to update the frequency request, but should also be
4032 * called when the range (min_delay and max_delay) is modified so that we can
4033 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4034 static void gen6_set_rps(struct drm_device *dev, u8 val)
4035 {
4036 struct drm_i915_private *dev_priv = dev->dev_private;
4037
4038 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4039 WARN_ON(val > dev_priv->rps.max_freq);
4040 WARN_ON(val < dev_priv->rps.min_freq);
4041
4042 /* min/max delay may still have been modified so be sure to
4043 * write the limits value.
4044 */
4045 if (val != dev_priv->rps.cur_freq) {
4046 gen6_set_rps_thresholds(dev_priv, val);
4047
4048 if (IS_GEN9(dev))
4049 I915_WRITE(GEN6_RPNSWREQ,
4050 GEN9_FREQUENCY(val));
4051 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4052 I915_WRITE(GEN6_RPNSWREQ,
4053 HSW_FREQUENCY(val));
4054 else
4055 I915_WRITE(GEN6_RPNSWREQ,
4056 GEN6_FREQUENCY(val) |
4057 GEN6_OFFSET(0) |
4058 GEN6_AGGRESSIVE_TURBO);
4059 }
4060
4061 /* Make sure we continue to get interrupts
4062 * until we hit the minimum or maximum frequencies.
4063 */
4064 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4065 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4066
4067 POSTING_READ(GEN6_RPNSWREQ);
4068
4069 dev_priv->rps.cur_freq = val;
4070 trace_intel_gpu_freq_change(val * 50);
4071 }
4072
4073 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4074 {
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076
4077 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4078 WARN_ON(val > dev_priv->rps.max_freq);
4079 WARN_ON(val < dev_priv->rps.min_freq);
4080
4081 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4082 "Odd GPU freq value\n"))
4083 val &= ~1;
4084
4085 if (val != dev_priv->rps.cur_freq) {
4086 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4087 if (!IS_CHERRYVIEW(dev_priv))
4088 gen6_set_rps_thresholds(dev_priv, val);
4089 }
4090
4091 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4092
4093 dev_priv->rps.cur_freq = val;
4094 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4095 }
4096
4097 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4098 *
4099 * * If Gfx is Idle, then
4100 * 1. Forcewake Media well.
4101 * 2. Request idle freq.
4102 * 3. Release Forcewake of Media well.
4103 */
4104 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4105 {
4106 u32 val = dev_priv->rps.idle_freq;
4107
4108 if (dev_priv->rps.cur_freq <= val)
4109 return;
4110
4111 /* Wake up the media well, as that takes a lot less
4112 * power than the Render well. */
4113 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4114 valleyview_set_rps(dev_priv->dev, val);
4115 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4116 }
4117
4118 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4119 {
4120 mutex_lock(&dev_priv->rps.hw_lock);
4121 if (dev_priv->rps.enabled) {
4122 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4123 gen6_rps_reset_ei(dev_priv);
4124 I915_WRITE(GEN6_PMINTRMSK,
4125 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4126 }
4127 mutex_unlock(&dev_priv->rps.hw_lock);
4128 }
4129
4130 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4131 {
4132 struct drm_device *dev = dev_priv->dev;
4133
4134 mutex_lock(&dev_priv->rps.hw_lock);
4135 if (dev_priv->rps.enabled) {
4136 if (IS_VALLEYVIEW(dev))
4137 vlv_set_rps_idle(dev_priv);
4138 else
4139 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4140 dev_priv->rps.last_adj = 0;
4141 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4142 }
4143 mutex_unlock(&dev_priv->rps.hw_lock);
4144
4145 spin_lock(&dev_priv->rps.client_lock);
4146 while (!list_empty(&dev_priv->rps.clients))
4147 list_del_init(dev_priv->rps.clients.next);
4148 spin_unlock(&dev_priv->rps.client_lock);
4149 }
4150
4151 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4152 struct intel_rps_client *rps,
4153 unsigned long submitted)
4154 {
4155 /* This is intentionally racy! We peek at the state here, then
4156 * validate inside the RPS worker.
4157 */
4158 if (!(dev_priv->mm.busy &&
4159 dev_priv->rps.enabled &&
4160 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4161 return;
4162
4163 /* Force a RPS boost (and don't count it against the client) if
4164 * the GPU is severely congested.
4165 */
4166 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4167 rps = NULL;
4168
4169 spin_lock(&dev_priv->rps.client_lock);
4170 if (rps == NULL || list_empty(&rps->link)) {
4171 spin_lock_irq(&dev_priv->irq_lock);
4172 if (dev_priv->rps.interrupts_enabled) {
4173 dev_priv->rps.client_boost = true;
4174 queue_work(dev_priv->wq, &dev_priv->rps.work);
4175 }
4176 spin_unlock_irq(&dev_priv->irq_lock);
4177
4178 if (rps != NULL) {
4179 list_add(&rps->link, &dev_priv->rps.clients);
4180 rps->boosts++;
4181 } else
4182 dev_priv->rps.boosts++;
4183 }
4184 spin_unlock(&dev_priv->rps.client_lock);
4185 }
4186
4187 void intel_set_rps(struct drm_device *dev, u8 val)
4188 {
4189 if (IS_VALLEYVIEW(dev))
4190 valleyview_set_rps(dev, val);
4191 else
4192 gen6_set_rps(dev, val);
4193 }
4194
4195 static void gen9_disable_rps(struct drm_device *dev)
4196 {
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4198
4199 I915_WRITE(GEN6_RC_CONTROL, 0);
4200 I915_WRITE(GEN9_PG_ENABLE, 0);
4201 }
4202
4203 static void gen6_disable_rps(struct drm_device *dev)
4204 {
4205 struct drm_i915_private *dev_priv = dev->dev_private;
4206
4207 I915_WRITE(GEN6_RC_CONTROL, 0);
4208 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4209 }
4210
4211 static void cherryview_disable_rps(struct drm_device *dev)
4212 {
4213 struct drm_i915_private *dev_priv = dev->dev_private;
4214
4215 I915_WRITE(GEN6_RC_CONTROL, 0);
4216 }
4217
4218 static void valleyview_disable_rps(struct drm_device *dev)
4219 {
4220 struct drm_i915_private *dev_priv = dev->dev_private;
4221
4222 /* we're doing forcewake before Disabling RC6,
4223 * This what the BIOS expects when going into suspend */
4224 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4225
4226 I915_WRITE(GEN6_RC_CONTROL, 0);
4227
4228 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4229 }
4230
4231 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4232 {
4233 if (IS_VALLEYVIEW(dev)) {
4234 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4235 mode = GEN6_RC_CTL_RC6_ENABLE;
4236 else
4237 mode = 0;
4238 }
4239 if (HAS_RC6p(dev))
4240 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4241 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4242 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4243 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4244
4245 else
4246 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4247 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4248 }
4249
4250 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4251 {
4252 /* No RC6 before Ironlake and code is gone for ilk. */
4253 if (INTEL_INFO(dev)->gen < 6)
4254 return 0;
4255
4256 /* Respect the kernel parameter if it is set */
4257 if (enable_rc6 >= 0) {
4258 int mask;
4259
4260 if (HAS_RC6p(dev))
4261 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4262 INTEL_RC6pp_ENABLE;
4263 else
4264 mask = INTEL_RC6_ENABLE;
4265
4266 if ((enable_rc6 & mask) != enable_rc6)
4267 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4268 enable_rc6 & mask, enable_rc6, mask);
4269
4270 return enable_rc6 & mask;
4271 }
4272
4273 if (IS_IVYBRIDGE(dev))
4274 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4275
4276 return INTEL_RC6_ENABLE;
4277 }
4278
4279 int intel_enable_rc6(const struct drm_device *dev)
4280 {
4281 return i915.enable_rc6;
4282 }
4283
4284 static void gen6_init_rps_frequencies(struct drm_device *dev)
4285 {
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4287 uint32_t rp_state_cap;
4288 u32 ddcc_status = 0;
4289 int ret;
4290
4291 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4292 /* All of these values are in units of 50MHz */
4293 dev_priv->rps.cur_freq = 0;
4294 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4295 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4296 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4297 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4298 if (IS_SKYLAKE(dev)) {
4299 /* Store the frequency values in 16.66 MHZ units, which is
4300 the natural hardware unit for SKL */
4301 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4302 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4303 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4304 }
4305 /* hw_max = RP0 until we check for overclocking */
4306 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4307
4308 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4309 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4310 ret = sandybridge_pcode_read(dev_priv,
4311 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4312 &ddcc_status);
4313 if (0 == ret)
4314 dev_priv->rps.efficient_freq =
4315 clamp_t(u8,
4316 ((ddcc_status >> 8) & 0xff),
4317 dev_priv->rps.min_freq,
4318 dev_priv->rps.max_freq);
4319 }
4320
4321 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4322
4323 /* Preserve min/max settings in case of re-init */
4324 if (dev_priv->rps.max_freq_softlimit == 0)
4325 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4326
4327 if (dev_priv->rps.min_freq_softlimit == 0) {
4328 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4329 dev_priv->rps.min_freq_softlimit =
4330 max_t(int, dev_priv->rps.efficient_freq,
4331 intel_freq_opcode(dev_priv, 450));
4332 else
4333 dev_priv->rps.min_freq_softlimit =
4334 dev_priv->rps.min_freq;
4335 }
4336 }
4337
4338 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4339 static void gen9_enable_rps(struct drm_device *dev)
4340 {
4341 struct drm_i915_private *dev_priv = dev->dev_private;
4342
4343 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4344
4345 gen6_init_rps_frequencies(dev);
4346
4347 /* Program defaults and thresholds for RPS*/
4348 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4349 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4350
4351 /* 1 second timeout*/
4352 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4353 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4354
4355 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4356
4357 /* Leaning on the below call to gen6_set_rps to program/setup the
4358 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4359 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4360 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4361 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4362
4363 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4364 }
4365
4366 static void gen9_enable_rc6(struct drm_device *dev)
4367 {
4368 struct drm_i915_private *dev_priv = dev->dev_private;
4369 struct intel_engine_cs *ring;
4370 uint32_t rc6_mask = 0;
4371 int unused;
4372
4373 /* 1a: Software RC state - RC0 */
4374 I915_WRITE(GEN6_RC_STATE, 0);
4375
4376 /* 1b: Get forcewake during program sequence. Although the driver
4377 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4378 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4379
4380 /* 2a: Disable RC states. */
4381 I915_WRITE(GEN6_RC_CONTROL, 0);
4382
4383 /* 2b: Program RC6 thresholds.*/
4384 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4385 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4386 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4387 for_each_ring(ring, dev_priv, unused)
4388 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4389 I915_WRITE(GEN6_RC_SLEEP, 0);
4390 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4391
4392 /* 2c: Program Coarse Power Gating Policies. */
4393 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4394 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4395
4396 /* 3a: Enable RC6 */
4397 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4398 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4399 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4400 "on" : "off");
4401 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4402 GEN6_RC_CTL_EI_MODE(1) |
4403 rc6_mask);
4404
4405 /*
4406 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4407 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4408 */
4409 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4410 GEN9_MEDIA_PG_ENABLE : 0);
4411
4412
4413 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4414
4415 }
4416
4417 static void gen8_enable_rps(struct drm_device *dev)
4418 {
4419 struct drm_i915_private *dev_priv = dev->dev_private;
4420 struct intel_engine_cs *ring;
4421 uint32_t rc6_mask = 0;
4422 int unused;
4423
4424 /* 1a: Software RC state - RC0 */
4425 I915_WRITE(GEN6_RC_STATE, 0);
4426
4427 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4428 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4429 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4430
4431 /* 2a: Disable RC states. */
4432 I915_WRITE(GEN6_RC_CONTROL, 0);
4433
4434 /* Initialize rps frequencies */
4435 gen6_init_rps_frequencies(dev);
4436
4437 /* 2b: Program RC6 thresholds.*/
4438 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4439 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4440 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4441 for_each_ring(ring, dev_priv, unused)
4442 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4443 I915_WRITE(GEN6_RC_SLEEP, 0);
4444 if (IS_BROADWELL(dev))
4445 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4446 else
4447 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4448
4449 /* 3: Enable RC6 */
4450 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4451 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4452 intel_print_rc6_info(dev, rc6_mask);
4453 if (IS_BROADWELL(dev))
4454 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4455 GEN7_RC_CTL_TO_MODE |
4456 rc6_mask);
4457 else
4458 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4459 GEN6_RC_CTL_EI_MODE(1) |
4460 rc6_mask);
4461
4462 /* 4 Program defaults and thresholds for RPS*/
4463 I915_WRITE(GEN6_RPNSWREQ,
4464 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4465 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4466 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4467 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4468 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4469
4470 /* Docs recommend 900MHz, and 300 MHz respectively */
4471 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4472 dev_priv->rps.max_freq_softlimit << 24 |
4473 dev_priv->rps.min_freq_softlimit << 16);
4474
4475 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4476 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4477 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4478 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4479
4480 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4481
4482 /* 5: Enable RPS */
4483 I915_WRITE(GEN6_RP_CONTROL,
4484 GEN6_RP_MEDIA_TURBO |
4485 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4486 GEN6_RP_MEDIA_IS_GFX |
4487 GEN6_RP_ENABLE |
4488 GEN6_RP_UP_BUSY_AVG |
4489 GEN6_RP_DOWN_IDLE_AVG);
4490
4491 /* 6: Ring frequency + overclocking (our driver does this later */
4492
4493 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4494 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4495
4496 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4497 }
4498
4499 static void gen6_enable_rps(struct drm_device *dev)
4500 {
4501 struct drm_i915_private *dev_priv = dev->dev_private;
4502 struct intel_engine_cs *ring;
4503 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4504 u32 gtfifodbg;
4505 int rc6_mode;
4506 int i, ret;
4507
4508 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4509
4510 /* Here begins a magic sequence of register writes to enable
4511 * auto-downclocking.
4512 *
4513 * Perhaps there might be some value in exposing these to
4514 * userspace...
4515 */
4516 I915_WRITE(GEN6_RC_STATE, 0);
4517
4518 /* Clear the DBG now so we don't confuse earlier errors */
4519 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4520 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4521 I915_WRITE(GTFIFODBG, gtfifodbg);
4522 }
4523
4524 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4525
4526 /* Initialize rps frequencies */
4527 gen6_init_rps_frequencies(dev);
4528
4529 /* disable the counters and set deterministic thresholds */
4530 I915_WRITE(GEN6_RC_CONTROL, 0);
4531
4532 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4533 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4534 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4535 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4536 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4537
4538 for_each_ring(ring, dev_priv, i)
4539 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4540
4541 I915_WRITE(GEN6_RC_SLEEP, 0);
4542 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4543 if (IS_IVYBRIDGE(dev))
4544 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4545 else
4546 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4547 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4548 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4549
4550 /* Check if we are enabling RC6 */
4551 rc6_mode = intel_enable_rc6(dev_priv->dev);
4552 if (rc6_mode & INTEL_RC6_ENABLE)
4553 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4554
4555 /* We don't use those on Haswell */
4556 if (!IS_HASWELL(dev)) {
4557 if (rc6_mode & INTEL_RC6p_ENABLE)
4558 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4559
4560 if (rc6_mode & INTEL_RC6pp_ENABLE)
4561 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4562 }
4563
4564 intel_print_rc6_info(dev, rc6_mask);
4565
4566 I915_WRITE(GEN6_RC_CONTROL,
4567 rc6_mask |
4568 GEN6_RC_CTL_EI_MODE(1) |
4569 GEN6_RC_CTL_HW_ENABLE);
4570
4571 /* Power down if completely idle for over 50ms */
4572 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4573 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4574
4575 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4576 if (ret)
4577 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4578
4579 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4580 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4581 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4582 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4583 (pcu_mbox & 0xff) * 50);
4584 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4585 }
4586
4587 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4588 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4589
4590 rc6vids = 0;
4591 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4592 if (IS_GEN6(dev) && ret) {
4593 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4594 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4595 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4596 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4597 rc6vids &= 0xffff00;
4598 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4599 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4600 if (ret)
4601 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4602 }
4603
4604 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4605 }
4606
4607 static void __gen6_update_ring_freq(struct drm_device *dev)
4608 {
4609 struct drm_i915_private *dev_priv = dev->dev_private;
4610 int min_freq = 15;
4611 unsigned int gpu_freq;
4612 unsigned int max_ia_freq, min_ring_freq;
4613 int scaling_factor = 180;
4614 struct cpufreq_policy *policy;
4615
4616 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4617
4618 policy = cpufreq_cpu_get(0);
4619 if (policy) {
4620 max_ia_freq = policy->cpuinfo.max_freq;
4621 cpufreq_cpu_put(policy);
4622 } else {
4623 /*
4624 * Default to measured freq if none found, PCU will ensure we
4625 * don't go over
4626 */
4627 max_ia_freq = tsc_khz;
4628 }
4629
4630 /* Convert from kHz to MHz */
4631 max_ia_freq /= 1000;
4632
4633 min_ring_freq = I915_READ(DCLK) & 0xf;
4634 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4635 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4636
4637 /*
4638 * For each potential GPU frequency, load a ring frequency we'd like
4639 * to use for memory access. We do this by specifying the IA frequency
4640 * the PCU should use as a reference to determine the ring frequency.
4641 */
4642 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
4643 gpu_freq--) {
4644 int diff = dev_priv->rps.max_freq - gpu_freq;
4645 unsigned int ia_freq = 0, ring_freq = 0;
4646
4647 if (INTEL_INFO(dev)->gen >= 8) {
4648 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4649 ring_freq = max(min_ring_freq, gpu_freq);
4650 } else if (IS_HASWELL(dev)) {
4651 ring_freq = mult_frac(gpu_freq, 5, 4);
4652 ring_freq = max(min_ring_freq, ring_freq);
4653 /* leave ia_freq as the default, chosen by cpufreq */
4654 } else {
4655 /* On older processors, there is no separate ring
4656 * clock domain, so in order to boost the bandwidth
4657 * of the ring, we need to upclock the CPU (ia_freq).
4658 *
4659 * For GPU frequencies less than 750MHz,
4660 * just use the lowest ring freq.
4661 */
4662 if (gpu_freq < min_freq)
4663 ia_freq = 800;
4664 else
4665 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4666 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4667 }
4668
4669 sandybridge_pcode_write(dev_priv,
4670 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4671 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4672 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4673 gpu_freq);
4674 }
4675 }
4676
4677 void gen6_update_ring_freq(struct drm_device *dev)
4678 {
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4680
4681 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4682 return;
4683
4684 mutex_lock(&dev_priv->rps.hw_lock);
4685 __gen6_update_ring_freq(dev);
4686 mutex_unlock(&dev_priv->rps.hw_lock);
4687 }
4688
4689 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
4690 {
4691 struct drm_device *dev = dev_priv->dev;
4692 u32 val, rp0;
4693
4694 if (dev->pdev->revision >= 0x20) {
4695 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4696
4697 switch (INTEL_INFO(dev)->eu_total) {
4698 case 8:
4699 /* (2 * 4) config */
4700 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4701 break;
4702 case 12:
4703 /* (2 * 6) config */
4704 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4705 break;
4706 case 16:
4707 /* (2 * 8) config */
4708 default:
4709 /* Setting (2 * 8) Min RP0 for any other combination */
4710 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4711 break;
4712 }
4713 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4714 } else {
4715 /* For pre-production hardware */
4716 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4717 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4718 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4719 }
4720 return rp0;
4721 }
4722
4723 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4724 {
4725 u32 val, rpe;
4726
4727 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4728 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4729
4730 return rpe;
4731 }
4732
4733 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4734 {
4735 struct drm_device *dev = dev_priv->dev;
4736 u32 val, rp1;
4737
4738 if (dev->pdev->revision >= 0x20) {
4739 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4740 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4741 } else {
4742 /* For pre-production hardware */
4743 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4744 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4745 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4746 }
4747 return rp1;
4748 }
4749
4750 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4751 {
4752 u32 val, rp1;
4753
4754 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4755
4756 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4757
4758 return rp1;
4759 }
4760
4761 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4762 {
4763 u32 val, rp0;
4764
4765 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4766
4767 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4768 /* Clamp to max */
4769 rp0 = min_t(u32, rp0, 0xea);
4770
4771 return rp0;
4772 }
4773
4774 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4775 {
4776 u32 val, rpe;
4777
4778 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4779 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4780 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4781 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4782
4783 return rpe;
4784 }
4785
4786 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4787 {
4788 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4789 }
4790
4791 /* Check that the pctx buffer wasn't move under us. */
4792 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4793 {
4794 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4795
4796 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4797 dev_priv->vlv_pctx->stolen->start);
4798 }
4799
4800
4801 /* Check that the pcbr address is not empty. */
4802 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4803 {
4804 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4805
4806 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4807 }
4808
4809 static void cherryview_setup_pctx(struct drm_device *dev)
4810 {
4811 struct drm_i915_private *dev_priv = dev->dev_private;
4812 unsigned long pctx_paddr, paddr;
4813 struct i915_gtt *gtt = &dev_priv->gtt;
4814 u32 pcbr;
4815 int pctx_size = 32*1024;
4816
4817 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4818
4819 pcbr = I915_READ(VLV_PCBR);
4820 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4821 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4822 paddr = (dev_priv->mm.stolen_base +
4823 (gtt->stolen_size - pctx_size));
4824
4825 pctx_paddr = (paddr & (~4095));
4826 I915_WRITE(VLV_PCBR, pctx_paddr);
4827 }
4828
4829 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
4830 }
4831
4832 static void valleyview_setup_pctx(struct drm_device *dev)
4833 {
4834 struct drm_i915_private *dev_priv = dev->dev_private;
4835 struct drm_i915_gem_object *pctx;
4836 unsigned long pctx_paddr;
4837 u32 pcbr;
4838 int pctx_size = 24*1024;
4839
4840 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4841
4842 pcbr = I915_READ(VLV_PCBR);
4843 if (pcbr) {
4844 /* BIOS set it up already, grab the pre-alloc'd space */
4845 int pcbr_offset;
4846
4847 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4848 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4849 pcbr_offset,
4850 I915_GTT_OFFSET_NONE,
4851 pctx_size);
4852 goto out;
4853 }
4854
4855 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4856
4857 /*
4858 * From the Gunit register HAS:
4859 * The Gfx driver is expected to program this register and ensure
4860 * proper allocation within Gfx stolen memory. For example, this
4861 * register should be programmed such than the PCBR range does not
4862 * overlap with other ranges, such as the frame buffer, protected
4863 * memory, or any other relevant ranges.
4864 */
4865 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4866 if (!pctx) {
4867 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4868 return;
4869 }
4870
4871 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4872 I915_WRITE(VLV_PCBR, pctx_paddr);
4873
4874 out:
4875 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
4876 dev_priv->vlv_pctx = pctx;
4877 }
4878
4879 static void valleyview_cleanup_pctx(struct drm_device *dev)
4880 {
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4882
4883 if (WARN_ON(!dev_priv->vlv_pctx))
4884 return;
4885
4886 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4887 dev_priv->vlv_pctx = NULL;
4888 }
4889
4890 static void valleyview_init_gt_powersave(struct drm_device *dev)
4891 {
4892 struct drm_i915_private *dev_priv = dev->dev_private;
4893 u32 val;
4894
4895 valleyview_setup_pctx(dev);
4896
4897 mutex_lock(&dev_priv->rps.hw_lock);
4898
4899 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4900 switch ((val >> 6) & 3) {
4901 case 0:
4902 case 1:
4903 dev_priv->mem_freq = 800;
4904 break;
4905 case 2:
4906 dev_priv->mem_freq = 1066;
4907 break;
4908 case 3:
4909 dev_priv->mem_freq = 1333;
4910 break;
4911 }
4912 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
4913
4914 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4915 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4916 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4917 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4918 dev_priv->rps.max_freq);
4919
4920 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4921 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4922 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4923 dev_priv->rps.efficient_freq);
4924
4925 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4926 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4927 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4928 dev_priv->rps.rp1_freq);
4929
4930 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4931 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4932 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4933 dev_priv->rps.min_freq);
4934
4935 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4936
4937 /* Preserve min/max settings in case of re-init */
4938 if (dev_priv->rps.max_freq_softlimit == 0)
4939 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4940
4941 if (dev_priv->rps.min_freq_softlimit == 0)
4942 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4943
4944 mutex_unlock(&dev_priv->rps.hw_lock);
4945 }
4946
4947 static void cherryview_init_gt_powersave(struct drm_device *dev)
4948 {
4949 struct drm_i915_private *dev_priv = dev->dev_private;
4950 u32 val;
4951
4952 cherryview_setup_pctx(dev);
4953
4954 mutex_lock(&dev_priv->rps.hw_lock);
4955
4956 mutex_lock(&dev_priv->sb_lock);
4957 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4958 mutex_unlock(&dev_priv->sb_lock);
4959
4960 switch ((val >> 2) & 0x7) {
4961 case 0:
4962 case 1:
4963 dev_priv->rps.cz_freq = 200;
4964 dev_priv->mem_freq = 1600;
4965 break;
4966 case 2:
4967 dev_priv->rps.cz_freq = 267;
4968 dev_priv->mem_freq = 1600;
4969 break;
4970 case 3:
4971 dev_priv->rps.cz_freq = 333;
4972 dev_priv->mem_freq = 2000;
4973 break;
4974 case 4:
4975 dev_priv->rps.cz_freq = 320;
4976 dev_priv->mem_freq = 1600;
4977 break;
4978 case 5:
4979 dev_priv->rps.cz_freq = 400;
4980 dev_priv->mem_freq = 1600;
4981 break;
4982 }
4983 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
4984
4985 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4986 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4987 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4988 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4989 dev_priv->rps.max_freq);
4990
4991 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4992 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4993 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4994 dev_priv->rps.efficient_freq);
4995
4996 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4997 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4998 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4999 dev_priv->rps.rp1_freq);
5000
5001 /* PUnit validated range is only [RPe, RP0] */
5002 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5003 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5004 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5005 dev_priv->rps.min_freq);
5006
5007 WARN_ONCE((dev_priv->rps.max_freq |
5008 dev_priv->rps.efficient_freq |
5009 dev_priv->rps.rp1_freq |
5010 dev_priv->rps.min_freq) & 1,
5011 "Odd GPU freq values\n");
5012
5013 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5014
5015 /* Preserve min/max settings in case of re-init */
5016 if (dev_priv->rps.max_freq_softlimit == 0)
5017 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5018
5019 if (dev_priv->rps.min_freq_softlimit == 0)
5020 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5021
5022 mutex_unlock(&dev_priv->rps.hw_lock);
5023 }
5024
5025 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5026 {
5027 valleyview_cleanup_pctx(dev);
5028 }
5029
5030 static void cherryview_enable_rps(struct drm_device *dev)
5031 {
5032 struct drm_i915_private *dev_priv = dev->dev_private;
5033 struct intel_engine_cs *ring;
5034 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5035 int i;
5036
5037 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5038
5039 gtfifodbg = I915_READ(GTFIFODBG);
5040 if (gtfifodbg) {
5041 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5042 gtfifodbg);
5043 I915_WRITE(GTFIFODBG, gtfifodbg);
5044 }
5045
5046 cherryview_check_pctx(dev_priv);
5047
5048 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5049 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5050 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5051
5052 /* Disable RC states. */
5053 I915_WRITE(GEN6_RC_CONTROL, 0);
5054
5055 /* 2a: Program RC6 thresholds.*/
5056 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5057 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5058 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5059
5060 for_each_ring(ring, dev_priv, i)
5061 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5062 I915_WRITE(GEN6_RC_SLEEP, 0);
5063
5064 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5065 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5066
5067 /* allows RC6 residency counter to work */
5068 I915_WRITE(VLV_COUNTER_CONTROL,
5069 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5070 VLV_MEDIA_RC6_COUNT_EN |
5071 VLV_RENDER_RC6_COUNT_EN));
5072
5073 /* For now we assume BIOS is allocating and populating the PCBR */
5074 pcbr = I915_READ(VLV_PCBR);
5075
5076 /* 3: Enable RC6 */
5077 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5078 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5079 rc6_mode = GEN7_RC_CTL_TO_MODE;
5080
5081 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5082
5083 /* 4 Program defaults and thresholds for RPS*/
5084 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5085 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5086 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5087 I915_WRITE(GEN6_RP_UP_EI, 66000);
5088 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5089
5090 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5091
5092 /* 5: Enable RPS */
5093 I915_WRITE(GEN6_RP_CONTROL,
5094 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5095 GEN6_RP_MEDIA_IS_GFX |
5096 GEN6_RP_ENABLE |
5097 GEN6_RP_UP_BUSY_AVG |
5098 GEN6_RP_DOWN_IDLE_AVG);
5099
5100 /* Setting Fixed Bias */
5101 val = VLV_OVERRIDE_EN |
5102 VLV_SOC_TDP_EN |
5103 CHV_BIAS_CPU_50_SOC_50;
5104 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5105
5106 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5107
5108 /* RPS code assumes GPLL is used */
5109 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5110
5111 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
5112 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5113
5114 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5115 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5116 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5117 dev_priv->rps.cur_freq);
5118
5119 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5120 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5121 dev_priv->rps.efficient_freq);
5122
5123 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5124
5125 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5126 }
5127
5128 static void valleyview_enable_rps(struct drm_device *dev)
5129 {
5130 struct drm_i915_private *dev_priv = dev->dev_private;
5131 struct intel_engine_cs *ring;
5132 u32 gtfifodbg, val, rc6_mode = 0;
5133 int i;
5134
5135 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5136
5137 valleyview_check_pctx(dev_priv);
5138
5139 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5140 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5141 gtfifodbg);
5142 I915_WRITE(GTFIFODBG, gtfifodbg);
5143 }
5144
5145 /* If VLV, Forcewake all wells, else re-direct to regular path */
5146 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5147
5148 /* Disable RC states. */
5149 I915_WRITE(GEN6_RC_CONTROL, 0);
5150
5151 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5152 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5153 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5154 I915_WRITE(GEN6_RP_UP_EI, 66000);
5155 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5156
5157 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5158
5159 I915_WRITE(GEN6_RP_CONTROL,
5160 GEN6_RP_MEDIA_TURBO |
5161 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5162 GEN6_RP_MEDIA_IS_GFX |
5163 GEN6_RP_ENABLE |
5164 GEN6_RP_UP_BUSY_AVG |
5165 GEN6_RP_DOWN_IDLE_CONT);
5166
5167 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5168 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5169 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5170
5171 for_each_ring(ring, dev_priv, i)
5172 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5173
5174 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5175
5176 /* allows RC6 residency counter to work */
5177 I915_WRITE(VLV_COUNTER_CONTROL,
5178 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5179 VLV_RENDER_RC0_COUNT_EN |
5180 VLV_MEDIA_RC6_COUNT_EN |
5181 VLV_RENDER_RC6_COUNT_EN));
5182
5183 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5184 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5185
5186 intel_print_rc6_info(dev, rc6_mode);
5187
5188 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5189
5190 /* Setting Fixed Bias */
5191 val = VLV_OVERRIDE_EN |
5192 VLV_SOC_TDP_EN |
5193 VLV_BIAS_CPU_125_SOC_875;
5194 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5195
5196 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5197
5198 /* RPS code assumes GPLL is used */
5199 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5200
5201 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
5202 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5203
5204 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5205 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5206 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5207 dev_priv->rps.cur_freq);
5208
5209 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5210 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5211 dev_priv->rps.efficient_freq);
5212
5213 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5214
5215 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5216 }
5217
5218 static unsigned long intel_pxfreq(u32 vidfreq)
5219 {
5220 unsigned long freq;
5221 int div = (vidfreq & 0x3f0000) >> 16;
5222 int post = (vidfreq & 0x3000) >> 12;
5223 int pre = (vidfreq & 0x7);
5224
5225 if (!pre)
5226 return 0;
5227
5228 freq = ((div * 133333) / ((1<<post) * pre));
5229
5230 return freq;
5231 }
5232
5233 static const struct cparams {
5234 u16 i;
5235 u16 t;
5236 u16 m;
5237 u16 c;
5238 } cparams[] = {
5239 { 1, 1333, 301, 28664 },
5240 { 1, 1066, 294, 24460 },
5241 { 1, 800, 294, 25192 },
5242 { 0, 1333, 276, 27605 },
5243 { 0, 1066, 276, 27605 },
5244 { 0, 800, 231, 23784 },
5245 };
5246
5247 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5248 {
5249 u64 total_count, diff, ret;
5250 u32 count1, count2, count3, m = 0, c = 0;
5251 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5252 int i;
5253
5254 assert_spin_locked(&mchdev_lock);
5255
5256 diff1 = now - dev_priv->ips.last_time1;
5257
5258 /* Prevent division-by-zero if we are asking too fast.
5259 * Also, we don't get interesting results if we are polling
5260 * faster than once in 10ms, so just return the saved value
5261 * in such cases.
5262 */
5263 if (diff1 <= 10)
5264 return dev_priv->ips.chipset_power;
5265
5266 count1 = I915_READ(DMIEC);
5267 count2 = I915_READ(DDREC);
5268 count3 = I915_READ(CSIEC);
5269
5270 total_count = count1 + count2 + count3;
5271
5272 /* FIXME: handle per-counter overflow */
5273 if (total_count < dev_priv->ips.last_count1) {
5274 diff = ~0UL - dev_priv->ips.last_count1;
5275 diff += total_count;
5276 } else {
5277 diff = total_count - dev_priv->ips.last_count1;
5278 }
5279
5280 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5281 if (cparams[i].i == dev_priv->ips.c_m &&
5282 cparams[i].t == dev_priv->ips.r_t) {
5283 m = cparams[i].m;
5284 c = cparams[i].c;
5285 break;
5286 }
5287 }
5288
5289 diff = div_u64(diff, diff1);
5290 ret = ((m * diff) + c);
5291 ret = div_u64(ret, 10);
5292
5293 dev_priv->ips.last_count1 = total_count;
5294 dev_priv->ips.last_time1 = now;
5295
5296 dev_priv->ips.chipset_power = ret;
5297
5298 return ret;
5299 }
5300
5301 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5302 {
5303 struct drm_device *dev = dev_priv->dev;
5304 unsigned long val;
5305
5306 if (INTEL_INFO(dev)->gen != 5)
5307 return 0;
5308
5309 spin_lock_irq(&mchdev_lock);
5310
5311 val = __i915_chipset_val(dev_priv);
5312
5313 spin_unlock_irq(&mchdev_lock);
5314
5315 return val;
5316 }
5317
5318 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5319 {
5320 unsigned long m, x, b;
5321 u32 tsfs;
5322
5323 tsfs = I915_READ(TSFS);
5324
5325 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5326 x = I915_READ8(TR1);
5327
5328 b = tsfs & TSFS_INTR_MASK;
5329
5330 return ((m * x) / 127) - b;
5331 }
5332
5333 static int _pxvid_to_vd(u8 pxvid)
5334 {
5335 if (pxvid == 0)
5336 return 0;
5337
5338 if (pxvid >= 8 && pxvid < 31)
5339 pxvid = 31;
5340
5341 return (pxvid + 2) * 125;
5342 }
5343
5344 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5345 {
5346 struct drm_device *dev = dev_priv->dev;
5347 const int vd = _pxvid_to_vd(pxvid);
5348 const int vm = vd - 1125;
5349
5350 if (INTEL_INFO(dev)->is_mobile)
5351 return vm > 0 ? vm : 0;
5352
5353 return vd;
5354 }
5355
5356 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5357 {
5358 u64 now, diff, diffms;
5359 u32 count;
5360
5361 assert_spin_locked(&mchdev_lock);
5362
5363 now = ktime_get_raw_ns();
5364 diffms = now - dev_priv->ips.last_time2;
5365 do_div(diffms, NSEC_PER_MSEC);
5366
5367 /* Don't divide by 0 */
5368 if (!diffms)
5369 return;
5370
5371 count = I915_READ(GFXEC);
5372
5373 if (count < dev_priv->ips.last_count2) {
5374 diff = ~0UL - dev_priv->ips.last_count2;
5375 diff += count;
5376 } else {
5377 diff = count - dev_priv->ips.last_count2;
5378 }
5379
5380 dev_priv->ips.last_count2 = count;
5381 dev_priv->ips.last_time2 = now;
5382
5383 /* More magic constants... */
5384 diff = diff * 1181;
5385 diff = div_u64(diff, diffms * 10);
5386 dev_priv->ips.gfx_power = diff;
5387 }
5388
5389 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5390 {
5391 struct drm_device *dev = dev_priv->dev;
5392
5393 if (INTEL_INFO(dev)->gen != 5)
5394 return;
5395
5396 spin_lock_irq(&mchdev_lock);
5397
5398 __i915_update_gfx_val(dev_priv);
5399
5400 spin_unlock_irq(&mchdev_lock);
5401 }
5402
5403 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5404 {
5405 unsigned long t, corr, state1, corr2, state2;
5406 u32 pxvid, ext_v;
5407
5408 assert_spin_locked(&mchdev_lock);
5409
5410 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5411 pxvid = (pxvid >> 24) & 0x7f;
5412 ext_v = pvid_to_extvid(dev_priv, pxvid);
5413
5414 state1 = ext_v;
5415
5416 t = i915_mch_val(dev_priv);
5417
5418 /* Revel in the empirically derived constants */
5419
5420 /* Correction factor in 1/100000 units */
5421 if (t > 80)
5422 corr = ((t * 2349) + 135940);
5423 else if (t >= 50)
5424 corr = ((t * 964) + 29317);
5425 else /* < 50 */
5426 corr = ((t * 301) + 1004);
5427
5428 corr = corr * ((150142 * state1) / 10000 - 78642);
5429 corr /= 100000;
5430 corr2 = (corr * dev_priv->ips.corr);
5431
5432 state2 = (corr2 * state1) / 10000;
5433 state2 /= 100; /* convert to mW */
5434
5435 __i915_update_gfx_val(dev_priv);
5436
5437 return dev_priv->ips.gfx_power + state2;
5438 }
5439
5440 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5441 {
5442 struct drm_device *dev = dev_priv->dev;
5443 unsigned long val;
5444
5445 if (INTEL_INFO(dev)->gen != 5)
5446 return 0;
5447
5448 spin_lock_irq(&mchdev_lock);
5449
5450 val = __i915_gfx_val(dev_priv);
5451
5452 spin_unlock_irq(&mchdev_lock);
5453
5454 return val;
5455 }
5456
5457 /**
5458 * i915_read_mch_val - return value for IPS use
5459 *
5460 * Calculate and return a value for the IPS driver to use when deciding whether
5461 * we have thermal and power headroom to increase CPU or GPU power budget.
5462 */
5463 unsigned long i915_read_mch_val(void)
5464 {
5465 struct drm_i915_private *dev_priv;
5466 unsigned long chipset_val, graphics_val, ret = 0;
5467
5468 spin_lock_irq(&mchdev_lock);
5469 if (!i915_mch_dev)
5470 goto out_unlock;
5471 dev_priv = i915_mch_dev;
5472
5473 chipset_val = __i915_chipset_val(dev_priv);
5474 graphics_val = __i915_gfx_val(dev_priv);
5475
5476 ret = chipset_val + graphics_val;
5477
5478 out_unlock:
5479 spin_unlock_irq(&mchdev_lock);
5480
5481 return ret;
5482 }
5483 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5484
5485 /**
5486 * i915_gpu_raise - raise GPU frequency limit
5487 *
5488 * Raise the limit; IPS indicates we have thermal headroom.
5489 */
5490 bool i915_gpu_raise(void)
5491 {
5492 struct drm_i915_private *dev_priv;
5493 bool ret = true;
5494
5495 spin_lock_irq(&mchdev_lock);
5496 if (!i915_mch_dev) {
5497 ret = false;
5498 goto out_unlock;
5499 }
5500 dev_priv = i915_mch_dev;
5501
5502 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5503 dev_priv->ips.max_delay--;
5504
5505 out_unlock:
5506 spin_unlock_irq(&mchdev_lock);
5507
5508 return ret;
5509 }
5510 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5511
5512 /**
5513 * i915_gpu_lower - lower GPU frequency limit
5514 *
5515 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5516 * frequency maximum.
5517 */
5518 bool i915_gpu_lower(void)
5519 {
5520 struct drm_i915_private *dev_priv;
5521 bool ret = true;
5522
5523 spin_lock_irq(&mchdev_lock);
5524 if (!i915_mch_dev) {
5525 ret = false;
5526 goto out_unlock;
5527 }
5528 dev_priv = i915_mch_dev;
5529
5530 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5531 dev_priv->ips.max_delay++;
5532
5533 out_unlock:
5534 spin_unlock_irq(&mchdev_lock);
5535
5536 return ret;
5537 }
5538 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5539
5540 /**
5541 * i915_gpu_busy - indicate GPU business to IPS
5542 *
5543 * Tell the IPS driver whether or not the GPU is busy.
5544 */
5545 bool i915_gpu_busy(void)
5546 {
5547 struct drm_i915_private *dev_priv;
5548 struct intel_engine_cs *ring;
5549 bool ret = false;
5550 int i;
5551
5552 spin_lock_irq(&mchdev_lock);
5553 if (!i915_mch_dev)
5554 goto out_unlock;
5555 dev_priv = i915_mch_dev;
5556
5557 for_each_ring(ring, dev_priv, i)
5558 ret |= !list_empty(&ring->request_list);
5559
5560 out_unlock:
5561 spin_unlock_irq(&mchdev_lock);
5562
5563 return ret;
5564 }
5565 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5566
5567 /**
5568 * i915_gpu_turbo_disable - disable graphics turbo
5569 *
5570 * Disable graphics turbo by resetting the max frequency and setting the
5571 * current frequency to the default.
5572 */
5573 bool i915_gpu_turbo_disable(void)
5574 {
5575 struct drm_i915_private *dev_priv;
5576 bool ret = true;
5577
5578 spin_lock_irq(&mchdev_lock);
5579 if (!i915_mch_dev) {
5580 ret = false;
5581 goto out_unlock;
5582 }
5583 dev_priv = i915_mch_dev;
5584
5585 dev_priv->ips.max_delay = dev_priv->ips.fstart;
5586
5587 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5588 ret = false;
5589
5590 out_unlock:
5591 spin_unlock_irq(&mchdev_lock);
5592
5593 return ret;
5594 }
5595 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5596
5597 /**
5598 * Tells the intel_ips driver that the i915 driver is now loaded, if
5599 * IPS got loaded first.
5600 *
5601 * This awkward dance is so that neither module has to depend on the
5602 * other in order for IPS to do the appropriate communication of
5603 * GPU turbo limits to i915.
5604 */
5605 static void
5606 ips_ping_for_i915_load(void)
5607 {
5608 void (*link)(void);
5609
5610 link = symbol_get(ips_link_to_i915_driver);
5611 if (link) {
5612 link();
5613 symbol_put(ips_link_to_i915_driver);
5614 }
5615 }
5616
5617 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5618 {
5619 /* We only register the i915 ips part with intel-ips once everything is
5620 * set up, to avoid intel-ips sneaking in and reading bogus values. */
5621 spin_lock_irq(&mchdev_lock);
5622 i915_mch_dev = dev_priv;
5623 spin_unlock_irq(&mchdev_lock);
5624
5625 ips_ping_for_i915_load();
5626 }
5627
5628 void intel_gpu_ips_teardown(void)
5629 {
5630 spin_lock_irq(&mchdev_lock);
5631 i915_mch_dev = NULL;
5632 spin_unlock_irq(&mchdev_lock);
5633 }
5634
5635 static void intel_init_emon(struct drm_device *dev)
5636 {
5637 struct drm_i915_private *dev_priv = dev->dev_private;
5638 u32 lcfuse;
5639 u8 pxw[16];
5640 int i;
5641
5642 /* Disable to program */
5643 I915_WRITE(ECR, 0);
5644 POSTING_READ(ECR);
5645
5646 /* Program energy weights for various events */
5647 I915_WRITE(SDEW, 0x15040d00);
5648 I915_WRITE(CSIEW0, 0x007f0000);
5649 I915_WRITE(CSIEW1, 0x1e220004);
5650 I915_WRITE(CSIEW2, 0x04000004);
5651
5652 for (i = 0; i < 5; i++)
5653 I915_WRITE(PEW + (i * 4), 0);
5654 for (i = 0; i < 3; i++)
5655 I915_WRITE(DEW + (i * 4), 0);
5656
5657 /* Program P-state weights to account for frequency power adjustment */
5658 for (i = 0; i < 16; i++) {
5659 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5660 unsigned long freq = intel_pxfreq(pxvidfreq);
5661 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5662 PXVFREQ_PX_SHIFT;
5663 unsigned long val;
5664
5665 val = vid * vid;
5666 val *= (freq / 1000);
5667 val *= 255;
5668 val /= (127*127*900);
5669 if (val > 0xff)
5670 DRM_ERROR("bad pxval: %ld\n", val);
5671 pxw[i] = val;
5672 }
5673 /* Render standby states get 0 weight */
5674 pxw[14] = 0;
5675 pxw[15] = 0;
5676
5677 for (i = 0; i < 4; i++) {
5678 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5679 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5680 I915_WRITE(PXW + (i * 4), val);
5681 }
5682
5683 /* Adjust magic regs to magic values (more experimental results) */
5684 I915_WRITE(OGW0, 0);
5685 I915_WRITE(OGW1, 0);
5686 I915_WRITE(EG0, 0x00007f00);
5687 I915_WRITE(EG1, 0x0000000e);
5688 I915_WRITE(EG2, 0x000e0000);
5689 I915_WRITE(EG3, 0x68000300);
5690 I915_WRITE(EG4, 0x42000000);
5691 I915_WRITE(EG5, 0x00140031);
5692 I915_WRITE(EG6, 0);
5693 I915_WRITE(EG7, 0);
5694
5695 for (i = 0; i < 8; i++)
5696 I915_WRITE(PXWL + (i * 4), 0);
5697
5698 /* Enable PMON + select events */
5699 I915_WRITE(ECR, 0x80000019);
5700
5701 lcfuse = I915_READ(LCFUSE02);
5702
5703 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5704 }
5705
5706 void intel_init_gt_powersave(struct drm_device *dev)
5707 {
5708 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5709
5710 if (IS_CHERRYVIEW(dev))
5711 cherryview_init_gt_powersave(dev);
5712 else if (IS_VALLEYVIEW(dev))
5713 valleyview_init_gt_powersave(dev);
5714 }
5715
5716 void intel_cleanup_gt_powersave(struct drm_device *dev)
5717 {
5718 if (IS_CHERRYVIEW(dev))
5719 return;
5720 else if (IS_VALLEYVIEW(dev))
5721 valleyview_cleanup_gt_powersave(dev);
5722 }
5723
5724 static void gen6_suspend_rps(struct drm_device *dev)
5725 {
5726 struct drm_i915_private *dev_priv = dev->dev_private;
5727
5728 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5729
5730 gen6_disable_rps_interrupts(dev);
5731 }
5732
5733 /**
5734 * intel_suspend_gt_powersave - suspend PM work and helper threads
5735 * @dev: drm device
5736 *
5737 * We don't want to disable RC6 or other features here, we just want
5738 * to make sure any work we've queued has finished and won't bother
5739 * us while we're suspended.
5740 */
5741 void intel_suspend_gt_powersave(struct drm_device *dev)
5742 {
5743 struct drm_i915_private *dev_priv = dev->dev_private;
5744
5745 if (INTEL_INFO(dev)->gen < 6)
5746 return;
5747
5748 gen6_suspend_rps(dev);
5749
5750 /* Force GPU to min freq during suspend */
5751 gen6_rps_idle(dev_priv);
5752 }
5753
5754 void intel_disable_gt_powersave(struct drm_device *dev)
5755 {
5756 struct drm_i915_private *dev_priv = dev->dev_private;
5757
5758 if (IS_IRONLAKE_M(dev)) {
5759 ironlake_disable_drps(dev);
5760 } else if (INTEL_INFO(dev)->gen >= 6) {
5761 intel_suspend_gt_powersave(dev);
5762
5763 mutex_lock(&dev_priv->rps.hw_lock);
5764 if (INTEL_INFO(dev)->gen >= 9)
5765 gen9_disable_rps(dev);
5766 else if (IS_CHERRYVIEW(dev))
5767 cherryview_disable_rps(dev);
5768 else if (IS_VALLEYVIEW(dev))
5769 valleyview_disable_rps(dev);
5770 else
5771 gen6_disable_rps(dev);
5772
5773 dev_priv->rps.enabled = false;
5774 mutex_unlock(&dev_priv->rps.hw_lock);
5775 }
5776 }
5777
5778 static void intel_gen6_powersave_work(struct work_struct *work)
5779 {
5780 struct drm_i915_private *dev_priv =
5781 container_of(work, struct drm_i915_private,
5782 rps.delayed_resume_work.work);
5783 struct drm_device *dev = dev_priv->dev;
5784
5785 mutex_lock(&dev_priv->rps.hw_lock);
5786
5787 gen6_reset_rps_interrupts(dev);
5788
5789 if (IS_CHERRYVIEW(dev)) {
5790 cherryview_enable_rps(dev);
5791 } else if (IS_VALLEYVIEW(dev)) {
5792 valleyview_enable_rps(dev);
5793 } else if (INTEL_INFO(dev)->gen >= 9) {
5794 gen9_enable_rc6(dev);
5795 gen9_enable_rps(dev);
5796 __gen6_update_ring_freq(dev);
5797 } else if (IS_BROADWELL(dev)) {
5798 gen8_enable_rps(dev);
5799 __gen6_update_ring_freq(dev);
5800 } else {
5801 gen6_enable_rps(dev);
5802 __gen6_update_ring_freq(dev);
5803 }
5804
5805 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
5806 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
5807
5808 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
5809 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
5810
5811 dev_priv->rps.enabled = true;
5812
5813 gen6_enable_rps_interrupts(dev);
5814
5815 mutex_unlock(&dev_priv->rps.hw_lock);
5816
5817 intel_runtime_pm_put(dev_priv);
5818 }
5819
5820 void intel_enable_gt_powersave(struct drm_device *dev)
5821 {
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823
5824 /* Powersaving is controlled by the host when inside a VM */
5825 if (intel_vgpu_active(dev))
5826 return;
5827
5828 if (IS_IRONLAKE_M(dev)) {
5829 mutex_lock(&dev->struct_mutex);
5830 ironlake_enable_drps(dev);
5831 intel_init_emon(dev);
5832 mutex_unlock(&dev->struct_mutex);
5833 } else if (INTEL_INFO(dev)->gen >= 6) {
5834 /*
5835 * PCU communication is slow and this doesn't need to be
5836 * done at any specific time, so do this out of our fast path
5837 * to make resume and init faster.
5838 *
5839 * We depend on the HW RC6 power context save/restore
5840 * mechanism when entering D3 through runtime PM suspend. So
5841 * disable RPM until RPS/RC6 is properly setup. We can only
5842 * get here via the driver load/system resume/runtime resume
5843 * paths, so the _noresume version is enough (and in case of
5844 * runtime resume it's necessary).
5845 */
5846 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5847 round_jiffies_up_relative(HZ)))
5848 intel_runtime_pm_get_noresume(dev_priv);
5849 }
5850 }
5851
5852 void intel_reset_gt_powersave(struct drm_device *dev)
5853 {
5854 struct drm_i915_private *dev_priv = dev->dev_private;
5855
5856 if (INTEL_INFO(dev)->gen < 6)
5857 return;
5858
5859 gen6_suspend_rps(dev);
5860 dev_priv->rps.enabled = false;
5861 }
5862
5863 static void ibx_init_clock_gating(struct drm_device *dev)
5864 {
5865 struct drm_i915_private *dev_priv = dev->dev_private;
5866
5867 /*
5868 * On Ibex Peak and Cougar Point, we need to disable clock
5869 * gating for the panel power sequencer or it will fail to
5870 * start up when no ports are active.
5871 */
5872 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5873 }
5874
5875 static void g4x_disable_trickle_feed(struct drm_device *dev)
5876 {
5877 struct drm_i915_private *dev_priv = dev->dev_private;
5878 enum pipe pipe;
5879
5880 for_each_pipe(dev_priv, pipe) {
5881 I915_WRITE(DSPCNTR(pipe),
5882 I915_READ(DSPCNTR(pipe)) |
5883 DISPPLANE_TRICKLE_FEED_DISABLE);
5884
5885 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
5886 POSTING_READ(DSPSURF(pipe));
5887 }
5888 }
5889
5890 static void ilk_init_lp_watermarks(struct drm_device *dev)
5891 {
5892 struct drm_i915_private *dev_priv = dev->dev_private;
5893
5894 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5895 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5896 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5897
5898 /*
5899 * Don't touch WM1S_LP_EN here.
5900 * Doing so could cause underruns.
5901 */
5902 }
5903
5904 static void ironlake_init_clock_gating(struct drm_device *dev)
5905 {
5906 struct drm_i915_private *dev_priv = dev->dev_private;
5907 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5908
5909 /*
5910 * Required for FBC
5911 * WaFbcDisableDpfcClockGating:ilk
5912 */
5913 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5914 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5915 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5916
5917 I915_WRITE(PCH_3DCGDIS0,
5918 MARIUNIT_CLOCK_GATE_DISABLE |
5919 SVSMUNIT_CLOCK_GATE_DISABLE);
5920 I915_WRITE(PCH_3DCGDIS1,
5921 VFMUNIT_CLOCK_GATE_DISABLE);
5922
5923 /*
5924 * According to the spec the following bits should be set in
5925 * order to enable memory self-refresh
5926 * The bit 22/21 of 0x42004
5927 * The bit 5 of 0x42020
5928 * The bit 15 of 0x45000
5929 */
5930 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5931 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5932 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5933 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5934 I915_WRITE(DISP_ARB_CTL,
5935 (I915_READ(DISP_ARB_CTL) |
5936 DISP_FBC_WM_DIS));
5937
5938 ilk_init_lp_watermarks(dev);
5939
5940 /*
5941 * Based on the document from hardware guys the following bits
5942 * should be set unconditionally in order to enable FBC.
5943 * The bit 22 of 0x42000
5944 * The bit 22 of 0x42004
5945 * The bit 7,8,9 of 0x42020.
5946 */
5947 if (IS_IRONLAKE_M(dev)) {
5948 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5949 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5950 I915_READ(ILK_DISPLAY_CHICKEN1) |
5951 ILK_FBCQ_DIS);
5952 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5953 I915_READ(ILK_DISPLAY_CHICKEN2) |
5954 ILK_DPARB_GATE);
5955 }
5956
5957 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5958
5959 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5960 I915_READ(ILK_DISPLAY_CHICKEN2) |
5961 ILK_ELPIN_409_SELECT);
5962 I915_WRITE(_3D_CHICKEN2,
5963 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5964 _3D_CHICKEN2_WM_READ_PIPELINED);
5965
5966 /* WaDisableRenderCachePipelinedFlush:ilk */
5967 I915_WRITE(CACHE_MODE_0,
5968 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5969
5970 /* WaDisable_RenderCache_OperationalFlush:ilk */
5971 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5972
5973 g4x_disable_trickle_feed(dev);
5974
5975 ibx_init_clock_gating(dev);
5976 }
5977
5978 static void cpt_init_clock_gating(struct drm_device *dev)
5979 {
5980 struct drm_i915_private *dev_priv = dev->dev_private;
5981 int pipe;
5982 uint32_t val;
5983
5984 /*
5985 * On Ibex Peak and Cougar Point, we need to disable clock
5986 * gating for the panel power sequencer or it will fail to
5987 * start up when no ports are active.
5988 */
5989 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5990 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5991 PCH_CPUNIT_CLOCK_GATE_DISABLE);
5992 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5993 DPLS_EDP_PPS_FIX_DIS);
5994 /* The below fixes the weird display corruption, a few pixels shifted
5995 * downward, on (only) LVDS of some HP laptops with IVY.
5996 */
5997 for_each_pipe(dev_priv, pipe) {
5998 val = I915_READ(TRANS_CHICKEN2(pipe));
5999 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6000 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6001 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6002 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6003 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6004 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6005 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6006 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6007 }
6008 /* WADP0ClockGatingDisable */
6009 for_each_pipe(dev_priv, pipe) {
6010 I915_WRITE(TRANS_CHICKEN1(pipe),
6011 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6012 }
6013 }
6014
6015 static void gen6_check_mch_setup(struct drm_device *dev)
6016 {
6017 struct drm_i915_private *dev_priv = dev->dev_private;
6018 uint32_t tmp;
6019
6020 tmp = I915_READ(MCH_SSKPD);
6021 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6022 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6023 tmp);
6024 }
6025
6026 static void gen6_init_clock_gating(struct drm_device *dev)
6027 {
6028 struct drm_i915_private *dev_priv = dev->dev_private;
6029 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6030
6031 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6032
6033 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6034 I915_READ(ILK_DISPLAY_CHICKEN2) |
6035 ILK_ELPIN_409_SELECT);
6036
6037 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6038 I915_WRITE(_3D_CHICKEN,
6039 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6040
6041 /* WaDisable_RenderCache_OperationalFlush:snb */
6042 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6043
6044 /*
6045 * BSpec recoomends 8x4 when MSAA is used,
6046 * however in practice 16x4 seems fastest.
6047 *
6048 * Note that PS/WM thread counts depend on the WIZ hashing
6049 * disable bit, which we don't touch here, but it's good
6050 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6051 */
6052 I915_WRITE(GEN6_GT_MODE,
6053 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6054
6055 ilk_init_lp_watermarks(dev);
6056
6057 I915_WRITE(CACHE_MODE_0,
6058 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6059
6060 I915_WRITE(GEN6_UCGCTL1,
6061 I915_READ(GEN6_UCGCTL1) |
6062 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6063 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6064
6065 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6066 * gating disable must be set. Failure to set it results in
6067 * flickering pixels due to Z write ordering failures after
6068 * some amount of runtime in the Mesa "fire" demo, and Unigine
6069 * Sanctuary and Tropics, and apparently anything else with
6070 * alpha test or pixel discard.
6071 *
6072 * According to the spec, bit 11 (RCCUNIT) must also be set,
6073 * but we didn't debug actual testcases to find it out.
6074 *
6075 * WaDisableRCCUnitClockGating:snb
6076 * WaDisableRCPBUnitClockGating:snb
6077 */
6078 I915_WRITE(GEN6_UCGCTL2,
6079 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6080 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6081
6082 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6083 I915_WRITE(_3D_CHICKEN3,
6084 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6085
6086 /*
6087 * Bspec says:
6088 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6089 * 3DSTATE_SF number of SF output attributes is more than 16."
6090 */
6091 I915_WRITE(_3D_CHICKEN3,
6092 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6093
6094 /*
6095 * According to the spec the following bits should be
6096 * set in order to enable memory self-refresh and fbc:
6097 * The bit21 and bit22 of 0x42000
6098 * The bit21 and bit22 of 0x42004
6099 * The bit5 and bit7 of 0x42020
6100 * The bit14 of 0x70180
6101 * The bit14 of 0x71180
6102 *
6103 * WaFbcAsynchFlipDisableFbcQueue:snb
6104 */
6105 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6106 I915_READ(ILK_DISPLAY_CHICKEN1) |
6107 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6108 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6109 I915_READ(ILK_DISPLAY_CHICKEN2) |
6110 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6111 I915_WRITE(ILK_DSPCLK_GATE_D,
6112 I915_READ(ILK_DSPCLK_GATE_D) |
6113 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6114 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6115
6116 g4x_disable_trickle_feed(dev);
6117
6118 cpt_init_clock_gating(dev);
6119
6120 gen6_check_mch_setup(dev);
6121 }
6122
6123 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6124 {
6125 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6126
6127 /*
6128 * WaVSThreadDispatchOverride:ivb,vlv
6129 *
6130 * This actually overrides the dispatch
6131 * mode for all thread types.
6132 */
6133 reg &= ~GEN7_FF_SCHED_MASK;
6134 reg |= GEN7_FF_TS_SCHED_HW;
6135 reg |= GEN7_FF_VS_SCHED_HW;
6136 reg |= GEN7_FF_DS_SCHED_HW;
6137
6138 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6139 }
6140
6141 static void lpt_init_clock_gating(struct drm_device *dev)
6142 {
6143 struct drm_i915_private *dev_priv = dev->dev_private;
6144
6145 /*
6146 * TODO: this bit should only be enabled when really needed, then
6147 * disabled when not needed anymore in order to save power.
6148 */
6149 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6150 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6151 I915_READ(SOUTH_DSPCLK_GATE_D) |
6152 PCH_LP_PARTITION_LEVEL_DISABLE);
6153
6154 /* WADPOClockGatingDisable:hsw */
6155 I915_WRITE(_TRANSA_CHICKEN1,
6156 I915_READ(_TRANSA_CHICKEN1) |
6157 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6158 }
6159
6160 static void lpt_suspend_hw(struct drm_device *dev)
6161 {
6162 struct drm_i915_private *dev_priv = dev->dev_private;
6163
6164 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6165 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6166
6167 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6168 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6169 }
6170 }
6171
6172 static void broadwell_init_clock_gating(struct drm_device *dev)
6173 {
6174 struct drm_i915_private *dev_priv = dev->dev_private;
6175 enum pipe pipe;
6176 uint32_t misccpctl;
6177
6178 ilk_init_lp_watermarks(dev);
6179
6180 /* WaSwitchSolVfFArbitrationPriority:bdw */
6181 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6182
6183 /* WaPsrDPAMaskVBlankInSRD:bdw */
6184 I915_WRITE(CHICKEN_PAR1_1,
6185 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6186
6187 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6188 for_each_pipe(dev_priv, pipe) {
6189 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6190 I915_READ(CHICKEN_PIPESL_1(pipe)) |
6191 BDW_DPRS_MASK_VBLANK_SRD);
6192 }
6193
6194 /* WaVSRefCountFullforceMissDisable:bdw */
6195 /* WaDSRefCountFullforceMissDisable:bdw */
6196 I915_WRITE(GEN7_FF_THREAD_MODE,
6197 I915_READ(GEN7_FF_THREAD_MODE) &
6198 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6199
6200 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6201 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6202
6203 /* WaDisableSDEUnitClockGating:bdw */
6204 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6205 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6206
6207 /*
6208 * WaProgramL3SqcReg1Default:bdw
6209 * WaTempDisableDOPClkGating:bdw
6210 */
6211 misccpctl = I915_READ(GEN7_MISCCPCTL);
6212 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6213 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6214 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6215
6216 /*
6217 * WaGttCachingOffByDefault:bdw
6218 * GTT cache may not work with big pages, so if those
6219 * are ever enabled GTT cache may need to be disabled.
6220 */
6221 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6222
6223 lpt_init_clock_gating(dev);
6224 }
6225
6226 static void haswell_init_clock_gating(struct drm_device *dev)
6227 {
6228 struct drm_i915_private *dev_priv = dev->dev_private;
6229
6230 ilk_init_lp_watermarks(dev);
6231
6232 /* L3 caching of data atomics doesn't work -- disable it. */
6233 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6234 I915_WRITE(HSW_ROW_CHICKEN3,
6235 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6236
6237 /* This is required by WaCatErrorRejectionIssue:hsw */
6238 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6239 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6240 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6241
6242 /* WaVSRefCountFullforceMissDisable:hsw */
6243 I915_WRITE(GEN7_FF_THREAD_MODE,
6244 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6245
6246 /* WaDisable_RenderCache_OperationalFlush:hsw */
6247 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6248
6249 /* enable HiZ Raw Stall Optimization */
6250 I915_WRITE(CACHE_MODE_0_GEN7,
6251 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6252
6253 /* WaDisable4x2SubspanOptimization:hsw */
6254 I915_WRITE(CACHE_MODE_1,
6255 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6256
6257 /*
6258 * BSpec recommends 8x4 when MSAA is used,
6259 * however in practice 16x4 seems fastest.
6260 *
6261 * Note that PS/WM thread counts depend on the WIZ hashing
6262 * disable bit, which we don't touch here, but it's good
6263 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6264 */
6265 I915_WRITE(GEN7_GT_MODE,
6266 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6267
6268 /* WaSampleCChickenBitEnable:hsw */
6269 I915_WRITE(HALF_SLICE_CHICKEN3,
6270 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6271
6272 /* WaSwitchSolVfFArbitrationPriority:hsw */
6273 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6274
6275 /* WaRsPkgCStateDisplayPMReq:hsw */
6276 I915_WRITE(CHICKEN_PAR1_1,
6277 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6278
6279 lpt_init_clock_gating(dev);
6280 }
6281
6282 static void ivybridge_init_clock_gating(struct drm_device *dev)
6283 {
6284 struct drm_i915_private *dev_priv = dev->dev_private;
6285 uint32_t snpcr;
6286
6287 ilk_init_lp_watermarks(dev);
6288
6289 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6290
6291 /* WaDisableEarlyCull:ivb */
6292 I915_WRITE(_3D_CHICKEN3,
6293 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6294
6295 /* WaDisableBackToBackFlipFix:ivb */
6296 I915_WRITE(IVB_CHICKEN3,
6297 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6298 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6299
6300 /* WaDisablePSDDualDispatchEnable:ivb */
6301 if (IS_IVB_GT1(dev))
6302 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6303 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6304
6305 /* WaDisable_RenderCache_OperationalFlush:ivb */
6306 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6307
6308 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6309 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6310 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6311
6312 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6313 I915_WRITE(GEN7_L3CNTLREG1,
6314 GEN7_WA_FOR_GEN7_L3_CONTROL);
6315 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6316 GEN7_WA_L3_CHICKEN_MODE);
6317 if (IS_IVB_GT1(dev))
6318 I915_WRITE(GEN7_ROW_CHICKEN2,
6319 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6320 else {
6321 /* must write both registers */
6322 I915_WRITE(GEN7_ROW_CHICKEN2,
6323 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6324 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6325 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6326 }
6327
6328 /* WaForceL3Serialization:ivb */
6329 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6330 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6331
6332 /*
6333 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6334 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6335 */
6336 I915_WRITE(GEN6_UCGCTL2,
6337 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6338
6339 /* This is required by WaCatErrorRejectionIssue:ivb */
6340 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6341 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6342 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6343
6344 g4x_disable_trickle_feed(dev);
6345
6346 gen7_setup_fixed_func_scheduler(dev_priv);
6347
6348 if (0) { /* causes HiZ corruption on ivb:gt1 */
6349 /* enable HiZ Raw Stall Optimization */
6350 I915_WRITE(CACHE_MODE_0_GEN7,
6351 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6352 }
6353
6354 /* WaDisable4x2SubspanOptimization:ivb */
6355 I915_WRITE(CACHE_MODE_1,
6356 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6357
6358 /*
6359 * BSpec recommends 8x4 when MSAA is used,
6360 * however in practice 16x4 seems fastest.
6361 *
6362 * Note that PS/WM thread counts depend on the WIZ hashing
6363 * disable bit, which we don't touch here, but it's good
6364 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6365 */
6366 I915_WRITE(GEN7_GT_MODE,
6367 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6368
6369 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6370 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6371 snpcr |= GEN6_MBC_SNPCR_MED;
6372 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6373
6374 if (!HAS_PCH_NOP(dev))
6375 cpt_init_clock_gating(dev);
6376
6377 gen6_check_mch_setup(dev);
6378 }
6379
6380 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6381 {
6382 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6383
6384 /*
6385 * Disable trickle feed and enable pnd deadline calculation
6386 */
6387 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6388 I915_WRITE(CBR1_VLV, 0);
6389 }
6390
6391 static void valleyview_init_clock_gating(struct drm_device *dev)
6392 {
6393 struct drm_i915_private *dev_priv = dev->dev_private;
6394
6395 vlv_init_display_clock_gating(dev_priv);
6396
6397 /* WaDisableEarlyCull:vlv */
6398 I915_WRITE(_3D_CHICKEN3,
6399 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6400
6401 /* WaDisableBackToBackFlipFix:vlv */
6402 I915_WRITE(IVB_CHICKEN3,
6403 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6404 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6405
6406 /* WaPsdDispatchEnable:vlv */
6407 /* WaDisablePSDDualDispatchEnable:vlv */
6408 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6409 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6410 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6411
6412 /* WaDisable_RenderCache_OperationalFlush:vlv */
6413 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6414
6415 /* WaForceL3Serialization:vlv */
6416 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6417 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6418
6419 /* WaDisableDopClockGating:vlv */
6420 I915_WRITE(GEN7_ROW_CHICKEN2,
6421 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6422
6423 /* This is required by WaCatErrorRejectionIssue:vlv */
6424 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6425 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6426 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6427
6428 gen7_setup_fixed_func_scheduler(dev_priv);
6429
6430 /*
6431 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6432 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6433 */
6434 I915_WRITE(GEN6_UCGCTL2,
6435 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6436
6437 /* WaDisableL3Bank2xClockGate:vlv
6438 * Disabling L3 clock gating- MMIO 940c[25] = 1
6439 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6440 I915_WRITE(GEN7_UCGCTL4,
6441 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6442
6443 /*
6444 * BSpec says this must be set, even though
6445 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6446 */
6447 I915_WRITE(CACHE_MODE_1,
6448 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6449
6450 /*
6451 * BSpec recommends 8x4 when MSAA is used,
6452 * however in practice 16x4 seems fastest.
6453 *
6454 * Note that PS/WM thread counts depend on the WIZ hashing
6455 * disable bit, which we don't touch here, but it's good
6456 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6457 */
6458 I915_WRITE(GEN7_GT_MODE,
6459 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6460
6461 /*
6462 * WaIncreaseL3CreditsForVLVB0:vlv
6463 * This is the hardware default actually.
6464 */
6465 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6466
6467 /*
6468 * WaDisableVLVClockGating_VBIIssue:vlv
6469 * Disable clock gating on th GCFG unit to prevent a delay
6470 * in the reporting of vblank events.
6471 */
6472 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6473 }
6474
6475 static void cherryview_init_clock_gating(struct drm_device *dev)
6476 {
6477 struct drm_i915_private *dev_priv = dev->dev_private;
6478
6479 vlv_init_display_clock_gating(dev_priv);
6480
6481 /* WaVSRefCountFullforceMissDisable:chv */
6482 /* WaDSRefCountFullforceMissDisable:chv */
6483 I915_WRITE(GEN7_FF_THREAD_MODE,
6484 I915_READ(GEN7_FF_THREAD_MODE) &
6485 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6486
6487 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6488 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6489 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6490
6491 /* WaDisableCSUnitClockGating:chv */
6492 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6493 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6494
6495 /* WaDisableSDEUnitClockGating:chv */
6496 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6497 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6498
6499 /*
6500 * GTT cache may not work with big pages, so if those
6501 * are ever enabled GTT cache may need to be disabled.
6502 */
6503 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6504 }
6505
6506 static void g4x_init_clock_gating(struct drm_device *dev)
6507 {
6508 struct drm_i915_private *dev_priv = dev->dev_private;
6509 uint32_t dspclk_gate;
6510
6511 I915_WRITE(RENCLK_GATE_D1, 0);
6512 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6513 GS_UNIT_CLOCK_GATE_DISABLE |
6514 CL_UNIT_CLOCK_GATE_DISABLE);
6515 I915_WRITE(RAMCLK_GATE_D, 0);
6516 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6517 OVRUNIT_CLOCK_GATE_DISABLE |
6518 OVCUNIT_CLOCK_GATE_DISABLE;
6519 if (IS_GM45(dev))
6520 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6521 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6522
6523 /* WaDisableRenderCachePipelinedFlush */
6524 I915_WRITE(CACHE_MODE_0,
6525 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6526
6527 /* WaDisable_RenderCache_OperationalFlush:g4x */
6528 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6529
6530 g4x_disable_trickle_feed(dev);
6531 }
6532
6533 static void crestline_init_clock_gating(struct drm_device *dev)
6534 {
6535 struct drm_i915_private *dev_priv = dev->dev_private;
6536
6537 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6538 I915_WRITE(RENCLK_GATE_D2, 0);
6539 I915_WRITE(DSPCLK_GATE_D, 0);
6540 I915_WRITE(RAMCLK_GATE_D, 0);
6541 I915_WRITE16(DEUC, 0);
6542 I915_WRITE(MI_ARB_STATE,
6543 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6544
6545 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6546 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6547 }
6548
6549 static void broadwater_init_clock_gating(struct drm_device *dev)
6550 {
6551 struct drm_i915_private *dev_priv = dev->dev_private;
6552
6553 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6554 I965_RCC_CLOCK_GATE_DISABLE |
6555 I965_RCPB_CLOCK_GATE_DISABLE |
6556 I965_ISC_CLOCK_GATE_DISABLE |
6557 I965_FBC_CLOCK_GATE_DISABLE);
6558 I915_WRITE(RENCLK_GATE_D2, 0);
6559 I915_WRITE(MI_ARB_STATE,
6560 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6561
6562 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6563 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6564 }
6565
6566 static void gen3_init_clock_gating(struct drm_device *dev)
6567 {
6568 struct drm_i915_private *dev_priv = dev->dev_private;
6569 u32 dstate = I915_READ(D_STATE);
6570
6571 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6572 DSTATE_DOT_CLOCK_GATING;
6573 I915_WRITE(D_STATE, dstate);
6574
6575 if (IS_PINEVIEW(dev))
6576 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6577
6578 /* IIR "flip pending" means done if this bit is set */
6579 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6580
6581 /* interrupts should cause a wake up from C3 */
6582 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6583
6584 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6585 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6586
6587 I915_WRITE(MI_ARB_STATE,
6588 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6589 }
6590
6591 static void i85x_init_clock_gating(struct drm_device *dev)
6592 {
6593 struct drm_i915_private *dev_priv = dev->dev_private;
6594
6595 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6596
6597 /* interrupts should cause a wake up from C3 */
6598 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6599 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6600
6601 I915_WRITE(MEM_MODE,
6602 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6603 }
6604
6605 static void i830_init_clock_gating(struct drm_device *dev)
6606 {
6607 struct drm_i915_private *dev_priv = dev->dev_private;
6608
6609 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6610
6611 I915_WRITE(MEM_MODE,
6612 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6613 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6614 }
6615
6616 void intel_init_clock_gating(struct drm_device *dev)
6617 {
6618 struct drm_i915_private *dev_priv = dev->dev_private;
6619
6620 if (dev_priv->display.init_clock_gating)
6621 dev_priv->display.init_clock_gating(dev);
6622 }
6623
6624 void intel_suspend_hw(struct drm_device *dev)
6625 {
6626 if (HAS_PCH_LPT(dev))
6627 lpt_suspend_hw(dev);
6628 }
6629
6630 /* Set up chip specific power management-related functions */
6631 void intel_init_pm(struct drm_device *dev)
6632 {
6633 struct drm_i915_private *dev_priv = dev->dev_private;
6634
6635 intel_fbc_init(dev_priv);
6636
6637 /* For cxsr */
6638 if (IS_PINEVIEW(dev))
6639 i915_pineview_get_mem_freq(dev);
6640 else if (IS_GEN5(dev))
6641 i915_ironlake_get_mem_freq(dev);
6642
6643 /* For FIFO watermark updates */
6644 if (INTEL_INFO(dev)->gen >= 9) {
6645 skl_setup_wm_latency(dev);
6646
6647 if (IS_BROXTON(dev))
6648 dev_priv->display.init_clock_gating =
6649 bxt_init_clock_gating;
6650 else if (IS_SKYLAKE(dev))
6651 dev_priv->display.init_clock_gating =
6652 skl_init_clock_gating;
6653 dev_priv->display.update_wm = skl_update_wm;
6654 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
6655 } else if (HAS_PCH_SPLIT(dev)) {
6656 ilk_setup_wm_latency(dev);
6657
6658 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6659 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6660 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6661 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6662 dev_priv->display.update_wm = ilk_update_wm;
6663 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6664 } else {
6665 DRM_DEBUG_KMS("Failed to read display plane latency. "
6666 "Disable CxSR\n");
6667 }
6668
6669 if (IS_GEN5(dev))
6670 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6671 else if (IS_GEN6(dev))
6672 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6673 else if (IS_IVYBRIDGE(dev))
6674 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6675 else if (IS_HASWELL(dev))
6676 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6677 else if (INTEL_INFO(dev)->gen == 8)
6678 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
6679 } else if (IS_CHERRYVIEW(dev)) {
6680 dev_priv->display.update_wm = valleyview_update_wm;
6681 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6682 dev_priv->display.init_clock_gating =
6683 cherryview_init_clock_gating;
6684 } else if (IS_VALLEYVIEW(dev)) {
6685 dev_priv->display.update_wm = valleyview_update_wm;
6686 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6687 dev_priv->display.init_clock_gating =
6688 valleyview_init_clock_gating;
6689 } else if (IS_PINEVIEW(dev)) {
6690 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6691 dev_priv->is_ddr3,
6692 dev_priv->fsb_freq,
6693 dev_priv->mem_freq)) {
6694 DRM_INFO("failed to find known CxSR latency "
6695 "(found ddr%s fsb freq %d, mem freq %d), "
6696 "disabling CxSR\n",
6697 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6698 dev_priv->fsb_freq, dev_priv->mem_freq);
6699 /* Disable CxSR and never update its watermark again */
6700 intel_set_memory_cxsr(dev_priv, false);
6701 dev_priv->display.update_wm = NULL;
6702 } else
6703 dev_priv->display.update_wm = pineview_update_wm;
6704 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6705 } else if (IS_G4X(dev)) {
6706 dev_priv->display.update_wm = g4x_update_wm;
6707 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6708 } else if (IS_GEN4(dev)) {
6709 dev_priv->display.update_wm = i965_update_wm;
6710 if (IS_CRESTLINE(dev))
6711 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6712 else if (IS_BROADWATER(dev))
6713 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6714 } else if (IS_GEN3(dev)) {
6715 dev_priv->display.update_wm = i9xx_update_wm;
6716 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6717 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6718 } else if (IS_GEN2(dev)) {
6719 if (INTEL_INFO(dev)->num_pipes == 1) {
6720 dev_priv->display.update_wm = i845_update_wm;
6721 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6722 } else {
6723 dev_priv->display.update_wm = i9xx_update_wm;
6724 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6725 }
6726
6727 if (IS_I85X(dev) || IS_I865G(dev))
6728 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6729 else
6730 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6731 } else {
6732 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6733 }
6734 }
6735
6736 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
6737 {
6738 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6739
6740 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6741 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6742 return -EAGAIN;
6743 }
6744
6745 I915_WRITE(GEN6_PCODE_DATA, *val);
6746 I915_WRITE(GEN6_PCODE_DATA1, 0);
6747 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6748
6749 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6750 500)) {
6751 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6752 return -ETIMEDOUT;
6753 }
6754
6755 *val = I915_READ(GEN6_PCODE_DATA);
6756 I915_WRITE(GEN6_PCODE_DATA, 0);
6757
6758 return 0;
6759 }
6760
6761 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
6762 {
6763 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6764
6765 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6766 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6767 return -EAGAIN;
6768 }
6769
6770 I915_WRITE(GEN6_PCODE_DATA, val);
6771 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6772
6773 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6774 500)) {
6775 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6776 return -ETIMEDOUT;
6777 }
6778
6779 I915_WRITE(GEN6_PCODE_DATA, 0);
6780
6781 return 0;
6782 }
6783
6784 static int vlv_gpu_freq_div(unsigned int czclk_freq)
6785 {
6786 switch (czclk_freq) {
6787 case 200:
6788 return 10;
6789 case 267:
6790 return 12;
6791 case 320:
6792 case 333:
6793 return 16;
6794 case 400:
6795 return 20;
6796 default:
6797 return -1;
6798 }
6799 }
6800
6801 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6802 {
6803 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6804
6805 div = vlv_gpu_freq_div(czclk_freq);
6806 if (div < 0)
6807 return div;
6808
6809 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
6810 }
6811
6812 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
6813 {
6814 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6815
6816 mul = vlv_gpu_freq_div(czclk_freq);
6817 if (mul < 0)
6818 return mul;
6819
6820 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
6821 }
6822
6823 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6824 {
6825 int div, czclk_freq = dev_priv->rps.cz_freq;
6826
6827 div = vlv_gpu_freq_div(czclk_freq) / 2;
6828 if (div < 0)
6829 return div;
6830
6831 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
6832 }
6833
6834 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6835 {
6836 int mul, czclk_freq = dev_priv->rps.cz_freq;
6837
6838 mul = vlv_gpu_freq_div(czclk_freq) / 2;
6839 if (mul < 0)
6840 return mul;
6841
6842 /* CHV needs even values */
6843 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
6844 }
6845
6846 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
6847 {
6848 if (IS_GEN9(dev_priv->dev))
6849 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
6850 else if (IS_CHERRYVIEW(dev_priv->dev))
6851 return chv_gpu_freq(dev_priv, val);
6852 else if (IS_VALLEYVIEW(dev_priv->dev))
6853 return byt_gpu_freq(dev_priv, val);
6854 else
6855 return val * GT_FREQUENCY_MULTIPLIER;
6856 }
6857
6858 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6859 {
6860 if (IS_GEN9(dev_priv->dev))
6861 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
6862 else if (IS_CHERRYVIEW(dev_priv->dev))
6863 return chv_freq_opcode(dev_priv, val);
6864 else if (IS_VALLEYVIEW(dev_priv->dev))
6865 return byt_freq_opcode(dev_priv, val);
6866 else
6867 return val / GT_FREQUENCY_MULTIPLIER;
6868 }
6869
6870 struct request_boost {
6871 struct work_struct work;
6872 struct drm_i915_gem_request *req;
6873 };
6874
6875 static void __intel_rps_boost_work(struct work_struct *work)
6876 {
6877 struct request_boost *boost = container_of(work, struct request_boost, work);
6878 struct drm_i915_gem_request *req = boost->req;
6879
6880 if (!i915_gem_request_completed(req, true))
6881 gen6_rps_boost(to_i915(req->ring->dev), NULL,
6882 req->emitted_jiffies);
6883
6884 i915_gem_request_unreference__unlocked(req);
6885 kfree(boost);
6886 }
6887
6888 void intel_queue_rps_boost_for_request(struct drm_device *dev,
6889 struct drm_i915_gem_request *req)
6890 {
6891 struct request_boost *boost;
6892
6893 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6894 return;
6895
6896 if (i915_gem_request_completed(req, true))
6897 return;
6898
6899 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
6900 if (boost == NULL)
6901 return;
6902
6903 i915_gem_request_reference(req);
6904 boost->req = req;
6905
6906 INIT_WORK(&boost->work, __intel_rps_boost_work);
6907 queue_work(to_i915(dev)->wq, &boost->work);
6908 }
6909
6910 void intel_pm_setup(struct drm_device *dev)
6911 {
6912 struct drm_i915_private *dev_priv = dev->dev_private;
6913
6914 mutex_init(&dev_priv->rps.hw_lock);
6915 spin_lock_init(&dev_priv->rps.client_lock);
6916
6917 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6918 intel_gen6_powersave_work);
6919 INIT_LIST_HEAD(&dev_priv->rps.clients);
6920 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
6921 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
6922
6923 dev_priv->pm.suspended = false;
6924 }
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