drivers/mmc/mmci.c

   1 /*
   2  *  linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/config.h>
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/device.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/highmem.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/protocol.h>
  22 #include <linux/amba/bus.h>
  23 #include <linux/clk.h>
  24
  25 #include <asm/cacheflush.h>
  26 #include <asm/div64.h>
  27 #include <asm/io.h>
  28 #include <asm/scatterlist.h>
  29 #include <asm/sizes.h>
  30 #include <asm/mach/mmc.h>
  31
  32 #include "mmci.h"
  33
  34 #define DRIVER_NAME "mmci-pl18x"
  35
  36 #ifdef CONFIG_MMC_DEBUG
  37 #define DBG(host,fmt,args...)   \
  38         pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
  39 #else
  40 #define DBG(host,fmt,args...)   do { } while (0)
  41 #endif
  42
  43 static unsigned int fmax = 515633;
  44
  45 static void
  46 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
  47 {
  48         writel(0, host->base + MMCICOMMAND);
  49
  50         host->mrq = NULL;
  51         host->cmd = NULL;
  52
  53         if (mrq->data)
  54                 mrq->data->bytes_xfered = host->data_xfered;
  55
  56         /*
  57          * Need to drop the host lock here; mmc_request_done may call
  58          * back into the driver...
  59          */
  60         spin_unlock(&host->lock);
  61         mmc_request_done(host->mmc, mrq);
  62         spin_lock(&host->lock);
  63 }
  64
  65 static void mmci_stop_data(struct mmci_host *host)
  66 {
  67         writel(0, host->base + MMCIDATACTRL);
  68         writel(0, host->base + MMCIMASK1);
  69         host->data = NULL;
  70 }
  71
  72 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
  73 {
  74         unsigned int datactrl, timeout, irqmask;
  75         unsigned long long clks;
  76         void __iomem *base;
  77
  78         DBG(host, "blksz %04x blks %04x flags %08x\n",
  79             1 << data->blksz_bits, data->blocks, data->flags);
  80
  81         host->data = data;
  82         host->size = data->blocks << data->blksz_bits;
  83         host->data_xfered = 0;
  84
  85         mmci_init_sg(host, data);
  86
  87         clks = (unsigned long long)data->timeout_ns * host->cclk;
  88         do_div(clks, 1000000000UL);
  89
  90         timeout = data->timeout_clks + (unsigned int)clks;
  91
  92         base = host->base;
  93         writel(timeout, base + MMCIDATATIMER);
  94         writel(host->size, base + MMCIDATALENGTH);
  95
  96         datactrl = MCI_DPSM_ENABLE | data->blksz_bits << 4;
  97         if (data->flags & MMC_DATA_READ) {
  98                 datactrl |= MCI_DPSM_DIRECTION;
  99                 irqmask = MCI_RXFIFOHALFFULLMASK;
 100
 101                 /*
 102                  * If we have less than a FIFOSIZE of bytes to transfer,
 103                  * trigger a PIO interrupt as soon as any data is available.
 104                  */
 105                 if (host->size < MCI_FIFOSIZE)
 106                         irqmask |= MCI_RXDATAAVLBLMASK;
 107         } else {
 108                 /*
 109                  * We don't actually need to include "FIFO empty" here
 110                  * since its implicit in "FIFO half empty".
 111                  */
 112                 irqmask = MCI_TXFIFOHALFEMPTYMASK;
 113         }
 114
 115         writel(datactrl, base + MMCIDATACTRL);
 116         writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
 117         writel(irqmask, base + MMCIMASK1);
 118 }
 119
 120 static void
 121 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
 122 {
 123         void __iomem *base = host->base;
 124
 125         DBG(host, "op %02x arg %08x flags %08x\n",
 126             cmd->opcode, cmd->arg, cmd->flags);
 127
 128         if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
 129                 writel(0, base + MMCICOMMAND);
 130                 udelay(1);
 131         }
 132
 133         c |= cmd->opcode | MCI_CPSM_ENABLE;
 134         if (cmd->flags & MMC_RSP_PRESENT) {
 135                 if (cmd->flags & MMC_RSP_136)
 136                         c |= MCI_CPSM_LONGRSP;
 137                 c |= MCI_CPSM_RESPONSE;
 138         }
 139         if (/*interrupt*/0)
 140                 c |= MCI_CPSM_INTERRUPT;
 141
 142         host->cmd = cmd;
 143
 144         writel(cmd->arg, base + MMCIARGUMENT);
 145         writel(c, base + MMCICOMMAND);
 146 }
 147
 148 static void
 149 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
 150               unsigned int status)
 151 {
 152         if (status & MCI_DATABLOCKEND) {
 153                 host->data_xfered += 1 << data->blksz_bits;
 154         }
 155         if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
 156                 if (status & MCI_DATACRCFAIL)
 157                         data->error = MMC_ERR_BADCRC;
 158                 else if (status & MCI_DATATIMEOUT)
 159                         data->error = MMC_ERR_TIMEOUT;
 160                 else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
 161                         data->error = MMC_ERR_FIFO;
 162                 status |= MCI_DATAEND;
 163
 164                 /*
 165                  * We hit an error condition.  Ensure that any data
 166                  * partially written to a page is properly coherent.
 167                  */
 168                 if (host->sg_len && data->flags & MMC_DATA_READ)
 169                         flush_dcache_page(host->sg_ptr->page);
 170         }
 171         if (status & MCI_DATAEND) {
 172                 mmci_stop_data(host);
 173
 174                 if (!data->stop) {
 175                         mmci_request_end(host, data->mrq);
 176                 } else {
 177                         mmci_start_command(host, data->stop, 0);
 178                 }
 179         }
 180 }
 181
 182 static void
 183 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
 184              unsigned int status)
 185 {
 186         void __iomem *base = host->base;
 187
 188         host->cmd = NULL;
 189
 190         cmd->resp[0] = readl(base + MMCIRESPONSE0);
 191         cmd->resp[1] = readl(base + MMCIRESPONSE1);
 192         cmd->resp[2] = readl(base + MMCIRESPONSE2);
 193         cmd->resp[3] = readl(base + MMCIRESPONSE3);
 194
 195         if (status & MCI_CMDTIMEOUT) {
 196                 cmd->error = MMC_ERR_TIMEOUT;
 197         } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
 198                 cmd->error = MMC_ERR_BADCRC;
 199         }
 200
 201         if (!cmd->data || cmd->error != MMC_ERR_NONE) {
 202                 mmci_request_end(host, cmd->mrq);
 203         } else if (!(cmd->data->flags & MMC_DATA_READ)) {
 204                 mmci_start_data(host, cmd->data);
 205         }
 206 }
 207
 208 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
 209 {
 210         void __iomem *base = host->base;
 211         char *ptr = buffer;
 212         u32 status;
 213
 214         do {
 215                 int count = host->size - (readl(base + MMCIFIFOCNT) << 2);
 216
 217                 if (count > remain)
 218                         count = remain;
 219
 220                 if (count <= 0)
 221                         break;
 222
 223                 readsl(base + MMCIFIFO, ptr, count >> 2);
 224
 225                 ptr += count;
 226                 remain -= count;
 227
 228                 if (remain == 0)
 229                         break;
 230
 231                 status = readl(base + MMCISTATUS);
 232         } while (status & MCI_RXDATAAVLBL);
 233
 234         return ptr - buffer;
 235 }
 236
 237 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
 238 {
 239         void __iomem *base = host->base;
 240         char *ptr = buffer;
 241
 242         do {
 243                 unsigned int count, maxcnt;
 244
 245                 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
 246                 count = min(remain, maxcnt);
 247
 248                 writesl(base + MMCIFIFO, ptr, count >> 2);
 249
 250                 ptr += count;
 251                 remain -= count;
 252
 253                 if (remain == 0)
 254                         break;
 255
 256                 status = readl(base + MMCISTATUS);
 257         } while (status & MCI_TXFIFOHALFEMPTY);
 258
 259         return ptr - buffer;
 260 }
 261
 262 /*
 263  * PIO data transfer IRQ handler.
 264  */
 265 static irqreturn_t mmci_pio_irq(int irq, void *dev_id, struct pt_regs *regs)
 266 {
 267         struct mmci_host *host = dev_id;
 268         void __iomem *base = host->base;
 269         u32 status;
 270
 271         status = readl(base + MMCISTATUS);
 272
 273         DBG(host, "irq1 %08x\n", status);
 274
 275         do {
 276                 unsigned long flags;
 277                 unsigned int remain, len;
 278                 char *buffer;
 279
 280                 /*
 281                  * For write, we only need to test the half-empty flag
 282                  * here - if the FIFO is completely empty, then by
 283                  * definition it is more than half empty.
 284                  *
 285                  * For read, check for data available.
 286                  */
 287                 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
 288                         break;
 289
 290                 /*
 291                  * Map the current scatter buffer.
 292                  */
 293                 buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
 294                 remain = host->sg_ptr->length - host->sg_off;
 295
 296                 len = 0;
 297                 if (status & MCI_RXACTIVE)
 298                         len = mmci_pio_read(host, buffer, remain);
 299                 if (status & MCI_TXACTIVE)
 300                         len = mmci_pio_write(host, buffer, remain, status);
 301
 302                 /*
 303                  * Unmap the buffer.
 304                  */
 305                 mmci_kunmap_atomic(host, buffer, &flags);
 306
 307                 host->sg_off += len;
 308                 host->size -= len;
 309                 remain -= len;
 310
 311                 if (remain)
 312                         break;
 313
 314                 /*
 315                  * If we were reading, and we have completed this
 316                  * page, ensure that the data cache is coherent.
 317                  */
 318                 if (status & MCI_RXACTIVE)
 319                         flush_dcache_page(host->sg_ptr->page);
 320
 321                 if (!mmci_next_sg(host))
 322                         break;
 323
 324                 status = readl(base + MMCISTATUS);
 325         } while (1);
 326
 327         /*
 328          * If we're nearing the end of the read, switch to
 329          * "any data available" mode.
 330          */
 331         if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
 332                 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
 333
 334         /*
 335          * If we run out of data, disable the data IRQs; this
 336          * prevents a race where the FIFO becomes empty before
 337          * the chip itself has disabled the data path, and
 338          * stops us racing with our data end IRQ.
 339          */
 340         if (host->size == 0) {
 341                 writel(0, base + MMCIMASK1);
 342                 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
 343         }
 344
 345         return IRQ_HANDLED;
 346 }
 347
 348 /*
 349  * Handle completion of command and data transfers.
 350  */
 351 static irqreturn_t mmci_irq(int irq, void *dev_id, struct pt_regs *regs)
 352 {
 353         struct mmci_host *host = dev_id;
 354         u32 status;
 355         int ret = 0;
 356
 357         spin_lock(&host->lock);
 358
 359         do {
 360                 struct mmc_command *cmd;
 361                 struct mmc_data *data;
 362
 363                 status = readl(host->base + MMCISTATUS);
 364                 status &= readl(host->base + MMCIMASK0);
 365                 writel(status, host->base + MMCICLEAR);
 366
 367                 DBG(host, "irq0 %08x\n", status);
 368
 369                 data = host->data;
 370                 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
 371                               MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
 372                         mmci_data_irq(host, data, status);
 373
 374                 cmd = host->cmd;
 375                 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
 376                         mmci_cmd_irq(host, cmd, status);
 377
 378                 ret = 1;
 379         } while (status);
 380
 381         spin_unlock(&host->lock);
 382
 383         return IRQ_RETVAL(ret);
 384 }
 385
 386 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 387 {
 388         struct mmci_host *host = mmc_priv(mmc);
 389
 390         WARN_ON(host->mrq != NULL);
 391
 392         spin_lock_irq(&host->lock);
 393
 394         host->mrq = mrq;
 395
 396         if (mrq->data && mrq->data->flags & MMC_DATA_READ)
 397                 mmci_start_data(host, mrq->data);
 398
 399         mmci_start_command(host, mrq->cmd, 0);
 400
 401         spin_unlock_irq(&host->lock);
 402 }
 403
 404 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 405 {
 406         struct mmci_host *host = mmc_priv(mmc);
 407         u32 clk = 0, pwr = 0;
 408
 409         DBG(host, "clock %uHz busmode %u powermode %u Vdd %u\n",
 410             ios->clock, ios->bus_mode, ios->power_mode, ios->vdd);
 411
 412         if (ios->clock) {
 413                 if (ios->clock >= host->mclk) {
 414                         clk = MCI_CLK_BYPASS;
 415                         host->cclk = host->mclk;
 416                 } else {
 417                         clk = host->mclk / (2 * ios->clock) - 1;
 418                         if (clk > 256)
 419                                 clk = 255;
 420                         host->cclk = host->mclk / (2 * (clk + 1));
 421                 }
 422                 clk |= MCI_CLK_ENABLE;
 423         }
 424
 425         if (host->plat->translate_vdd)
 426                 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
 427
 428         switch (ios->power_mode) {
 429         case MMC_POWER_OFF:
 430                 break;
 431         case MMC_POWER_UP:
 432                 pwr |= MCI_PWR_UP;
 433                 break;
 434         case MMC_POWER_ON:
 435                 pwr |= MCI_PWR_ON;
 436                 break;
 437         }
 438
 439         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 440                 pwr |= MCI_ROD;
 441
 442         writel(clk, host->base + MMCICLOCK);
 443
 444         if (host->pwr != pwr) {
 445                 host->pwr = pwr;
 446                 writel(pwr, host->base + MMCIPOWER);
 447         }
 448 }
 449
 450 static struct mmc_host_ops mmci_ops = {
 451         .request        = mmci_request,
 452         .set_ios        = mmci_set_ios,
 453 };
 454
 455 static void mmci_check_status(unsigned long data)
 456 {
 457         struct mmci_host *host = (struct mmci_host *)data;
 458         unsigned int status;
 459
 460         status = host->plat->status(mmc_dev(host->mmc));
 461         if (status ^ host->oldstat)
 462                 mmc_detect_change(host->mmc, 0);
 463
 464         host->oldstat = status;
 465         mod_timer(&host->timer, jiffies + HZ);
 466 }
 467
 468 static int mmci_probe(struct amba_device *dev, void *id)
 469 {
 470         struct mmc_platform_data *plat = dev->dev.platform_data;
 471         struct mmci_host *host;
 472         struct mmc_host *mmc;
 473         int ret;
 474
 475         /* must have platform data */
 476         if (!plat) {
 477                 ret = -EINVAL;
 478                 goto out;
 479         }
 480
 481         ret = amba_request_regions(dev, DRIVER_NAME);
 482         if (ret)
 483                 goto out;
 484
 485         mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
 486         if (!mmc) {
 487                 ret = -ENOMEM;
 488                 goto rel_regions;
 489         }
 490
 491         host = mmc_priv(mmc);
 492         host->clk = clk_get(&dev->dev, "MCLK");
 493         if (IS_ERR(host->clk)) {
 494                 ret = PTR_ERR(host->clk);
 495                 host->clk = NULL;
 496                 goto host_free;
 497         }
 498
 499         ret = clk_enable(host->clk);
 500         if (ret)
 501                 goto clk_free;
 502
 503         host->plat = plat;
 504         host->mclk = clk_get_rate(host->clk);
 505         host->mmc = mmc;
 506         host->base = ioremap(dev->res.start, SZ_4K);
 507         if (!host->base) {
 508                 ret = -ENOMEM;
 509                 goto clk_disable;
 510         }
 511
 512         mmc->ops = &mmci_ops;
 513         mmc->f_min = (host->mclk + 511) / 512;
 514         mmc->f_max = min(host->mclk, fmax);
 515         mmc->ocr_avail = plat->ocr_mask;
 516
 517         /*
 518          * We can do SGIO
 519          */
 520         mmc->max_hw_segs = 16;
 521         mmc->max_phys_segs = NR_SG;
 522
 523         /*
 524          * Since we only have a 16-bit data length register, we must
 525          * ensure that we don't exceed 2^16-1 bytes in a single request.
 526          * Choose 64 (512-byte) sectors as the limit.
 527          */
 528         mmc->max_sectors = 64;
 529
 530         /*
 531          * Set the maximum segment size.  Since we aren't doing DMA
 532          * (yet) we are only limited by the data length register.
 533          */
 534         mmc->max_seg_size = mmc->max_sectors << 9;
 535
 536         spin_lock_init(&host->lock);
 537
 538         writel(0, host->base + MMCIMASK0);
 539         writel(0, host->base + MMCIMASK1);
 540         writel(0xfff, host->base + MMCICLEAR);
 541
 542         ret = request_irq(dev->irq[0], mmci_irq, SA_SHIRQ, DRIVER_NAME " (cmd)", host);
 543         if (ret)
 544                 goto unmap;
 545
 546         ret = request_irq(dev->irq[1], mmci_pio_irq, SA_SHIRQ, DRIVER_NAME " (pio)", host);
 547         if (ret)
 548                 goto irq0_free;
 549
 550         writel(MCI_IRQENABLE, host->base + MMCIMASK0);
 551
 552         amba_set_drvdata(dev, mmc);
 553
 554         mmc_add_host(mmc);
 555
 556         printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%08lx irq %d,%d\n",
 557                 mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
 558                 dev->res.start, dev->irq[0], dev->irq[1]);
 559
 560         init_timer(&host->timer);
 561         host->timer.data = (unsigned long)host;
 562         host->timer.function = mmci_check_status;
 563         host->timer.expires = jiffies + HZ;
 564         add_timer(&host->timer);
 565
 566         return 0;
 567
 568  irq0_free:
 569         free_irq(dev->irq[0], host);
 570  unmap:
 571         iounmap(host->base);
 572  clk_disable:
 573         clk_disable(host->clk);
 574  clk_free:
 575         clk_put(host->clk);
 576  host_free:
 577         mmc_free_host(mmc);
 578  rel_regions:
 579         amba_release_regions(dev);
 580  out:
 581         return ret;
 582 }
 583
 584 static int mmci_remove(struct amba_device *dev)
 585 {
 586         struct mmc_host *mmc = amba_get_drvdata(dev);
 587
 588         amba_set_drvdata(dev, NULL);
 589
 590         if (mmc) {
 591                 struct mmci_host *host = mmc_priv(mmc);
 592
 593                 del_timer_sync(&host->timer);
 594
 595                 mmc_remove_host(mmc);
 596
 597                 writel(0, host->base + MMCIMASK0);
 598                 writel(0, host->base + MMCIMASK1);
 599
 600                 writel(0, host->base + MMCICOMMAND);
 601                 writel(0, host->base + MMCIDATACTRL);
 602
 603                 free_irq(dev->irq[0], host);
 604                 free_irq(dev->irq[1], host);
 605
 606                 iounmap(host->base);
 607                 clk_disable(host->clk);
 608                 clk_put(host->clk);
 609
 610                 mmc_free_host(mmc);
 611
 612                 amba_release_regions(dev);
 613         }
 614
 615         return 0;
 616 }
 617
 618 #ifdef CONFIG_PM
 619 static int mmci_suspend(struct amba_device *dev, pm_message_t state)
 620 {
 621         struct mmc_host *mmc = amba_get_drvdata(dev);
 622         int ret = 0;
 623
 624         if (mmc) {
 625                 struct mmci_host *host = mmc_priv(mmc);
 626
 627                 ret = mmc_suspend_host(mmc, state);
 628                 if (ret == 0)
 629                         writel(0, host->base + MMCIMASK0);
 630         }
 631
 632         return ret;
 633 }
 634
 635 static int mmci_resume(struct amba_device *dev)
 636 {
 637         struct mmc_host *mmc = amba_get_drvdata(dev);
 638         int ret = 0;
 639
 640         if (mmc) {
 641                 struct mmci_host *host = mmc_priv(mmc);
 642
 643                 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
 644
 645                 ret = mmc_resume_host(mmc);
 646         }
 647
 648         return ret;
 649 }
 650 #else
 651 #define mmci_suspend    NULL
 652 #define mmci_resume     NULL
 653 #endif
 654
 655 static struct amba_id mmci_ids[] = {
 656         {
 657                 .id     = 0x00041180,
 658                 .mask   = 0x000fffff,
 659         },
 660         {
 661                 .id     = 0x00041181,
 662                 .mask   = 0x000fffff,
 663         },
 664         { 0, 0 },
 665 };
 666
 667 static struct amba_driver mmci_driver = {
 668         .drv            = {
 669                 .name   = DRIVER_NAME,
 670         },
 671         .probe          = mmci_probe,
 672         .remove         = mmci_remove,
 673         .suspend        = mmci_suspend,
 674         .resume         = mmci_resume,
 675         .id_table       = mmci_ids,
 676 };
 677
 678 static int __init mmci_init(void)
 679 {
 680         return amba_driver_register(&mmci_driver);
 681 }
 682
 683 static void __exit mmci_exit(void)
 684 {
 685         amba_driver_unregister(&mmci_driver);
 686 }
 687
 688 module_init(mmci_init);
 689 module_exit(mmci_exit);
 690 module_param(fmax, uint, 0444);
 691
 692 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
 693 MODULE_LICENSE("GPL");