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x86, UV: Add common uv_early_read_mmr() function for reading MMRs
[linux-2.6/btrfs-unstable.git] / arch / x86 / kernel / apic / x2apic_uv_x.c
blob0c3675f0474f3425561291dd36b54bf4740a5dbc
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
9 */
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/pci.h>
25 #include <linux/kdebug.h>
26
27 #include <asm/uv/uv_mmrs.h>
28 #include <asm/uv/uv_hub.h>
29 #include <asm/current.h>
30 #include <asm/pgtable.h>
31 #include <asm/uv/bios.h>
32 #include <asm/uv/uv.h>
33 #include <asm/apic.h>
34 #include <asm/ipi.h>
35 #include <asm/smp.h>
36 #include <asm/x86_init.h>
37
38 DEFINE_PER_CPU(int, x2apic_extra_bits);
39
40 #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
41
42 static enum uv_system_type uv_system_type;
43 static u64 gru_start_paddr, gru_end_paddr;
44 static union uvh_apicid uvh_apicid;
45 int uv_min_hub_revision_id;
46 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
47 unsigned int uv_apicid_hibits;
48 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
49 static DEFINE_SPINLOCK(uv_nmi_lock);
50
51 static unsigned long __init uv_early_read_mmr(unsigned long addr)
52 {
53 unsigned long val, *mmr;
54
55 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
56 val = *mmr;
57 early_iounmap(mmr, sizeof(*mmr));
58 return val;
59 }
60
61 static inline bool is_GRU_range(u64 start, u64 end)
62 {
63 return start >= gru_start_paddr && end <= gru_end_paddr;
64 }
65
66 static bool uv_is_untracked_pat_range(u64 start, u64 end)
67 {
68 return is_ISA_range(start, end) || is_GRU_range(start, end);
69 }
70
71 static int __init early_get_nodeid(void)
72 {
73 union uvh_node_id_u node_id;
74
75 /* Currently, all blades have same revision number */
76 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
77 uv_min_hub_revision_id = node_id.s.revision;
78
79 return node_id.s.node_id;
80 }
81
82 static void __init early_get_apic_pnode_shift(void)
83 {
84 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
85 if (!uvh_apicid.v)
86 /*
87 * Old bios, use default value
88 */
89 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
90 }
91
92 /*
93 * Add an extra bit as dictated by bios to the destination apicid of
94 * interrupts potentially passing through the UV HUB. This prevents
95 * a deadlock between interrupts and IO port operations.
96 */
97 static void __init uv_set_apicid_hibit(void)
98 {
99 union uvh_lb_target_physical_apic_id_mask_u apicid_mask;
100
101 apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK);
102 uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK;
103 }
104
105 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
106 {
107 int nodeid;
108
109 if (!strcmp(oem_id, "SGI")) {
110 nodeid = early_get_nodeid();
111 early_get_apic_pnode_shift();
112 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
113 x86_platform.nmi_init = uv_nmi_init;
114 if (!strcmp(oem_table_id, "UVL"))
115 uv_system_type = UV_LEGACY_APIC;
116 else if (!strcmp(oem_table_id, "UVX"))
117 uv_system_type = UV_X2APIC;
118 else if (!strcmp(oem_table_id, "UVH")) {
119 __get_cpu_var(x2apic_extra_bits) =
120 nodeid << (uvh_apicid.s.pnode_shift - 1);
121 uv_system_type = UV_NON_UNIQUE_APIC;
122 uv_set_apicid_hibit();
123 return 1;
124 }
125 }
126 return 0;
127 }
128
129 enum uv_system_type get_uv_system_type(void)
130 {
131 return uv_system_type;
132 }
133
134 int is_uv_system(void)
135 {
136 return uv_system_type != UV_NONE;
137 }
138 EXPORT_SYMBOL_GPL(is_uv_system);
139
140 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
141 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
142
143 struct uv_blade_info *uv_blade_info;
144 EXPORT_SYMBOL_GPL(uv_blade_info);
145
146 short *uv_node_to_blade;
147 EXPORT_SYMBOL_GPL(uv_node_to_blade);
148
149 short *uv_cpu_to_blade;
150 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
151
152 short uv_possible_blades;
153 EXPORT_SYMBOL_GPL(uv_possible_blades);
154
155 unsigned long sn_rtc_cycles_per_second;
156 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
157
158 static const struct cpumask *uv_target_cpus(void)
159 {
160 return cpu_online_mask;
161 }
162
163 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
164 {
165 cpumask_clear(retmask);
166 cpumask_set_cpu(cpu, retmask);
167 }
168
169 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
170 {
171 #ifdef CONFIG_SMP
172 unsigned long val;
173 int pnode;
174
175 pnode = uv_apicid_to_pnode(phys_apicid);
176 phys_apicid |= uv_apicid_hibits;
177 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
178 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
179 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
180 APIC_DM_INIT;
181 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
182 mdelay(10);
183
184 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
185 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
186 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
187 APIC_DM_STARTUP;
188 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
189
190 atomic_set(&init_deasserted, 1);
191 #endif
192 return 0;
193 }
194
195 static void uv_send_IPI_one(int cpu, int vector)
196 {
197 unsigned long apicid;
198 int pnode;
199
200 apicid = per_cpu(x86_cpu_to_apicid, cpu);
201 pnode = uv_apicid_to_pnode(apicid);
202 uv_hub_send_ipi(pnode, apicid, vector);
203 }
204
205 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
206 {
207 unsigned int cpu;
208
209 for_each_cpu(cpu, mask)
210 uv_send_IPI_one(cpu, vector);
211 }
212
213 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
214 {
215 unsigned int this_cpu = smp_processor_id();
216 unsigned int cpu;
217
218 for_each_cpu(cpu, mask) {
219 if (cpu != this_cpu)
220 uv_send_IPI_one(cpu, vector);
221 }
222 }
223
224 static void uv_send_IPI_allbutself(int vector)
225 {
226 unsigned int this_cpu = smp_processor_id();
227 unsigned int cpu;
228
229 for_each_online_cpu(cpu) {
230 if (cpu != this_cpu)
231 uv_send_IPI_one(cpu, vector);
232 }
233 }
234
235 static void uv_send_IPI_all(int vector)
236 {
237 uv_send_IPI_mask(cpu_online_mask, vector);
238 }
239
240 static int uv_apic_id_registered(void)
241 {
242 return 1;
243 }
244
245 static void uv_init_apic_ldr(void)
246 {
247 }
248
249 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
250 {
251 /*
252 * We're using fixed IRQ delivery, can only return one phys APIC ID.
253 * May as well be the first.
254 */
255 int cpu = cpumask_first(cpumask);
256
257 if ((unsigned)cpu < nr_cpu_ids)
258 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
259 else
260 return BAD_APICID;
261 }
262
263 static unsigned int
264 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
265 const struct cpumask *andmask)
266 {
267 int cpu;
268
269 /*
270 * We're using fixed IRQ delivery, can only return one phys APIC ID.
271 * May as well be the first.
272 */
273 for_each_cpu_and(cpu, cpumask, andmask) {
274 if (cpumask_test_cpu(cpu, cpu_online_mask))
275 break;
276 }
277 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
278 }
279
280 static unsigned int x2apic_get_apic_id(unsigned long x)
281 {
282 unsigned int id;
283
284 WARN_ON(preemptible() && num_online_cpus() > 1);
285 id = x | __get_cpu_var(x2apic_extra_bits);
286
287 return id;
288 }
289
290 static unsigned long set_apic_id(unsigned int id)
291 {
292 unsigned long x;
293
294 /* maskout x2apic_extra_bits ? */
295 x = id;
296 return x;
297 }
298
299 static unsigned int uv_read_apic_id(void)
300 {
301
302 return x2apic_get_apic_id(apic_read(APIC_ID));
303 }
304
305 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
306 {
307 return uv_read_apic_id() >> index_msb;
308 }
309
310 static void uv_send_IPI_self(int vector)
311 {
312 apic_write(APIC_SELF_IPI, vector);
313 }
314
315 struct apic __refdata apic_x2apic_uv_x = {
316
317 .name = "UV large system",
318 .probe = NULL,
319 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
320 .apic_id_registered = uv_apic_id_registered,
321
322 .irq_delivery_mode = dest_Fixed,
323 .irq_dest_mode = 0, /* physical */
324
325 .target_cpus = uv_target_cpus,
326 .disable_esr = 0,
327 .dest_logical = APIC_DEST_LOGICAL,
328 .check_apicid_used = NULL,
329 .check_apicid_present = NULL,
330
331 .vector_allocation_domain = uv_vector_allocation_domain,
332 .init_apic_ldr = uv_init_apic_ldr,
333
334 .ioapic_phys_id_map = NULL,
335 .setup_apic_routing = NULL,
336 .multi_timer_check = NULL,
337 .apicid_to_node = NULL,
338 .cpu_to_logical_apicid = NULL,
339 .cpu_present_to_apicid = default_cpu_present_to_apicid,
340 .apicid_to_cpu_present = NULL,
341 .setup_portio_remap = NULL,
342 .check_phys_apicid_present = default_check_phys_apicid_present,
343 .enable_apic_mode = NULL,
344 .phys_pkg_id = uv_phys_pkg_id,
345 .mps_oem_check = NULL,
346
347 .get_apic_id = x2apic_get_apic_id,
348 .set_apic_id = set_apic_id,
349 .apic_id_mask = 0xFFFFFFFFu,
350
351 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
352 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
353
354 .send_IPI_mask = uv_send_IPI_mask,
355 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
356 .send_IPI_allbutself = uv_send_IPI_allbutself,
357 .send_IPI_all = uv_send_IPI_all,
358 .send_IPI_self = uv_send_IPI_self,
359
360 .wakeup_secondary_cpu = uv_wakeup_secondary,
361 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
362 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
363 .wait_for_init_deassert = NULL,
364 .smp_callin_clear_local_apic = NULL,
365 .inquire_remote_apic = NULL,
366
367 .read = native_apic_msr_read,
368 .write = native_apic_msr_write,
369 .icr_read = native_x2apic_icr_read,
370 .icr_write = native_x2apic_icr_write,
371 .wait_icr_idle = native_x2apic_wait_icr_idle,
372 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
373 };
374
375 static __cpuinit void set_x2apic_extra_bits(int pnode)
376 {
377 __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
378 }
379
380 /*
381 * Called on boot cpu.
382 */
383 static __init int boot_pnode_to_blade(int pnode)
384 {
385 int blade;
386
387 for (blade = 0; blade < uv_num_possible_blades(); blade++)
388 if (pnode == uv_blade_info[blade].pnode)
389 return blade;
390 BUG();
391 }
392
393 struct redir_addr {
394 unsigned long redirect;
395 unsigned long alias;
396 };
397
398 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
399
400 static __initdata struct redir_addr redir_addrs[] = {
401 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
402 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
403 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
404 };
405
406 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
407 {
408 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
409 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
410 int i;
411
412 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
413 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
414 if (alias.s.enable && alias.s.base == 0) {
415 *size = (1UL << alias.s.m_alias);
416 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
417 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
418 return;
419 }
420 }
421 *base = *size = 0;
422 }
423
424 enum map_type {map_wb, map_uc};
425
426 static __init void map_high(char *id, unsigned long base, int pshift,
427 int bshift, int max_pnode, enum map_type map_type)
428 {
429 unsigned long bytes, paddr;
430
431 paddr = base << pshift;
432 bytes = (1UL << bshift) * (max_pnode + 1);
433 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
434 paddr + bytes);
435 if (map_type == map_uc)
436 init_extra_mapping_uc(paddr, bytes);
437 else
438 init_extra_mapping_wb(paddr, bytes);
439
440 }
441 static __init void map_gru_high(int max_pnode)
442 {
443 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
444 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
445
446 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
447 if (gru.s.enable) {
448 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
449 gru_start_paddr = ((u64)gru.s.base << shift);
450 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
451
452 }
453 }
454
455 static __init void map_mmr_high(int max_pnode)
456 {
457 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
458 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
459
460 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
461 if (mmr.s.enable)
462 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
463 }
464
465 static __init void map_mmioh_high(int max_pnode)
466 {
467 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
468 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
469
470 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
471 if (mmioh.s.enable)
472 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
473 max_pnode, map_uc);
474 }
475
476 static __init void map_low_mmrs(void)
477 {
478 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
479 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
480 }
481
482 static __init void uv_rtc_init(void)
483 {
484 long status;
485 u64 ticks_per_sec;
486
487 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
488 &ticks_per_sec);
489 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
490 printk(KERN_WARNING
491 "unable to determine platform RTC clock frequency, "
492 "guessing.\n");
493 /* BIOS gives wrong value for clock freq. so guess */
494 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
495 } else
496 sn_rtc_cycles_per_second = ticks_per_sec;
497 }
498
499 /*
500 * percpu heartbeat timer
501 */
502 static void uv_heartbeat(unsigned long ignored)
503 {
504 struct timer_list *timer = &uv_hub_info->scir.timer;
505 unsigned char bits = uv_hub_info->scir.state;
506
507 /* flip heartbeat bit */
508 bits ^= SCIR_CPU_HEARTBEAT;
509
510 /* is this cpu idle? */
511 if (idle_cpu(raw_smp_processor_id()))
512 bits &= ~SCIR_CPU_ACTIVITY;
513 else
514 bits |= SCIR_CPU_ACTIVITY;
515
516 /* update system controller interface reg */
517 uv_set_scir_bits(bits);
518
519 /* enable next timer period */
520 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
521 }
522
523 static void __cpuinit uv_heartbeat_enable(int cpu)
524 {
525 while (!uv_cpu_hub_info(cpu)->scir.enabled) {
526 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
527
528 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
529 setup_timer(timer, uv_heartbeat, cpu);
530 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
531 add_timer_on(timer, cpu);
532 uv_cpu_hub_info(cpu)->scir.enabled = 1;
533
534 /* also ensure that boot cpu is enabled */
535 cpu = 0;
536 }
537 }
538
539 #ifdef CONFIG_HOTPLUG_CPU
540 static void __cpuinit uv_heartbeat_disable(int cpu)
541 {
542 if (uv_cpu_hub_info(cpu)->scir.enabled) {
543 uv_cpu_hub_info(cpu)->scir.enabled = 0;
544 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
545 }
546 uv_set_cpu_scir_bits(cpu, 0xff);
547 }
548
549 /*
550 * cpu hotplug notifier
551 */
552 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
553 unsigned long action, void *hcpu)
554 {
555 long cpu = (long)hcpu;
556
557 switch (action) {
558 case CPU_ONLINE:
559 uv_heartbeat_enable(cpu);
560 break;
561 case CPU_DOWN_PREPARE:
562 uv_heartbeat_disable(cpu);
563 break;
564 default:
565 break;
566 }
567 return NOTIFY_OK;
568 }
569
570 static __init void uv_scir_register_cpu_notifier(void)
571 {
572 hotcpu_notifier(uv_scir_cpu_notify, 0);
573 }
574
575 #else /* !CONFIG_HOTPLUG_CPU */
576
577 static __init void uv_scir_register_cpu_notifier(void)
578 {
579 }
580
581 static __init int uv_init_heartbeat(void)
582 {
583 int cpu;
584
585 if (is_uv_system())
586 for_each_online_cpu(cpu)
587 uv_heartbeat_enable(cpu);
588 return 0;
589 }
590
591 late_initcall(uv_init_heartbeat);
592
593 #endif /* !CONFIG_HOTPLUG_CPU */
594
595 /* Direct Legacy VGA I/O traffic to designated IOH */
596 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
597 unsigned int command_bits, bool change_bridge)
598 {
599 int domain, bus, rc;
600
601 PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n",
602 pdev->devfn, decode, command_bits, change_bridge);
603
604 if (!change_bridge)
605 return 0;
606
607 if ((command_bits & PCI_COMMAND_IO) == 0)
608 return 0;
609
610 domain = pci_domain_nr(pdev->bus);
611 bus = pdev->bus->number;
612
613 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
614 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
615
616 return rc;
617 }
618
619 /*
620 * Called on each cpu to initialize the per_cpu UV data area.
621 * FIXME: hotplug not supported yet
622 */
623 void __cpuinit uv_cpu_init(void)
624 {
625 /* CPU 0 initilization will be done via uv_system_init. */
626 if (!uv_blade_info)
627 return;
628
629 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
630
631 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
632 set_x2apic_extra_bits(uv_hub_info->pnode);
633 }
634
635 /*
636 * When NMI is received, print a stack trace.
637 */
638 int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
639 {
640 if (reason != DIE_NMI_IPI)
641 return NOTIFY_OK;
642
643 if (in_crash_kexec)
644 /* do nothing if entering the crash kernel */
645 return NOTIFY_OK;
646 /*
647 * Use a lock so only one cpu prints at a time
648 * to prevent intermixed output.
649 */
650 spin_lock(&uv_nmi_lock);
651 pr_info("NMI stack dump cpu %u:\n", smp_processor_id());
652 dump_stack();
653 spin_unlock(&uv_nmi_lock);
654
655 return NOTIFY_STOP;
656 }
657
658 static struct notifier_block uv_dump_stack_nmi_nb = {
659 .notifier_call = uv_handle_nmi
660 };
661
662 void uv_register_nmi_notifier(void)
663 {
664 if (register_die_notifier(&uv_dump_stack_nmi_nb))
665 printk(KERN_WARNING "UV NMI handler failed to register\n");
666 }
667
668 void uv_nmi_init(void)
669 {
670 unsigned int value;
671
672 /*
673 * Unmask NMI on all cpus
674 */
675 value = apic_read(APIC_LVT1) | APIC_DM_NMI;
676 value &= ~APIC_LVT_MASKED;
677 apic_write(APIC_LVT1, value);
678 }
679
680 void __init uv_system_init(void)
681 {
682 union uvh_rh_gam_config_mmr_u m_n_config;
683 union uvh_node_id_u node_id;
684 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
685 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
686 int gnode_extra, max_pnode = 0;
687 unsigned long mmr_base, present, paddr;
688 unsigned short pnode_mask;
689
690 map_low_mmrs();
691
692 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
693 m_val = m_n_config.s.m_skt;
694 n_val = m_n_config.s.n_skt;
695 mmr_base =
696 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
697 ~UV_MMR_ENABLE;
698 pnode_mask = (1 << n_val) - 1;
699 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
700 gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
701 gnode_upper = ((unsigned long)gnode_extra << m_val);
702 printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
703 n_val, m_val, gnode_upper, gnode_extra);
704
705 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
706
707 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
708 uv_possible_blades +=
709 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
710 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
711
712 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
713 uv_blade_info = kmalloc(bytes, GFP_KERNEL);
714 BUG_ON(!uv_blade_info);
715 for (blade = 0; blade < uv_num_possible_blades(); blade++)
716 uv_blade_info[blade].memory_nid = -1;
717
718 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
719
720 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
721 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
722 BUG_ON(!uv_node_to_blade);
723 memset(uv_node_to_blade, 255, bytes);
724
725 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
726 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
727 BUG_ON(!uv_cpu_to_blade);
728 memset(uv_cpu_to_blade, 255, bytes);
729
730 blade = 0;
731 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
732 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
733 for (j = 0; j < 64; j++) {
734 if (!test_bit(j, &present))
735 continue;
736 pnode = (i * 64 + j);
737 uv_blade_info[blade].pnode = pnode;
738 uv_blade_info[blade].nr_possible_cpus = 0;
739 uv_blade_info[blade].nr_online_cpus = 0;
740 max_pnode = max(pnode, max_pnode);
741 blade++;
742 }
743 }
744
745 uv_bios_init();
746 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
747 &sn_region_size, &system_serial_number);
748 uv_rtc_init();
749
750 for_each_present_cpu(cpu) {
751 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
752
753 nid = cpu_to_node(cpu);
754 /*
755 * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
756 */
757 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
758 pnode = uv_apicid_to_pnode(apicid);
759 blade = boot_pnode_to_blade(pnode);
760 lcpu = uv_blade_info[blade].nr_possible_cpus;
761 uv_blade_info[blade].nr_possible_cpus++;
762
763 /* Any node on the blade, else will contain -1. */
764 uv_blade_info[blade].memory_nid = nid;
765
766 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
767 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
768 uv_cpu_hub_info(cpu)->m_val = m_val;
769 uv_cpu_hub_info(cpu)->n_val = n_val;
770 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
771 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
772 uv_cpu_hub_info(cpu)->pnode = pnode;
773 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
774 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
775 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
776 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
777 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
778 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
779 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
780 uv_node_to_blade[nid] = blade;
781 uv_cpu_to_blade[cpu] = blade;
782 }
783
784 /* Add blade/pnode info for nodes without cpus */
785 for_each_online_node(nid) {
786 if (uv_node_to_blade[nid] >= 0)
787 continue;
788 paddr = node_start_pfn(nid) << PAGE_SHIFT;
789 paddr = uv_soc_phys_ram_to_gpa(paddr);
790 pnode = (paddr >> m_val) & pnode_mask;
791 blade = boot_pnode_to_blade(pnode);
792 uv_node_to_blade[nid] = blade;
793 }
794
795 map_gru_high(max_pnode);
796 map_mmr_high(max_pnode);
797 map_mmioh_high(max_pnode);
798
799 uv_cpu_init();
800 uv_scir_register_cpu_notifier();
801 uv_register_nmi_notifier();
802 proc_mkdir("sgi_uv", NULL);
803
804 /* register Legacy VGA I/O redirection handler */
805 pci_register_set_vga_state(uv_set_vga_state);
806 }
(deprecated) Btrfs devel tree