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soc/qman: Remove redundant checks from qman_create_cgr()
[linux-2.6/btrfs-unstable.git] / drivers / soc / fsl / qbman / qman.c
blob4a1697eefcdfc59da3a2ef05bb34a3800a6116b7
1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are met:
5 * * Redistributions of source code must retain the above copyright
6 * notice, this list of conditions and the following disclaimer.
7 * * Redistributions in binary form must reproduce the above copyright
8 * notice, this list of conditions and the following disclaimer in the
9 * documentation and/or other materials provided with the distribution.
10 * * Neither the name of Freescale Semiconductor nor the
11 * names of its contributors may be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * ALTERNATIVELY, this software may be distributed under the terms of the
15 * GNU General Public License ("GPL") as published by the Free Software
16 * Foundation, either version 2 of that License or (at your option) any
17 * later version.
18 *
19 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "qman_priv.h"
32
33 #define DQRR_MAXFILL 15
34 #define EQCR_ITHRESH 4 /* if EQCR congests, interrupt threshold */
35 #define IRQNAME "QMan portal %d"
36 #define MAX_IRQNAME 16 /* big enough for "QMan portal %d" */
37 #define QMAN_POLL_LIMIT 32
38 #define QMAN_PIRQ_DQRR_ITHRESH 12
39 #define QMAN_PIRQ_MR_ITHRESH 4
40 #define QMAN_PIRQ_IPERIOD 100
41
42 /* Portal register assists */
43
44 /* Cache-inhibited register offsets */
45 #define QM_REG_EQCR_PI_CINH 0x0000
46 #define QM_REG_EQCR_CI_CINH 0x0004
47 #define QM_REG_EQCR_ITR 0x0008
48 #define QM_REG_DQRR_PI_CINH 0x0040
49 #define QM_REG_DQRR_CI_CINH 0x0044
50 #define QM_REG_DQRR_ITR 0x0048
51 #define QM_REG_DQRR_DCAP 0x0050
52 #define QM_REG_DQRR_SDQCR 0x0054
53 #define QM_REG_DQRR_VDQCR 0x0058
54 #define QM_REG_DQRR_PDQCR 0x005c
55 #define QM_REG_MR_PI_CINH 0x0080
56 #define QM_REG_MR_CI_CINH 0x0084
57 #define QM_REG_MR_ITR 0x0088
58 #define QM_REG_CFG 0x0100
59 #define QM_REG_ISR 0x0e00
60 #define QM_REG_IER 0x0e04
61 #define QM_REG_ISDR 0x0e08
62 #define QM_REG_IIR 0x0e0c
63 #define QM_REG_ITPR 0x0e14
64
65 /* Cache-enabled register offsets */
66 #define QM_CL_EQCR 0x0000
67 #define QM_CL_DQRR 0x1000
68 #define QM_CL_MR 0x2000
69 #define QM_CL_EQCR_PI_CENA 0x3000
70 #define QM_CL_EQCR_CI_CENA 0x3100
71 #define QM_CL_DQRR_PI_CENA 0x3200
72 #define QM_CL_DQRR_CI_CENA 0x3300
73 #define QM_CL_MR_PI_CENA 0x3400
74 #define QM_CL_MR_CI_CENA 0x3500
75 #define QM_CL_CR 0x3800
76 #define QM_CL_RR0 0x3900
77 #define QM_CL_RR1 0x3940
78
79 /*
80 * BTW, the drivers (and h/w programming model) already obtain the required
81 * synchronisation for portal accesses and data-dependencies. Use of barrier()s
82 * or other order-preserving primitives simply degrade performance. Hence the
83 * use of the __raw_*() interfaces, which simply ensure that the compiler treats
84 * the portal registers as volatile
85 */
86
87 /* Cache-enabled ring access */
88 #define qm_cl(base, idx) ((void *)base + ((idx) << 6))
89
90 /*
91 * Portal modes.
92 * Enum types;
93 * pmode == production mode
94 * cmode == consumption mode,
95 * dmode == h/w dequeue mode.
96 * Enum values use 3 letter codes. First letter matches the portal mode,
97 * remaining two letters indicate;
98 * ci == cache-inhibited portal register
99 * ce == cache-enabled portal register
100 * vb == in-band valid-bit (cache-enabled)
101 * dc == DCA (Discrete Consumption Acknowledgment), DQRR-only
102 * As for "enum qm_dqrr_dmode", it should be self-explanatory.
103 */
104 enum qm_eqcr_pmode { /* matches QCSP_CFG::EPM */
105 qm_eqcr_pci = 0, /* PI index, cache-inhibited */
106 qm_eqcr_pce = 1, /* PI index, cache-enabled */
107 qm_eqcr_pvb = 2 /* valid-bit */
108 };
109 enum qm_dqrr_dmode { /* matches QCSP_CFG::DP */
110 qm_dqrr_dpush = 0, /* SDQCR + VDQCR */
111 qm_dqrr_dpull = 1 /* PDQCR */
112 };
113 enum qm_dqrr_pmode { /* s/w-only */
114 qm_dqrr_pci, /* reads DQRR_PI_CINH */
115 qm_dqrr_pce, /* reads DQRR_PI_CENA */
116 qm_dqrr_pvb /* reads valid-bit */
117 };
118 enum qm_dqrr_cmode { /* matches QCSP_CFG::DCM */
119 qm_dqrr_cci = 0, /* CI index, cache-inhibited */
120 qm_dqrr_cce = 1, /* CI index, cache-enabled */
121 qm_dqrr_cdc = 2 /* Discrete Consumption Acknowledgment */
122 };
123 enum qm_mr_pmode { /* s/w-only */
124 qm_mr_pci, /* reads MR_PI_CINH */
125 qm_mr_pce, /* reads MR_PI_CENA */
126 qm_mr_pvb /* reads valid-bit */
127 };
128 enum qm_mr_cmode { /* matches QCSP_CFG::MM */
129 qm_mr_cci = 0, /* CI index, cache-inhibited */
130 qm_mr_cce = 1 /* CI index, cache-enabled */
131 };
132
133 /* --- Portal structures --- */
134
135 #define QM_EQCR_SIZE 8
136 #define QM_DQRR_SIZE 16
137 #define QM_MR_SIZE 8
138
139 /* "Enqueue Command" */
140 struct qm_eqcr_entry {
141 u8 _ncw_verb; /* writes to this are non-coherent */
142 u8 dca;
143 u16 seqnum;
144 u32 orp; /* 24-bit */
145 u32 fqid; /* 24-bit */
146 u32 tag;
147 struct qm_fd fd;
148 u8 __reserved3[32];
149 } __packed;
150 #define QM_EQCR_VERB_VBIT 0x80
151 #define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */
152 #define QM_EQCR_VERB_CMD_ENQUEUE 0x01
153 #define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */
154 #define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */
155 #define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */
156
157 struct qm_eqcr {
158 struct qm_eqcr_entry *ring, *cursor;
159 u8 ci, available, ithresh, vbit;
160 #ifdef CONFIG_FSL_DPAA_CHECKING
161 u32 busy;
162 enum qm_eqcr_pmode pmode;
163 #endif
164 };
165
166 struct qm_dqrr {
167 const struct qm_dqrr_entry *ring, *cursor;
168 u8 pi, ci, fill, ithresh, vbit;
169 #ifdef CONFIG_FSL_DPAA_CHECKING
170 enum qm_dqrr_dmode dmode;
171 enum qm_dqrr_pmode pmode;
172 enum qm_dqrr_cmode cmode;
173 #endif
174 };
175
176 struct qm_mr {
177 union qm_mr_entry *ring, *cursor;
178 u8 pi, ci, fill, ithresh, vbit;
179 #ifdef CONFIG_FSL_DPAA_CHECKING
180 enum qm_mr_pmode pmode;
181 enum qm_mr_cmode cmode;
182 #endif
183 };
184
185 /* MC (Management Command) command */
186 /* "Query FQ" */
187 struct qm_mcc_queryfq {
188 u8 _ncw_verb;
189 u8 __reserved1[3];
190 u32 fqid; /* 24-bit */
191 u8 __reserved2[56];
192 } __packed;
193 /* "Alter FQ State Commands " */
194 struct qm_mcc_alterfq {
195 u8 _ncw_verb;
196 u8 __reserved1[3];
197 u32 fqid; /* 24-bit */
198 u8 __reserved2;
199 u8 count; /* number of consecutive FQID */
200 u8 __reserved3[10];
201 u32 context_b; /* frame queue context b */
202 u8 __reserved4[40];
203 } __packed;
204
205 /* "Query CGR" */
206 struct qm_mcc_querycgr {
207 u8 _ncw_verb;
208 u8 __reserved1[30];
209 u8 cgid;
210 u8 __reserved2[32];
211 };
212
213 struct qm_mcc_querywq {
214 u8 _ncw_verb;
215 u8 __reserved;
216 /* select channel if verb != QUERYWQ_DEDICATED */
217 u16 channel_wq; /* ignores wq (3 lsbits): _res[0-2] */
218 u8 __reserved2[60];
219 } __packed;
220
221 #define QM_MCC_VERB_VBIT 0x80
222 #define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */
223 #define QM_MCC_VERB_INITFQ_PARKED 0x40
224 #define QM_MCC_VERB_INITFQ_SCHED 0x41
225 #define QM_MCC_VERB_QUERYFQ 0x44
226 #define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */
227 #define QM_MCC_VERB_QUERYWQ 0x46
228 #define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47
229 #define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */
230 #define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */
231 #define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */
232 #define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */
233 #define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */
234 #define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */
235 #define QM_MCC_VERB_INITCGR 0x50
236 #define QM_MCC_VERB_MODIFYCGR 0x51
237 #define QM_MCC_VERB_CGRTESTWRITE 0x52
238 #define QM_MCC_VERB_QUERYCGR 0x58
239 #define QM_MCC_VERB_QUERYCONGESTION 0x59
240 union qm_mc_command {
241 struct {
242 u8 _ncw_verb; /* writes to this are non-coherent */
243 u8 __reserved[63];
244 };
245 struct qm_mcc_initfq initfq;
246 struct qm_mcc_queryfq queryfq;
247 struct qm_mcc_alterfq alterfq;
248 struct qm_mcc_initcgr initcgr;
249 struct qm_mcc_querycgr querycgr;
250 struct qm_mcc_querywq querywq;
251 struct qm_mcc_queryfq_np queryfq_np;
252 };
253
254 /* MC (Management Command) result */
255 /* "Query FQ" */
256 struct qm_mcr_queryfq {
257 u8 verb;
258 u8 result;
259 u8 __reserved1[8];
260 struct qm_fqd fqd; /* the FQD fields are here */
261 u8 __reserved2[30];
262 } __packed;
263
264 /* "Alter FQ State Commands" */
265 struct qm_mcr_alterfq {
266 u8 verb;
267 u8 result;
268 u8 fqs; /* Frame Queue Status */
269 u8 __reserved1[61];
270 };
271 #define QM_MCR_VERB_RRID 0x80
272 #define QM_MCR_VERB_MASK QM_MCC_VERB_MASK
273 #define QM_MCR_VERB_INITFQ_PARKED QM_MCC_VERB_INITFQ_PARKED
274 #define QM_MCR_VERB_INITFQ_SCHED QM_MCC_VERB_INITFQ_SCHED
275 #define QM_MCR_VERB_QUERYFQ QM_MCC_VERB_QUERYFQ
276 #define QM_MCR_VERB_QUERYFQ_NP QM_MCC_VERB_QUERYFQ_NP
277 #define QM_MCR_VERB_QUERYWQ QM_MCC_VERB_QUERYWQ
278 #define QM_MCR_VERB_QUERYWQ_DEDICATED QM_MCC_VERB_QUERYWQ_DEDICATED
279 #define QM_MCR_VERB_ALTER_SCHED QM_MCC_VERB_ALTER_SCHED
280 #define QM_MCR_VERB_ALTER_FE QM_MCC_VERB_ALTER_FE
281 #define QM_MCR_VERB_ALTER_RETIRE QM_MCC_VERB_ALTER_RETIRE
282 #define QM_MCR_VERB_ALTER_OOS QM_MCC_VERB_ALTER_OOS
283 #define QM_MCR_RESULT_NULL 0x00
284 #define QM_MCR_RESULT_OK 0xf0
285 #define QM_MCR_RESULT_ERR_FQID 0xf1
286 #define QM_MCR_RESULT_ERR_FQSTATE 0xf2
287 #define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */
288 #define QM_MCR_RESULT_ERR_BADCHANNEL 0xf4
289 #define QM_MCR_RESULT_PENDING 0xf8
290 #define QM_MCR_RESULT_ERR_BADCOMMAND 0xff
291 #define QM_MCR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */
292 #define QM_MCR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */
293 #define QM_MCR_TIMEOUT 10000 /* us */
294 union qm_mc_result {
295 struct {
296 u8 verb;
297 u8 result;
298 u8 __reserved1[62];
299 };
300 struct qm_mcr_queryfq queryfq;
301 struct qm_mcr_alterfq alterfq;
302 struct qm_mcr_querycgr querycgr;
303 struct qm_mcr_querycongestion querycongestion;
304 struct qm_mcr_querywq querywq;
305 struct qm_mcr_queryfq_np queryfq_np;
306 };
307
308 struct qm_mc {
309 union qm_mc_command *cr;
310 union qm_mc_result *rr;
311 u8 rridx, vbit;
312 #ifdef CONFIG_FSL_DPAA_CHECKING
313 enum {
314 /* Can be _mc_start()ed */
315 qman_mc_idle,
316 /* Can be _mc_commit()ed or _mc_abort()ed */
317 qman_mc_user,
318 /* Can only be _mc_retry()ed */
319 qman_mc_hw
320 } state;
321 #endif
322 };
323
324 struct qm_addr {
325 void __iomem *ce; /* cache-enabled */
326 void __iomem *ci; /* cache-inhibited */
327 };
328
329 struct qm_portal {
330 /*
331 * In the non-CONFIG_FSL_DPAA_CHECKING case, the following stuff up to
332 * and including 'mc' fits within a cacheline (yay!). The 'config' part
333 * is setup-only, so isn't a cause for a concern. In other words, don't
334 * rearrange this structure on a whim, there be dragons ...
335 */
336 struct qm_addr addr;
337 struct qm_eqcr eqcr;
338 struct qm_dqrr dqrr;
339 struct qm_mr mr;
340 struct qm_mc mc;
341 } ____cacheline_aligned;
342
343 /* Cache-inhibited register access. */
344 static inline u32 qm_in(struct qm_portal *p, u32 offset)
345 {
346 return __raw_readl(p->addr.ci + offset);
347 }
348
349 static inline void qm_out(struct qm_portal *p, u32 offset, u32 val)
350 {
351 __raw_writel(val, p->addr.ci + offset);
352 }
353
354 /* Cache Enabled Portal Access */
355 static inline void qm_cl_invalidate(struct qm_portal *p, u32 offset)
356 {
357 dpaa_invalidate(p->addr.ce + offset);
358 }
359
360 static inline void qm_cl_touch_ro(struct qm_portal *p, u32 offset)
361 {
362 dpaa_touch_ro(p->addr.ce + offset);
363 }
364
365 static inline u32 qm_ce_in(struct qm_portal *p, u32 offset)
366 {
367 return __raw_readl(p->addr.ce + offset);
368 }
369
370 /* --- EQCR API --- */
371
372 #define EQCR_SHIFT ilog2(sizeof(struct qm_eqcr_entry))
373 #define EQCR_CARRY (uintptr_t)(QM_EQCR_SIZE << EQCR_SHIFT)
374
375 /* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
376 static struct qm_eqcr_entry *eqcr_carryclear(struct qm_eqcr_entry *p)
377 {
378 uintptr_t addr = (uintptr_t)p;
379
380 addr &= ~EQCR_CARRY;
381
382 return (struct qm_eqcr_entry *)addr;
383 }
384
385 /* Bit-wise logic to convert a ring pointer to a ring index */
386 static int eqcr_ptr2idx(struct qm_eqcr_entry *e)
387 {
388 return ((uintptr_t)e >> EQCR_SHIFT) & (QM_EQCR_SIZE - 1);
389 }
390
391 /* Increment the 'cursor' ring pointer, taking 'vbit' into account */
392 static inline void eqcr_inc(struct qm_eqcr *eqcr)
393 {
394 /* increment to the next EQCR pointer and handle overflow and 'vbit' */
395 struct qm_eqcr_entry *partial = eqcr->cursor + 1;
396
397 eqcr->cursor = eqcr_carryclear(partial);
398 if (partial != eqcr->cursor)
399 eqcr->vbit ^= QM_EQCR_VERB_VBIT;
400 }
401
402 static inline int qm_eqcr_init(struct qm_portal *portal,
403 enum qm_eqcr_pmode pmode,
404 unsigned int eq_stash_thresh,
405 int eq_stash_prio)
406 {
407 struct qm_eqcr *eqcr = &portal->eqcr;
408 u32 cfg;
409 u8 pi;
410
411 eqcr->ring = portal->addr.ce + QM_CL_EQCR;
412 eqcr->ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
413 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
414 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
415 eqcr->cursor = eqcr->ring + pi;
416 eqcr->vbit = (qm_in(portal, QM_REG_EQCR_PI_CINH) & QM_EQCR_SIZE) ?
417 QM_EQCR_VERB_VBIT : 0;
418 eqcr->available = QM_EQCR_SIZE - 1 -
419 dpaa_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi);
420 eqcr->ithresh = qm_in(portal, QM_REG_EQCR_ITR);
421 #ifdef CONFIG_FSL_DPAA_CHECKING
422 eqcr->busy = 0;
423 eqcr->pmode = pmode;
424 #endif
425 cfg = (qm_in(portal, QM_REG_CFG) & 0x00ffffff) |
426 (eq_stash_thresh << 28) | /* QCSP_CFG: EST */
427 (eq_stash_prio << 26) | /* QCSP_CFG: EP */
428 ((pmode & 0x3) << 24); /* QCSP_CFG::EPM */
429 qm_out(portal, QM_REG_CFG, cfg);
430 return 0;
431 }
432
433 static inline unsigned int qm_eqcr_get_ci_stashing(struct qm_portal *portal)
434 {
435 return (qm_in(portal, QM_REG_CFG) >> 28) & 0x7;
436 }
437
438 static inline void qm_eqcr_finish(struct qm_portal *portal)
439 {
440 struct qm_eqcr *eqcr = &portal->eqcr;
441 u8 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
442 u8 ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
443
444 DPAA_ASSERT(!eqcr->busy);
445 if (pi != eqcr_ptr2idx(eqcr->cursor))
446 pr_crit("losing uncommitted EQCR entries\n");
447 if (ci != eqcr->ci)
448 pr_crit("missing existing EQCR completions\n");
449 if (eqcr->ci != eqcr_ptr2idx(eqcr->cursor))
450 pr_crit("EQCR destroyed unquiesced\n");
451 }
452
453 static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal
454 *portal)
455 {
456 struct qm_eqcr *eqcr = &portal->eqcr;
457
458 DPAA_ASSERT(!eqcr->busy);
459 if (!eqcr->available)
460 return NULL;
461
462 #ifdef CONFIG_FSL_DPAA_CHECKING
463 eqcr->busy = 1;
464 #endif
465 dpaa_zero(eqcr->cursor);
466 return eqcr->cursor;
467 }
468
469 static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal
470 *portal)
471 {
472 struct qm_eqcr *eqcr = &portal->eqcr;
473 u8 diff, old_ci;
474
475 DPAA_ASSERT(!eqcr->busy);
476 if (!eqcr->available) {
477 old_ci = eqcr->ci;
478 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) &
479 (QM_EQCR_SIZE - 1);
480 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
481 eqcr->available += diff;
482 if (!diff)
483 return NULL;
484 }
485 #ifdef CONFIG_FSL_DPAA_CHECKING
486 eqcr->busy = 1;
487 #endif
488 dpaa_zero(eqcr->cursor);
489 return eqcr->cursor;
490 }
491
492 static inline void eqcr_commit_checks(struct qm_eqcr *eqcr)
493 {
494 DPAA_ASSERT(eqcr->busy);
495 DPAA_ASSERT(eqcr->cursor->orp == (eqcr->cursor->orp & 0x00ffffff));
496 DPAA_ASSERT(eqcr->cursor->fqid == (eqcr->cursor->fqid & 0x00ffffff));
497 DPAA_ASSERT(eqcr->available >= 1);
498 }
499
500 static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb)
501 {
502 struct qm_eqcr *eqcr = &portal->eqcr;
503 struct qm_eqcr_entry *eqcursor;
504
505 eqcr_commit_checks(eqcr);
506 DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb);
507 dma_wmb();
508 eqcursor = eqcr->cursor;
509 eqcursor->_ncw_verb = myverb | eqcr->vbit;
510 dpaa_flush(eqcursor);
511 eqcr_inc(eqcr);
512 eqcr->available--;
513 #ifdef CONFIG_FSL_DPAA_CHECKING
514 eqcr->busy = 0;
515 #endif
516 }
517
518 static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal)
519 {
520 qm_cl_touch_ro(portal, QM_CL_EQCR_CI_CENA);
521 }
522
523 static inline u8 qm_eqcr_cce_update(struct qm_portal *portal)
524 {
525 struct qm_eqcr *eqcr = &portal->eqcr;
526 u8 diff, old_ci = eqcr->ci;
527
528 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) & (QM_EQCR_SIZE - 1);
529 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
530 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
531 eqcr->available += diff;
532 return diff;
533 }
534
535 static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh)
536 {
537 struct qm_eqcr *eqcr = &portal->eqcr;
538
539 eqcr->ithresh = ithresh;
540 qm_out(portal, QM_REG_EQCR_ITR, ithresh);
541 }
542
543 static inline u8 qm_eqcr_get_avail(struct qm_portal *portal)
544 {
545 struct qm_eqcr *eqcr = &portal->eqcr;
546
547 return eqcr->available;
548 }
549
550 static inline u8 qm_eqcr_get_fill(struct qm_portal *portal)
551 {
552 struct qm_eqcr *eqcr = &portal->eqcr;
553
554 return QM_EQCR_SIZE - 1 - eqcr->available;
555 }
556
557 /* --- DQRR API --- */
558
559 #define DQRR_SHIFT ilog2(sizeof(struct qm_dqrr_entry))
560 #define DQRR_CARRY (uintptr_t)(QM_DQRR_SIZE << DQRR_SHIFT)
561
562 static const struct qm_dqrr_entry *dqrr_carryclear(
563 const struct qm_dqrr_entry *p)
564 {
565 uintptr_t addr = (uintptr_t)p;
566
567 addr &= ~DQRR_CARRY;
568
569 return (const struct qm_dqrr_entry *)addr;
570 }
571
572 static inline int dqrr_ptr2idx(const struct qm_dqrr_entry *e)
573 {
574 return ((uintptr_t)e >> DQRR_SHIFT) & (QM_DQRR_SIZE - 1);
575 }
576
577 static const struct qm_dqrr_entry *dqrr_inc(const struct qm_dqrr_entry *e)
578 {
579 return dqrr_carryclear(e + 1);
580 }
581
582 static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf)
583 {
584 qm_out(portal, QM_REG_CFG, (qm_in(portal, QM_REG_CFG) & 0xff0fffff) |
585 ((mf & (QM_DQRR_SIZE - 1)) << 20));
586 }
587
588 static inline int qm_dqrr_init(struct qm_portal *portal,
589 const struct qm_portal_config *config,
590 enum qm_dqrr_dmode dmode,
591 enum qm_dqrr_pmode pmode,
592 enum qm_dqrr_cmode cmode, u8 max_fill)
593 {
594 struct qm_dqrr *dqrr = &portal->dqrr;
595 u32 cfg;
596
597 /* Make sure the DQRR will be idle when we enable */
598 qm_out(portal, QM_REG_DQRR_SDQCR, 0);
599 qm_out(portal, QM_REG_DQRR_VDQCR, 0);
600 qm_out(portal, QM_REG_DQRR_PDQCR, 0);
601 dqrr->ring = portal->addr.ce + QM_CL_DQRR;
602 dqrr->pi = qm_in(portal, QM_REG_DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
603 dqrr->ci = qm_in(portal, QM_REG_DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
604 dqrr->cursor = dqrr->ring + dqrr->ci;
605 dqrr->fill = dpaa_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi);
606 dqrr->vbit = (qm_in(portal, QM_REG_DQRR_PI_CINH) & QM_DQRR_SIZE) ?
607 QM_DQRR_VERB_VBIT : 0;
608 dqrr->ithresh = qm_in(portal, QM_REG_DQRR_ITR);
609 #ifdef CONFIG_FSL_DPAA_CHECKING
610 dqrr->dmode = dmode;
611 dqrr->pmode = pmode;
612 dqrr->cmode = cmode;
613 #endif
614 /* Invalidate every ring entry before beginning */
615 for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++)
616 dpaa_invalidate(qm_cl(dqrr->ring, cfg));
617 cfg = (qm_in(portal, QM_REG_CFG) & 0xff000f00) |
618 ((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */
619 ((dmode & 1) << 18) | /* DP */
620 ((cmode & 3) << 16) | /* DCM */
621 0xa0 | /* RE+SE */
622 (0 ? 0x40 : 0) | /* Ignore RP */
623 (0 ? 0x10 : 0); /* Ignore SP */
624 qm_out(portal, QM_REG_CFG, cfg);
625 qm_dqrr_set_maxfill(portal, max_fill);
626 return 0;
627 }
628
629 static inline void qm_dqrr_finish(struct qm_portal *portal)
630 {
631 #ifdef CONFIG_FSL_DPAA_CHECKING
632 struct qm_dqrr *dqrr = &portal->dqrr;
633
634 if (dqrr->cmode != qm_dqrr_cdc &&
635 dqrr->ci != dqrr_ptr2idx(dqrr->cursor))
636 pr_crit("Ignoring completed DQRR entries\n");
637 #endif
638 }
639
640 static inline const struct qm_dqrr_entry *qm_dqrr_current(
641 struct qm_portal *portal)
642 {
643 struct qm_dqrr *dqrr = &portal->dqrr;
644
645 if (!dqrr->fill)
646 return NULL;
647 return dqrr->cursor;
648 }
649
650 static inline u8 qm_dqrr_next(struct qm_portal *portal)
651 {
652 struct qm_dqrr *dqrr = &portal->dqrr;
653
654 DPAA_ASSERT(dqrr->fill);
655 dqrr->cursor = dqrr_inc(dqrr->cursor);
656 return --dqrr->fill;
657 }
658
659 static inline void qm_dqrr_pvb_update(struct qm_portal *portal)
660 {
661 struct qm_dqrr *dqrr = &portal->dqrr;
662 struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi);
663
664 DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb);
665 #ifndef CONFIG_FSL_PAMU
666 /*
667 * If PAMU is not available we need to invalidate the cache.
668 * When PAMU is available the cache is updated by stash
669 */
670 dpaa_invalidate_touch_ro(res);
671 #endif
672 /*
673 * when accessing 'verb', use __raw_readb() to ensure that compiler
674 * inlining doesn't try to optimise out "excess reads".
675 */
676 if ((__raw_readb(&res->verb) & QM_DQRR_VERB_VBIT) == dqrr->vbit) {
677 dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1);
678 if (!dqrr->pi)
679 dqrr->vbit ^= QM_DQRR_VERB_VBIT;
680 dqrr->fill++;
681 }
682 }
683
684 static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal,
685 const struct qm_dqrr_entry *dq,
686 int park)
687 {
688 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
689 int idx = dqrr_ptr2idx(dq);
690
691 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
692 DPAA_ASSERT((dqrr->ring + idx) == dq);
693 DPAA_ASSERT(idx < QM_DQRR_SIZE);
694 qm_out(portal, QM_REG_DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */
695 ((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */
696 idx); /* DQRR_DCAP::DCAP_CI */
697 }
698
699 static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u32 bitmask)
700 {
701 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
702
703 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
704 qm_out(portal, QM_REG_DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */
705 (bitmask << 16)); /* DQRR_DCAP::DCAP_CI */
706 }
707
708 static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr)
709 {
710 qm_out(portal, QM_REG_DQRR_SDQCR, sdqcr);
711 }
712
713 static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr)
714 {
715 qm_out(portal, QM_REG_DQRR_VDQCR, vdqcr);
716 }
717
718 static inline void qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh)
719 {
720 qm_out(portal, QM_REG_DQRR_ITR, ithresh);
721 }
722
723 /* --- MR API --- */
724
725 #define MR_SHIFT ilog2(sizeof(union qm_mr_entry))
726 #define MR_CARRY (uintptr_t)(QM_MR_SIZE << MR_SHIFT)
727
728 static union qm_mr_entry *mr_carryclear(union qm_mr_entry *p)
729 {
730 uintptr_t addr = (uintptr_t)p;
731
732 addr &= ~MR_CARRY;
733
734 return (union qm_mr_entry *)addr;
735 }
736
737 static inline int mr_ptr2idx(const union qm_mr_entry *e)
738 {
739 return ((uintptr_t)e >> MR_SHIFT) & (QM_MR_SIZE - 1);
740 }
741
742 static inline union qm_mr_entry *mr_inc(union qm_mr_entry *e)
743 {
744 return mr_carryclear(e + 1);
745 }
746
747 static inline int qm_mr_init(struct qm_portal *portal, enum qm_mr_pmode pmode,
748 enum qm_mr_cmode cmode)
749 {
750 struct qm_mr *mr = &portal->mr;
751 u32 cfg;
752
753 mr->ring = portal->addr.ce + QM_CL_MR;
754 mr->pi = qm_in(portal, QM_REG_MR_PI_CINH) & (QM_MR_SIZE - 1);
755 mr->ci = qm_in(portal, QM_REG_MR_CI_CINH) & (QM_MR_SIZE - 1);
756 mr->cursor = mr->ring + mr->ci;
757 mr->fill = dpaa_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi);
758 mr->vbit = (qm_in(portal, QM_REG_MR_PI_CINH) & QM_MR_SIZE)
759 ? QM_MR_VERB_VBIT : 0;
760 mr->ithresh = qm_in(portal, QM_REG_MR_ITR);
761 #ifdef CONFIG_FSL_DPAA_CHECKING
762 mr->pmode = pmode;
763 mr->cmode = cmode;
764 #endif
765 cfg = (qm_in(portal, QM_REG_CFG) & 0xfffff0ff) |
766 ((cmode & 1) << 8); /* QCSP_CFG:MM */
767 qm_out(portal, QM_REG_CFG, cfg);
768 return 0;
769 }
770
771 static inline void qm_mr_finish(struct qm_portal *portal)
772 {
773 struct qm_mr *mr = &portal->mr;
774
775 if (mr->ci != mr_ptr2idx(mr->cursor))
776 pr_crit("Ignoring completed MR entries\n");
777 }
778
779 static inline const union qm_mr_entry *qm_mr_current(struct qm_portal *portal)
780 {
781 struct qm_mr *mr = &portal->mr;
782
783 if (!mr->fill)
784 return NULL;
785 return mr->cursor;
786 }
787
788 static inline int qm_mr_next(struct qm_portal *portal)
789 {
790 struct qm_mr *mr = &portal->mr;
791
792 DPAA_ASSERT(mr->fill);
793 mr->cursor = mr_inc(mr->cursor);
794 return --mr->fill;
795 }
796
797 static inline void qm_mr_pvb_update(struct qm_portal *portal)
798 {
799 struct qm_mr *mr = &portal->mr;
800 union qm_mr_entry *res = qm_cl(mr->ring, mr->pi);
801
802 DPAA_ASSERT(mr->pmode == qm_mr_pvb);
803 /*
804 * when accessing 'verb', use __raw_readb() to ensure that compiler
805 * inlining doesn't try to optimise out "excess reads".
806 */
807 if ((__raw_readb(&res->verb) & QM_MR_VERB_VBIT) == mr->vbit) {
808 mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1);
809 if (!mr->pi)
810 mr->vbit ^= QM_MR_VERB_VBIT;
811 mr->fill++;
812 res = mr_inc(res);
813 }
814 dpaa_invalidate_touch_ro(res);
815 }
816
817 static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num)
818 {
819 struct qm_mr *mr = &portal->mr;
820
821 DPAA_ASSERT(mr->cmode == qm_mr_cci);
822 mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1);
823 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
824 }
825
826 static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal)
827 {
828 struct qm_mr *mr = &portal->mr;
829
830 DPAA_ASSERT(mr->cmode == qm_mr_cci);
831 mr->ci = mr_ptr2idx(mr->cursor);
832 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
833 }
834
835 static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh)
836 {
837 qm_out(portal, QM_REG_MR_ITR, ithresh);
838 }
839
840 /* --- Management command API --- */
841
842 static inline int qm_mc_init(struct qm_portal *portal)
843 {
844 struct qm_mc *mc = &portal->mc;
845
846 mc->cr = portal->addr.ce + QM_CL_CR;
847 mc->rr = portal->addr.ce + QM_CL_RR0;
848 mc->rridx = (__raw_readb(&mc->cr->_ncw_verb) & QM_MCC_VERB_VBIT)
849 ? 0 : 1;
850 mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
851 #ifdef CONFIG_FSL_DPAA_CHECKING
852 mc->state = qman_mc_idle;
853 #endif
854 return 0;
855 }
856
857 static inline void qm_mc_finish(struct qm_portal *portal)
858 {
859 #ifdef CONFIG_FSL_DPAA_CHECKING
860 struct qm_mc *mc = &portal->mc;
861
862 DPAA_ASSERT(mc->state == qman_mc_idle);
863 if (mc->state != qman_mc_idle)
864 pr_crit("Losing incomplete MC command\n");
865 #endif
866 }
867
868 static inline union qm_mc_command *qm_mc_start(struct qm_portal *portal)
869 {
870 struct qm_mc *mc = &portal->mc;
871
872 DPAA_ASSERT(mc->state == qman_mc_idle);
873 #ifdef CONFIG_FSL_DPAA_CHECKING
874 mc->state = qman_mc_user;
875 #endif
876 dpaa_zero(mc->cr);
877 return mc->cr;
878 }
879
880 static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb)
881 {
882 struct qm_mc *mc = &portal->mc;
883 union qm_mc_result *rr = mc->rr + mc->rridx;
884
885 DPAA_ASSERT(mc->state == qman_mc_user);
886 dma_wmb();
887 mc->cr->_ncw_verb = myverb | mc->vbit;
888 dpaa_flush(mc->cr);
889 dpaa_invalidate_touch_ro(rr);
890 #ifdef CONFIG_FSL_DPAA_CHECKING
891 mc->state = qman_mc_hw;
892 #endif
893 }
894
895 static inline union qm_mc_result *qm_mc_result(struct qm_portal *portal)
896 {
897 struct qm_mc *mc = &portal->mc;
898 union qm_mc_result *rr = mc->rr + mc->rridx;
899
900 DPAA_ASSERT(mc->state == qman_mc_hw);
901 /*
902 * The inactive response register's verb byte always returns zero until
903 * its command is submitted and completed. This includes the valid-bit,
904 * in case you were wondering...
905 */
906 if (!__raw_readb(&rr->verb)) {
907 dpaa_invalidate_touch_ro(rr);
908 return NULL;
909 }
910 mc->rridx ^= 1;
911 mc->vbit ^= QM_MCC_VERB_VBIT;
912 #ifdef CONFIG_FSL_DPAA_CHECKING
913 mc->state = qman_mc_idle;
914 #endif
915 return rr;
916 }
917
918 static inline int qm_mc_result_timeout(struct qm_portal *portal,
919 union qm_mc_result **mcr)
920 {
921 int timeout = QM_MCR_TIMEOUT;
922
923 do {
924 *mcr = qm_mc_result(portal);
925 if (*mcr)
926 break;
927 udelay(1);
928 } while (--timeout);
929
930 return timeout;
931 }
932
933 static inline void fq_set(struct qman_fq *fq, u32 mask)
934 {
935 set_bits(mask, &fq->flags);
936 }
937
938 static inline void fq_clear(struct qman_fq *fq, u32 mask)
939 {
940 clear_bits(mask, &fq->flags);
941 }
942
943 static inline int fq_isset(struct qman_fq *fq, u32 mask)
944 {
945 return fq->flags & mask;
946 }
947
948 static inline int fq_isclear(struct qman_fq *fq, u32 mask)
949 {
950 return !(fq->flags & mask);
951 }
952
953 struct qman_portal {
954 struct qm_portal p;
955 /* PORTAL_BITS_*** - dynamic, strictly internal */
956 unsigned long bits;
957 /* interrupt sources processed by portal_isr(), configurable */
958 unsigned long irq_sources;
959 u32 use_eqcr_ci_stashing;
960 /* only 1 volatile dequeue at a time */
961 struct qman_fq *vdqcr_owned;
962 u32 sdqcr;
963 /* probing time config params for cpu-affine portals */
964 const struct qm_portal_config *config;
965 /* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */
966 struct qman_cgrs *cgrs;
967 /* linked-list of CSCN handlers. */
968 struct list_head cgr_cbs;
969 /* list lock */
970 spinlock_t cgr_lock;
971 struct work_struct congestion_work;
972 struct work_struct mr_work;
973 char irqname[MAX_IRQNAME];
974 };
975
976 static cpumask_t affine_mask;
977 static DEFINE_SPINLOCK(affine_mask_lock);
978 static u16 affine_channels[NR_CPUS];
979 static DEFINE_PER_CPU(struct qman_portal, qman_affine_portal);
980 struct qman_portal *affine_portals[NR_CPUS];
981
982 static inline struct qman_portal *get_affine_portal(void)
983 {
984 return &get_cpu_var(qman_affine_portal);
985 }
986
987 static inline void put_affine_portal(void)
988 {
989 put_cpu_var(qman_affine_portal);
990 }
991
992 static struct workqueue_struct *qm_portal_wq;
993
994 int qman_wq_alloc(void)
995 {
996 qm_portal_wq = alloc_workqueue("qman_portal_wq", 0, 1);
997 if (!qm_portal_wq)
998 return -ENOMEM;
999 return 0;
1000 }
1001
1002 /*
1003 * This is what everything can wait on, even if it migrates to a different cpu
1004 * to the one whose affine portal it is waiting on.
1005 */
1006 static DECLARE_WAIT_QUEUE_HEAD(affine_queue);
1007
1008 static struct qman_fq **fq_table;
1009 static u32 num_fqids;
1010
1011 int qman_alloc_fq_table(u32 _num_fqids)
1012 {
1013 num_fqids = _num_fqids;
1014
1015 fq_table = vzalloc(num_fqids * 2 * sizeof(struct qman_fq *));
1016 if (!fq_table)
1017 return -ENOMEM;
1018
1019 pr_debug("Allocated fq lookup table at %p, entry count %u\n",
1020 fq_table, num_fqids * 2);
1021 return 0;
1022 }
1023
1024 static struct qman_fq *idx_to_fq(u32 idx)
1025 {
1026 struct qman_fq *fq;
1027
1028 #ifdef CONFIG_FSL_DPAA_CHECKING
1029 if (WARN_ON(idx >= num_fqids * 2))
1030 return NULL;
1031 #endif
1032 fq = fq_table[idx];
1033 DPAA_ASSERT(!fq || idx == fq->idx);
1034
1035 return fq;
1036 }
1037
1038 /*
1039 * Only returns full-service fq objects, not enqueue-only
1040 * references (QMAN_FQ_FLAG_NO_MODIFY).
1041 */
1042 static struct qman_fq *fqid_to_fq(u32 fqid)
1043 {
1044 return idx_to_fq(fqid * 2);
1045 }
1046
1047 static struct qman_fq *tag_to_fq(u32 tag)
1048 {
1049 #if BITS_PER_LONG == 64
1050 return idx_to_fq(tag);
1051 #else
1052 return (struct qman_fq *)tag;
1053 #endif
1054 }
1055
1056 static u32 fq_to_tag(struct qman_fq *fq)
1057 {
1058 #if BITS_PER_LONG == 64
1059 return fq->idx;
1060 #else
1061 return (u32)fq;
1062 #endif
1063 }
1064
1065 static u32 __poll_portal_slow(struct qman_portal *p, u32 is);
1066 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1067 unsigned int poll_limit);
1068 static void qm_congestion_task(struct work_struct *work);
1069 static void qm_mr_process_task(struct work_struct *work);
1070
1071 static irqreturn_t portal_isr(int irq, void *ptr)
1072 {
1073 struct qman_portal *p = ptr;
1074
1075 u32 clear = QM_DQAVAIL_MASK | p->irq_sources;
1076 u32 is = qm_in(&p->p, QM_REG_ISR) & p->irq_sources;
1077
1078 if (unlikely(!is))
1079 return IRQ_NONE;
1080
1081 /* DQRR-handling if it's interrupt-driven */
1082 if (is & QM_PIRQ_DQRI)
1083 __poll_portal_fast(p, QMAN_POLL_LIMIT);
1084 /* Handling of anything else that's interrupt-driven */
1085 clear |= __poll_portal_slow(p, is);
1086 qm_out(&p->p, QM_REG_ISR, clear);
1087 return IRQ_HANDLED;
1088 }
1089
1090 static int drain_mr_fqrni(struct qm_portal *p)
1091 {
1092 const union qm_mr_entry *msg;
1093 loop:
1094 msg = qm_mr_current(p);
1095 if (!msg) {
1096 /*
1097 * if MR was full and h/w had other FQRNI entries to produce, we
1098 * need to allow it time to produce those entries once the
1099 * existing entries are consumed. A worst-case situation
1100 * (fully-loaded system) means h/w sequencers may have to do 3-4
1101 * other things before servicing the portal's MR pump, each of
1102 * which (if slow) may take ~50 qman cycles (which is ~200
1103 * processor cycles). So rounding up and then multiplying this
1104 * worst-case estimate by a factor of 10, just to be
1105 * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume
1106 * one entry at a time, so h/w has an opportunity to produce new
1107 * entries well before the ring has been fully consumed, so
1108 * we're being *really* paranoid here.
1109 */
1110 u64 now, then = jiffies;
1111
1112 do {
1113 now = jiffies;
1114 } while ((then + 10000) > now);
1115 msg = qm_mr_current(p);
1116 if (!msg)
1117 return 0;
1118 }
1119 if ((msg->verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) {
1120 /* We aren't draining anything but FQRNIs */
1121 pr_err("Found verb 0x%x in MR\n", msg->verb);
1122 return -1;
1123 }
1124 qm_mr_next(p);
1125 qm_mr_cci_consume(p, 1);
1126 goto loop;
1127 }
1128
1129 static int qman_create_portal(struct qman_portal *portal,
1130 const struct qm_portal_config *c,
1131 const struct qman_cgrs *cgrs)
1132 {
1133 struct qm_portal *p;
1134 int ret;
1135 u32 isdr;
1136
1137 p = &portal->p;
1138
1139 #ifdef CONFIG_FSL_PAMU
1140 /* PAMU is required for stashing */
1141 portal->use_eqcr_ci_stashing = ((qman_ip_rev >= QMAN_REV30) ? 1 : 0);
1142 #else
1143 portal->use_eqcr_ci_stashing = 0;
1144 #endif
1145 /*
1146 * prep the low-level portal struct with the mapped addresses from the
1147 * config, everything that follows depends on it and "config" is more
1148 * for (de)reference
1149 */
1150 p->addr.ce = c->addr_virt[DPAA_PORTAL_CE];
1151 p->addr.ci = c->addr_virt[DPAA_PORTAL_CI];
1152 /*
1153 * If CI-stashing is used, the current defaults use a threshold of 3,
1154 * and stash with high-than-DQRR priority.
1155 */
1156 if (qm_eqcr_init(p, qm_eqcr_pvb,
1157 portal->use_eqcr_ci_stashing ? 3 : 0, 1)) {
1158 dev_err(c->dev, "EQCR initialisation failed\n");
1159 goto fail_eqcr;
1160 }
1161 if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
1162 qm_dqrr_cdc, DQRR_MAXFILL)) {
1163 dev_err(c->dev, "DQRR initialisation failed\n");
1164 goto fail_dqrr;
1165 }
1166 if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
1167 dev_err(c->dev, "MR initialisation failed\n");
1168 goto fail_mr;
1169 }
1170 if (qm_mc_init(p)) {
1171 dev_err(c->dev, "MC initialisation failed\n");
1172 goto fail_mc;
1173 }
1174 /* static interrupt-gating controls */
1175 qm_dqrr_set_ithresh(p, QMAN_PIRQ_DQRR_ITHRESH);
1176 qm_mr_set_ithresh(p, QMAN_PIRQ_MR_ITHRESH);
1177 qm_out(p, QM_REG_ITPR, QMAN_PIRQ_IPERIOD);
1178 portal->cgrs = kmalloc(2 * sizeof(*cgrs), GFP_KERNEL);
1179 if (!portal->cgrs)
1180 goto fail_cgrs;
1181 /* initial snapshot is no-depletion */
1182 qman_cgrs_init(&portal->cgrs[1]);
1183 if (cgrs)
1184 portal->cgrs[0] = *cgrs;
1185 else
1186 /* if the given mask is NULL, assume all CGRs can be seen */
1187 qman_cgrs_fill(&portal->cgrs[0]);
1188 INIT_LIST_HEAD(&portal->cgr_cbs);
1189 spin_lock_init(&portal->cgr_lock);
1190 INIT_WORK(&portal->congestion_work, qm_congestion_task);
1191 INIT_WORK(&portal->mr_work, qm_mr_process_task);
1192 portal->bits = 0;
1193 portal->sdqcr = QM_SDQCR_SOURCE_CHANNELS | QM_SDQCR_COUNT_UPTO3 |
1194 QM_SDQCR_DEDICATED_PRECEDENCE | QM_SDQCR_TYPE_PRIO_QOS |
1195 QM_SDQCR_TOKEN_SET(0xab) | QM_SDQCR_CHANNELS_DEDICATED;
1196 isdr = 0xffffffff;
1197 qm_out(p, QM_REG_ISDR, isdr);
1198 portal->irq_sources = 0;
1199 qm_out(p, QM_REG_IER, 0);
1200 qm_out(p, QM_REG_ISR, 0xffffffff);
1201 snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
1202 if (request_irq(c->irq, portal_isr, 0, portal->irqname, portal)) {
1203 dev_err(c->dev, "request_irq() failed\n");
1204 goto fail_irq;
1205 }
1206 if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
1207 irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
1208 dev_err(c->dev, "irq_set_affinity() failed\n");
1209 goto fail_affinity;
1210 }
1211
1212 /* Need EQCR to be empty before continuing */
1213 isdr &= ~QM_PIRQ_EQCI;
1214 qm_out(p, QM_REG_ISDR, isdr);
1215 ret = qm_eqcr_get_fill(p);
1216 if (ret) {
1217 dev_err(c->dev, "EQCR unclean\n");
1218 goto fail_eqcr_empty;
1219 }
1220 isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI);
1221 qm_out(p, QM_REG_ISDR, isdr);
1222 if (qm_dqrr_current(p)) {
1223 dev_err(c->dev, "DQRR unclean\n");
1224 qm_dqrr_cdc_consume_n(p, 0xffff);
1225 }
1226 if (qm_mr_current(p) && drain_mr_fqrni(p)) {
1227 /* special handling, drain just in case it's a few FQRNIs */
1228 const union qm_mr_entry *e = qm_mr_current(p);
1229
1230 dev_err(c->dev, "MR dirty, VB 0x%x, rc 0x%x, addr 0x%llx\n",
1231 e->verb, e->ern.rc, qm_fd_addr_get64(&e->ern.fd));
1232 goto fail_dqrr_mr_empty;
1233 }
1234 /* Success */
1235 portal->config = c;
1236 qm_out(p, QM_REG_ISDR, 0);
1237 qm_out(p, QM_REG_IIR, 0);
1238 /* Write a sane SDQCR */
1239 qm_dqrr_sdqcr_set(p, portal->sdqcr);
1240 return 0;
1241
1242 fail_dqrr_mr_empty:
1243 fail_eqcr_empty:
1244 fail_affinity:
1245 free_irq(c->irq, portal);
1246 fail_irq:
1247 kfree(portal->cgrs);
1248 fail_cgrs:
1249 qm_mc_finish(p);
1250 fail_mc:
1251 qm_mr_finish(p);
1252 fail_mr:
1253 qm_dqrr_finish(p);
1254 fail_dqrr:
1255 qm_eqcr_finish(p);
1256 fail_eqcr:
1257 return -EIO;
1258 }
1259
1260 struct qman_portal *qman_create_affine_portal(const struct qm_portal_config *c,
1261 const struct qman_cgrs *cgrs)
1262 {
1263 struct qman_portal *portal;
1264 int err;
1265
1266 portal = &per_cpu(qman_affine_portal, c->cpu);
1267 err = qman_create_portal(portal, c, cgrs);
1268 if (err)
1269 return NULL;
1270
1271 spin_lock(&affine_mask_lock);
1272 cpumask_set_cpu(c->cpu, &affine_mask);
1273 affine_channels[c->cpu] = c->channel;
1274 affine_portals[c->cpu] = portal;
1275 spin_unlock(&affine_mask_lock);
1276
1277 return portal;
1278 }
1279
1280 static void qman_destroy_portal(struct qman_portal *qm)
1281 {
1282 const struct qm_portal_config *pcfg;
1283
1284 /* Stop dequeues on the portal */
1285 qm_dqrr_sdqcr_set(&qm->p, 0);
1286
1287 /*
1288 * NB we do this to "quiesce" EQCR. If we add enqueue-completions or
1289 * something related to QM_PIRQ_EQCI, this may need fixing.
1290 * Also, due to the prefetching model used for CI updates in the enqueue
1291 * path, this update will only invalidate the CI cacheline *after*
1292 * working on it, so we need to call this twice to ensure a full update
1293 * irrespective of where the enqueue processing was at when the teardown
1294 * began.
1295 */
1296 qm_eqcr_cce_update(&qm->p);
1297 qm_eqcr_cce_update(&qm->p);
1298 pcfg = qm->config;
1299
1300 free_irq(pcfg->irq, qm);
1301
1302 kfree(qm->cgrs);
1303 qm_mc_finish(&qm->p);
1304 qm_mr_finish(&qm->p);
1305 qm_dqrr_finish(&qm->p);
1306 qm_eqcr_finish(&qm->p);
1307
1308 qm->config = NULL;
1309 }
1310
1311 const struct qm_portal_config *qman_destroy_affine_portal(void)
1312 {
1313 struct qman_portal *qm = get_affine_portal();
1314 const struct qm_portal_config *pcfg;
1315 int cpu;
1316
1317 pcfg = qm->config;
1318 cpu = pcfg->cpu;
1319
1320 qman_destroy_portal(qm);
1321
1322 spin_lock(&affine_mask_lock);
1323 cpumask_clear_cpu(cpu, &affine_mask);
1324 spin_unlock(&affine_mask_lock);
1325 put_affine_portal();
1326 return pcfg;
1327 }
1328
1329 /* Inline helper to reduce nesting in __poll_portal_slow() */
1330 static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq,
1331 const union qm_mr_entry *msg, u8 verb)
1332 {
1333 switch (verb) {
1334 case QM_MR_VERB_FQRL:
1335 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_ORL));
1336 fq_clear(fq, QMAN_FQ_STATE_ORL);
1337 break;
1338 case QM_MR_VERB_FQRN:
1339 DPAA_ASSERT(fq->state == qman_fq_state_parked ||
1340 fq->state == qman_fq_state_sched);
1341 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_CHANGING));
1342 fq_clear(fq, QMAN_FQ_STATE_CHANGING);
1343 if (msg->fq.fqs & QM_MR_FQS_NOTEMPTY)
1344 fq_set(fq, QMAN_FQ_STATE_NE);
1345 if (msg->fq.fqs & QM_MR_FQS_ORLPRESENT)
1346 fq_set(fq, QMAN_FQ_STATE_ORL);
1347 fq->state = qman_fq_state_retired;
1348 break;
1349 case QM_MR_VERB_FQPN:
1350 DPAA_ASSERT(fq->state == qman_fq_state_sched);
1351 DPAA_ASSERT(fq_isclear(fq, QMAN_FQ_STATE_CHANGING));
1352 fq->state = qman_fq_state_parked;
1353 }
1354 }
1355
1356 static void qm_congestion_task(struct work_struct *work)
1357 {
1358 struct qman_portal *p = container_of(work, struct qman_portal,
1359 congestion_work);
1360 struct qman_cgrs rr, c;
1361 union qm_mc_result *mcr;
1362 struct qman_cgr *cgr;
1363
1364 spin_lock(&p->cgr_lock);
1365 qm_mc_start(&p->p);
1366 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION);
1367 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1368 spin_unlock(&p->cgr_lock);
1369 dev_crit(p->config->dev, "QUERYCONGESTION timeout\n");
1370 return;
1371 }
1372 /* mask out the ones I'm not interested in */
1373 qman_cgrs_and(&rr, (struct qman_cgrs *)&mcr->querycongestion.state,
1374 &p->cgrs[0]);
1375 /* check previous snapshot for delta, enter/exit congestion */
1376 qman_cgrs_xor(&c, &rr, &p->cgrs[1]);
1377 /* update snapshot */
1378 qman_cgrs_cp(&p->cgrs[1], &rr);
1379 /* Invoke callback */
1380 list_for_each_entry(cgr, &p->cgr_cbs, node)
1381 if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid))
1382 cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid));
1383 spin_unlock(&p->cgr_lock);
1384 }
1385
1386 static void qm_mr_process_task(struct work_struct *work)
1387 {
1388 struct qman_portal *p = container_of(work, struct qman_portal,
1389 mr_work);
1390 const union qm_mr_entry *msg;
1391 struct qman_fq *fq;
1392 u8 verb, num = 0;
1393
1394 preempt_disable();
1395
1396 while (1) {
1397 qm_mr_pvb_update(&p->p);
1398 msg = qm_mr_current(&p->p);
1399 if (!msg)
1400 break;
1401
1402 verb = msg->verb & QM_MR_VERB_TYPE_MASK;
1403 /* The message is a software ERN iff the 0x20 bit is clear */
1404 if (verb & 0x20) {
1405 switch (verb) {
1406 case QM_MR_VERB_FQRNI:
1407 /* nada, we drop FQRNIs on the floor */
1408 break;
1409 case QM_MR_VERB_FQRN:
1410 case QM_MR_VERB_FQRL:
1411 /* Lookup in the retirement table */
1412 fq = fqid_to_fq(msg->fq.fqid);
1413 if (WARN_ON(!fq))
1414 break;
1415 fq_state_change(p, fq, msg, verb);
1416 if (fq->cb.fqs)
1417 fq->cb.fqs(p, fq, msg);
1418 break;
1419 case QM_MR_VERB_FQPN:
1420 /* Parked */
1421 fq = tag_to_fq(msg->fq.contextB);
1422 fq_state_change(p, fq, msg, verb);
1423 if (fq->cb.fqs)
1424 fq->cb.fqs(p, fq, msg);
1425 break;
1426 case QM_MR_VERB_DC_ERN:
1427 /* DCP ERN */
1428 pr_crit_once("Leaking DCP ERNs!\n");
1429 break;
1430 default:
1431 pr_crit("Invalid MR verb 0x%02x\n", verb);
1432 }
1433 } else {
1434 /* Its a software ERN */
1435 fq = tag_to_fq(msg->ern.tag);
1436 fq->cb.ern(p, fq, msg);
1437 }
1438 num++;
1439 qm_mr_next(&p->p);
1440 }
1441
1442 qm_mr_cci_consume(&p->p, num);
1443 preempt_enable();
1444 }
1445
1446 static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
1447 {
1448 if (is & QM_PIRQ_CSCI) {
1449 queue_work_on(smp_processor_id(), qm_portal_wq,
1450 &p->congestion_work);
1451 }
1452
1453 if (is & QM_PIRQ_EQRI) {
1454 qm_eqcr_cce_update(&p->p);
1455 qm_eqcr_set_ithresh(&p->p, 0);
1456 wake_up(&affine_queue);
1457 }
1458
1459 if (is & QM_PIRQ_MRI) {
1460 queue_work_on(smp_processor_id(), qm_portal_wq,
1461 &p->mr_work);
1462 }
1463
1464 return is;
1465 }
1466
1467 /*
1468 * remove some slowish-path stuff from the "fast path" and make sure it isn't
1469 * inlined.
1470 */
1471 static noinline void clear_vdqcr(struct qman_portal *p, struct qman_fq *fq)
1472 {
1473 p->vdqcr_owned = NULL;
1474 fq_clear(fq, QMAN_FQ_STATE_VDQCR);
1475 wake_up(&affine_queue);
1476 }
1477
1478 /*
1479 * The only states that would conflict with other things if they ran at the
1480 * same time on the same cpu are:
1481 *
1482 * (i) setting/clearing vdqcr_owned, and
1483 * (ii) clearing the NE (Not Empty) flag.
1484 *
1485 * Both are safe. Because;
1486 *
1487 * (i) this clearing can only occur after qman_volatile_dequeue() has set the
1488 * vdqcr_owned field (which it does before setting VDQCR), and
1489 * qman_volatile_dequeue() blocks interrupts and preemption while this is
1490 * done so that we can't interfere.
1491 * (ii) the NE flag is only cleared after qman_retire_fq() has set it, and as
1492 * with (i) that API prevents us from interfering until it's safe.
1493 *
1494 * The good thing is that qman_volatile_dequeue() and qman_retire_fq() run far
1495 * less frequently (ie. per-FQ) than __poll_portal_fast() does, so the nett
1496 * advantage comes from this function not having to "lock" anything at all.
1497 *
1498 * Note also that the callbacks are invoked at points which are safe against the
1499 * above potential conflicts, but that this function itself is not re-entrant
1500 * (this is because the function tracks one end of each FIFO in the portal and
1501 * we do *not* want to lock that). So the consequence is that it is safe for
1502 * user callbacks to call into any QMan API.
1503 */
1504 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1505 unsigned int poll_limit)
1506 {
1507 const struct qm_dqrr_entry *dq;
1508 struct qman_fq *fq;
1509 enum qman_cb_dqrr_result res;
1510 unsigned int limit = 0;
1511
1512 do {
1513 qm_dqrr_pvb_update(&p->p);
1514 dq = qm_dqrr_current(&p->p);
1515 if (!dq)
1516 break;
1517
1518 if (dq->stat & QM_DQRR_STAT_UNSCHEDULED) {
1519 /*
1520 * VDQCR: don't trust contextB as the FQ may have
1521 * been configured for h/w consumption and we're
1522 * draining it post-retirement.
1523 */
1524 fq = p->vdqcr_owned;
1525 /*
1526 * We only set QMAN_FQ_STATE_NE when retiring, so we
1527 * only need to check for clearing it when doing
1528 * volatile dequeues. It's one less thing to check
1529 * in the critical path (SDQCR).
1530 */
1531 if (dq->stat & QM_DQRR_STAT_FQ_EMPTY)
1532 fq_clear(fq, QMAN_FQ_STATE_NE);
1533 /*
1534 * This is duplicated from the SDQCR code, but we
1535 * have stuff to do before *and* after this callback,
1536 * and we don't want multiple if()s in the critical
1537 * path (SDQCR).
1538 */
1539 res = fq->cb.dqrr(p, fq, dq);
1540 if (res == qman_cb_dqrr_stop)
1541 break;
1542 /* Check for VDQCR completion */
1543 if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED)
1544 clear_vdqcr(p, fq);
1545 } else {
1546 /* SDQCR: contextB points to the FQ */
1547 fq = tag_to_fq(dq->contextB);
1548 /* Now let the callback do its stuff */
1549 res = fq->cb.dqrr(p, fq, dq);
1550 /*
1551 * The callback can request that we exit without
1552 * consuming this entry nor advancing;
1553 */
1554 if (res == qman_cb_dqrr_stop)
1555 break;
1556 }
1557 /* Interpret 'dq' from a driver perspective. */
1558 /*
1559 * Parking isn't possible unless HELDACTIVE was set. NB,
1560 * FORCEELIGIBLE implies HELDACTIVE, so we only need to
1561 * check for HELDACTIVE to cover both.
1562 */
1563 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) ||
1564 (res != qman_cb_dqrr_park));
1565 /* just means "skip it, I'll consume it myself later on" */
1566 if (res != qman_cb_dqrr_defer)
1567 qm_dqrr_cdc_consume_1ptr(&p->p, dq,
1568 res == qman_cb_dqrr_park);
1569 /* Move forward */
1570 qm_dqrr_next(&p->p);
1571 /*
1572 * Entry processed and consumed, increment our counter. The
1573 * callback can request that we exit after consuming the
1574 * entry, and we also exit if we reach our processing limit,
1575 * so loop back only if neither of these conditions is met.
1576 */
1577 } while (++limit < poll_limit && res != qman_cb_dqrr_consume_stop);
1578
1579 return limit;
1580 }
1581
1582 void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
1583 {
1584 unsigned long irqflags;
1585
1586 local_irq_save(irqflags);
1587 set_bits(bits & QM_PIRQ_VISIBLE, &p->irq_sources);
1588 qm_out(&p->p, QM_REG_IER, p->irq_sources);
1589 local_irq_restore(irqflags);
1590 }
1591 EXPORT_SYMBOL(qman_p_irqsource_add);
1592
1593 void qman_p_irqsource_remove(struct qman_portal *p, u32 bits)
1594 {
1595 unsigned long irqflags;
1596 u32 ier;
1597
1598 /*
1599 * Our interrupt handler only processes+clears status register bits that
1600 * are in p->irq_sources. As we're trimming that mask, if one of them
1601 * were to assert in the status register just before we remove it from
1602 * the enable register, there would be an interrupt-storm when we
1603 * release the IRQ lock. So we wait for the enable register update to
1604 * take effect in h/w (by reading it back) and then clear all other bits
1605 * in the status register. Ie. we clear them from ISR once it's certain
1606 * IER won't allow them to reassert.
1607 */
1608 local_irq_save(irqflags);
1609 bits &= QM_PIRQ_VISIBLE;
1610 clear_bits(bits, &p->irq_sources);
1611 qm_out(&p->p, QM_REG_IER, p->irq_sources);
1612 ier = qm_in(&p->p, QM_REG_IER);
1613 /*
1614 * Using "~ier" (rather than "bits" or "~p->irq_sources") creates a
1615 * data-dependency, ie. to protect against re-ordering.
1616 */
1617 qm_out(&p->p, QM_REG_ISR, ~ier);
1618 local_irq_restore(irqflags);
1619 }
1620 EXPORT_SYMBOL(qman_p_irqsource_remove);
1621
1622 const cpumask_t *qman_affine_cpus(void)
1623 {
1624 return &affine_mask;
1625 }
1626 EXPORT_SYMBOL(qman_affine_cpus);
1627
1628 u16 qman_affine_channel(int cpu)
1629 {
1630 if (cpu < 0) {
1631 struct qman_portal *portal = get_affine_portal();
1632
1633 cpu = portal->config->cpu;
1634 put_affine_portal();
1635 }
1636 WARN_ON(!cpumask_test_cpu(cpu, &affine_mask));
1637 return affine_channels[cpu];
1638 }
1639 EXPORT_SYMBOL(qman_affine_channel);
1640
1641 struct qman_portal *qman_get_affine_portal(int cpu)
1642 {
1643 return affine_portals[cpu];
1644 }
1645 EXPORT_SYMBOL(qman_get_affine_portal);
1646
1647 int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit)
1648 {
1649 return __poll_portal_fast(p, limit);
1650 }
1651 EXPORT_SYMBOL(qman_p_poll_dqrr);
1652
1653 void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools)
1654 {
1655 unsigned long irqflags;
1656
1657 local_irq_save(irqflags);
1658 pools &= p->config->pools;
1659 p->sdqcr |= pools;
1660 qm_dqrr_sdqcr_set(&p->p, p->sdqcr);
1661 local_irq_restore(irqflags);
1662 }
1663 EXPORT_SYMBOL(qman_p_static_dequeue_add);
1664
1665 /* Frame queue API */
1666
1667 static const char *mcr_result_str(u8 result)
1668 {
1669 switch (result) {
1670 case QM_MCR_RESULT_NULL:
1671 return "QM_MCR_RESULT_NULL";
1672 case QM_MCR_RESULT_OK:
1673 return "QM_MCR_RESULT_OK";
1674 case QM_MCR_RESULT_ERR_FQID:
1675 return "QM_MCR_RESULT_ERR_FQID";
1676 case QM_MCR_RESULT_ERR_FQSTATE:
1677 return "QM_MCR_RESULT_ERR_FQSTATE";
1678 case QM_MCR_RESULT_ERR_NOTEMPTY:
1679 return "QM_MCR_RESULT_ERR_NOTEMPTY";
1680 case QM_MCR_RESULT_PENDING:
1681 return "QM_MCR_RESULT_PENDING";
1682 case QM_MCR_RESULT_ERR_BADCOMMAND:
1683 return "QM_MCR_RESULT_ERR_BADCOMMAND";
1684 }
1685 return "<unknown MCR result>";
1686 }
1687
1688 int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
1689 {
1690 if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) {
1691 int ret = qman_alloc_fqid(&fqid);
1692
1693 if (ret)
1694 return ret;
1695 }
1696 fq->fqid = fqid;
1697 fq->flags = flags;
1698 fq->state = qman_fq_state_oos;
1699 fq->cgr_groupid = 0;
1700
1701 /* A context_b of 0 is allegedly special, so don't use that fqid */
1702 if (fqid == 0 || fqid >= num_fqids) {
1703 WARN(1, "bad fqid %d\n", fqid);
1704 return -EINVAL;
1705 }
1706
1707 fq->idx = fqid * 2;
1708 if (flags & QMAN_FQ_FLAG_NO_MODIFY)
1709 fq->idx++;
1710
1711 WARN_ON(fq_table[fq->idx]);
1712 fq_table[fq->idx] = fq;
1713
1714 return 0;
1715 }
1716 EXPORT_SYMBOL(qman_create_fq);
1717
1718 void qman_destroy_fq(struct qman_fq *fq)
1719 {
1720 /*
1721 * We don't need to lock the FQ as it is a pre-condition that the FQ be
1722 * quiesced. Instead, run some checks.
1723 */
1724 switch (fq->state) {
1725 case qman_fq_state_parked:
1726 case qman_fq_state_oos:
1727 if (fq_isset(fq, QMAN_FQ_FLAG_DYNAMIC_FQID))
1728 qman_release_fqid(fq->fqid);
1729
1730 DPAA_ASSERT(fq_table[fq->idx]);
1731 fq_table[fq->idx] = NULL;
1732 return;
1733 default:
1734 break;
1735 }
1736 DPAA_ASSERT(NULL == "qman_free_fq() on unquiesced FQ!");
1737 }
1738 EXPORT_SYMBOL(qman_destroy_fq);
1739
1740 u32 qman_fq_fqid(struct qman_fq *fq)
1741 {
1742 return fq->fqid;
1743 }
1744 EXPORT_SYMBOL(qman_fq_fqid);
1745
1746 int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
1747 {
1748 union qm_mc_command *mcc;
1749 union qm_mc_result *mcr;
1750 struct qman_portal *p;
1751 u8 res, myverb;
1752 int ret = 0;
1753
1754 myverb = (flags & QMAN_INITFQ_FLAG_SCHED)
1755 ? QM_MCC_VERB_INITFQ_SCHED : QM_MCC_VERB_INITFQ_PARKED;
1756
1757 if (fq->state != qman_fq_state_oos &&
1758 fq->state != qman_fq_state_parked)
1759 return -EINVAL;
1760 #ifdef CONFIG_FSL_DPAA_CHECKING
1761 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1762 return -EINVAL;
1763 #endif
1764 if (opts && (opts->we_mask & QM_INITFQ_WE_OAC)) {
1765 /* And can't be set at the same time as TDTHRESH */
1766 if (opts->we_mask & QM_INITFQ_WE_TDTHRESH)
1767 return -EINVAL;
1768 }
1769 /* Issue an INITFQ_[PARKED|SCHED] management command */
1770 p = get_affine_portal();
1771 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1772 (fq->state != qman_fq_state_oos &&
1773 fq->state != qman_fq_state_parked)) {
1774 ret = -EBUSY;
1775 goto out;
1776 }
1777 mcc = qm_mc_start(&p->p);
1778 if (opts)
1779 mcc->initfq = *opts;
1780 mcc->initfq.fqid = fq->fqid;
1781 mcc->initfq.count = 0;
1782 /*
1783 * If the FQ does *not* have the TO_DCPORTAL flag, contextB is set as a
1784 * demux pointer. Otherwise, the caller-provided value is allowed to
1785 * stand, don't overwrite it.
1786 */
1787 if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) {
1788 dma_addr_t phys_fq;
1789
1790 mcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTB;
1791 mcc->initfq.fqd.context_b = fq_to_tag(fq);
1792 /*
1793 * and the physical address - NB, if the user wasn't trying to
1794 * set CONTEXTA, clear the stashing settings.
1795 */
1796 if (!(mcc->initfq.we_mask & QM_INITFQ_WE_CONTEXTA)) {
1797 mcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTA;
1798 memset(&mcc->initfq.fqd.context_a, 0,
1799 sizeof(mcc->initfq.fqd.context_a));
1800 } else {
1801 struct qman_portal *p = qman_dma_portal;
1802
1803 phys_fq = dma_map_single(p->config->dev, fq,
1804 sizeof(*fq), DMA_TO_DEVICE);
1805 if (dma_mapping_error(p->config->dev, phys_fq)) {
1806 dev_err(p->config->dev, "dma_mapping failed\n");
1807 ret = -EIO;
1808 goto out;
1809 }
1810
1811 qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq);
1812 }
1813 }
1814 if (flags & QMAN_INITFQ_FLAG_LOCAL) {
1815 int wq = 0;
1816
1817 if (!(mcc->initfq.we_mask & QM_INITFQ_WE_DESTWQ)) {
1818 mcc->initfq.we_mask |= QM_INITFQ_WE_DESTWQ;
1819 wq = 4;
1820 }
1821 qm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq);
1822 }
1823 qm_mc_commit(&p->p, myverb);
1824 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1825 dev_err(p->config->dev, "MCR timeout\n");
1826 ret = -ETIMEDOUT;
1827 goto out;
1828 }
1829
1830 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1831 res = mcr->result;
1832 if (res != QM_MCR_RESULT_OK) {
1833 ret = -EIO;
1834 goto out;
1835 }
1836 if (opts) {
1837 if (opts->we_mask & QM_INITFQ_WE_FQCTRL) {
1838 if (opts->fqd.fq_ctrl & QM_FQCTRL_CGE)
1839 fq_set(fq, QMAN_FQ_STATE_CGR_EN);
1840 else
1841 fq_clear(fq, QMAN_FQ_STATE_CGR_EN);
1842 }
1843 if (opts->we_mask & QM_INITFQ_WE_CGID)
1844 fq->cgr_groupid = opts->fqd.cgid;
1845 }
1846 fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ?
1847 qman_fq_state_sched : qman_fq_state_parked;
1848
1849 out:
1850 put_affine_portal();
1851 return ret;
1852 }
1853 EXPORT_SYMBOL(qman_init_fq);
1854
1855 int qman_schedule_fq(struct qman_fq *fq)
1856 {
1857 union qm_mc_command *mcc;
1858 union qm_mc_result *mcr;
1859 struct qman_portal *p;
1860 int ret = 0;
1861
1862 if (fq->state != qman_fq_state_parked)
1863 return -EINVAL;
1864 #ifdef CONFIG_FSL_DPAA_CHECKING
1865 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1866 return -EINVAL;
1867 #endif
1868 /* Issue a ALTERFQ_SCHED management command */
1869 p = get_affine_portal();
1870 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1871 fq->state != qman_fq_state_parked) {
1872 ret = -EBUSY;
1873 goto out;
1874 }
1875 mcc = qm_mc_start(&p->p);
1876 mcc->alterfq.fqid = fq->fqid;
1877 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_SCHED);
1878 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1879 dev_err(p->config->dev, "ALTER_SCHED timeout\n");
1880 ret = -ETIMEDOUT;
1881 goto out;
1882 }
1883
1884 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_SCHED);
1885 if (mcr->result != QM_MCR_RESULT_OK) {
1886 ret = -EIO;
1887 goto out;
1888 }
1889 fq->state = qman_fq_state_sched;
1890 out:
1891 put_affine_portal();
1892 return ret;
1893 }
1894 EXPORT_SYMBOL(qman_schedule_fq);
1895
1896 int qman_retire_fq(struct qman_fq *fq, u32 *flags)
1897 {
1898 union qm_mc_command *mcc;
1899 union qm_mc_result *mcr;
1900 struct qman_portal *p;
1901 int ret;
1902 u8 res;
1903
1904 if (fq->state != qman_fq_state_parked &&
1905 fq->state != qman_fq_state_sched)
1906 return -EINVAL;
1907 #ifdef CONFIG_FSL_DPAA_CHECKING
1908 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1909 return -EINVAL;
1910 #endif
1911 p = get_affine_portal();
1912 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1913 fq->state == qman_fq_state_retired ||
1914 fq->state == qman_fq_state_oos) {
1915 ret = -EBUSY;
1916 goto out;
1917 }
1918 mcc = qm_mc_start(&p->p);
1919 mcc->alterfq.fqid = fq->fqid;
1920 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
1921 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1922 dev_crit(p->config->dev, "ALTER_RETIRE timeout\n");
1923 ret = -ETIMEDOUT;
1924 goto out;
1925 }
1926
1927 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_RETIRE);
1928 res = mcr->result;
1929 /*
1930 * "Elegant" would be to treat OK/PENDING the same way; set CHANGING,
1931 * and defer the flags until FQRNI or FQRN (respectively) show up. But
1932 * "Friendly" is to process OK immediately, and not set CHANGING. We do
1933 * friendly, otherwise the caller doesn't necessarily have a fully
1934 * "retired" FQ on return even if the retirement was immediate. However
1935 * this does mean some code duplication between here and
1936 * fq_state_change().
1937 */
1938 if (res == QM_MCR_RESULT_OK) {
1939 ret = 0;
1940 /* Process 'fq' right away, we'll ignore FQRNI */
1941 if (mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY)
1942 fq_set(fq, QMAN_FQ_STATE_NE);
1943 if (mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)
1944 fq_set(fq, QMAN_FQ_STATE_ORL);
1945 if (flags)
1946 *flags = fq->flags;
1947 fq->state = qman_fq_state_retired;
1948 if (fq->cb.fqs) {
1949 /*
1950 * Another issue with supporting "immediate" retirement
1951 * is that we're forced to drop FQRNIs, because by the
1952 * time they're seen it may already be "too late" (the
1953 * fq may have been OOS'd and free()'d already). But if
1954 * the upper layer wants a callback whether it's
1955 * immediate or not, we have to fake a "MR" entry to
1956 * look like an FQRNI...
1957 */
1958 union qm_mr_entry msg;
1959
1960 msg.verb = QM_MR_VERB_FQRNI;
1961 msg.fq.fqs = mcr->alterfq.fqs;
1962 msg.fq.fqid = fq->fqid;
1963 msg.fq.contextB = fq_to_tag(fq);
1964 fq->cb.fqs(p, fq, &msg);
1965 }
1966 } else if (res == QM_MCR_RESULT_PENDING) {
1967 ret = 1;
1968 fq_set(fq, QMAN_FQ_STATE_CHANGING);
1969 } else {
1970 ret = -EIO;
1971 }
1972 out:
1973 put_affine_portal();
1974 return ret;
1975 }
1976 EXPORT_SYMBOL(qman_retire_fq);
1977
1978 int qman_oos_fq(struct qman_fq *fq)
1979 {
1980 union qm_mc_command *mcc;
1981 union qm_mc_result *mcr;
1982 struct qman_portal *p;
1983 int ret = 0;
1984
1985 if (fq->state != qman_fq_state_retired)
1986 return -EINVAL;
1987 #ifdef CONFIG_FSL_DPAA_CHECKING
1988 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1989 return -EINVAL;
1990 #endif
1991 p = get_affine_portal();
1992 if (fq_isset(fq, QMAN_FQ_STATE_BLOCKOOS) ||
1993 fq->state != qman_fq_state_retired) {
1994 ret = -EBUSY;
1995 goto out;
1996 }
1997 mcc = qm_mc_start(&p->p);
1998 mcc->alterfq.fqid = fq->fqid;
1999 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2000 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2001 ret = -ETIMEDOUT;
2002 goto out;
2003 }
2004 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_OOS);
2005 if (mcr->result != QM_MCR_RESULT_OK) {
2006 ret = -EIO;
2007 goto out;
2008 }
2009 fq->state = qman_fq_state_oos;
2010 out:
2011 put_affine_portal();
2012 return ret;
2013 }
2014 EXPORT_SYMBOL(qman_oos_fq);
2015
2016 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd)
2017 {
2018 union qm_mc_command *mcc;
2019 union qm_mc_result *mcr;
2020 struct qman_portal *p = get_affine_portal();
2021 int ret = 0;
2022
2023 mcc = qm_mc_start(&p->p);
2024 mcc->queryfq.fqid = fq->fqid;
2025 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2026 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2027 ret = -ETIMEDOUT;
2028 goto out;
2029 }
2030
2031 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2032 if (mcr->result == QM_MCR_RESULT_OK)
2033 *fqd = mcr->queryfq.fqd;
2034 else
2035 ret = -EIO;
2036 out:
2037 put_affine_portal();
2038 return ret;
2039 }
2040
2041 static int qman_query_fq_np(struct qman_fq *fq,
2042 struct qm_mcr_queryfq_np *np)
2043 {
2044 union qm_mc_command *mcc;
2045 union qm_mc_result *mcr;
2046 struct qman_portal *p = get_affine_portal();
2047 int ret = 0;
2048
2049 mcc = qm_mc_start(&p->p);
2050 mcc->queryfq.fqid = fq->fqid;
2051 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2052 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2053 ret = -ETIMEDOUT;
2054 goto out;
2055 }
2056
2057 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2058 if (mcr->result == QM_MCR_RESULT_OK)
2059 *np = mcr->queryfq_np;
2060 else if (mcr->result == QM_MCR_RESULT_ERR_FQID)
2061 ret = -ERANGE;
2062 else
2063 ret = -EIO;
2064 out:
2065 put_affine_portal();
2066 return ret;
2067 }
2068
2069 static int qman_query_cgr(struct qman_cgr *cgr,
2070 struct qm_mcr_querycgr *cgrd)
2071 {
2072 union qm_mc_command *mcc;
2073 union qm_mc_result *mcr;
2074 struct qman_portal *p = get_affine_portal();
2075 int ret = 0;
2076
2077 mcc = qm_mc_start(&p->p);
2078 mcc->querycgr.cgid = cgr->cgrid;
2079 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCGR);
2080 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2081 ret = -ETIMEDOUT;
2082 goto out;
2083 }
2084 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYCGR);
2085 if (mcr->result == QM_MCR_RESULT_OK)
2086 *cgrd = mcr->querycgr;
2087 else {
2088 dev_err(p->config->dev, "QUERY_CGR failed: %s\n",
2089 mcr_result_str(mcr->result));
2090 ret = -EIO;
2091 }
2092 out:
2093 put_affine_portal();
2094 return ret;
2095 }
2096
2097 int qman_query_cgr_congested(struct qman_cgr *cgr, bool *result)
2098 {
2099 struct qm_mcr_querycgr query_cgr;
2100 int err;
2101
2102 err = qman_query_cgr(cgr, &query_cgr);
2103 if (err)
2104 return err;
2105
2106 *result = !!query_cgr.cgr.cs;
2107 return 0;
2108 }
2109 EXPORT_SYMBOL(qman_query_cgr_congested);
2110
2111 /* internal function used as a wait_event() expression */
2112 static int set_p_vdqcr(struct qman_portal *p, struct qman_fq *fq, u32 vdqcr)
2113 {
2114 unsigned long irqflags;
2115 int ret = -EBUSY;
2116
2117 local_irq_save(irqflags);
2118 if (p->vdqcr_owned)
2119 goto out;
2120 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2121 goto out;
2122
2123 fq_set(fq, QMAN_FQ_STATE_VDQCR);
2124 p->vdqcr_owned = fq;
2125 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2126 ret = 0;
2127 out:
2128 local_irq_restore(irqflags);
2129 return ret;
2130 }
2131
2132 static int set_vdqcr(struct qman_portal **p, struct qman_fq *fq, u32 vdqcr)
2133 {
2134 int ret;
2135
2136 *p = get_affine_portal();
2137 ret = set_p_vdqcr(*p, fq, vdqcr);
2138 put_affine_portal();
2139 return ret;
2140 }
2141
2142 static int wait_vdqcr_start(struct qman_portal **p, struct qman_fq *fq,
2143 u32 vdqcr, u32 flags)
2144 {
2145 int ret = 0;
2146
2147 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2148 ret = wait_event_interruptible(affine_queue,
2149 !set_vdqcr(p, fq, vdqcr));
2150 else
2151 wait_event(affine_queue, !set_vdqcr(p, fq, vdqcr));
2152 return ret;
2153 }
2154
2155 int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr)
2156 {
2157 struct qman_portal *p;
2158 int ret;
2159
2160 if (fq->state != qman_fq_state_parked &&
2161 fq->state != qman_fq_state_retired)
2162 return -EINVAL;
2163 if (vdqcr & QM_VDQCR_FQID_MASK)
2164 return -EINVAL;
2165 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2166 return -EBUSY;
2167 vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid;
2168 if (flags & QMAN_VOLATILE_FLAG_WAIT)
2169 ret = wait_vdqcr_start(&p, fq, vdqcr, flags);
2170 else
2171 ret = set_vdqcr(&p, fq, vdqcr);
2172 if (ret)
2173 return ret;
2174 /* VDQCR is set */
2175 if (flags & QMAN_VOLATILE_FLAG_FINISH) {
2176 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2177 /*
2178 * NB: don't propagate any error - the caller wouldn't
2179 * know whether the VDQCR was issued or not. A signal
2180 * could arrive after returning anyway, so the caller
2181 * can check signal_pending() if that's an issue.
2182 */
2183 wait_event_interruptible(affine_queue,
2184 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2185 else
2186 wait_event(affine_queue,
2187 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2188 }
2189 return 0;
2190 }
2191 EXPORT_SYMBOL(qman_volatile_dequeue);
2192
2193 static void update_eqcr_ci(struct qman_portal *p, u8 avail)
2194 {
2195 if (avail)
2196 qm_eqcr_cce_prefetch(&p->p);
2197 else
2198 qm_eqcr_cce_update(&p->p);
2199 }
2200
2201 int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd)
2202 {
2203 struct qman_portal *p;
2204 struct qm_eqcr_entry *eq;
2205 unsigned long irqflags;
2206 u8 avail;
2207
2208 p = get_affine_portal();
2209 local_irq_save(irqflags);
2210
2211 if (p->use_eqcr_ci_stashing) {
2212 /*
2213 * The stashing case is easy, only update if we need to in
2214 * order to try and liberate ring entries.
2215 */
2216 eq = qm_eqcr_start_stash(&p->p);
2217 } else {
2218 /*
2219 * The non-stashing case is harder, need to prefetch ahead of
2220 * time.
2221 */
2222 avail = qm_eqcr_get_avail(&p->p);
2223 if (avail < 2)
2224 update_eqcr_ci(p, avail);
2225 eq = qm_eqcr_start_no_stash(&p->p);
2226 }
2227
2228 if (unlikely(!eq))
2229 goto out;
2230
2231 eq->fqid = fq->fqid;
2232 eq->tag = fq_to_tag(fq);
2233 eq->fd = *fd;
2234
2235 qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE);
2236 out:
2237 local_irq_restore(irqflags);
2238 put_affine_portal();
2239 return 0;
2240 }
2241 EXPORT_SYMBOL(qman_enqueue);
2242
2243 static int qm_modify_cgr(struct qman_cgr *cgr, u32 flags,
2244 struct qm_mcc_initcgr *opts)
2245 {
2246 union qm_mc_command *mcc;
2247 union qm_mc_result *mcr;
2248 struct qman_portal *p = get_affine_portal();
2249 u8 verb = QM_MCC_VERB_MODIFYCGR;
2250 int ret = 0;
2251
2252 mcc = qm_mc_start(&p->p);
2253 if (opts)
2254 mcc->initcgr = *opts;
2255 mcc->initcgr.cgid = cgr->cgrid;
2256 if (flags & QMAN_CGR_FLAG_USE_INIT)
2257 verb = QM_MCC_VERB_INITCGR;
2258 qm_mc_commit(&p->p, verb);
2259 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2260 ret = -ETIMEDOUT;
2261 goto out;
2262 }
2263
2264 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == verb);
2265 if (mcr->result != QM_MCR_RESULT_OK)
2266 ret = -EIO;
2267
2268 out:
2269 put_affine_portal();
2270 return ret;
2271 }
2272
2273 #define PORTAL_IDX(n) (n->config->channel - QM_CHANNEL_SWPORTAL0)
2274 #define TARG_MASK(n) (BIT(31) >> PORTAL_IDX(n))
2275
2276 static u8 qman_cgr_cpus[CGR_NUM];
2277
2278 void qman_init_cgr_all(void)
2279 {
2280 struct qman_cgr cgr;
2281 int err_cnt = 0;
2282
2283 for (cgr.cgrid = 0; cgr.cgrid < CGR_NUM; cgr.cgrid++) {
2284 if (qm_modify_cgr(&cgr, QMAN_CGR_FLAG_USE_INIT, NULL))
2285 err_cnt++;
2286 }
2287
2288 if (err_cnt)
2289 pr_err("Warning: %d error%s while initialising CGR h/w\n",
2290 err_cnt, (err_cnt > 1) ? "s" : "");
2291 }
2292
2293 int qman_create_cgr(struct qman_cgr *cgr, u32 flags,
2294 struct qm_mcc_initcgr *opts)
2295 {
2296 struct qm_mcr_querycgr cgr_state;
2297 int ret;
2298 struct qman_portal *p;
2299
2300 /*
2301 * We have to check that the provided CGRID is within the limits of the
2302 * data-structures, for obvious reasons. However we'll let h/w take
2303 * care of determining whether it's within the limits of what exists on
2304 * the SoC.
2305 */
2306 if (cgr->cgrid >= CGR_NUM)
2307 return -EINVAL;
2308
2309 preempt_disable();
2310 p = get_affine_portal();
2311 qman_cgr_cpus[cgr->cgrid] = smp_processor_id();
2312 preempt_enable();
2313
2314 cgr->chan = p->config->channel;
2315 spin_lock(&p->cgr_lock);
2316
2317 if (opts) {
2318 struct qm_mcc_initcgr local_opts = *opts;
2319
2320 ret = qman_query_cgr(cgr, &cgr_state);
2321 if (ret)
2322 goto out;
2323
2324 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
2325 local_opts.cgr.cscn_targ_upd_ctrl =
2326 QM_CGR_TARG_UDP_CTRL_WRITE_BIT | PORTAL_IDX(p);
2327 else
2328 /* Overwrite TARG */
2329 local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ |
2330 TARG_MASK(p);
2331 local_opts.we_mask |= QM_CGR_WE_CSCN_TARG;
2332
2333 /* send init if flags indicate so */
2334 if (flags & QMAN_CGR_FLAG_USE_INIT)
2335 ret = qm_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT,
2336 &local_opts);
2337 else
2338 ret = qm_modify_cgr(cgr, 0, &local_opts);
2339 if (ret)
2340 goto out;
2341 }
2342
2343 list_add(&cgr->node, &p->cgr_cbs);
2344
2345 /* Determine if newly added object requires its callback to be called */
2346 ret = qman_query_cgr(cgr, &cgr_state);
2347 if (ret) {
2348 /* we can't go back, so proceed and return success */
2349 dev_err(p->config->dev, "CGR HW state partially modified\n");
2350 ret = 0;
2351 goto out;
2352 }
2353 if (cgr->cb && cgr_state.cgr.cscn_en &&
2354 qman_cgrs_get(&p->cgrs[1], cgr->cgrid))
2355 cgr->cb(p, cgr, 1);
2356 out:
2357 spin_unlock(&p->cgr_lock);
2358 put_affine_portal();
2359 return ret;
2360 }
2361 EXPORT_SYMBOL(qman_create_cgr);
2362
2363 int qman_delete_cgr(struct qman_cgr *cgr)
2364 {
2365 unsigned long irqflags;
2366 struct qm_mcr_querycgr cgr_state;
2367 struct qm_mcc_initcgr local_opts;
2368 int ret = 0;
2369 struct qman_cgr *i;
2370 struct qman_portal *p = get_affine_portal();
2371
2372 if (cgr->chan != p->config->channel) {
2373 /* attempt to delete from other portal than creator */
2374 dev_err(p->config->dev, "CGR not owned by current portal");
2375 dev_dbg(p->config->dev, " create 0x%x, delete 0x%x\n",
2376 cgr->chan, p->config->channel);
2377
2378 ret = -EINVAL;
2379 goto put_portal;
2380 }
2381 memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2382 spin_lock_irqsave(&p->cgr_lock, irqflags);
2383 list_del(&cgr->node);
2384 /*
2385 * If there are no other CGR objects for this CGRID in the list,
2386 * update CSCN_TARG accordingly
2387 */
2388 list_for_each_entry(i, &p->cgr_cbs, node)
2389 if (i->cgrid == cgr->cgrid && i->cb)
2390 goto release_lock;
2391 ret = qman_query_cgr(cgr, &cgr_state);
2392 if (ret) {
2393 /* add back to the list */
2394 list_add(&cgr->node, &p->cgr_cbs);
2395 goto release_lock;
2396 }
2397 /* Overwrite TARG */
2398 local_opts.we_mask = QM_CGR_WE_CSCN_TARG;
2399 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
2400 local_opts.cgr.cscn_targ_upd_ctrl = PORTAL_IDX(p);
2401 else
2402 local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ &
2403 ~(TARG_MASK(p));
2404 ret = qm_modify_cgr(cgr, 0, &local_opts);
2405 if (ret)
2406 /* add back to the list */
2407 list_add(&cgr->node, &p->cgr_cbs);
2408 release_lock:
2409 spin_unlock_irqrestore(&p->cgr_lock, irqflags);
2410 put_portal:
2411 put_affine_portal();
2412 return ret;
2413 }
2414 EXPORT_SYMBOL(qman_delete_cgr);
2415
2416 struct cgr_comp {
2417 struct qman_cgr *cgr;
2418 struct completion completion;
2419 };
2420
2421 static int qman_delete_cgr_thread(void *p)
2422 {
2423 struct cgr_comp *cgr_comp = (struct cgr_comp *)p;
2424 int ret;
2425
2426 ret = qman_delete_cgr(cgr_comp->cgr);
2427 complete(&cgr_comp->completion);
2428
2429 return ret;
2430 }
2431
2432 void qman_delete_cgr_safe(struct qman_cgr *cgr)
2433 {
2434 struct task_struct *thread;
2435 struct cgr_comp cgr_comp;
2436
2437 preempt_disable();
2438 if (qman_cgr_cpus[cgr->cgrid] != smp_processor_id()) {
2439 init_completion(&cgr_comp.completion);
2440 cgr_comp.cgr = cgr;
2441 thread = kthread_create(qman_delete_cgr_thread, &cgr_comp,
2442 "cgr_del");
2443
2444 if (IS_ERR(thread))
2445 goto out;
2446
2447 kthread_bind(thread, qman_cgr_cpus[cgr->cgrid]);
2448 wake_up_process(thread);
2449 wait_for_completion(&cgr_comp.completion);
2450 preempt_enable();
2451 return;
2452 }
2453 out:
2454 qman_delete_cgr(cgr);
2455 preempt_enable();
2456 }
2457 EXPORT_SYMBOL(qman_delete_cgr_safe);
2458
2459 /* Cleanup FQs */
2460
2461 static int _qm_mr_consume_and_match_verb(struct qm_portal *p, int v)
2462 {
2463 const union qm_mr_entry *msg;
2464 int found = 0;
2465
2466 qm_mr_pvb_update(p);
2467 msg = qm_mr_current(p);
2468 while (msg) {
2469 if ((msg->verb & QM_MR_VERB_TYPE_MASK) == v)
2470 found = 1;
2471 qm_mr_next(p);
2472 qm_mr_cci_consume_to_current(p);
2473 qm_mr_pvb_update(p);
2474 msg = qm_mr_current(p);
2475 }
2476 return found;
2477 }
2478
2479 static int _qm_dqrr_consume_and_match(struct qm_portal *p, u32 fqid, int s,
2480 bool wait)
2481 {
2482 const struct qm_dqrr_entry *dqrr;
2483 int found = 0;
2484
2485 do {
2486 qm_dqrr_pvb_update(p);
2487 dqrr = qm_dqrr_current(p);
2488 if (!dqrr)
2489 cpu_relax();
2490 } while (wait && !dqrr);
2491
2492 while (dqrr) {
2493 if (dqrr->fqid == fqid && (dqrr->stat & s))
2494 found = 1;
2495 qm_dqrr_cdc_consume_1ptr(p, dqrr, 0);
2496 qm_dqrr_pvb_update(p);
2497 qm_dqrr_next(p);
2498 dqrr = qm_dqrr_current(p);
2499 }
2500 return found;
2501 }
2502
2503 #define qm_mr_drain(p, V) \
2504 _qm_mr_consume_and_match_verb(p, QM_MR_VERB_##V)
2505
2506 #define qm_dqrr_drain(p, f, S) \
2507 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, false)
2508
2509 #define qm_dqrr_drain_wait(p, f, S) \
2510 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, true)
2511
2512 #define qm_dqrr_drain_nomatch(p) \
2513 _qm_dqrr_consume_and_match(p, 0, 0, false)
2514
2515 static int qman_shutdown_fq(u32 fqid)
2516 {
2517 struct qman_portal *p;
2518 struct device *dev;
2519 union qm_mc_command *mcc;
2520 union qm_mc_result *mcr;
2521 int orl_empty, drain = 0, ret = 0;
2522 u32 channel, wq, res;
2523 u8 state;
2524
2525 p = get_affine_portal();
2526 dev = p->config->dev;
2527 /* Determine the state of the FQID */
2528 mcc = qm_mc_start(&p->p);
2529 mcc->queryfq_np.fqid = fqid;
2530 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2531 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2532 dev_err(dev, "QUERYFQ_NP timeout\n");
2533 ret = -ETIMEDOUT;
2534 goto out;
2535 }
2536
2537 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2538 state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
2539 if (state == QM_MCR_NP_STATE_OOS)
2540 goto out; /* Already OOS, no need to do anymore checks */
2541
2542 /* Query which channel the FQ is using */
2543 mcc = qm_mc_start(&p->p);
2544 mcc->queryfq.fqid = fqid;
2545 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2546 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2547 dev_err(dev, "QUERYFQ timeout\n");
2548 ret = -ETIMEDOUT;
2549 goto out;
2550 }
2551
2552 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2553 /* Need to store these since the MCR gets reused */
2554 channel = qm_fqd_get_chan(&mcr->queryfq.fqd);
2555 wq = qm_fqd_get_wq(&mcr->queryfq.fqd);
2556
2557 switch (state) {
2558 case QM_MCR_NP_STATE_TEN_SCHED:
2559 case QM_MCR_NP_STATE_TRU_SCHED:
2560 case QM_MCR_NP_STATE_ACTIVE:
2561 case QM_MCR_NP_STATE_PARKED:
2562 orl_empty = 0;
2563 mcc = qm_mc_start(&p->p);
2564 mcc->alterfq.fqid = fqid;
2565 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
2566 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2567 dev_err(dev, "QUERYFQ_NP timeout\n");
2568 ret = -ETIMEDOUT;
2569 goto out;
2570 }
2571 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2572 QM_MCR_VERB_ALTER_RETIRE);
2573 res = mcr->result; /* Make a copy as we reuse MCR below */
2574
2575 if (res == QM_MCR_RESULT_PENDING) {
2576 /*
2577 * Need to wait for the FQRN in the message ring, which
2578 * will only occur once the FQ has been drained. In
2579 * order for the FQ to drain the portal needs to be set
2580 * to dequeue from the channel the FQ is scheduled on
2581 */
2582 int found_fqrn = 0;
2583 u16 dequeue_wq = 0;
2584
2585 /* Flag that we need to drain FQ */
2586 drain = 1;
2587
2588 if (channel >= qm_channel_pool1 &&
2589 channel < qm_channel_pool1 + 15) {
2590 /* Pool channel, enable the bit in the portal */
2591 dequeue_wq = (channel -
2592 qm_channel_pool1 + 1)<<4 | wq;
2593 } else if (channel < qm_channel_pool1) {
2594 /* Dedicated channel */
2595 dequeue_wq = wq;
2596 } else {
2597 dev_err(dev, "Can't recover FQ 0x%x, ch: 0x%x",
2598 fqid, channel);
2599 ret = -EBUSY;
2600 goto out;
2601 }
2602 /* Set the sdqcr to drain this channel */
2603 if (channel < qm_channel_pool1)
2604 qm_dqrr_sdqcr_set(&p->p,
2605 QM_SDQCR_TYPE_ACTIVE |
2606 QM_SDQCR_CHANNELS_DEDICATED);
2607 else
2608 qm_dqrr_sdqcr_set(&p->p,
2609 QM_SDQCR_TYPE_ACTIVE |
2610 QM_SDQCR_CHANNELS_POOL_CONV
2611 (channel));
2612 do {
2613 /* Keep draining DQRR while checking the MR*/
2614 qm_dqrr_drain_nomatch(&p->p);
2615 /* Process message ring too */
2616 found_fqrn = qm_mr_drain(&p->p, FQRN);
2617 cpu_relax();
2618 } while (!found_fqrn);
2619
2620 }
2621 if (res != QM_MCR_RESULT_OK &&
2622 res != QM_MCR_RESULT_PENDING) {
2623 dev_err(dev, "retire_fq failed: FQ 0x%x, res=0x%x\n",
2624 fqid, res);
2625 ret = -EIO;
2626 goto out;
2627 }
2628 if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
2629 /*
2630 * ORL had no entries, no need to wait until the
2631 * ERNs come in
2632 */
2633 orl_empty = 1;
2634 }
2635 /*
2636 * Retirement succeeded, check to see if FQ needs
2637 * to be drained
2638 */
2639 if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) {
2640 /* FQ is Not Empty, drain using volatile DQ commands */
2641 do {
2642 u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3);
2643
2644 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2645 /*
2646 * Wait for a dequeue and process the dequeues,
2647 * making sure to empty the ring completely
2648 */
2649 } while (qm_dqrr_drain_wait(&p->p, fqid, FQ_EMPTY));
2650 }
2651 qm_dqrr_sdqcr_set(&p->p, 0);
2652
2653 while (!orl_empty) {
2654 /* Wait for the ORL to have been completely drained */
2655 orl_empty = qm_mr_drain(&p->p, FQRL);
2656 cpu_relax();
2657 }
2658 mcc = qm_mc_start(&p->p);
2659 mcc->alterfq.fqid = fqid;
2660 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2661 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2662 ret = -ETIMEDOUT;
2663 goto out;
2664 }
2665
2666 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2667 QM_MCR_VERB_ALTER_OOS);
2668 if (mcr->result != QM_MCR_RESULT_OK) {
2669 dev_err(dev, "OOS after drain fail: FQ 0x%x (0x%x)\n",
2670 fqid, mcr->result);
2671 ret = -EIO;
2672 goto out;
2673 }
2674 break;
2675
2676 case QM_MCR_NP_STATE_RETIRED:
2677 /* Send OOS Command */
2678 mcc = qm_mc_start(&p->p);
2679 mcc->alterfq.fqid = fqid;
2680 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2681 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2682 ret = -ETIMEDOUT;
2683 goto out;
2684 }
2685
2686 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2687 QM_MCR_VERB_ALTER_OOS);
2688 if (mcr->result) {
2689 dev_err(dev, "OOS fail: FQ 0x%x (0x%x)\n",
2690 fqid, mcr->result);
2691 ret = -EIO;
2692 goto out;
2693 }
2694 break;
2695
2696 case QM_MCR_NP_STATE_OOS:
2697 /* Done */
2698 break;
2699
2700 default:
2701 ret = -EIO;
2702 }
2703
2704 out:
2705 put_affine_portal();
2706 return ret;
2707 }
2708
2709 const struct qm_portal_config *qman_get_qm_portal_config(
2710 struct qman_portal *portal)
2711 {
2712 return portal->config;
2713 }
2714 EXPORT_SYMBOL(qman_get_qm_portal_config);
2715
2716 struct gen_pool *qm_fqalloc; /* FQID allocator */
2717 struct gen_pool *qm_qpalloc; /* pool-channel allocator */
2718 struct gen_pool *qm_cgralloc; /* CGR ID allocator */
2719
2720 static int qman_alloc_range(struct gen_pool *p, u32 *result, u32 cnt)
2721 {
2722 unsigned long addr;
2723
2724 addr = gen_pool_alloc(p, cnt);
2725 if (!addr)
2726 return -ENOMEM;
2727
2728 *result = addr & ~DPAA_GENALLOC_OFF;
2729
2730 return 0;
2731 }
2732
2733 int qman_alloc_fqid_range(u32 *result, u32 count)
2734 {
2735 return qman_alloc_range(qm_fqalloc, result, count);
2736 }
2737 EXPORT_SYMBOL(qman_alloc_fqid_range);
2738
2739 int qman_alloc_pool_range(u32 *result, u32 count)
2740 {
2741 return qman_alloc_range(qm_qpalloc, result, count);
2742 }
2743 EXPORT_SYMBOL(qman_alloc_pool_range);
2744
2745 int qman_alloc_cgrid_range(u32 *result, u32 count)
2746 {
2747 return qman_alloc_range(qm_cgralloc, result, count);
2748 }
2749 EXPORT_SYMBOL(qman_alloc_cgrid_range);
2750
2751 int qman_release_fqid(u32 fqid)
2752 {
2753 int ret = qman_shutdown_fq(fqid);
2754
2755 if (ret) {
2756 pr_debug("FQID %d leaked\n", fqid);
2757 return ret;
2758 }
2759
2760 gen_pool_free(qm_fqalloc, fqid | DPAA_GENALLOC_OFF, 1);
2761 return 0;
2762 }
2763 EXPORT_SYMBOL(qman_release_fqid);
2764
2765 static int qpool_cleanup(u32 qp)
2766 {
2767 /*
2768 * We query all FQDs starting from
2769 * FQID 1 until we get an "invalid FQID" error, looking for non-OOS FQDs
2770 * whose destination channel is the pool-channel being released.
2771 * When a non-OOS FQD is found we attempt to clean it up
2772 */
2773 struct qman_fq fq = {
2774 .fqid = QM_FQID_RANGE_START
2775 };
2776 int err;
2777
2778 do {
2779 struct qm_mcr_queryfq_np np;
2780
2781 err = qman_query_fq_np(&fq, &np);
2782 if (err == -ERANGE)
2783 /* FQID range exceeded, found no problems */
2784 return 0;
2785 else if (WARN_ON(err))
2786 return err;
2787
2788 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2789 struct qm_fqd fqd;
2790
2791 err = qman_query_fq(&fq, &fqd);
2792 if (WARN_ON(err))
2793 return err;
2794 if (qm_fqd_get_chan(&fqd) == qp) {
2795 /* The channel is the FQ's target, clean it */
2796 err = qman_shutdown_fq(fq.fqid);
2797 if (err)
2798 /*
2799 * Couldn't shut down the FQ
2800 * so the pool must be leaked
2801 */
2802 return err;
2803 }
2804 }
2805 /* Move to the next FQID */
2806 fq.fqid++;
2807 } while (1);
2808 }
2809
2810 int qman_release_pool(u32 qp)
2811 {
2812 int ret;
2813
2814 ret = qpool_cleanup(qp);
2815 if (ret) {
2816 pr_debug("CHID %d leaked\n", qp);
2817 return ret;
2818 }
2819
2820 gen_pool_free(qm_qpalloc, qp | DPAA_GENALLOC_OFF, 1);
2821 return 0;
2822 }
2823 EXPORT_SYMBOL(qman_release_pool);
2824
2825 static int cgr_cleanup(u32 cgrid)
2826 {
2827 /*
2828 * query all FQDs starting from FQID 1 until we get an "invalid FQID"
2829 * error, looking for non-OOS FQDs whose CGR is the CGR being released
2830 */
2831 struct qman_fq fq = {
2832 .fqid = QM_FQID_RANGE_START
2833 };
2834 int err;
2835
2836 do {
2837 struct qm_mcr_queryfq_np np;
2838
2839 err = qman_query_fq_np(&fq, &np);
2840 if (err == -ERANGE)
2841 /* FQID range exceeded, found no problems */
2842 return 0;
2843 else if (WARN_ON(err))
2844 return err;
2845
2846 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2847 struct qm_fqd fqd;
2848
2849 err = qman_query_fq(&fq, &fqd);
2850 if (WARN_ON(err))
2851 return err;
2852 if ((fqd.fq_ctrl & QM_FQCTRL_CGE) &&
2853 fqd.cgid == cgrid) {
2854 pr_err("CRGID 0x%x is being used by FQID 0x%x, CGR will be leaked\n",
2855 cgrid, fq.fqid);
2856 return -EIO;
2857 }
2858 }
2859 /* Move to the next FQID */
2860 fq.fqid++;
2861 } while (1);
2862 }
2863
2864 int qman_release_cgrid(u32 cgrid)
2865 {
2866 int ret;
2867
2868 ret = cgr_cleanup(cgrid);
2869 if (ret) {
2870 pr_debug("CGRID %d leaked\n", cgrid);
2871 return ret;
2872 }
2873
2874 gen_pool_free(qm_cgralloc, cgrid | DPAA_GENALLOC_OFF, 1);
2875 return 0;
2876 }
2877 EXPORT_SYMBOL(qman_release_cgrid);
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