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rtc: ds1307: factor out century bit handling
[linux-2.6/btrfs-unstable.git] / drivers / rtc / rtc-ds1307.c
blob922675281b7aee06c54e19115a35f9b16a632998
1 /*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/acpi.h>
15 #include <linux/bcd.h>
16 #include <linux/i2c.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/rtc/ds1307.h>
21 #include <linux/rtc.h>
22 #include <linux/slab.h>
23 #include <linux/string.h>
24 #include <linux/hwmon.h>
25 #include <linux/hwmon-sysfs.h>
26 #include <linux/clk-provider.h>
27 #include <linux/regmap.h>
28
29 /*
30 * We can't determine type by probing, but if we expect pre-Linux code
31 * to have set the chip up as a clock (turning on the oscillator and
32 * setting the date and time), Linux can ignore the non-clock features.
33 * That's a natural job for a factory or repair bench.
34 */
35 enum ds_type {
36 ds_1307,
37 ds_1337,
38 ds_1338,
39 ds_1339,
40 ds_1340,
41 ds_1388,
42 ds_3231,
43 m41t0,
44 m41t00,
45 mcp794xx,
46 rx_8025,
47 rx_8130,
48 last_ds_type /* always last */
49 /* rs5c372 too? different address... */
50 };
51
52
53 /* RTC registers don't differ much, except for the century flag */
54 #define DS1307_REG_SECS 0x00 /* 00-59 */
55 # define DS1307_BIT_CH 0x80
56 # define DS1340_BIT_nEOSC 0x80
57 # define MCP794XX_BIT_ST 0x80
58 #define DS1307_REG_MIN 0x01 /* 00-59 */
59 # define M41T0_BIT_OF 0x80
60 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
61 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
62 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
63 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
64 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
65 #define DS1307_REG_WDAY 0x03 /* 01-07 */
66 # define MCP794XX_BIT_VBATEN 0x08
67 #define DS1307_REG_MDAY 0x04 /* 01-31 */
68 #define DS1307_REG_MONTH 0x05 /* 01-12 */
69 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
70 #define DS1307_REG_YEAR 0x06 /* 00-99 */
71
72 /*
73 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
74 * start at 7, and they differ a LOT. Only control and status matter for
75 * basic RTC date and time functionality; be careful using them.
76 */
77 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
78 # define DS1307_BIT_OUT 0x80
79 # define DS1338_BIT_OSF 0x20
80 # define DS1307_BIT_SQWE 0x10
81 # define DS1307_BIT_RS1 0x02
82 # define DS1307_BIT_RS0 0x01
83 #define DS1337_REG_CONTROL 0x0e
84 # define DS1337_BIT_nEOSC 0x80
85 # define DS1339_BIT_BBSQI 0x20
86 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
87 # define DS1337_BIT_RS2 0x10
88 # define DS1337_BIT_RS1 0x08
89 # define DS1337_BIT_INTCN 0x04
90 # define DS1337_BIT_A2IE 0x02
91 # define DS1337_BIT_A1IE 0x01
92 #define DS1340_REG_CONTROL 0x07
93 # define DS1340_BIT_OUT 0x80
94 # define DS1340_BIT_FT 0x40
95 # define DS1340_BIT_CALIB_SIGN 0x20
96 # define DS1340_M_CALIBRATION 0x1f
97 #define DS1340_REG_FLAG 0x09
98 # define DS1340_BIT_OSF 0x80
99 #define DS1337_REG_STATUS 0x0f
100 # define DS1337_BIT_OSF 0x80
101 # define DS3231_BIT_EN32KHZ 0x08
102 # define DS1337_BIT_A2I 0x02
103 # define DS1337_BIT_A1I 0x01
104 #define DS1339_REG_ALARM1_SECS 0x07
105
106 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
107
108 #define RX8025_REG_CTRL1 0x0e
109 # define RX8025_BIT_2412 0x20
110 #define RX8025_REG_CTRL2 0x0f
111 # define RX8025_BIT_PON 0x10
112 # define RX8025_BIT_VDET 0x40
113 # define RX8025_BIT_XST 0x20
114
115
116 struct ds1307 {
117 u8 offset; /* register's offset */
118 u8 regs[11];
119 u16 nvram_offset;
120 struct bin_attribute *nvram;
121 enum ds_type type;
122 unsigned long flags;
123 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
124 #define HAS_ALARM 1 /* bit 1 == irq claimed */
125 struct device *dev;
126 struct regmap *regmap;
127 const char *name;
128 int irq;
129 struct rtc_device *rtc;
130 #ifdef CONFIG_COMMON_CLK
131 struct clk_hw clks[2];
132 #endif
133 };
134
135 struct chip_desc {
136 unsigned alarm:1;
137 u16 nvram_offset;
138 u16 nvram_size;
139 u8 century_reg;
140 u8 century_enable_bit;
141 u8 century_bit;
142 u16 trickle_charger_reg;
143 u8 trickle_charger_setup;
144 u8 (*do_trickle_setup)(struct ds1307 *, uint32_t,
145 bool);
146 };
147
148 static u8 do_trickle_setup_ds1339(struct ds1307 *, uint32_t ohms, bool diode);
149
150 static struct chip_desc chips[last_ds_type] = {
151 [ds_1307] = {
152 .nvram_offset = 8,
153 .nvram_size = 56,
154 },
155 [ds_1337] = {
156 .alarm = 1,
157 .century_reg = DS1307_REG_MONTH,
158 .century_bit = DS1337_BIT_CENTURY,
159 },
160 [ds_1338] = {
161 .nvram_offset = 8,
162 .nvram_size = 56,
163 },
164 [ds_1339] = {
165 .alarm = 1,
166 .century_reg = DS1307_REG_MONTH,
167 .century_bit = DS1337_BIT_CENTURY,
168 .trickle_charger_reg = 0x10,
169 .do_trickle_setup = &do_trickle_setup_ds1339,
170 },
171 [ds_1340] = {
172 .century_reg = DS1307_REG_HOUR,
173 .century_enable_bit = DS1340_BIT_CENTURY_EN,
174 .century_bit = DS1340_BIT_CENTURY,
175 .trickle_charger_reg = 0x08,
176 },
177 [ds_1388] = {
178 .trickle_charger_reg = 0x0a,
179 },
180 [ds_3231] = {
181 .alarm = 1,
182 .century_reg = DS1307_REG_MONTH,
183 .century_bit = DS1337_BIT_CENTURY,
184 },
185 [rx_8130] = {
186 .alarm = 1,
187 /* this is battery backed SRAM */
188 .nvram_offset = 0x20,
189 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
190 },
191 [mcp794xx] = {
192 .alarm = 1,
193 /* this is battery backed SRAM */
194 .nvram_offset = 0x20,
195 .nvram_size = 0x40,
196 },
197 };
198
199 static const struct i2c_device_id ds1307_id[] = {
200 { "ds1307", ds_1307 },
201 { "ds1337", ds_1337 },
202 { "ds1338", ds_1338 },
203 { "ds1339", ds_1339 },
204 { "ds1388", ds_1388 },
205 { "ds1340", ds_1340 },
206 { "ds3231", ds_3231 },
207 { "m41t0", m41t0 },
208 { "m41t00", m41t00 },
209 { "mcp7940x", mcp794xx },
210 { "mcp7941x", mcp794xx },
211 { "pt7c4338", ds_1307 },
212 { "rx8025", rx_8025 },
213 { "isl12057", ds_1337 },
214 { "rx8130", rx_8130 },
215 { }
216 };
217 MODULE_DEVICE_TABLE(i2c, ds1307_id);
218
219 #ifdef CONFIG_OF
220 static const struct of_device_id ds1307_of_match[] = {
221 {
222 .compatible = "dallas,ds1307",
223 .data = (void *)ds_1307
224 },
225 {
226 .compatible = "dallas,ds1337",
227 .data = (void *)ds_1337
228 },
229 {
230 .compatible = "dallas,ds1338",
231 .data = (void *)ds_1338
232 },
233 {
234 .compatible = "dallas,ds1339",
235 .data = (void *)ds_1339
236 },
237 {
238 .compatible = "dallas,ds1388",
239 .data = (void *)ds_1388
240 },
241 {
242 .compatible = "dallas,ds1340",
243 .data = (void *)ds_1340
244 },
245 {
246 .compatible = "maxim,ds3231",
247 .data = (void *)ds_3231
248 },
249 {
250 .compatible = "st,m41t0",
251 .data = (void *)m41t00
252 },
253 {
254 .compatible = "st,m41t00",
255 .data = (void *)m41t00
256 },
257 {
258 .compatible = "microchip,mcp7940x",
259 .data = (void *)mcp794xx
260 },
261 {
262 .compatible = "microchip,mcp7941x",
263 .data = (void *)mcp794xx
264 },
265 {
266 .compatible = "pericom,pt7c4338",
267 .data = (void *)ds_1307
268 },
269 {
270 .compatible = "epson,rx8025",
271 .data = (void *)rx_8025
272 },
273 {
274 .compatible = "isil,isl12057",
275 .data = (void *)ds_1337
276 },
277 { }
278 };
279 MODULE_DEVICE_TABLE(of, ds1307_of_match);
280 #endif
281
282 #ifdef CONFIG_ACPI
283 static const struct acpi_device_id ds1307_acpi_ids[] = {
284 { .id = "DS1307", .driver_data = ds_1307 },
285 { .id = "DS1337", .driver_data = ds_1337 },
286 { .id = "DS1338", .driver_data = ds_1338 },
287 { .id = "DS1339", .driver_data = ds_1339 },
288 { .id = "DS1388", .driver_data = ds_1388 },
289 { .id = "DS1340", .driver_data = ds_1340 },
290 { .id = "DS3231", .driver_data = ds_3231 },
291 { .id = "M41T0", .driver_data = m41t0 },
292 { .id = "M41T00", .driver_data = m41t00 },
293 { .id = "MCP7940X", .driver_data = mcp794xx },
294 { .id = "MCP7941X", .driver_data = mcp794xx },
295 { .id = "PT7C4338", .driver_data = ds_1307 },
296 { .id = "RX8025", .driver_data = rx_8025 },
297 { .id = "ISL12057", .driver_data = ds_1337 },
298 { }
299 };
300 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
301 #endif
302
303 /*
304 * The ds1337 and ds1339 both have two alarms, but we only use the first
305 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
306 * signal; ds1339 chips have only one alarm signal.
307 */
308 static irqreturn_t ds1307_irq(int irq, void *dev_id)
309 {
310 struct ds1307 *ds1307 = dev_id;
311 struct mutex *lock = &ds1307->rtc->ops_lock;
312 int stat, ret;
313
314 mutex_lock(lock);
315 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
316 if (ret)
317 goto out;
318
319 if (stat & DS1337_BIT_A1I) {
320 stat &= ~DS1337_BIT_A1I;
321 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
322
323 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
324 DS1337_BIT_A1IE, 0);
325 if (ret)
326 goto out;
327
328 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
329 }
330
331 out:
332 mutex_unlock(lock);
333
334 return IRQ_HANDLED;
335 }
336
337 /*----------------------------------------------------------------------*/
338
339 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
340 {
341 struct ds1307 *ds1307 = dev_get_drvdata(dev);
342 int tmp, ret;
343 const struct chip_desc *chip = &chips[ds1307->type];
344
345 /* read the RTC date and time registers all at once */
346 ret = regmap_bulk_read(ds1307->regmap, ds1307->offset, ds1307->regs, 7);
347 if (ret) {
348 dev_err(dev, "%s error %d\n", "read", ret);
349 return ret;
350 }
351
352 dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
353
354 /* if oscillator fail bit is set, no data can be trusted */
355 if (ds1307->type == m41t0 &&
356 ds1307->regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
357 dev_warn_once(dev, "oscillator failed, set time!\n");
358 return -EINVAL;
359 }
360
361 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
362 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
363 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
364 t->tm_hour = bcd2bin(tmp);
365 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
366 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
367 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
368 t->tm_mon = bcd2bin(tmp) - 1;
369 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
370
371 if (ds1307->regs[chip->century_reg] & chip->century_bit &&
372 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
373 t->tm_year += 100;
374
375 dev_dbg(dev, "%s secs=%d, mins=%d, "
376 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
377 "read", t->tm_sec, t->tm_min,
378 t->tm_hour, t->tm_mday,
379 t->tm_mon, t->tm_year, t->tm_wday);
380
381 /* initial clock setting can be undefined */
382 return rtc_valid_tm(t);
383 }
384
385 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
386 {
387 struct ds1307 *ds1307 = dev_get_drvdata(dev);
388 const struct chip_desc *chip = &chips[ds1307->type];
389 int result;
390 int tmp;
391 u8 *buf = ds1307->regs;
392
393 dev_dbg(dev, "%s secs=%d, mins=%d, "
394 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
395 "write", t->tm_sec, t->tm_min,
396 t->tm_hour, t->tm_mday,
397 t->tm_mon, t->tm_year, t->tm_wday);
398
399 if (t->tm_year < 100)
400 return -EINVAL;
401
402 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
403 if (t->tm_year > (chip->century_bit ? 299 : 199))
404 return -EINVAL;
405 #else
406 if (t->tm_year > 199)
407 return -EINVAL;
408 #endif
409
410 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
411 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
412 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
413 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
414 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
415 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
416
417 /* assume 20YY not 19YY */
418 tmp = t->tm_year - 100;
419 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
420
421 if (chip->century_enable_bit)
422 buf[chip->century_reg] |= chip->century_enable_bit;
423 if (t->tm_year > 199 && chip->century_bit)
424 buf[chip->century_reg] |= chip->century_bit;
425
426 if (ds1307->type == mcp794xx) {
427 /*
428 * these bits were cleared when preparing the date/time
429 * values and need to be set again before writing the
430 * buffer out to the device.
431 */
432 buf[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
433 buf[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
434 }
435
436 dev_dbg(dev, "%s: %7ph\n", "write", buf);
437
438 result = regmap_bulk_write(ds1307->regmap, ds1307->offset, buf, 7);
439 if (result) {
440 dev_err(dev, "%s error %d\n", "write", result);
441 return result;
442 }
443 return 0;
444 }
445
446 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
447 {
448 struct ds1307 *ds1307 = dev_get_drvdata(dev);
449 int ret;
450
451 if (!test_bit(HAS_ALARM, &ds1307->flags))
452 return -EINVAL;
453
454 /* read all ALARM1, ALARM2, and status registers at once */
455 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
456 ds1307->regs, 9);
457 if (ret) {
458 dev_err(dev, "%s error %d\n", "alarm read", ret);
459 return ret;
460 }
461
462 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
463 &ds1307->regs[0], &ds1307->regs[4], &ds1307->regs[7]);
464
465 /*
466 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
467 * and that all four fields are checked matches
468 */
469 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
470 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
471 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
472 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
473
474 /* ... and status */
475 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
476 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
477
478 dev_dbg(dev, "%s secs=%d, mins=%d, "
479 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
480 "alarm read", t->time.tm_sec, t->time.tm_min,
481 t->time.tm_hour, t->time.tm_mday,
482 t->enabled, t->pending);
483
484 return 0;
485 }
486
487 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
488 {
489 struct ds1307 *ds1307 = dev_get_drvdata(dev);
490 unsigned char *buf = ds1307->regs;
491 u8 control, status;
492 int ret;
493
494 if (!test_bit(HAS_ALARM, &ds1307->flags))
495 return -EINVAL;
496
497 dev_dbg(dev, "%s secs=%d, mins=%d, "
498 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
499 "alarm set", t->time.tm_sec, t->time.tm_min,
500 t->time.tm_hour, t->time.tm_mday,
501 t->enabled, t->pending);
502
503 /* read current status of both alarms and the chip */
504 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, buf, 9);
505 if (ret) {
506 dev_err(dev, "%s error %d\n", "alarm write", ret);
507 return ret;
508 }
509 control = ds1307->regs[7];
510 status = ds1307->regs[8];
511
512 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
513 &ds1307->regs[0], &ds1307->regs[4], control, status);
514
515 /* set ALARM1, using 24 hour and day-of-month modes */
516 buf[0] = bin2bcd(t->time.tm_sec);
517 buf[1] = bin2bcd(t->time.tm_min);
518 buf[2] = bin2bcd(t->time.tm_hour);
519 buf[3] = bin2bcd(t->time.tm_mday);
520
521 /* set ALARM2 to non-garbage */
522 buf[4] = 0;
523 buf[5] = 0;
524 buf[6] = 0;
525
526 /* disable alarms */
527 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
528 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
529
530 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, buf, 9);
531 if (ret) {
532 dev_err(dev, "can't set alarm time\n");
533 return ret;
534 }
535
536 /* optionally enable ALARM1 */
537 if (t->enabled) {
538 dev_dbg(dev, "alarm IRQ armed\n");
539 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
540 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, buf[7]);
541 }
542
543 return 0;
544 }
545
546 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
547 {
548 struct ds1307 *ds1307 = dev_get_drvdata(dev);
549
550 if (!test_bit(HAS_ALARM, &ds1307->flags))
551 return -ENOTTY;
552
553 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
554 DS1337_BIT_A1IE,
555 enabled ? DS1337_BIT_A1IE : 0);
556 }
557
558 static const struct rtc_class_ops ds13xx_rtc_ops = {
559 .read_time = ds1307_get_time,
560 .set_time = ds1307_set_time,
561 .read_alarm = ds1337_read_alarm,
562 .set_alarm = ds1337_set_alarm,
563 .alarm_irq_enable = ds1307_alarm_irq_enable,
564 };
565
566 /*----------------------------------------------------------------------*/
567
568 /*
569 * Alarm support for rx8130 devices.
570 */
571
572 #define RX8130_REG_ALARM_MIN 0x07
573 #define RX8130_REG_ALARM_HOUR 0x08
574 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x09
575 #define RX8130_REG_EXTENSION 0x0c
576 #define RX8130_REG_EXTENSION_WADA (1 << 3)
577 #define RX8130_REG_FLAG 0x0d
578 #define RX8130_REG_FLAG_AF (1 << 3)
579 #define RX8130_REG_CONTROL0 0x0e
580 #define RX8130_REG_CONTROL0_AIE (1 << 3)
581
582 static irqreturn_t rx8130_irq(int irq, void *dev_id)
583 {
584 struct ds1307 *ds1307 = dev_id;
585 struct mutex *lock = &ds1307->rtc->ops_lock;
586 u8 ctl[3];
587 int ret;
588
589 mutex_lock(lock);
590
591 /* Read control registers. */
592 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
593 if (ret < 0)
594 goto out;
595 if (!(ctl[1] & RX8130_REG_FLAG_AF))
596 goto out;
597 ctl[1] &= ~RX8130_REG_FLAG_AF;
598 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
599
600 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
601 if (ret < 0)
602 goto out;
603
604 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
605
606 out:
607 mutex_unlock(lock);
608
609 return IRQ_HANDLED;
610 }
611
612 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
613 {
614 struct ds1307 *ds1307 = dev_get_drvdata(dev);
615 u8 ald[3], ctl[3];
616 int ret;
617
618 if (!test_bit(HAS_ALARM, &ds1307->flags))
619 return -EINVAL;
620
621 /* Read alarm registers. */
622 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 3);
623 if (ret < 0)
624 return ret;
625
626 /* Read control registers. */
627 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
628 if (ret < 0)
629 return ret;
630
631 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
632 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
633
634 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
635 t->time.tm_sec = -1;
636 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
637 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
638 t->time.tm_wday = -1;
639 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
640 t->time.tm_mon = -1;
641 t->time.tm_year = -1;
642 t->time.tm_yday = -1;
643 t->time.tm_isdst = -1;
644
645 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
646 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
647 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
648
649 return 0;
650 }
651
652 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
653 {
654 struct ds1307 *ds1307 = dev_get_drvdata(dev);
655 u8 ald[3], ctl[3];
656 int ret;
657
658 if (!test_bit(HAS_ALARM, &ds1307->flags))
659 return -EINVAL;
660
661 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
662 "enabled=%d pending=%d\n", __func__,
663 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
664 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
665 t->enabled, t->pending);
666
667 /* Read control registers. */
668 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
669 if (ret < 0)
670 return ret;
671
672 ctl[0] &= ~RX8130_REG_EXTENSION_WADA;
673 ctl[1] |= RX8130_REG_FLAG_AF;
674 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
675
676 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
677 if (ret < 0)
678 return ret;
679
680 /* Hardware alarm precision is 1 minute! */
681 ald[0] = bin2bcd(t->time.tm_min);
682 ald[1] = bin2bcd(t->time.tm_hour);
683 ald[2] = bin2bcd(t->time.tm_mday);
684
685 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, 3);
686 if (ret < 0)
687 return ret;
688
689 if (!t->enabled)
690 return 0;
691
692 ctl[2] |= RX8130_REG_CONTROL0_AIE;
693
694 return regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 3);
695 }
696
697 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
698 {
699 struct ds1307 *ds1307 = dev_get_drvdata(dev);
700 int ret, reg;
701
702 if (!test_bit(HAS_ALARM, &ds1307->flags))
703 return -EINVAL;
704
705 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
706 if (ret < 0)
707 return ret;
708
709 if (enabled)
710 reg |= RX8130_REG_CONTROL0_AIE;
711 else
712 reg &= ~RX8130_REG_CONTROL0_AIE;
713
714 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
715 }
716
717 static const struct rtc_class_ops rx8130_rtc_ops = {
718 .read_time = ds1307_get_time,
719 .set_time = ds1307_set_time,
720 .read_alarm = rx8130_read_alarm,
721 .set_alarm = rx8130_set_alarm,
722 .alarm_irq_enable = rx8130_alarm_irq_enable,
723 };
724
725 /*----------------------------------------------------------------------*/
726
727 /*
728 * Alarm support for mcp794xx devices.
729 */
730
731 #define MCP794XX_REG_WEEKDAY 0x3
732 #define MCP794XX_REG_WEEKDAY_WDAY_MASK 0x7
733 #define MCP794XX_REG_CONTROL 0x07
734 # define MCP794XX_BIT_ALM0_EN 0x10
735 # define MCP794XX_BIT_ALM1_EN 0x20
736 #define MCP794XX_REG_ALARM0_BASE 0x0a
737 #define MCP794XX_REG_ALARM0_CTRL 0x0d
738 #define MCP794XX_REG_ALARM1_BASE 0x11
739 #define MCP794XX_REG_ALARM1_CTRL 0x14
740 # define MCP794XX_BIT_ALMX_IF (1 << 3)
741 # define MCP794XX_BIT_ALMX_C0 (1 << 4)
742 # define MCP794XX_BIT_ALMX_C1 (1 << 5)
743 # define MCP794XX_BIT_ALMX_C2 (1 << 6)
744 # define MCP794XX_BIT_ALMX_POL (1 << 7)
745 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
746 MCP794XX_BIT_ALMX_C1 | \
747 MCP794XX_BIT_ALMX_C2)
748
749 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
750 {
751 struct ds1307 *ds1307 = dev_id;
752 struct mutex *lock = &ds1307->rtc->ops_lock;
753 int reg, ret;
754
755 mutex_lock(lock);
756
757 /* Check and clear alarm 0 interrupt flag. */
758 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
759 if (ret)
760 goto out;
761 if (!(reg & MCP794XX_BIT_ALMX_IF))
762 goto out;
763 reg &= ~MCP794XX_BIT_ALMX_IF;
764 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
765 if (ret)
766 goto out;
767
768 /* Disable alarm 0. */
769 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
770 MCP794XX_BIT_ALM0_EN, 0);
771 if (ret)
772 goto out;
773
774 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
775
776 out:
777 mutex_unlock(lock);
778
779 return IRQ_HANDLED;
780 }
781
782 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
783 {
784 struct ds1307 *ds1307 = dev_get_drvdata(dev);
785 u8 *regs = ds1307->regs;
786 int ret;
787
788 if (!test_bit(HAS_ALARM, &ds1307->flags))
789 return -EINVAL;
790
791 /* Read control and alarm 0 registers. */
792 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 10);
793 if (ret)
794 return ret;
795
796 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
797
798 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
799 t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f);
800 t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f);
801 t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f);
802 t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1;
803 t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f);
804 t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1;
805 t->time.tm_year = -1;
806 t->time.tm_yday = -1;
807 t->time.tm_isdst = -1;
808
809 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
810 "enabled=%d polarity=%d irq=%d match=%d\n", __func__,
811 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
812 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
813 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_POL),
814 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_IF),
815 (ds1307->regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
816
817 return 0;
818 }
819
820 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
821 {
822 struct ds1307 *ds1307 = dev_get_drvdata(dev);
823 unsigned char *regs = ds1307->regs;
824 int ret;
825
826 if (!test_bit(HAS_ALARM, &ds1307->flags))
827 return -EINVAL;
828
829 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
830 "enabled=%d pending=%d\n", __func__,
831 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
832 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
833 t->enabled, t->pending);
834
835 /* Read control and alarm 0 registers. */
836 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 10);
837 if (ret)
838 return ret;
839
840 /* Set alarm 0, using 24-hour and day-of-month modes. */
841 regs[3] = bin2bcd(t->time.tm_sec);
842 regs[4] = bin2bcd(t->time.tm_min);
843 regs[5] = bin2bcd(t->time.tm_hour);
844 regs[6] = bin2bcd(t->time.tm_wday + 1);
845 regs[7] = bin2bcd(t->time.tm_mday);
846 regs[8] = bin2bcd(t->time.tm_mon + 1);
847
848 /* Clear the alarm 0 interrupt flag. */
849 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
850 /* Set alarm match: second, minute, hour, day, date, month. */
851 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
852 /* Disable interrupt. We will not enable until completely programmed */
853 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
854
855 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, 10);
856 if (ret)
857 return ret;
858
859 if (!t->enabled)
860 return 0;
861 regs[0] |= MCP794XX_BIT_ALM0_EN;
862 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
863 }
864
865 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
866 {
867 struct ds1307 *ds1307 = dev_get_drvdata(dev);
868
869 if (!test_bit(HAS_ALARM, &ds1307->flags))
870 return -EINVAL;
871
872 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
873 MCP794XX_BIT_ALM0_EN,
874 enabled ? MCP794XX_BIT_ALM0_EN : 0);
875 }
876
877 static const struct rtc_class_ops mcp794xx_rtc_ops = {
878 .read_time = ds1307_get_time,
879 .set_time = ds1307_set_time,
880 .read_alarm = mcp794xx_read_alarm,
881 .set_alarm = mcp794xx_set_alarm,
882 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
883 };
884
885 /*----------------------------------------------------------------------*/
886
887 static ssize_t
888 ds1307_nvram_read(struct file *filp, struct kobject *kobj,
889 struct bin_attribute *attr,
890 char *buf, loff_t off, size_t count)
891 {
892 struct ds1307 *ds1307;
893 int result;
894
895 ds1307 = dev_get_drvdata(kobj_to_dev(kobj));
896
897 result = regmap_bulk_read(ds1307->regmap, ds1307->nvram_offset + off,
898 buf, count);
899 if (result)
900 dev_err(ds1307->dev, "%s error %d\n", "nvram read", result);
901 return result;
902 }
903
904 static ssize_t
905 ds1307_nvram_write(struct file *filp, struct kobject *kobj,
906 struct bin_attribute *attr,
907 char *buf, loff_t off, size_t count)
908 {
909 struct ds1307 *ds1307;
910 int result;
911
912 ds1307 = dev_get_drvdata(kobj_to_dev(kobj));
913
914 result = regmap_bulk_write(ds1307->regmap, ds1307->nvram_offset + off,
915 buf, count);
916 if (result) {
917 dev_err(ds1307->dev, "%s error %d\n", "nvram write", result);
918 return result;
919 }
920 return count;
921 }
922
923
924 /*----------------------------------------------------------------------*/
925
926 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
927 uint32_t ohms, bool diode)
928 {
929 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
930 DS1307_TRICKLE_CHARGER_NO_DIODE;
931
932 switch (ohms) {
933 case 250:
934 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
935 break;
936 case 2000:
937 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
938 break;
939 case 4000:
940 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
941 break;
942 default:
943 dev_warn(ds1307->dev,
944 "Unsupported ohm value %u in dt\n", ohms);
945 return 0;
946 }
947 return setup;
948 }
949
950 static void ds1307_trickle_init(struct ds1307 *ds1307,
951 struct chip_desc *chip)
952 {
953 uint32_t ohms = 0;
954 bool diode = true;
955
956 if (!chip->do_trickle_setup)
957 goto out;
958 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
959 &ohms))
960 goto out;
961 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
962 diode = false;
963 chip->trickle_charger_setup = chip->do_trickle_setup(ds1307,
964 ohms, diode);
965 out:
966 return;
967 }
968
969 /*----------------------------------------------------------------------*/
970
971 #ifdef CONFIG_RTC_DRV_DS1307_HWMON
972
973 /*
974 * Temperature sensor support for ds3231 devices.
975 */
976
977 #define DS3231_REG_TEMPERATURE 0x11
978
979 /*
980 * A user-initiated temperature conversion is not started by this function,
981 * so the temperature is updated once every 64 seconds.
982 */
983 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
984 {
985 struct ds1307 *ds1307 = dev_get_drvdata(dev);
986 u8 temp_buf[2];
987 s16 temp;
988 int ret;
989
990 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
991 temp_buf, sizeof(temp_buf));
992 if (ret)
993 return ret;
994 /*
995 * Temperature is represented as a 10-bit code with a resolution of
996 * 0.25 degree celsius and encoded in two's complement format.
997 */
998 temp = (temp_buf[0] << 8) | temp_buf[1];
999 temp >>= 6;
1000 *mC = temp * 250;
1001
1002 return 0;
1003 }
1004
1005 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1006 struct device_attribute *attr, char *buf)
1007 {
1008 int ret;
1009 s32 temp;
1010
1011 ret = ds3231_hwmon_read_temp(dev, &temp);
1012 if (ret)
1013 return ret;
1014
1015 return sprintf(buf, "%d\n", temp);
1016 }
1017 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, ds3231_hwmon_show_temp,
1018 NULL, 0);
1019
1020 static struct attribute *ds3231_hwmon_attrs[] = {
1021 &sensor_dev_attr_temp1_input.dev_attr.attr,
1022 NULL,
1023 };
1024 ATTRIBUTE_GROUPS(ds3231_hwmon);
1025
1026 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1027 {
1028 struct device *dev;
1029
1030 if (ds1307->type != ds_3231)
1031 return;
1032
1033 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1034 ds1307, ds3231_hwmon_groups);
1035 if (IS_ERR(dev)) {
1036 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1037 PTR_ERR(dev));
1038 }
1039 }
1040
1041 #else
1042
1043 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1044 {
1045 }
1046
1047 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1048
1049 /*----------------------------------------------------------------------*/
1050
1051 /*
1052 * Square-wave output support for DS3231
1053 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1054 */
1055 #ifdef CONFIG_COMMON_CLK
1056
1057 enum {
1058 DS3231_CLK_SQW = 0,
1059 DS3231_CLK_32KHZ,
1060 };
1061
1062 #define clk_sqw_to_ds1307(clk) \
1063 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1064 #define clk_32khz_to_ds1307(clk) \
1065 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1066
1067 static int ds3231_clk_sqw_rates[] = {
1068 1,
1069 1024,
1070 4096,
1071 8192,
1072 };
1073
1074 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1075 {
1076 struct mutex *lock = &ds1307->rtc->ops_lock;
1077 int ret;
1078
1079 mutex_lock(lock);
1080 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1081 mask, value);
1082 mutex_unlock(lock);
1083
1084 return ret;
1085 }
1086
1087 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1088 unsigned long parent_rate)
1089 {
1090 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1091 int control, ret;
1092 int rate_sel = 0;
1093
1094 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1095 if (ret)
1096 return ret;
1097 if (control & DS1337_BIT_RS1)
1098 rate_sel += 1;
1099 if (control & DS1337_BIT_RS2)
1100 rate_sel += 2;
1101
1102 return ds3231_clk_sqw_rates[rate_sel];
1103 }
1104
1105 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1106 unsigned long *prate)
1107 {
1108 int i;
1109
1110 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1111 if (ds3231_clk_sqw_rates[i] <= rate)
1112 return ds3231_clk_sqw_rates[i];
1113 }
1114
1115 return 0;
1116 }
1117
1118 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1119 unsigned long parent_rate)
1120 {
1121 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1122 int control = 0;
1123 int rate_sel;
1124
1125 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1126 rate_sel++) {
1127 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1128 break;
1129 }
1130
1131 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1132 return -EINVAL;
1133
1134 if (rate_sel & 1)
1135 control |= DS1337_BIT_RS1;
1136 if (rate_sel & 2)
1137 control |= DS1337_BIT_RS2;
1138
1139 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1140 control);
1141 }
1142
1143 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1144 {
1145 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1146
1147 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1148 }
1149
1150 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1151 {
1152 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1153
1154 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1155 }
1156
1157 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1158 {
1159 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1160 int control, ret;
1161
1162 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1163 if (ret)
1164 return ret;
1165
1166 return !(control & DS1337_BIT_INTCN);
1167 }
1168
1169 static const struct clk_ops ds3231_clk_sqw_ops = {
1170 .prepare = ds3231_clk_sqw_prepare,
1171 .unprepare = ds3231_clk_sqw_unprepare,
1172 .is_prepared = ds3231_clk_sqw_is_prepared,
1173 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1174 .round_rate = ds3231_clk_sqw_round_rate,
1175 .set_rate = ds3231_clk_sqw_set_rate,
1176 };
1177
1178 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1179 unsigned long parent_rate)
1180 {
1181 return 32768;
1182 }
1183
1184 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1185 {
1186 struct mutex *lock = &ds1307->rtc->ops_lock;
1187 int ret;
1188
1189 mutex_lock(lock);
1190 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1191 DS3231_BIT_EN32KHZ,
1192 enable ? DS3231_BIT_EN32KHZ : 0);
1193 mutex_unlock(lock);
1194
1195 return ret;
1196 }
1197
1198 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1199 {
1200 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1201
1202 return ds3231_clk_32khz_control(ds1307, true);
1203 }
1204
1205 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1206 {
1207 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1208
1209 ds3231_clk_32khz_control(ds1307, false);
1210 }
1211
1212 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1213 {
1214 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1215 int status, ret;
1216
1217 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1218 if (ret)
1219 return ret;
1220
1221 return !!(status & DS3231_BIT_EN32KHZ);
1222 }
1223
1224 static const struct clk_ops ds3231_clk_32khz_ops = {
1225 .prepare = ds3231_clk_32khz_prepare,
1226 .unprepare = ds3231_clk_32khz_unprepare,
1227 .is_prepared = ds3231_clk_32khz_is_prepared,
1228 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1229 };
1230
1231 static struct clk_init_data ds3231_clks_init[] = {
1232 [DS3231_CLK_SQW] = {
1233 .name = "ds3231_clk_sqw",
1234 .ops = &ds3231_clk_sqw_ops,
1235 },
1236 [DS3231_CLK_32KHZ] = {
1237 .name = "ds3231_clk_32khz",
1238 .ops = &ds3231_clk_32khz_ops,
1239 },
1240 };
1241
1242 static int ds3231_clks_register(struct ds1307 *ds1307)
1243 {
1244 struct device_node *node = ds1307->dev->of_node;
1245 struct clk_onecell_data *onecell;
1246 int i;
1247
1248 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1249 if (!onecell)
1250 return -ENOMEM;
1251
1252 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1253 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1254 sizeof(onecell->clks[0]), GFP_KERNEL);
1255 if (!onecell->clks)
1256 return -ENOMEM;
1257
1258 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1259 struct clk_init_data init = ds3231_clks_init[i];
1260
1261 /*
1262 * Interrupt signal due to alarm conditions and square-wave
1263 * output share same pin, so don't initialize both.
1264 */
1265 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1266 continue;
1267
1268 /* optional override of the clockname */
1269 of_property_read_string_index(node, "clock-output-names", i,
1270 &init.name);
1271 ds1307->clks[i].init = &init;
1272
1273 onecell->clks[i] = devm_clk_register(ds1307->dev,
1274 &ds1307->clks[i]);
1275 if (IS_ERR(onecell->clks[i]))
1276 return PTR_ERR(onecell->clks[i]);
1277 }
1278
1279 if (!node)
1280 return 0;
1281
1282 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1283
1284 return 0;
1285 }
1286
1287 static void ds1307_clks_register(struct ds1307 *ds1307)
1288 {
1289 int ret;
1290
1291 if (ds1307->type != ds_3231)
1292 return;
1293
1294 ret = ds3231_clks_register(ds1307);
1295 if (ret) {
1296 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1297 ret);
1298 }
1299 }
1300
1301 #else
1302
1303 static void ds1307_clks_register(struct ds1307 *ds1307)
1304 {
1305 }
1306
1307 #endif /* CONFIG_COMMON_CLK */
1308
1309 static const struct regmap_config regmap_config = {
1310 .reg_bits = 8,
1311 .val_bits = 8,
1312 .max_register = 0x12,
1313 };
1314
1315 static int ds1307_probe(struct i2c_client *client,
1316 const struct i2c_device_id *id)
1317 {
1318 struct ds1307 *ds1307;
1319 int err = -ENODEV;
1320 int tmp, wday;
1321 struct chip_desc *chip;
1322 bool want_irq = false;
1323 bool ds1307_can_wakeup_device = false;
1324 unsigned char *buf;
1325 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1326 struct rtc_time tm;
1327 unsigned long timestamp;
1328
1329 irq_handler_t irq_handler = ds1307_irq;
1330
1331 static const int bbsqi_bitpos[] = {
1332 [ds_1337] = 0,
1333 [ds_1339] = DS1339_BIT_BBSQI,
1334 [ds_3231] = DS3231_BIT_BBSQW,
1335 };
1336 const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops;
1337
1338 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1339 if (!ds1307)
1340 return -ENOMEM;
1341
1342 dev_set_drvdata(&client->dev, ds1307);
1343 ds1307->dev = &client->dev;
1344 ds1307->name = client->name;
1345 ds1307->irq = client->irq;
1346
1347 ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1348 if (IS_ERR(ds1307->regmap)) {
1349 dev_err(ds1307->dev, "regmap allocation failed\n");
1350 return PTR_ERR(ds1307->regmap);
1351 }
1352
1353 i2c_set_clientdata(client, ds1307);
1354
1355 if (client->dev.of_node) {
1356 ds1307->type = (enum ds_type)
1357 of_device_get_match_data(&client->dev);
1358 chip = &chips[ds1307->type];
1359 } else if (id) {
1360 chip = &chips[id->driver_data];
1361 ds1307->type = id->driver_data;
1362 } else {
1363 const struct acpi_device_id *acpi_id;
1364
1365 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1366 ds1307->dev);
1367 if (!acpi_id)
1368 return -ENODEV;
1369 chip = &chips[acpi_id->driver_data];
1370 ds1307->type = acpi_id->driver_data;
1371 }
1372
1373 if (!pdata)
1374 ds1307_trickle_init(ds1307, chip);
1375 else if (pdata->trickle_charger_setup)
1376 chip->trickle_charger_setup = pdata->trickle_charger_setup;
1377
1378 if (chip->trickle_charger_setup && chip->trickle_charger_reg) {
1379 dev_dbg(ds1307->dev,
1380 "writing trickle charger info 0x%x to 0x%x\n",
1381 DS13XX_TRICKLE_CHARGER_MAGIC | chip->trickle_charger_setup,
1382 chip->trickle_charger_reg);
1383 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1384 DS13XX_TRICKLE_CHARGER_MAGIC |
1385 chip->trickle_charger_setup);
1386 }
1387
1388 buf = ds1307->regs;
1389
1390 #ifdef CONFIG_OF
1391 /*
1392 * For devices with no IRQ directly connected to the SoC, the RTC chip
1393 * can be forced as a wakeup source by stating that explicitly in
1394 * the device's .dts file using the "wakeup-source" boolean property.
1395 * If the "wakeup-source" property is set, don't request an IRQ.
1396 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1397 * if supported by the RTC.
1398 */
1399 if (of_property_read_bool(client->dev.of_node, "wakeup-source")) {
1400 ds1307_can_wakeup_device = true;
1401 }
1402 /* Intersil ISL12057 DT backward compatibility */
1403 if (of_property_read_bool(client->dev.of_node,
1404 "isil,irq2-can-wakeup-machine")) {
1405 ds1307_can_wakeup_device = true;
1406 }
1407 #endif
1408
1409 switch (ds1307->type) {
1410 case ds_1337:
1411 case ds_1339:
1412 case ds_3231:
1413 /* get registers that the "rtc" read below won't read... */
1414 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1415 buf, 2);
1416 if (err) {
1417 dev_dbg(ds1307->dev, "read error %d\n", err);
1418 goto exit;
1419 }
1420
1421 /* oscillator off? turn it on, so clock can tick. */
1422 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
1423 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
1424
1425 /*
1426 * Using IRQ or defined as wakeup-source?
1427 * Disable the square wave and both alarms.
1428 * For some variants, be sure alarms can trigger when we're
1429 * running on Vbackup (BBSQI/BBSQW)
1430 */
1431 if (chip->alarm && (ds1307->irq > 0 ||
1432 ds1307_can_wakeup_device)) {
1433 ds1307->regs[0] |= DS1337_BIT_INTCN
1434 | bbsqi_bitpos[ds1307->type];
1435 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1436
1437 want_irq = true;
1438 }
1439
1440 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1441 ds1307->regs[0]);
1442
1443 /* oscillator fault? clear flag, and warn */
1444 if (ds1307->regs[1] & DS1337_BIT_OSF) {
1445 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1446 ds1307->regs[1] & ~DS1337_BIT_OSF);
1447 dev_warn(ds1307->dev, "SET TIME!\n");
1448 }
1449 break;
1450
1451 case rx_8025:
1452 err = regmap_bulk_read(ds1307->regmap,
1453 RX8025_REG_CTRL1 << 4 | 0x08, buf, 2);
1454 if (err) {
1455 dev_dbg(ds1307->dev, "read error %d\n", err);
1456 goto exit;
1457 }
1458
1459 /* oscillator off? turn it on, so clock can tick. */
1460 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
1461 ds1307->regs[1] |= RX8025_BIT_XST;
1462 regmap_write(ds1307->regmap,
1463 RX8025_REG_CTRL2 << 4 | 0x08,
1464 ds1307->regs[1]);
1465 dev_warn(ds1307->dev,
1466 "oscillator stop detected - SET TIME!\n");
1467 }
1468
1469 if (ds1307->regs[1] & RX8025_BIT_PON) {
1470 ds1307->regs[1] &= ~RX8025_BIT_PON;
1471 regmap_write(ds1307->regmap,
1472 RX8025_REG_CTRL2 << 4 | 0x08,
1473 ds1307->regs[1]);
1474 dev_warn(ds1307->dev, "power-on detected\n");
1475 }
1476
1477 if (ds1307->regs[1] & RX8025_BIT_VDET) {
1478 ds1307->regs[1] &= ~RX8025_BIT_VDET;
1479 regmap_write(ds1307->regmap,
1480 RX8025_REG_CTRL2 << 4 | 0x08,
1481 ds1307->regs[1]);
1482 dev_warn(ds1307->dev, "voltage drop detected\n");
1483 }
1484
1485 /* make sure we are running in 24hour mode */
1486 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
1487 u8 hour;
1488
1489 /* switch to 24 hour mode */
1490 regmap_write(ds1307->regmap,
1491 RX8025_REG_CTRL1 << 4 | 0x08,
1492 ds1307->regs[0] | RX8025_BIT_2412);
1493
1494 err = regmap_bulk_read(ds1307->regmap,
1495 RX8025_REG_CTRL1 << 4 | 0x08,
1496 buf, 2);
1497 if (err) {
1498 dev_dbg(ds1307->dev, "read error %d\n", err);
1499 goto exit;
1500 }
1501
1502 /* correct hour */
1503 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
1504 if (hour == 12)
1505 hour = 0;
1506 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1507 hour += 12;
1508
1509 regmap_write(ds1307->regmap,
1510 DS1307_REG_HOUR << 4 | 0x08, hour);
1511 }
1512 break;
1513 case rx_8130:
1514 ds1307->offset = 0x10; /* Seconds starts at 0x10 */
1515 rtc_ops = &rx8130_rtc_ops;
1516 if (chip->alarm && ds1307->irq > 0) {
1517 irq_handler = rx8130_irq;
1518 want_irq = true;
1519 }
1520 break;
1521 case ds_1388:
1522 ds1307->offset = 1; /* Seconds starts at 1 */
1523 break;
1524 case mcp794xx:
1525 rtc_ops = &mcp794xx_rtc_ops;
1526 if (chip->alarm && (ds1307->irq > 0 ||
1527 ds1307_can_wakeup_device)) {
1528 irq_handler = mcp794xx_irq;
1529 want_irq = true;
1530 }
1531 break;
1532 default:
1533 break;
1534 }
1535
1536 read_rtc:
1537 /* read RTC registers */
1538 err = regmap_bulk_read(ds1307->regmap, ds1307->offset, buf, 8);
1539 if (err) {
1540 dev_dbg(ds1307->dev, "read error %d\n", err);
1541 goto exit;
1542 }
1543
1544 /*
1545 * minimal sanity checking; some chips (like DS1340) don't
1546 * specify the extra bits as must-be-zero, but there are
1547 * still a few values that are clearly out-of-range.
1548 */
1549 tmp = ds1307->regs[DS1307_REG_SECS];
1550 switch (ds1307->type) {
1551 case ds_1307:
1552 case m41t0:
1553 case m41t00:
1554 /* clock halted? turn it on, so clock can tick. */
1555 if (tmp & DS1307_BIT_CH) {
1556 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1557 dev_warn(ds1307->dev, "SET TIME!\n");
1558 goto read_rtc;
1559 }
1560 break;
1561 case ds_1338:
1562 /* clock halted? turn it on, so clock can tick. */
1563 if (tmp & DS1307_BIT_CH)
1564 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1565
1566 /* oscillator fault? clear flag, and warn */
1567 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1568 regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1569 ds1307->regs[DS1307_REG_CONTROL] &
1570 ~DS1338_BIT_OSF);
1571 dev_warn(ds1307->dev, "SET TIME!\n");
1572 goto read_rtc;
1573 }
1574 break;
1575 case ds_1340:
1576 /* clock halted? turn it on, so clock can tick. */
1577 if (tmp & DS1340_BIT_nEOSC)
1578 regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1579
1580 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1581 if (err) {
1582 dev_dbg(ds1307->dev, "read error %d\n", err);
1583 goto exit;
1584 }
1585
1586 /* oscillator fault? clear flag, and warn */
1587 if (tmp & DS1340_BIT_OSF) {
1588 regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1589 dev_warn(ds1307->dev, "SET TIME!\n");
1590 }
1591 break;
1592 case mcp794xx:
1593 /* make sure that the backup battery is enabled */
1594 if (!(ds1307->regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1595 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1596 ds1307->regs[DS1307_REG_WDAY] |
1597 MCP794XX_BIT_VBATEN);
1598 }
1599
1600 /* clock halted? turn it on, so clock can tick. */
1601 if (!(tmp & MCP794XX_BIT_ST)) {
1602 regmap_write(ds1307->regmap, DS1307_REG_SECS,
1603 MCP794XX_BIT_ST);
1604 dev_warn(ds1307->dev, "SET TIME!\n");
1605 goto read_rtc;
1606 }
1607
1608 break;
1609 default:
1610 break;
1611 }
1612
1613 tmp = ds1307->regs[DS1307_REG_HOUR];
1614 switch (ds1307->type) {
1615 case ds_1340:
1616 case m41t0:
1617 case m41t00:
1618 /*
1619 * NOTE: ignores century bits; fix before deploying
1620 * systems that will run through year 2100.
1621 */
1622 break;
1623 case rx_8025:
1624 break;
1625 default:
1626 if (!(tmp & DS1307_BIT_12HR))
1627 break;
1628
1629 /*
1630 * Be sure we're in 24 hour mode. Multi-master systems
1631 * take note...
1632 */
1633 tmp = bcd2bin(tmp & 0x1f);
1634 if (tmp == 12)
1635 tmp = 0;
1636 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1637 tmp += 12;
1638 regmap_write(ds1307->regmap, ds1307->offset + DS1307_REG_HOUR,
1639 bin2bcd(tmp));
1640 }
1641
1642 /*
1643 * Some IPs have weekday reset value = 0x1 which might not correct
1644 * hence compute the wday using the current date/month/year values
1645 */
1646 ds1307_get_time(ds1307->dev, &tm);
1647 wday = tm.tm_wday;
1648 timestamp = rtc_tm_to_time64(&tm);
1649 rtc_time64_to_tm(timestamp, &tm);
1650
1651 /*
1652 * Check if reset wday is different from the computed wday
1653 * If different then set the wday which we computed using
1654 * timestamp
1655 */
1656 if (wday != tm.tm_wday)
1657 regmap_update_bits(ds1307->regmap, MCP794XX_REG_WEEKDAY,
1658 MCP794XX_REG_WEEKDAY_WDAY_MASK,
1659 tm.tm_wday + 1);
1660
1661 if (want_irq) {
1662 device_set_wakeup_capable(ds1307->dev, true);
1663 set_bit(HAS_ALARM, &ds1307->flags);
1664 }
1665 ds1307->rtc = devm_rtc_device_register(ds1307->dev, ds1307->name,
1666 rtc_ops, THIS_MODULE);
1667 if (IS_ERR(ds1307->rtc)) {
1668 return PTR_ERR(ds1307->rtc);
1669 }
1670
1671 if (ds1307_can_wakeup_device && ds1307->irq <= 0) {
1672 /* Disable request for an IRQ */
1673 want_irq = false;
1674 dev_info(ds1307->dev,
1675 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1676 /* We cannot support UIE mode if we do not have an IRQ line */
1677 ds1307->rtc->uie_unsupported = 1;
1678 }
1679
1680 if (want_irq) {
1681 err = devm_request_threaded_irq(ds1307->dev,
1682 ds1307->irq, NULL, irq_handler,
1683 IRQF_SHARED | IRQF_ONESHOT,
1684 ds1307->name, ds1307);
1685 if (err) {
1686 client->irq = 0;
1687 device_set_wakeup_capable(ds1307->dev, false);
1688 clear_bit(HAS_ALARM, &ds1307->flags);
1689 dev_err(ds1307->dev, "unable to request IRQ!\n");
1690 } else
1691 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1692 }
1693
1694 if (chip->nvram_size) {
1695
1696 ds1307->nvram = devm_kzalloc(ds1307->dev,
1697 sizeof(struct bin_attribute),
1698 GFP_KERNEL);
1699 if (!ds1307->nvram) {
1700 dev_err(ds1307->dev,
1701 "cannot allocate memory for nvram sysfs\n");
1702 } else {
1703
1704 ds1307->nvram->attr.name = "nvram";
1705 ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
1706
1707 sysfs_bin_attr_init(ds1307->nvram);
1708
1709 ds1307->nvram->read = ds1307_nvram_read;
1710 ds1307->nvram->write = ds1307_nvram_write;
1711 ds1307->nvram->size = chip->nvram_size;
1712 ds1307->nvram_offset = chip->nvram_offset;
1713
1714 err = sysfs_create_bin_file(&ds1307->dev->kobj,
1715 ds1307->nvram);
1716 if (err) {
1717 dev_err(ds1307->dev,
1718 "unable to create sysfs file: %s\n",
1719 ds1307->nvram->attr.name);
1720 } else {
1721 set_bit(HAS_NVRAM, &ds1307->flags);
1722 dev_info(ds1307->dev, "%zu bytes nvram\n",
1723 ds1307->nvram->size);
1724 }
1725 }
1726 }
1727
1728 ds1307_hwmon_register(ds1307);
1729 ds1307_clks_register(ds1307);
1730
1731 return 0;
1732
1733 exit:
1734 return err;
1735 }
1736
1737 static int ds1307_remove(struct i2c_client *client)
1738 {
1739 struct ds1307 *ds1307 = i2c_get_clientdata(client);
1740
1741 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
1742 sysfs_remove_bin_file(&ds1307->dev->kobj, ds1307->nvram);
1743
1744 return 0;
1745 }
1746
1747 static struct i2c_driver ds1307_driver = {
1748 .driver = {
1749 .name = "rtc-ds1307",
1750 .of_match_table = of_match_ptr(ds1307_of_match),
1751 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1752 },
1753 .probe = ds1307_probe,
1754 .remove = ds1307_remove,
1755 .id_table = ds1307_id,
1756 };
1757
1758 module_i2c_driver(ds1307_driver);
1759
1760 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1761 MODULE_LICENSE("GPL");
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