arch/powerpc/sysdev/uic.c

   1 /*
   2  * arch/powerpc/sysdev/uic.c
   3  *
   4  * IBM PowerPC 4xx Universal Interrupt Controller
   5  *
   6  * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/errno.h>
  16 #include <linux/reboot.h>
  17 #include <linux/slab.h>
  18 #include <linux/stddef.h>
  19 #include <linux/sched.h>
  20 #include <linux/signal.h>
  21 #include <linux/device.h>
  22 #include <linux/bootmem.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/kernel_stat.h>
  27 #include <asm/irq.h>
  28 #include <asm/io.h>
  29 #include <asm/prom.h>
  30 #include <asm/dcr.h>
  31
  32 #define NR_UIC_INTS     32
  33
  34 #define UIC_SR          0x0
  35 #define UIC_ER          0x2
  36 #define UIC_CR          0x3
  37 #define UIC_PR          0x4
  38 #define UIC_TR          0x5
  39 #define UIC_MSR         0x6
  40 #define UIC_VR          0x7
  41 #define UIC_VCR         0x8
  42
  43 struct uic *primary_uic;
  44
  45 struct uic {
  46         int index;
  47         int dcrbase;
  48
  49         raw_spinlock_t lock;
  50
  51         /* The remapper for this UIC */
  52         struct irq_host *irqhost;
  53 };
  54
  55 static void uic_unmask_irq(struct irq_data *d)
  56 {
  57         struct uic *uic = irq_data_get_irq_chip_data(d);
  58         unsigned int src = irqd_to_hwirq(d);
  59         unsigned long flags;
  60         u32 er, sr;
  61
  62         sr = 1 << (31-src);
  63         raw_spin_lock_irqsave(&uic->lock, flags);
  64         /* ack level-triggered interrupts here */
  65         if (irqd_is_level_type(d))
  66                 mtdcr(uic->dcrbase + UIC_SR, sr);
  67         er = mfdcr(uic->dcrbase + UIC_ER);
  68         er |= sr;
  69         mtdcr(uic->dcrbase + UIC_ER, er);
  70         raw_spin_unlock_irqrestore(&uic->lock, flags);
  71 }
  72
  73 static void uic_mask_irq(struct irq_data *d)
  74 {
  75         struct uic *uic = irq_data_get_irq_chip_data(d);
  76         unsigned int src = irqd_to_hwirq(d);
  77         unsigned long flags;
  78         u32 er;
  79
  80         raw_spin_lock_irqsave(&uic->lock, flags);
  81         er = mfdcr(uic->dcrbase + UIC_ER);
  82         er &= ~(1 << (31 - src));
  83         mtdcr(uic->dcrbase + UIC_ER, er);
  84         raw_spin_unlock_irqrestore(&uic->lock, flags);
  85 }
  86
  87 static void uic_ack_irq(struct irq_data *d)
  88 {
  89         struct uic *uic = irq_data_get_irq_chip_data(d);
  90         unsigned int src = irqd_to_hwirq(d);
  91         unsigned long flags;
  92
  93         raw_spin_lock_irqsave(&uic->lock, flags);
  94         mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
  95         raw_spin_unlock_irqrestore(&uic->lock, flags);
  96 }
  97
  98 static void uic_mask_ack_irq(struct irq_data *d)
  99 {
 100         struct uic *uic = irq_data_get_irq_chip_data(d);
 101         unsigned int src = irqd_to_hwirq(d);
 102         unsigned long flags;
 103         u32 er, sr;
 104
 105         sr = 1 << (31-src);
 106         raw_spin_lock_irqsave(&uic->lock, flags);
 107         er = mfdcr(uic->dcrbase + UIC_ER);
 108         er &= ~sr;
 109         mtdcr(uic->dcrbase + UIC_ER, er);
 110         /* On the UIC, acking (i.e. clearing the SR bit)
 111          * a level irq will have no effect if the interrupt
 112          * is still asserted by the device, even if
 113          * the interrupt is already masked. Therefore
 114          * we only ack the egde interrupts here, while
 115          * level interrupts are ack'ed after the actual
 116          * isr call in the uic_unmask_irq()
 117          */
 118         if (!irqd_is_level_type(d))
 119                 mtdcr(uic->dcrbase + UIC_SR, sr);
 120         raw_spin_unlock_irqrestore(&uic->lock, flags);
 121 }
 122
 123 static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type)
 124 {
 125         struct uic *uic = irq_data_get_irq_chip_data(d);
 126         unsigned int src = irqd_to_hwirq(d);
 127         unsigned long flags;
 128         int trigger, polarity;
 129         u32 tr, pr, mask;
 130
 131         switch (flow_type & IRQ_TYPE_SENSE_MASK) {
 132         case IRQ_TYPE_NONE:
 133                 uic_mask_irq(d);
 134                 return 0;
 135
 136         case IRQ_TYPE_EDGE_RISING:
 137                 trigger = 1; polarity = 1;
 138                 break;
 139         case IRQ_TYPE_EDGE_FALLING:
 140                 trigger = 1; polarity = 0;
 141                 break;
 142         case IRQ_TYPE_LEVEL_HIGH:
 143                 trigger = 0; polarity = 1;
 144                 break;
 145         case IRQ_TYPE_LEVEL_LOW:
 146                 trigger = 0; polarity = 0;
 147                 break;
 148         default:
 149                 return -EINVAL;
 150         }
 151
 152         mask = ~(1 << (31 - src));
 153
 154         raw_spin_lock_irqsave(&uic->lock, flags);
 155         tr = mfdcr(uic->dcrbase + UIC_TR);
 156         pr = mfdcr(uic->dcrbase + UIC_PR);
 157         tr = (tr & mask) | (trigger << (31-src));
 158         pr = (pr & mask) | (polarity << (31-src));
 159
 160         mtdcr(uic->dcrbase + UIC_PR, pr);
 161         mtdcr(uic->dcrbase + UIC_TR, tr);
 162
 163         raw_spin_unlock_irqrestore(&uic->lock, flags);
 164
 165         return 0;
 166 }
 167
 168 static struct irq_chip uic_irq_chip = {
 169         .name           = "UIC",
 170         .irq_unmask     = uic_unmask_irq,
 171         .irq_mask       = uic_mask_irq,
 172         .irq_mask_ack   = uic_mask_ack_irq,
 173         .irq_ack        = uic_ack_irq,
 174         .irq_set_type   = uic_set_irq_type,
 175 };
 176
 177 static int uic_host_map(struct irq_host *h, unsigned int virq,
 178                         irq_hw_number_t hw)
 179 {
 180         struct uic *uic = h->host_data;
 181
 182         irq_set_chip_data(virq, uic);
 183         /* Despite the name, handle_level_irq() works for both level
 184          * and edge irqs on UIC.  FIXME: check this is correct */
 185         irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
 186
 187         /* Set default irq type */
 188         irq_set_irq_type(virq, IRQ_TYPE_NONE);
 189
 190         return 0;
 191 }
 192
 193 static int uic_host_xlate(struct irq_host *h, struct device_node *ct,
 194                           const u32 *intspec, unsigned int intsize,
 195                           irq_hw_number_t *out_hwirq, unsigned int *out_type)
 196
 197 {
 198         /* UIC intspecs must have 2 cells */
 199         BUG_ON(intsize != 2);
 200         *out_hwirq = intspec[0];
 201         *out_type = intspec[1];
 202         return 0;
 203 }
 204
 205 static struct irq_host_ops uic_host_ops = {
 206         .map    = uic_host_map,
 207         .xlate  = uic_host_xlate,
 208 };
 209
 210 void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
 211 {
 212         struct irq_chip *chip = irq_desc_get_chip(desc);
 213         struct irq_data *idata = irq_desc_get_irq_data(desc);
 214         struct uic *uic = irq_get_handler_data(virq);
 215         u32 msr;
 216         int src;
 217         int subvirq;
 218
 219         raw_spin_lock(&desc->lock);
 220         if (irqd_is_level_type(idata))
 221                 chip->irq_mask(idata);
 222         else
 223                 chip->irq_mask_ack(idata);
 224         raw_spin_unlock(&desc->lock);
 225
 226         msr = mfdcr(uic->dcrbase + UIC_MSR);
 227         if (!msr) /* spurious interrupt */
 228                 goto uic_irq_ret;
 229
 230         src = 32 - ffs(msr);
 231
 232         subvirq = irq_linear_revmap(uic->irqhost, src);
 233         generic_handle_irq(subvirq);
 234
 235 uic_irq_ret:
 236         raw_spin_lock(&desc->lock);
 237         if (irqd_is_level_type(idata))
 238                 chip->irq_ack(idata);
 239         if (!irqd_irq_disabled(idata) && chip->irq_unmask)
 240                 chip->irq_unmask(idata);
 241         raw_spin_unlock(&desc->lock);
 242 }
 243
 244 static struct uic * __init uic_init_one(struct device_node *node)
 245 {
 246         struct uic *uic;
 247         const u32 *indexp, *dcrreg;
 248         int len;
 249
 250         BUG_ON(! of_device_is_compatible(node, "ibm,uic"));
 251
 252         uic = kzalloc(sizeof(*uic), GFP_KERNEL);
 253         if (! uic)
 254                 return NULL; /* FIXME: panic? */
 255
 256         raw_spin_lock_init(&uic->lock);
 257         indexp = of_get_property(node, "cell-index", &len);
 258         if (!indexp || (len != sizeof(u32))) {
 259                 printk(KERN_ERR "uic: Device node %s has missing or invalid "
 260                        "cell-index property\n", node->full_name);
 261                 return NULL;
 262         }
 263         uic->index = *indexp;
 264
 265         dcrreg = of_get_property(node, "dcr-reg", &len);
 266         if (!dcrreg || (len != 2*sizeof(u32))) {
 267                 printk(KERN_ERR "uic: Device node %s has missing or invalid "
 268                        "dcr-reg property\n", node->full_name);
 269                 return NULL;
 270         }
 271         uic->dcrbase = *dcrreg;
 272
 273         uic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
 274                                       NR_UIC_INTS, &uic_host_ops, -1);
 275         if (! uic->irqhost)
 276                 return NULL; /* FIXME: panic? */
 277
 278         uic->irqhost->host_data = uic;
 279
 280         /* Start with all interrupts disabled, level and non-critical */
 281         mtdcr(uic->dcrbase + UIC_ER, 0);
 282         mtdcr(uic->dcrbase + UIC_CR, 0);
 283         mtdcr(uic->dcrbase + UIC_TR, 0);
 284         /* Clear any pending interrupts, in case the firmware left some */
 285         mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);
 286
 287         printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index,
 288                 NR_UIC_INTS, uic->dcrbase);
 289
 290         return uic;
 291 }
 292
 293 void __init uic_init_tree(void)
 294 {
 295         struct device_node *np;
 296         struct uic *uic;
 297         const u32 *interrupts;
 298
 299         /* First locate and initialize the top-level UIC */
 300         for_each_compatible_node(np, NULL, "ibm,uic") {
 301                 interrupts = of_get_property(np, "interrupts", NULL);
 302                 if (!interrupts)
 303                         break;
 304         }
 305
 306         BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the
 307                       * top-level interrupt controller */
 308         primary_uic = uic_init_one(np);
 309         if (!primary_uic)
 310                 panic("Unable to initialize primary UIC %s\n", np->full_name);
 311
 312         irq_set_default_host(primary_uic->irqhost);
 313         of_node_put(np);
 314
 315         /* The scan again for cascaded UICs */
 316         for_each_compatible_node(np, NULL, "ibm,uic") {
 317                 interrupts = of_get_property(np, "interrupts", NULL);
 318                 if (interrupts) {
 319                         /* Secondary UIC */
 320                         int cascade_virq;
 321
 322                         uic = uic_init_one(np);
 323                         if (! uic)
 324                                 panic("Unable to initialize a secondary UIC %s\n",
 325                                       np->full_name);
 326
 327                         cascade_virq = irq_of_parse_and_map(np, 0);
 328
 329                         irq_set_handler_data(cascade_virq, uic);
 330                         irq_set_chained_handler(cascade_virq, uic_irq_cascade);
 331
 332                         /* FIXME: setup critical cascade?? */
 333                 }
 334         }
 335 }
 336
 337 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
 338 unsigned int uic_get_irq(void)
 339 {
 340         u32 msr;
 341         int src;
 342
 343         BUG_ON(! primary_uic);
 344
 345         msr = mfdcr(primary_uic->dcrbase + UIC_MSR);
 346         src = 32 - ffs(msr);
 347
 348         return irq_linear_revmap(primary_uic->irqhost, src);
 349 }