drivers/net/ethernet/atheros/atlx/atl1.h

   1 /*
   2  * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
   3  * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
   4  * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
   5  *
   6  * Derived from Intel e1000 driver
   7  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the Free
  11  * Software Foundation; either version 2 of the License, or (at your option)
  12  * any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program; if not, write to the Free Software Foundation, Inc., 59
  21  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  22  */
  23
  24 #ifndef ATL1_H
  25 #define ATL1_H
  26
  27 #include <linux/compiler.h>
  28 #include <linux/ethtool.h>
  29 #include <linux/if_vlan.h>
  30 #include <linux/mii.h>
  31 #include <linux/module.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/timer.h>
  35 #include <linux/types.h>
  36 #include <linux/workqueue.h>
  37
  38 #include "atlx.h"
  39
  40 #define ATLX_DRIVER_NAME "atl1"
  41
  42 MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver");
  43
  44 #define atlx_adapter            atl1_adapter
  45 #define atlx_check_for_link     atl1_check_for_link
  46 #define atlx_check_link         atl1_check_link
  47 #define atlx_hash_mc_addr       atl1_hash_mc_addr
  48 #define atlx_hash_set           atl1_hash_set
  49 #define atlx_hw                 atl1_hw
  50 #define atlx_mii_ioctl          atl1_mii_ioctl
  51 #define atlx_read_phy_reg       atl1_read_phy_reg
  52 #define atlx_set_mac            atl1_set_mac
  53 #define atlx_set_mac_addr       atl1_set_mac_addr
  54
  55 struct atl1_adapter;
  56 struct atl1_hw;
  57
  58 /* function prototypes needed by multiple files */
  59 static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
  60 static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
  61 static void atl1_set_mac_addr(struct atl1_hw *hw);
  62 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
  63         int cmd);
  64 static u32 atl1_check_link(struct atl1_adapter *adapter);
  65
  66 /* hardware definitions specific to L1 */
  67
  68 /* Block IDLE Status Register */
  69 #define IDLE_STATUS_RXMAC                       0x1
  70 #define IDLE_STATUS_TXMAC                       0x2
  71 #define IDLE_STATUS_RXQ                         0x4
  72 #define IDLE_STATUS_TXQ                         0x8
  73 #define IDLE_STATUS_DMAR                        0x10
  74 #define IDLE_STATUS_DMAW                        0x20
  75 #define IDLE_STATUS_SMB                         0x40
  76 #define IDLE_STATUS_CMB                         0x80
  77
  78 /* MDIO Control Register */
  79 #define MDIO_WAIT_TIMES                         30
  80
  81 /* MAC Control Register */
  82 #define MAC_CTRL_TX_PAUSE                       0x10000
  83 #define MAC_CTRL_SCNT                           0x20000
  84 #define MAC_CTRL_SRST_TX                        0x40000
  85 #define MAC_CTRL_TX_SIMURST                     0x80000
  86 #define MAC_CTRL_SPEED_SHIFT                    20
  87 #define MAC_CTRL_SPEED_MASK                     0x300000
  88 #define MAC_CTRL_SPEED_1000                     0x2
  89 #define MAC_CTRL_SPEED_10_100                   0x1
  90 #define MAC_CTRL_DBG_TX_BKPRESURE               0x400000
  91 #define MAC_CTRL_TX_HUGE                        0x800000
  92 #define MAC_CTRL_RX_CHKSUM_EN                   0x1000000
  93 #define MAC_CTRL_DBG                            0x8000000
  94
  95 /* Wake-On-Lan control register */
  96 #define WOL_CLK_SWITCH_EN                       0x8000
  97 #define WOL_PT5_EN                              0x200000
  98 #define WOL_PT6_EN                              0x400000
  99 #define WOL_PT5_MATCH                           0x8000000
 100 #define WOL_PT6_MATCH                           0x10000000
 101
 102 /* WOL Length ( 2 DWORD ) */
 103 #define REG_WOL_PATTERN_LEN                     0x14A4
 104 #define WOL_PT_LEN_MASK                         0x7F
 105 #define WOL_PT0_LEN_SHIFT                       0
 106 #define WOL_PT1_LEN_SHIFT                       8
 107 #define WOL_PT2_LEN_SHIFT                       16
 108 #define WOL_PT3_LEN_SHIFT                       24
 109 #define WOL_PT4_LEN_SHIFT                       0
 110 #define WOL_PT5_LEN_SHIFT                       8
 111 #define WOL_PT6_LEN_SHIFT                       16
 112
 113 /* Internal SRAM Partition Registers, low 32 bits */
 114 #define REG_SRAM_RFD_LEN                        0x1504
 115 #define REG_SRAM_RRD_ADDR                       0x1508
 116 #define REG_SRAM_RRD_LEN                        0x150C
 117 #define REG_SRAM_TPD_ADDR                       0x1510
 118 #define REG_SRAM_TPD_LEN                        0x1514
 119 #define REG_SRAM_TRD_ADDR                       0x1518
 120 #define REG_SRAM_TRD_LEN                        0x151C
 121 #define REG_SRAM_RXF_ADDR                       0x1520
 122 #define REG_SRAM_RXF_LEN                        0x1524
 123 #define REG_SRAM_TXF_ADDR                       0x1528
 124 #define REG_SRAM_TXF_LEN                        0x152C
 125 #define REG_SRAM_TCPH_PATH_ADDR                 0x1530
 126 #define SRAM_TCPH_ADDR_MASK                     0xFFF
 127 #define SRAM_TCPH_ADDR_SHIFT                    0
 128 #define SRAM_PATH_ADDR_MASK                     0xFFF
 129 #define SRAM_PATH_ADDR_SHIFT                    16
 130
 131 /* Load Ptr Register */
 132 #define REG_LOAD_PTR                            0x1534
 133
 134 /* Descriptor Control registers, low 32 bits */
 135 #define REG_DESC_RFD_ADDR_LO                    0x1544
 136 #define REG_DESC_RRD_ADDR_LO                    0x1548
 137 #define REG_DESC_TPD_ADDR_LO                    0x154C
 138 #define REG_DESC_CMB_ADDR_LO                    0x1550
 139 #define REG_DESC_SMB_ADDR_LO                    0x1554
 140 #define REG_DESC_RFD_RRD_RING_SIZE              0x1558
 141 #define DESC_RFD_RING_SIZE_MASK                 0x7FF
 142 #define DESC_RFD_RING_SIZE_SHIFT                0
 143 #define DESC_RRD_RING_SIZE_MASK                 0x7FF
 144 #define DESC_RRD_RING_SIZE_SHIFT                16
 145 #define REG_DESC_TPD_RING_SIZE                  0x155C
 146 #define DESC_TPD_RING_SIZE_MASK                 0x3FF
 147 #define DESC_TPD_RING_SIZE_SHIFT                0
 148
 149 /* TXQ Control Register */
 150 #define REG_TXQ_CTRL                            0x1580
 151 #define TXQ_CTRL_TPD_BURST_NUM_SHIFT            0
 152 #define TXQ_CTRL_TPD_BURST_NUM_MASK             0x1F
 153 #define TXQ_CTRL_EN                             0x20
 154 #define TXQ_CTRL_ENH_MODE                       0x40
 155 #define TXQ_CTRL_TPD_FETCH_TH_SHIFT             8
 156 #define TXQ_CTRL_TPD_FETCH_TH_MASK              0x3F
 157 #define TXQ_CTRL_TXF_BURST_NUM_SHIFT            16
 158 #define TXQ_CTRL_TXF_BURST_NUM_MASK             0xFFFF
 159
 160 /* Jumbo packet Threshold for task offload */
 161 #define REG_TX_JUMBO_TASK_TH_TPD_IPG            0x1584
 162 #define TX_JUMBO_TASK_TH_MASK                   0x7FF
 163 #define TX_JUMBO_TASK_TH_SHIFT                  0
 164 #define TX_TPD_MIN_IPG_MASK                     0x1F
 165 #define TX_TPD_MIN_IPG_SHIFT                    16
 166
 167 /* RXQ Control Register */
 168 #define REG_RXQ_CTRL                            0x15A0
 169 #define RXQ_CTRL_RFD_BURST_NUM_SHIFT            0
 170 #define RXQ_CTRL_RFD_BURST_NUM_MASK             0xFF
 171 #define RXQ_CTRL_RRD_BURST_THRESH_SHIFT         8
 172 #define RXQ_CTRL_RRD_BURST_THRESH_MASK          0xFF
 173 #define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT         16
 174 #define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK          0x1F
 175 #define RXQ_CTRL_CUT_THRU_EN                    0x40000000
 176 #define RXQ_CTRL_EN                             0x80000000
 177
 178 /* Rx jumbo packet threshold and rrd  retirement timer */
 179 #define REG_RXQ_JMBOSZ_RRDTIM                   0x15A4
 180 #define RXQ_JMBOSZ_TH_MASK                      0x7FF
 181 #define RXQ_JMBOSZ_TH_SHIFT                     0
 182 #define RXQ_JMBO_LKAH_MASK                      0xF
 183 #define RXQ_JMBO_LKAH_SHIFT                     11
 184 #define RXQ_RRD_TIMER_MASK                      0xFFFF
 185 #define RXQ_RRD_TIMER_SHIFT                     16
 186
 187 /* RFD flow control register */
 188 #define REG_RXQ_RXF_PAUSE_THRESH                0x15A8
 189 #define RXQ_RXF_PAUSE_TH_HI_SHIFT               16
 190 #define RXQ_RXF_PAUSE_TH_HI_MASK                0xFFF
 191 #define RXQ_RXF_PAUSE_TH_LO_SHIFT               0
 192 #define RXQ_RXF_PAUSE_TH_LO_MASK                0xFFF
 193
 194 /* RRD flow control register */
 195 #define REG_RXQ_RRD_PAUSE_THRESH                0x15AC
 196 #define RXQ_RRD_PAUSE_TH_HI_SHIFT               0
 197 #define RXQ_RRD_PAUSE_TH_HI_MASK                0xFFF
 198 #define RXQ_RRD_PAUSE_TH_LO_SHIFT               16
 199 #define RXQ_RRD_PAUSE_TH_LO_MASK                0xFFF
 200
 201 /* DMA Engine Control Register */
 202 #define REG_DMA_CTRL                            0x15C0
 203 #define DMA_CTRL_DMAR_IN_ORDER                  0x1
 204 #define DMA_CTRL_DMAR_ENH_ORDER                 0x2
 205 #define DMA_CTRL_DMAR_OUT_ORDER                 0x4
 206 #define DMA_CTRL_RCB_VALUE                      0x8
 207 #define DMA_CTRL_DMAR_BURST_LEN_SHIFT           4
 208 #define DMA_CTRL_DMAR_BURST_LEN_MASK            7
 209 #define DMA_CTRL_DMAW_BURST_LEN_SHIFT           7
 210 #define DMA_CTRL_DMAW_BURST_LEN_MASK            7
 211 #define DMA_CTRL_DMAR_EN                        0x400
 212 #define DMA_CTRL_DMAW_EN                        0x800
 213
 214 /* CMB/SMB Control Register */
 215 #define REG_CSMB_CTRL                           0x15D0
 216 #define CSMB_CTRL_CMB_NOW                       1
 217 #define CSMB_CTRL_SMB_NOW                       2
 218 #define CSMB_CTRL_CMB_EN                        4
 219 #define CSMB_CTRL_SMB_EN                        8
 220
 221 /* CMB DMA Write Threshold Register */
 222 #define REG_CMB_WRITE_TH                        0x15D4
 223 #define CMB_RRD_TH_SHIFT                        0
 224 #define CMB_RRD_TH_MASK                         0x7FF
 225 #define CMB_TPD_TH_SHIFT                        16
 226 #define CMB_TPD_TH_MASK                         0x7FF
 227
 228 /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
 229 #define REG_CMB_WRITE_TIMER                     0x15D8
 230 #define CMB_RX_TM_SHIFT                         0
 231 #define CMB_RX_TM_MASK                          0xFFFF
 232 #define CMB_TX_TM_SHIFT                         16
 233 #define CMB_TX_TM_MASK                          0xFFFF
 234
 235 /* Number of packet received since last CMB write */
 236 #define REG_CMB_RX_PKT_CNT                      0x15DC
 237
 238 /* Number of packet transmitted since last CMB write */
 239 #define REG_CMB_TX_PKT_CNT                      0x15E0
 240
 241 /* SMB auto DMA timer register */
 242 #define REG_SMB_TIMER                           0x15E4
 243
 244 /* Mailbox Register */
 245 #define REG_MAILBOX                             0x15F0
 246 #define MB_RFD_PROD_INDX_SHIFT                  0
 247 #define MB_RFD_PROD_INDX_MASK                   0x7FF
 248 #define MB_RRD_CONS_INDX_SHIFT                  11
 249 #define MB_RRD_CONS_INDX_MASK                   0x7FF
 250 #define MB_TPD_PROD_INDX_SHIFT                  22
 251 #define MB_TPD_PROD_INDX_MASK                   0x3FF
 252
 253 /* Interrupt Status Register */
 254 #define ISR_SMB                                 0x1
 255 #define ISR_TIMER                               0x2
 256 #define ISR_MANUAL                              0x4
 257 #define ISR_RXF_OV                              0x8
 258 #define ISR_RFD_UNRUN                           0x10
 259 #define ISR_RRD_OV                              0x20
 260 #define ISR_TXF_UNRUN                           0x40
 261 #define ISR_LINK                                0x80
 262 #define ISR_HOST_RFD_UNRUN                      0x100
 263 #define ISR_HOST_RRD_OV                         0x200
 264 #define ISR_DMAR_TO_RST                         0x400
 265 #define ISR_DMAW_TO_RST                         0x800
 266 #define ISR_GPHY                                0x1000
 267 #define ISR_RX_PKT                              0x10000
 268 #define ISR_TX_PKT                              0x20000
 269 #define ISR_TX_DMA                              0x40000
 270 #define ISR_RX_DMA                              0x80000
 271 #define ISR_CMB_RX                              0x100000
 272 #define ISR_CMB_TX                              0x200000
 273 #define ISR_MAC_RX                              0x400000
 274 #define ISR_MAC_TX                              0x800000
 275 #define ISR_DIS_SMB                             0x20000000
 276 #define ISR_DIS_DMA                             0x40000000
 277
 278 /* Normal Interrupt mask without RX/TX enabled */
 279 #define IMR_NORXTX_MASK (\
 280         ISR_SMB         |\
 281         ISR_GPHY        |\
 282         ISR_PHY_LINKDOWN|\
 283         ISR_DMAR_TO_RST |\
 284         ISR_DMAW_TO_RST)
 285
 286 /* Normal Interrupt mask  */
 287 #define IMR_NORMAL_MASK (\
 288         IMR_NORXTX_MASK |\
 289         ISR_CMB_TX      |\
 290         ISR_CMB_RX)
 291
 292 /* Debug Interrupt Mask  (enable all interrupt) */
 293 #define IMR_DEBUG_MASK  (\
 294         ISR_SMB         |\
 295         ISR_TIMER       |\
 296         ISR_MANUAL      |\
 297         ISR_RXF_OV      |\
 298         ISR_RFD_UNRUN   |\
 299         ISR_RRD_OV      |\
 300         ISR_TXF_UNRUN   |\
 301         ISR_LINK        |\
 302         ISR_CMB_TX      |\
 303         ISR_CMB_RX      |\
 304         ISR_RX_PKT      |\
 305         ISR_TX_PKT      |\
 306         ISR_MAC_RX      |\
 307         ISR_MAC_TX)
 308
 309 #define MEDIA_TYPE_1000M_FULL                   1
 310 #define MEDIA_TYPE_100M_FULL                    2
 311 #define MEDIA_TYPE_100M_HALF                    3
 312 #define MEDIA_TYPE_10M_FULL                     4
 313 #define MEDIA_TYPE_10M_HALF                     5
 314
 315 #define AUTONEG_ADVERTISE_SPEED_DEFAULT         0x002F  /* All but 1000-Half */
 316
 317 #define MAX_JUMBO_FRAME_SIZE                    10240
 318
 319 #define ATL1_EEDUMP_LEN                         48
 320
 321 /* Statistics counters collected by the MAC */
 322 struct stats_msg_block {
 323         /* rx */
 324         u32 rx_ok;              /* good RX packets */
 325         u32 rx_bcast;           /* good RX broadcast packets */
 326         u32 rx_mcast;           /* good RX multicast packets */
 327         u32 rx_pause;           /* RX pause frames */
 328         u32 rx_ctrl;            /* RX control packets other than pause frames */
 329         u32 rx_fcs_err;         /* RX packets with bad FCS */
 330         u32 rx_len_err;         /* RX packets with length != actual size */
 331         u32 rx_byte_cnt;        /* good bytes received. FCS is NOT included */
 332         u32 rx_runt;            /* RX packets < 64 bytes with good FCS */
 333         u32 rx_frag;            /* RX packets < 64 bytes with bad FCS */
 334         u32 rx_sz_64;           /* 64 byte RX packets */
 335         u32 rx_sz_65_127;
 336         u32 rx_sz_128_255;
 337         u32 rx_sz_256_511;
 338         u32 rx_sz_512_1023;
 339         u32 rx_sz_1024_1518;
 340         u32 rx_sz_1519_max;     /* 1519 byte to MTU RX packets */
 341         u32 rx_sz_ov;           /* truncated RX packets > MTU */
 342         u32 rx_rxf_ov;          /* frames dropped due to RX FIFO overflow */
 343         u32 rx_rrd_ov;          /* frames dropped due to RRD overflow */
 344         u32 rx_align_err;       /* alignment errors */
 345         u32 rx_bcast_byte_cnt;  /* RX broadcast bytes, excluding FCS */
 346         u32 rx_mcast_byte_cnt;  /* RX multicast bytes, excluding FCS */
 347         u32 rx_err_addr;        /* packets dropped due to address filtering */
 348
 349         /* tx */
 350         u32 tx_ok;              /* good TX packets */
 351         u32 tx_bcast;           /* good TX broadcast packets */
 352         u32 tx_mcast;           /* good TX multicast packets */
 353         u32 tx_pause;           /* TX pause frames */
 354         u32 tx_exc_defer;       /* TX packets deferred excessively */
 355         u32 tx_ctrl;            /* TX control frames, excluding pause frames */
 356         u32 tx_defer;           /* TX packets deferred */
 357         u32 tx_byte_cnt;        /* bytes transmitted, FCS is NOT included */
 358         u32 tx_sz_64;           /* 64 byte TX packets */
 359         u32 tx_sz_65_127;
 360         u32 tx_sz_128_255;
 361         u32 tx_sz_256_511;
 362         u32 tx_sz_512_1023;
 363         u32 tx_sz_1024_1518;
 364         u32 tx_sz_1519_max;     /* 1519 byte to MTU TX packets */
 365         u32 tx_1_col;           /* packets TX after a single collision */
 366         u32 tx_2_col;           /* packets TX after multiple collisions */
 367         u32 tx_late_col;        /* TX packets with late collisions */
 368         u32 tx_abort_col;       /* TX packets aborted w/excessive collisions */
 369         u32 tx_underrun;        /* TX packets aborted due to TX FIFO underrun
 370                                  * or TRD FIFO underrun */
 371         u32 tx_rd_eop;          /* reads beyond the EOP into the next frame
 372                                  * when TRD was not written timely */
 373         u32 tx_len_err;         /* TX packets where length != actual size */
 374         u32 tx_trunc;           /* TX packets truncated due to size > MTU */
 375         u32 tx_bcast_byte;      /* broadcast bytes transmitted, excluding FCS */
 376         u32 tx_mcast_byte;      /* multicast bytes transmitted, excluding FCS */
 377         u32 smb_updated;        /* 1: SMB Updated. This is used by software to
 378                                  * indicate the statistics update. Software
 379                                  * should clear this bit after retrieving the
 380                                  * statistics information. */
 381 };
 382
 383 /* Coalescing Message Block */
 384 struct coals_msg_block {
 385         u32 int_stats;          /* interrupt status */
 386         u16 rrd_prod_idx;       /* TRD Producer Index. */
 387         u16 rfd_cons_idx;       /* RFD Consumer Index. */
 388         u16 update;             /* Selene sets this bit every time it DMAs the
 389                                  * CMB to host memory. Software should clear
 390                                  * this bit when CMB info is processed. */
 391         u16 tpd_cons_idx;       /* TPD Consumer Index. */
 392 };
 393
 394 /* RRD descriptor */
 395 struct rx_return_desc {
 396         u8 num_buf;     /* Number of RFD buffers used by the received packet */
 397         u8 resved;
 398         u16 buf_indx;   /* RFD Index of the first buffer */
 399         union {
 400                 u32 valid;
 401                 struct {
 402                         u16 rx_chksum;
 403                         u16 pkt_size;
 404                 } xsum_sz;
 405         } xsz;
 406
 407         u16 pkt_flg;    /* Packet flags */
 408         u16 err_flg;    /* Error flags */
 409         u16 resved2;
 410         u16 vlan_tag;   /* VLAN TAG */
 411 };
 412
 413 #define PACKET_FLAG_ETH_TYPE    0x0080
 414 #define PACKET_FLAG_VLAN_INS    0x0100
 415 #define PACKET_FLAG_ERR         0x0200
 416 #define PACKET_FLAG_IPV4        0x0400
 417 #define PACKET_FLAG_UDP         0x0800
 418 #define PACKET_FLAG_TCP         0x1000
 419 #define PACKET_FLAG_BCAST       0x2000
 420 #define PACKET_FLAG_MCAST       0x4000
 421 #define PACKET_FLAG_PAUSE       0x8000
 422
 423 #define ERR_FLAG_CRC            0x0001
 424 #define ERR_FLAG_CODE           0x0002
 425 #define ERR_FLAG_DRIBBLE        0x0004
 426 #define ERR_FLAG_RUNT           0x0008
 427 #define ERR_FLAG_OV             0x0010
 428 #define ERR_FLAG_TRUNC          0x0020
 429 #define ERR_FLAG_IP_CHKSUM      0x0040
 430 #define ERR_FLAG_L4_CHKSUM      0x0080
 431 #define ERR_FLAG_LEN            0x0100
 432 #define ERR_FLAG_DES_ADDR       0x0200
 433
 434 /* RFD descriptor */
 435 struct rx_free_desc {
 436         __le64 buffer_addr;     /* Address of the descriptor's data buffer */
 437         __le16 buf_len;         /* Size of the receive buffer in host memory */
 438         u16 coalese;            /* Update consumer index to host after the
 439                                  * reception of this frame */
 440         /* __packed is required */
 441 } __packed;
 442
 443 /*
 444  * The L1 transmit packet descriptor is comprised of four 32-bit words.
 445  *
 446  *      31                                      0
 447  *      +---------------------------------------+
 448  *      |       Word 0: Buffer addr lo          |
 449  *      +---------------------------------------+
 450  *      |       Word 1: Buffer addr hi          |
 451  *      +---------------------------------------+
 452  *      |               Word 2                  |
 453  *      +---------------------------------------+
 454  *      |               Word 3                  |
 455  *      +---------------------------------------+
 456  *
 457  * Words 0 and 1 combine to form a 64-bit buffer address.
 458  *
 459  * Word 2 is self explanatory in the #define block below.
 460  *
 461  * Word 3 has two forms, depending upon the state of bits 3 and 4.
 462  * If bits 3 and 4 are both zero, then bits 14:31 are unused by the
 463  * hardware.  Otherwise, if either bit 3 or 4 is set, the definition
 464  * of bits 14:31 vary according to the following depiction.
 465  *
 466  *      0       End of packet                   0       End of packet
 467  *      1       Coalesce                        1       Coalesce
 468  *      2       Insert VLAN tag                 2       Insert VLAN tag
 469  *      3       Custom csum enable = 0          3       Custom csum enable = 1
 470  *      4       Segment enable = 1              4       Segment enable = 0
 471  *      5       Generate IP checksum            5       Generate IP checksum
 472  *      6       Generate TCP checksum           6       Generate TCP checksum
 473  *      7       Generate UDP checksum           7       Generate UDP checksum
 474  *      8       VLAN tagged                     8       VLAN tagged
 475  *      9       Ethernet frame type             9       Ethernet frame type
 476  *      10-+                                    10-+
 477  *      11 |    IP hdr length (10:13)           11 |    IP hdr length (10:13)
 478  *      12 |    (num 32-bit words)              12 |    (num 32-bit words)
 479  *      13-+                                    13-+
 480  *      14-+                                    14      Unused
 481  *      15 |    TCP hdr length (14:17)          15      Unused
 482  *      16 |    (num 32-bit words)              16-+
 483  *      17-+                                    17 |
 484  *      18      Header TPD flag                 18 |
 485  *      19-+                                    19 |    Payload offset
 486  *      20 |                                    20 |        (16:23)
 487  *      21 |                                    21 |
 488  *      22 |                                    22 |
 489  *      23 |                                    23-+
 490  *      24 |                                    24-+
 491  *      25 |    MSS (19:31)                     25 |
 492  *      26 |                                    26 |
 493  *      27 |                                    27 |    Custom csum offset
 494  *      28 |                                    28 |         (24:31)
 495  *      29 |                                    29 |
 496  *      30 |                                    30 |
 497  *      31-+                                    31-+
 498  */
 499
 500 /* tpd word 2 */
 501 #define TPD_BUFLEN_MASK         0x3FFF
 502 #define TPD_BUFLEN_SHIFT        0
 503 #define TPD_DMAINT_MASK         0x0001
 504 #define TPD_DMAINT_SHIFT        14
 505 #define TPD_PKTNT_MASK          0x0001
 506 #define TPD_PKTINT_SHIFT        15
 507 #define TPD_VLANTAG_MASK        0xFFFF
 508 #define TPD_VLANTAG_SHIFT       16
 509
 510 /* tpd word 3 bits 0:13 */
 511 #define TPD_EOP_MASK            0x0001
 512 #define TPD_EOP_SHIFT           0
 513 #define TPD_COALESCE_MASK       0x0001
 514 #define TPD_COALESCE_SHIFT      1
 515 #define TPD_INS_VL_TAG_MASK     0x0001
 516 #define TPD_INS_VL_TAG_SHIFT    2
 517 #define TPD_CUST_CSUM_EN_MASK   0x0001
 518 #define TPD_CUST_CSUM_EN_SHIFT  3
 519 #define TPD_SEGMENT_EN_MASK     0x0001
 520 #define TPD_SEGMENT_EN_SHIFT    4
 521 #define TPD_IP_CSUM_MASK        0x0001
 522 #define TPD_IP_CSUM_SHIFT       5
 523 #define TPD_TCP_CSUM_MASK       0x0001
 524 #define TPD_TCP_CSUM_SHIFT      6
 525 #define TPD_UDP_CSUM_MASK       0x0001
 526 #define TPD_UDP_CSUM_SHIFT      7
 527 #define TPD_VL_TAGGED_MASK      0x0001
 528 #define TPD_VL_TAGGED_SHIFT     8
 529 #define TPD_ETHTYPE_MASK        0x0001
 530 #define TPD_ETHTYPE_SHIFT       9
 531 #define TPD_IPHL_MASK           0x000F
 532 #define TPD_IPHL_SHIFT          10
 533
 534 /* tpd word 3 bits 14:31 if segment enabled */
 535 #define TPD_TCPHDRLEN_MASK      0x000F
 536 #define TPD_TCPHDRLEN_SHIFT     14
 537 #define TPD_HDRFLAG_MASK        0x0001
 538 #define TPD_HDRFLAG_SHIFT       18
 539 #define TPD_MSS_MASK            0x1FFF
 540 #define TPD_MSS_SHIFT           19
 541
 542 /* tpd word 3 bits 16:31 if custom csum enabled */
 543 #define TPD_PLOADOFFSET_MASK    0x00FF
 544 #define TPD_PLOADOFFSET_SHIFT   16
 545 #define TPD_CCSUMOFFSET_MASK    0x00FF
 546 #define TPD_CCSUMOFFSET_SHIFT   24
 547
 548 struct tx_packet_desc {
 549         __le64 buffer_addr;
 550         __le32 word2;
 551         __le32 word3;
 552 };
 553
 554 /* DMA Order Settings */
 555 enum atl1_dma_order {
 556         atl1_dma_ord_in = 1,
 557         atl1_dma_ord_enh = 2,
 558         atl1_dma_ord_out = 4
 559 };
 560
 561 enum atl1_dma_rcb {
 562         atl1_rcb_64 = 0,
 563         atl1_rcb_128 = 1
 564 };
 565
 566 enum atl1_dma_req_block {
 567         atl1_dma_req_128 = 0,
 568         atl1_dma_req_256 = 1,
 569         atl1_dma_req_512 = 2,
 570         atl1_dma_req_1024 = 3,
 571         atl1_dma_req_2048 = 4,
 572         atl1_dma_req_4096 = 5
 573 };
 574
 575 #define ATL1_MAX_INTR           3
 576 #define ATL1_MAX_TX_BUF_LEN     0x3000  /* 12288 bytes */
 577
 578 #define ATL1_DEFAULT_TPD        256
 579 #define ATL1_MAX_TPD            1024
 580 #define ATL1_MIN_TPD            64
 581 #define ATL1_DEFAULT_RFD        512
 582 #define ATL1_MIN_RFD            128
 583 #define ATL1_MAX_RFD            2048
 584 #define ATL1_REG_COUNT          1538
 585
 586 #define ATL1_GET_DESC(R, i, type)       (&(((type *)((R)->desc))[i]))
 587 #define ATL1_RFD_DESC(R, i)     ATL1_GET_DESC(R, i, struct rx_free_desc)
 588 #define ATL1_TPD_DESC(R, i)     ATL1_GET_DESC(R, i, struct tx_packet_desc)
 589 #define ATL1_RRD_DESC(R, i)     ATL1_GET_DESC(R, i, struct rx_return_desc)
 590
 591 /*
 592  * atl1_ring_header represents a single, contiguous block of DMA space
 593  * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
 594  * message blocks (cmb, smb) described below
 595  */
 596 struct atl1_ring_header {
 597         void *desc;             /* virtual address */
 598         dma_addr_t dma;         /* physical address*/
 599         unsigned int size;      /* length in bytes */
 600 };
 601
 602 /*
 603  * atl1_buffer is wrapper around a pointer to a socket buffer
 604  * so a DMA handle can be stored along with the skb
 605  */
 606 struct atl1_buffer {
 607         struct sk_buff *skb;    /* socket buffer */
 608         u16 length;             /* rx buffer length */
 609         u16 alloced;            /* 1 if skb allocated */
 610         dma_addr_t dma;
 611 };
 612
 613 /* transmit packet descriptor (tpd) ring */
 614 struct atl1_tpd_ring {
 615         void *desc;             /* descriptor ring virtual address */
 616         dma_addr_t dma;         /* descriptor ring physical address */
 617         u16 size;               /* descriptor ring length in bytes */
 618         u16 count;              /* number of descriptors in the ring */
 619         u16 hw_idx;             /* hardware index */
 620         atomic_t next_to_clean;
 621         atomic_t next_to_use;
 622         struct atl1_buffer *buffer_info;
 623 };
 624
 625 /* receive free descriptor (rfd) ring */
 626 struct atl1_rfd_ring {
 627         void *desc;             /* descriptor ring virtual address */
 628         dma_addr_t dma;         /* descriptor ring physical address */
 629         u16 size;               /* descriptor ring length in bytes */
 630         u16 count;              /* number of descriptors in the ring */
 631         atomic_t next_to_use;
 632         u16 next_to_clean;
 633         struct atl1_buffer *buffer_info;
 634 };
 635
 636 /* receive return descriptor (rrd) ring */
 637 struct atl1_rrd_ring {
 638         void *desc;             /* descriptor ring virtual address */
 639         dma_addr_t dma;         /* descriptor ring physical address */
 640         unsigned int size;      /* descriptor ring length in bytes */
 641         u16 count;              /* number of descriptors in the ring */
 642         u16 next_to_use;
 643         atomic_t next_to_clean;
 644 };
 645
 646 /* coalescing message block (cmb) */
 647 struct atl1_cmb {
 648         struct coals_msg_block *cmb;
 649         dma_addr_t dma;
 650 };
 651
 652 /* statistics message block (smb) */
 653 struct atl1_smb {
 654         struct stats_msg_block *smb;
 655         dma_addr_t dma;
 656 };
 657
 658 /* Statistics counters */
 659 struct atl1_sft_stats {
 660         u64 rx_packets;
 661         u64 tx_packets;
 662         u64 rx_bytes;
 663         u64 tx_bytes;
 664         u64 multicast;
 665         u64 collisions;
 666         u64 rx_errors;
 667         u64 rx_length_errors;
 668         u64 rx_crc_errors;
 669         u64 rx_dropped;
 670         u64 rx_frame_errors;
 671         u64 rx_fifo_errors;
 672         u64 rx_missed_errors;
 673         u64 tx_errors;
 674         u64 tx_fifo_errors;
 675         u64 tx_aborted_errors;
 676         u64 tx_window_errors;
 677         u64 tx_carrier_errors;
 678         u64 tx_pause;           /* TX pause frames */
 679         u64 excecol;            /* TX packets w/ excessive collisions */
 680         u64 deffer;             /* TX packets deferred */
 681         u64 scc;                /* packets TX after a single collision */
 682         u64 mcc;                /* packets TX after multiple collisions */
 683         u64 latecol;            /* TX packets w/ late collisions */
 684         u64 tx_underun;         /* TX packets aborted due to TX FIFO underrun
 685                                  * or TRD FIFO underrun */
 686         u64 tx_trunc;           /* TX packets truncated due to size > MTU */
 687         u64 rx_pause;           /* num Pause packets received. */
 688         u64 rx_rrd_ov;
 689         u64 rx_trunc;
 690 };
 691
 692 /* hardware structure */
 693 struct atl1_hw {
 694         u8 __iomem *hw_addr;
 695         struct atl1_adapter *back;
 696         enum atl1_dma_order dma_ord;
 697         enum atl1_dma_rcb rcb_value;
 698         enum atl1_dma_req_block dmar_block;
 699         enum atl1_dma_req_block dmaw_block;
 700         u8 preamble_len;
 701         u8 max_retry;
 702         u8 jam_ipg;             /* IPG to start JAM for collision based flow
 703                                  * control in half-duplex mode. In units of
 704                                  * 8-bit time */
 705         u8 ipgt;                /* Desired back to back inter-packet gap.
 706                                  * The default is 96-bit time */
 707         u8 min_ifg;             /* Minimum number of IFG to enforce in between
 708                                  * receive frames. Frame gap below such IFP
 709                                  * is dropped */
 710         u8 ipgr1;               /* 64bit Carrier-Sense window */
 711         u8 ipgr2;               /* 96-bit IPG window */
 712         u8 tpd_burst;           /* Number of TPD to prefetch in cache-aligned
 713                                  * burst. Each TPD is 16 bytes long */
 714         u8 rfd_burst;           /* Number of RFD to prefetch in cache-aligned
 715                                  * burst. Each RFD is 12 bytes long */
 716         u8 rfd_fetch_gap;
 717         u8 rrd_burst;           /* Threshold number of RRDs that can be retired
 718                                  * in a burst. Each RRD is 16 bytes long */
 719         u8 tpd_fetch_th;
 720         u8 tpd_fetch_gap;
 721         u16 tx_jumbo_task_th;
 722         u16 txf_burst;          /* Number of data bytes to read in a cache-
 723                                  * aligned burst. Each SRAM entry is 8 bytes */
 724         u16 rx_jumbo_th;        /* Jumbo packet size for non-VLAN packet. VLAN
 725                                  * packets should add 4 bytes */
 726         u16 rx_jumbo_lkah;
 727         u16 rrd_ret_timer;      /* RRD retirement timer. Decrement by 1 after
 728                                  * every 512ns passes. */
 729         u16 lcol;               /* Collision Window */
 730
 731         u16 cmb_tpd;
 732         u16 cmb_rrd;
 733         u16 cmb_rx_timer;
 734         u16 cmb_tx_timer;
 735         u32 smb_timer;
 736         u16 media_type;
 737         u16 autoneg_advertised;
 738
 739         u16 mii_autoneg_adv_reg;
 740         u16 mii_1000t_ctrl_reg;
 741
 742         u32 max_frame_size;
 743         u32 min_frame_size;
 744
 745         u16 dev_rev;
 746
 747         /* spi flash */
 748         u8 flash_vendor;
 749
 750         u8 mac_addr[ETH_ALEN];
 751         u8 perm_mac_addr[ETH_ALEN];
 752
 753         bool phy_configured;
 754 };
 755
 756 struct atl1_adapter {
 757         struct net_device *netdev;
 758         struct pci_dev *pdev;
 759
 760         struct atl1_sft_stats soft_stats;
 761         u32 rx_buffer_len;
 762         u32 wol;
 763         u16 link_speed;
 764         u16 link_duplex;
 765         spinlock_t lock;
 766         struct napi_struct napi;
 767         struct work_struct reset_dev_task;
 768         struct work_struct link_chg_task;
 769
 770         struct timer_list phy_config_timer;
 771         bool phy_timer_pending;
 772
 773         /* all descriptor rings' memory */
 774         struct atl1_ring_header ring_header;
 775
 776         /* TX */
 777         struct atl1_tpd_ring tpd_ring;
 778         spinlock_t mb_lock;
 779
 780         /* RX */
 781         struct atl1_rfd_ring rfd_ring;
 782         struct atl1_rrd_ring rrd_ring;
 783         u64 hw_csum_err;
 784         u64 hw_csum_good;
 785         u32 msg_enable;
 786         u16 imt;                /* interrupt moderator timer (2us resolution) */
 787         u16 ict;                /* interrupt clear timer (2us resolution */
 788         struct mii_if_info mii; /* MII interface info */
 789
 790         /*
 791          * Use this value to check is napi handler allowed to
 792          * enable ints or not
 793          */
 794         bool int_enabled;
 795
 796         u32 bd_number;          /* board number */
 797         bool pci_using_64;
 798         struct atl1_hw hw;
 799         struct atl1_smb smb;
 800         struct atl1_cmb cmb;
 801 };
 802
 803 #endif /* ATL1_H */