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ixgbe: only register DCA requester once
[linux-2.6/btrfs-unstable.git] / drivers / net / ixgbe / ixgbe_main.c
blobe52798c4816b0837bd1729c59a88d418865c9466
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/ipv6.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42 #include <scsi/fc/fc_fcoe.h>
43
44 #include "ixgbe.h"
45 #include "ixgbe_common.h"
46
47 char ixgbe_driver_name[] = "ixgbe";
48 static const char ixgbe_driver_string[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver";
50
51 #define DRV_VERSION "2.0.24-k2"
52 const char ixgbe_driver_version[] = DRV_VERSION;
53 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
54
55 static const struct ixgbe_info *ixgbe_info_tbl[] = {
56 [board_82598] = &ixgbe_82598_info,
57 [board_82599] = &ixgbe_82599_info,
58 };
59
60 /* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68 static struct pci_device_id ixgbe_pci_tbl[] = {
69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
70 board_82598 },
71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
72 board_82598 },
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
74 board_82598 },
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
76 board_82598 },
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
78 board_82598 },
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
80 board_82598 },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
84 board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
92 board_82599 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
94 board_82599 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
96 board_82599 },
97
98 /* required last entry */
99 {0, }
100 };
101 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
102
103 #ifdef CONFIG_IXGBE_DCA
104 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
105 void *p);
106 static struct notifier_block dca_notifier = {
107 .notifier_call = ixgbe_notify_dca,
108 .next = NULL,
109 .priority = 0
110 };
111 #endif
112
113 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
114 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
115 MODULE_LICENSE("GPL");
116 MODULE_VERSION(DRV_VERSION);
117
118 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
119
120 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
121 {
122 u32 ctrl_ext;
123
124 /* Let firmware take over control of h/w */
125 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
126 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
127 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
128 }
129
130 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
131 {
132 u32 ctrl_ext;
133
134 /* Let firmware know the driver has taken over */
135 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
136 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
137 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
138 }
139
140 /*
141 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
142 * @adapter: pointer to adapter struct
143 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
144 * @queue: queue to map the corresponding interrupt to
145 * @msix_vector: the vector to map to the corresponding queue
146 *
147 */
148 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
149 u8 queue, u8 msix_vector)
150 {
151 u32 ivar, index;
152 struct ixgbe_hw *hw = &adapter->hw;
153 switch (hw->mac.type) {
154 case ixgbe_mac_82598EB:
155 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
156 if (direction == -1)
157 direction = 0;
158 index = (((direction * 64) + queue) >> 2) & 0x1F;
159 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
160 ivar &= ~(0xFF << (8 * (queue & 0x3)));
161 ivar |= (msix_vector << (8 * (queue & 0x3)));
162 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
163 break;
164 case ixgbe_mac_82599EB:
165 if (direction == -1) {
166 /* other causes */
167 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
168 index = ((queue & 1) * 8);
169 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
170 ivar &= ~(0xFF << index);
171 ivar |= (msix_vector << index);
172 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
173 break;
174 } else {
175 /* tx or rx causes */
176 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
177 index = ((16 * (queue & 1)) + (8 * direction));
178 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
179 ivar &= ~(0xFF << index);
180 ivar |= (msix_vector << index);
181 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
182 break;
183 }
184 default:
185 break;
186 }
187 }
188
189 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
190 struct ixgbe_tx_buffer
191 *tx_buffer_info)
192 {
193 tx_buffer_info->dma = 0;
194 if (tx_buffer_info->skb) {
195 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
196 DMA_TO_DEVICE);
197 dev_kfree_skb_any(tx_buffer_info->skb);
198 tx_buffer_info->skb = NULL;
199 }
200 tx_buffer_info->time_stamp = 0;
201 /* tx_buffer_info must be completely set up in the transmit path */
202 }
203
204 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
205 struct ixgbe_ring *tx_ring,
206 unsigned int eop)
207 {
208 struct ixgbe_hw *hw = &adapter->hw;
209
210 /* Detect a transmit hang in hardware, this serializes the
211 * check with the clearing of time_stamp and movement of eop */
212 adapter->detect_tx_hung = false;
213 if (tx_ring->tx_buffer_info[eop].time_stamp &&
214 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
215 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
216 /* detected Tx unit hang */
217 union ixgbe_adv_tx_desc *tx_desc;
218 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
219 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
220 " Tx Queue <%d>\n"
221 " TDH, TDT <%x>, <%x>\n"
222 " next_to_use <%x>\n"
223 " next_to_clean <%x>\n"
224 "tx_buffer_info[next_to_clean]\n"
225 " time_stamp <%lx>\n"
226 " jiffies <%lx>\n",
227 tx_ring->queue_index,
228 IXGBE_READ_REG(hw, tx_ring->head),
229 IXGBE_READ_REG(hw, tx_ring->tail),
230 tx_ring->next_to_use, eop,
231 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
232 return true;
233 }
234
235 return false;
236 }
237
238 #define IXGBE_MAX_TXD_PWR 14
239 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
240
241 /* Tx Descriptors needed, worst case */
242 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
243 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
244 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
245 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
246
247 static void ixgbe_tx_timeout(struct net_device *netdev);
248
249 /**
250 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
251 * @adapter: board private structure
252 * @tx_ring: tx ring to clean
253 *
254 * returns true if transmit work is done
255 **/
256 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
257 struct ixgbe_ring *tx_ring)
258 {
259 struct net_device *netdev = adapter->netdev;
260 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
261 struct ixgbe_tx_buffer *tx_buffer_info;
262 unsigned int i, eop, count = 0;
263 unsigned int total_bytes = 0, total_packets = 0;
264
265 i = tx_ring->next_to_clean;
266 eop = tx_ring->tx_buffer_info[i].next_to_watch;
267 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
268
269 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
270 (count < tx_ring->work_limit)) {
271 bool cleaned = false;
272 for ( ; !cleaned; count++) {
273 struct sk_buff *skb;
274 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
275 tx_buffer_info = &tx_ring->tx_buffer_info[i];
276 cleaned = (i == eop);
277 skb = tx_buffer_info->skb;
278
279 if (cleaned && skb) {
280 unsigned int segs, bytecount;
281
282 /* gso_segs is currently only valid for tcp */
283 segs = skb_shinfo(skb)->gso_segs ?: 1;
284 /* multiply data chunks by size of headers */
285 bytecount = ((segs - 1) * skb_headlen(skb)) +
286 skb->len;
287 total_packets += segs;
288 total_bytes += bytecount;
289 }
290
291 ixgbe_unmap_and_free_tx_resource(adapter,
292 tx_buffer_info);
293
294 tx_desc->wb.status = 0;
295
296 i++;
297 if (i == tx_ring->count)
298 i = 0;
299 }
300
301 eop = tx_ring->tx_buffer_info[i].next_to_watch;
302 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
303 }
304
305 tx_ring->next_to_clean = i;
306
307 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
308 if (unlikely(count && netif_carrier_ok(netdev) &&
309 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
310 /* Make sure that anybody stopping the queue after this
311 * sees the new next_to_clean.
312 */
313 smp_mb();
314 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
315 !test_bit(__IXGBE_DOWN, &adapter->state)) {
316 netif_wake_subqueue(netdev, tx_ring->queue_index);
317 ++adapter->restart_queue;
318 }
319 }
320
321 if (adapter->detect_tx_hung) {
322 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
323 /* schedule immediate reset if we believe we hung */
324 DPRINTK(PROBE, INFO,
325 "tx hang %d detected, resetting adapter\n",
326 adapter->tx_timeout_count + 1);
327 ixgbe_tx_timeout(adapter->netdev);
328 }
329 }
330
331 /* re-arm the interrupt */
332 if (count >= tx_ring->work_limit) {
333 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
335 tx_ring->v_idx);
336 else if (tx_ring->v_idx & 0xFFFFFFFF)
337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0),
338 tx_ring->v_idx);
339 else
340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1),
341 (tx_ring->v_idx >> 32));
342 }
343
344
345 tx_ring->total_bytes += total_bytes;
346 tx_ring->total_packets += total_packets;
347 tx_ring->stats.packets += total_packets;
348 tx_ring->stats.bytes += total_bytes;
349 adapter->net_stats.tx_bytes += total_bytes;
350 adapter->net_stats.tx_packets += total_packets;
351 return (count < tx_ring->work_limit);
352 }
353
354 #ifdef CONFIG_IXGBE_DCA
355 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
356 struct ixgbe_ring *rx_ring)
357 {
358 u32 rxctrl;
359 int cpu = get_cpu();
360 int q = rx_ring - adapter->rx_ring;
361
362 if (rx_ring->cpu != cpu) {
363 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
364 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
365 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
366 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
367 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
368 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
369 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
370 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
371 }
372 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
373 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
374 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
375 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
376 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
377 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
378 rx_ring->cpu = cpu;
379 }
380 put_cpu();
381 }
382
383 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
384 struct ixgbe_ring *tx_ring)
385 {
386 u32 txctrl;
387 int cpu = get_cpu();
388 int q = tx_ring - adapter->tx_ring;
389
390 if (tx_ring->cpu != cpu) {
391 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
392 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
393 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
394 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
395 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
396 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
397 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
398 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
399 }
400 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
401 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
402 tx_ring->cpu = cpu;
403 }
404 put_cpu();
405 }
406
407 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
408 {
409 int i;
410
411 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
412 return;
413
414 /* always use CB2 mode, difference is masked in the CB driver */
415 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
416
417 for (i = 0; i < adapter->num_tx_queues; i++) {
418 adapter->tx_ring[i].cpu = -1;
419 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
420 }
421 for (i = 0; i < adapter->num_rx_queues; i++) {
422 adapter->rx_ring[i].cpu = -1;
423 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
424 }
425 }
426
427 static int __ixgbe_notify_dca(struct device *dev, void *data)
428 {
429 struct net_device *netdev = dev_get_drvdata(dev);
430 struct ixgbe_adapter *adapter = netdev_priv(netdev);
431 unsigned long event = *(unsigned long *)data;
432
433 switch (event) {
434 case DCA_PROVIDER_ADD:
435 /* if we're already enabled, don't do it again */
436 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
437 break;
438 if (dca_add_requester(dev) == 0) {
439 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
440 ixgbe_setup_dca(adapter);
441 break;
442 }
443 /* Fall Through since DCA is disabled. */
444 case DCA_PROVIDER_REMOVE:
445 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
446 dca_remove_requester(dev);
447 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
448 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
449 }
450 break;
451 }
452
453 return 0;
454 }
455
456 #endif /* CONFIG_IXGBE_DCA */
457 /**
458 * ixgbe_receive_skb - Send a completed packet up the stack
459 * @adapter: board private structure
460 * @skb: packet to send up
461 * @status: hardware indication of status of receive
462 * @rx_ring: rx descriptor ring (for a specific queue) to setup
463 * @rx_desc: rx descriptor
464 **/
465 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
466 struct sk_buff *skb, u8 status,
467 struct ixgbe_ring *ring,
468 union ixgbe_adv_rx_desc *rx_desc)
469 {
470 struct ixgbe_adapter *adapter = q_vector->adapter;
471 struct napi_struct *napi = &q_vector->napi;
472 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
473 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
474
475 skb_record_rx_queue(skb, ring->queue_index);
476 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
477 if (adapter->vlgrp && is_vlan && (tag != 0))
478 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
479 else
480 napi_gro_receive(napi, skb);
481 } else {
482 if (adapter->vlgrp && is_vlan && (tag != 0))
483 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
484 else
485 netif_rx(skb);
486 }
487 }
488
489 /**
490 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
491 * @adapter: address of board private structure
492 * @status_err: hardware indication of status of receive
493 * @skb: skb currently being received and modified
494 **/
495 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
496 u32 status_err, struct sk_buff *skb)
497 {
498 skb->ip_summed = CHECKSUM_NONE;
499
500 /* Rx csum disabled */
501 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
502 return;
503
504 /* if IP and error */
505 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
506 (status_err & IXGBE_RXDADV_ERR_IPE)) {
507 adapter->hw_csum_rx_error++;
508 return;
509 }
510
511 if (!(status_err & IXGBE_RXD_STAT_L4CS))
512 return;
513
514 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
515 adapter->hw_csum_rx_error++;
516 return;
517 }
518
519 /* It must be a TCP or UDP packet with a valid checksum */
520 skb->ip_summed = CHECKSUM_UNNECESSARY;
521 adapter->hw_csum_rx_good++;
522 }
523
524 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
525 struct ixgbe_ring *rx_ring, u32 val)
526 {
527 /*
528 * Force memory writes to complete before letting h/w
529 * know there are new descriptors to fetch. (Only
530 * applicable for weak-ordered memory model archs,
531 * such as IA-64).
532 */
533 wmb();
534 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
535 }
536
537 /**
538 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
539 * @adapter: address of board private structure
540 **/
541 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
542 struct ixgbe_ring *rx_ring,
543 int cleaned_count)
544 {
545 struct pci_dev *pdev = adapter->pdev;
546 union ixgbe_adv_rx_desc *rx_desc;
547 struct ixgbe_rx_buffer *bi;
548 unsigned int i;
549 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
550
551 i = rx_ring->next_to_use;
552 bi = &rx_ring->rx_buffer_info[i];
553
554 while (cleaned_count--) {
555 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
556
557 if (!bi->page_dma &&
558 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
559 if (!bi->page) {
560 bi->page = alloc_page(GFP_ATOMIC);
561 if (!bi->page) {
562 adapter->alloc_rx_page_failed++;
563 goto no_buffers;
564 }
565 bi->page_offset = 0;
566 } else {
567 /* use a half page if we're re-using */
568 bi->page_offset ^= (PAGE_SIZE / 2);
569 }
570
571 bi->page_dma = pci_map_page(pdev, bi->page,
572 bi->page_offset,
573 (PAGE_SIZE / 2),
574 PCI_DMA_FROMDEVICE);
575 }
576
577 if (!bi->skb) {
578 struct sk_buff *skb;
579 skb = netdev_alloc_skb(adapter->netdev, bufsz);
580
581 if (!skb) {
582 adapter->alloc_rx_buff_failed++;
583 goto no_buffers;
584 }
585
586 /*
587 * Make buffer alignment 2 beyond a 16 byte boundary
588 * this will result in a 16 byte aligned IP header after
589 * the 14 byte MAC header is removed
590 */
591 skb_reserve(skb, NET_IP_ALIGN);
592
593 bi->skb = skb;
594 bi->dma = pci_map_single(pdev, skb->data, bufsz,
595 PCI_DMA_FROMDEVICE);
596 }
597 /* Refresh the desc even if buffer_addrs didn't change because
598 * each write-back erases this info. */
599 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
600 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
601 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
602 } else {
603 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
604 }
605
606 i++;
607 if (i == rx_ring->count)
608 i = 0;
609 bi = &rx_ring->rx_buffer_info[i];
610 }
611
612 no_buffers:
613 if (rx_ring->next_to_use != i) {
614 rx_ring->next_to_use = i;
615 if (i-- == 0)
616 i = (rx_ring->count - 1);
617
618 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
619 }
620 }
621
622 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
623 {
624 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
625 }
626
627 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
628 {
629 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
630 }
631
632 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
633 {
634 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
635 IXGBE_RXDADV_RSCCNT_MASK) >>
636 IXGBE_RXDADV_RSCCNT_SHIFT;
637 }
638
639 /**
640 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
641 * @skb: pointer to the last skb in the rsc queue
642 *
643 * This function changes a queue full of hw rsc buffers into a completed
644 * packet. It uses the ->prev pointers to find the first packet and then
645 * turns it into the frag list owner.
646 **/
647 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
648 {
649 unsigned int frag_list_size = 0;
650
651 while (skb->prev) {
652 struct sk_buff *prev = skb->prev;
653 frag_list_size += skb->len;
654 skb->prev = NULL;
655 skb = prev;
656 }
657
658 skb_shinfo(skb)->frag_list = skb->next;
659 skb->next = NULL;
660 skb->len += frag_list_size;
661 skb->data_len += frag_list_size;
662 skb->truesize += frag_list_size;
663 return skb;
664 }
665
666 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
667 struct ixgbe_ring *rx_ring,
668 int *work_done, int work_to_do)
669 {
670 struct ixgbe_adapter *adapter = q_vector->adapter;
671 struct pci_dev *pdev = adapter->pdev;
672 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
673 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
674 struct sk_buff *skb;
675 unsigned int i, rsc_count = 0;
676 u32 len, staterr;
677 u16 hdr_info;
678 bool cleaned = false;
679 int cleaned_count = 0;
680 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
681
682 i = rx_ring->next_to_clean;
683 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
684 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
685 rx_buffer_info = &rx_ring->rx_buffer_info[i];
686
687 while (staterr & IXGBE_RXD_STAT_DD) {
688 u32 upper_len = 0;
689 if (*work_done >= work_to_do)
690 break;
691 (*work_done)++;
692
693 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
694 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
695 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
696 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
697 if (hdr_info & IXGBE_RXDADV_SPH)
698 adapter->rx_hdr_split++;
699 if (len > IXGBE_RX_HDR_SIZE)
700 len = IXGBE_RX_HDR_SIZE;
701 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
702 } else {
703 len = le16_to_cpu(rx_desc->wb.upper.length);
704 }
705
706 cleaned = true;
707 skb = rx_buffer_info->skb;
708 prefetch(skb->data - NET_IP_ALIGN);
709 rx_buffer_info->skb = NULL;
710
711 if (len && !skb_shinfo(skb)->nr_frags) {
712 pci_unmap_single(pdev, rx_buffer_info->dma,
713 rx_ring->rx_buf_len,
714 PCI_DMA_FROMDEVICE);
715 skb_put(skb, len);
716 }
717
718 if (upper_len) {
719 pci_unmap_page(pdev, rx_buffer_info->page_dma,
720 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
721 rx_buffer_info->page_dma = 0;
722 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
723 rx_buffer_info->page,
724 rx_buffer_info->page_offset,
725 upper_len);
726
727 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
728 (page_count(rx_buffer_info->page) != 1))
729 rx_buffer_info->page = NULL;
730 else
731 get_page(rx_buffer_info->page);
732
733 skb->len += upper_len;
734 skb->data_len += upper_len;
735 skb->truesize += upper_len;
736 }
737
738 i++;
739 if (i == rx_ring->count)
740 i = 0;
741
742 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
743 prefetch(next_rxd);
744 cleaned_count++;
745
746 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
747 rsc_count = ixgbe_get_rsc_count(rx_desc);
748
749 if (rsc_count) {
750 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
751 IXGBE_RXDADV_NEXTP_SHIFT;
752 next_buffer = &rx_ring->rx_buffer_info[nextp];
753 rx_ring->rsc_count += (rsc_count - 1);
754 } else {
755 next_buffer = &rx_ring->rx_buffer_info[i];
756 }
757
758 if (staterr & IXGBE_RXD_STAT_EOP) {
759 if (skb->prev)
760 skb = ixgbe_transform_rsc_queue(skb);
761 rx_ring->stats.packets++;
762 rx_ring->stats.bytes += skb->len;
763 } else {
764 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
765 rx_buffer_info->skb = next_buffer->skb;
766 rx_buffer_info->dma = next_buffer->dma;
767 next_buffer->skb = skb;
768 next_buffer->dma = 0;
769 } else {
770 skb->next = next_buffer->skb;
771 skb->next->prev = skb;
772 }
773 adapter->non_eop_descs++;
774 goto next_desc;
775 }
776
777 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
778 dev_kfree_skb_irq(skb);
779 goto next_desc;
780 }
781
782 ixgbe_rx_checksum(adapter, staterr, skb);
783
784 /* probably a little skewed due to removing CRC */
785 total_rx_bytes += skb->len;
786 total_rx_packets++;
787
788 skb->protocol = eth_type_trans(skb, adapter->netdev);
789 #ifdef IXGBE_FCOE
790 /* if ddp, not passing to ULD unless for FCP_RSP or error */
791 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
792 if (!ixgbe_fcoe_ddp(adapter, rx_desc, skb))
793 goto next_desc;
794 #endif /* IXGBE_FCOE */
795 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
796
797 next_desc:
798 rx_desc->wb.upper.status_error = 0;
799
800 /* return some buffers to hardware, one at a time is too slow */
801 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
802 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
803 cleaned_count = 0;
804 }
805
806 /* use prefetched values */
807 rx_desc = next_rxd;
808 rx_buffer_info = &rx_ring->rx_buffer_info[i];
809
810 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
811 }
812
813 rx_ring->next_to_clean = i;
814 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
815
816 if (cleaned_count)
817 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
818
819 rx_ring->total_packets += total_rx_packets;
820 rx_ring->total_bytes += total_rx_bytes;
821 adapter->net_stats.rx_bytes += total_rx_bytes;
822 adapter->net_stats.rx_packets += total_rx_packets;
823
824 return cleaned;
825 }
826
827 static int ixgbe_clean_rxonly(struct napi_struct *, int);
828 /**
829 * ixgbe_configure_msix - Configure MSI-X hardware
830 * @adapter: board private structure
831 *
832 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
833 * interrupts.
834 **/
835 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
836 {
837 struct ixgbe_q_vector *q_vector;
838 int i, j, q_vectors, v_idx, r_idx;
839 u32 mask;
840
841 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
842
843 /*
844 * Populate the IVAR table and set the ITR values to the
845 * corresponding register.
846 */
847 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
848 q_vector = adapter->q_vector[v_idx];
849 /* XXX for_each_bit(...) */
850 r_idx = find_first_bit(q_vector->rxr_idx,
851 adapter->num_rx_queues);
852
853 for (i = 0; i < q_vector->rxr_count; i++) {
854 j = adapter->rx_ring[r_idx].reg_idx;
855 ixgbe_set_ivar(adapter, 0, j, v_idx);
856 r_idx = find_next_bit(q_vector->rxr_idx,
857 adapter->num_rx_queues,
858 r_idx + 1);
859 }
860 r_idx = find_first_bit(q_vector->txr_idx,
861 adapter->num_tx_queues);
862
863 for (i = 0; i < q_vector->txr_count; i++) {
864 j = adapter->tx_ring[r_idx].reg_idx;
865 ixgbe_set_ivar(adapter, 1, j, v_idx);
866 r_idx = find_next_bit(q_vector->txr_idx,
867 adapter->num_tx_queues,
868 r_idx + 1);
869 }
870
871 /* if this is a tx only vector halve the interrupt rate */
872 if (q_vector->txr_count && !q_vector->rxr_count)
873 q_vector->eitr = (adapter->eitr_param >> 1);
874 else if (q_vector->rxr_count)
875 /* rx only */
876 q_vector->eitr = adapter->eitr_param;
877
878 /*
879 * since this is initial set up don't need to call
880 * ixgbe_write_eitr helper
881 */
882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
883 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
884 }
885
886 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
887 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
888 v_idx);
889 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
890 ixgbe_set_ivar(adapter, -1, 1, v_idx);
891 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
892
893 /* set up to autoclear timer, and the vectors */
894 mask = IXGBE_EIMS_ENABLE_MASK;
895 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
897 }
898
899 enum latency_range {
900 lowest_latency = 0,
901 low_latency = 1,
902 bulk_latency = 2,
903 latency_invalid = 255
904 };
905
906 /**
907 * ixgbe_update_itr - update the dynamic ITR value based on statistics
908 * @adapter: pointer to adapter
909 * @eitr: eitr setting (ints per sec) to give last timeslice
910 * @itr_setting: current throttle rate in ints/second
911 * @packets: the number of packets during this measurement interval
912 * @bytes: the number of bytes during this measurement interval
913 *
914 * Stores a new ITR value based on packets and byte
915 * counts during the last interrupt. The advantage of per interrupt
916 * computation is faster updates and more accurate ITR for the current
917 * traffic pattern. Constants in this function were computed
918 * based on theoretical maximum wire speed and thresholds were set based
919 * on testing data as well as attempting to minimize response time
920 * while increasing bulk throughput.
921 * this functionality is controlled by the InterruptThrottleRate module
922 * parameter (see ixgbe_param.c)
923 **/
924 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
925 u32 eitr, u8 itr_setting,
926 int packets, int bytes)
927 {
928 unsigned int retval = itr_setting;
929 u32 timepassed_us;
930 u64 bytes_perint;
931
932 if (packets == 0)
933 goto update_itr_done;
934
935
936 /* simple throttlerate management
937 * 0-20MB/s lowest (100000 ints/s)
938 * 20-100MB/s low (20000 ints/s)
939 * 100-1249MB/s bulk (8000 ints/s)
940 */
941 /* what was last interrupt timeslice? */
942 timepassed_us = 1000000/eitr;
943 bytes_perint = bytes / timepassed_us; /* bytes/usec */
944
945 switch (itr_setting) {
946 case lowest_latency:
947 if (bytes_perint > adapter->eitr_low)
948 retval = low_latency;
949 break;
950 case low_latency:
951 if (bytes_perint > adapter->eitr_high)
952 retval = bulk_latency;
953 else if (bytes_perint <= adapter->eitr_low)
954 retval = lowest_latency;
955 break;
956 case bulk_latency:
957 if (bytes_perint <= adapter->eitr_high)
958 retval = low_latency;
959 break;
960 }
961
962 update_itr_done:
963 return retval;
964 }
965
966 /**
967 * ixgbe_write_eitr - write EITR register in hardware specific way
968 * @adapter: pointer to adapter struct
969 * @v_idx: vector index into q_vector array
970 * @itr_reg: new value to be written in *register* format, not ints/s
971 *
972 * This function is made to be called by ethtool and by the driver
973 * when it needs to update EITR registers at runtime. Hardware
974 * specific quirks/differences are taken care of here.
975 */
976 void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
977 {
978 struct ixgbe_hw *hw = &adapter->hw;
979 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
980 /* must write high and low 16 bits to reset counter */
981 itr_reg |= (itr_reg << 16);
982 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
983 /*
984 * set the WDIS bit to not clear the timer bits and cause an
985 * immediate assertion of the interrupt
986 */
987 itr_reg |= IXGBE_EITR_CNT_WDIS;
988 }
989 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
990 }
991
992 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
993 {
994 struct ixgbe_adapter *adapter = q_vector->adapter;
995 u32 new_itr;
996 u8 current_itr, ret_itr;
997 int i, r_idx, v_idx = q_vector->v_idx;
998 struct ixgbe_ring *rx_ring, *tx_ring;
999
1000 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1001 for (i = 0; i < q_vector->txr_count; i++) {
1002 tx_ring = &(adapter->tx_ring[r_idx]);
1003 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1004 q_vector->tx_itr,
1005 tx_ring->total_packets,
1006 tx_ring->total_bytes);
1007 /* if the result for this queue would decrease interrupt
1008 * rate for this vector then use that result */
1009 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1010 q_vector->tx_itr - 1 : ret_itr);
1011 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1012 r_idx + 1);
1013 }
1014
1015 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1016 for (i = 0; i < q_vector->rxr_count; i++) {
1017 rx_ring = &(adapter->rx_ring[r_idx]);
1018 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1019 q_vector->rx_itr,
1020 rx_ring->total_packets,
1021 rx_ring->total_bytes);
1022 /* if the result for this queue would decrease interrupt
1023 * rate for this vector then use that result */
1024 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1025 q_vector->rx_itr - 1 : ret_itr);
1026 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1027 r_idx + 1);
1028 }
1029
1030 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1031
1032 switch (current_itr) {
1033 /* counts and packets in update_itr are dependent on these numbers */
1034 case lowest_latency:
1035 new_itr = 100000;
1036 break;
1037 case low_latency:
1038 new_itr = 20000; /* aka hwitr = ~200 */
1039 break;
1040 case bulk_latency:
1041 default:
1042 new_itr = 8000;
1043 break;
1044 }
1045
1046 if (new_itr != q_vector->eitr) {
1047 u32 itr_reg;
1048
1049 /* save the algorithm value here, not the smoothed one */
1050 q_vector->eitr = new_itr;
1051 /* do an exponential smoothing */
1052 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1053 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1054 ixgbe_write_eitr(adapter, v_idx, itr_reg);
1055 }
1056
1057 return;
1058 }
1059
1060 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1061 {
1062 struct ixgbe_hw *hw = &adapter->hw;
1063
1064 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1065 (eicr & IXGBE_EICR_GPI_SDP1)) {
1066 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1067 /* write to clear the interrupt */
1068 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1069 }
1070 }
1071
1072 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1073 {
1074 struct ixgbe_hw *hw = &adapter->hw;
1075
1076 if (eicr & IXGBE_EICR_GPI_SDP1) {
1077 /* Clear the interrupt */
1078 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1079 schedule_work(&adapter->multispeed_fiber_task);
1080 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1081 /* Clear the interrupt */
1082 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1083 schedule_work(&adapter->sfp_config_module_task);
1084 } else {
1085 /* Interrupt isn't for us... */
1086 return;
1087 }
1088 }
1089
1090 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1091 {
1092 struct ixgbe_hw *hw = &adapter->hw;
1093
1094 adapter->lsc_int++;
1095 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1096 adapter->link_check_timeout = jiffies;
1097 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1098 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1099 schedule_work(&adapter->watchdog_task);
1100 }
1101 }
1102
1103 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1104 {
1105 struct net_device *netdev = data;
1106 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1107 struct ixgbe_hw *hw = &adapter->hw;
1108 u32 eicr;
1109
1110 /*
1111 * Workaround for Silicon errata. Use clear-by-write instead
1112 * of clear-by-read. Reading with EICS will return the
1113 * interrupt causes without clearing, which later be done
1114 * with the write to EICR.
1115 */
1116 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1117 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1118
1119 if (eicr & IXGBE_EICR_LSC)
1120 ixgbe_check_lsc(adapter);
1121
1122 if (hw->mac.type == ixgbe_mac_82598EB)
1123 ixgbe_check_fan_failure(adapter, eicr);
1124
1125 if (hw->mac.type == ixgbe_mac_82599EB)
1126 ixgbe_check_sfp_event(adapter, eicr);
1127 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1128 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1129
1130 return IRQ_HANDLED;
1131 }
1132
1133 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1134 {
1135 struct ixgbe_q_vector *q_vector = data;
1136 struct ixgbe_adapter *adapter = q_vector->adapter;
1137 struct ixgbe_ring *tx_ring;
1138 int i, r_idx;
1139
1140 if (!q_vector->txr_count)
1141 return IRQ_HANDLED;
1142
1143 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1144 for (i = 0; i < q_vector->txr_count; i++) {
1145 tx_ring = &(adapter->tx_ring[r_idx]);
1146 #ifdef CONFIG_IXGBE_DCA
1147 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1148 ixgbe_update_tx_dca(adapter, tx_ring);
1149 #endif
1150 tx_ring->total_bytes = 0;
1151 tx_ring->total_packets = 0;
1152 ixgbe_clean_tx_irq(adapter, tx_ring);
1153 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1154 r_idx + 1);
1155 }
1156
1157 return IRQ_HANDLED;
1158 }
1159
1160 /**
1161 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1162 * @irq: unused
1163 * @data: pointer to our q_vector struct for this interrupt vector
1164 **/
1165 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1166 {
1167 struct ixgbe_q_vector *q_vector = data;
1168 struct ixgbe_adapter *adapter = q_vector->adapter;
1169 struct ixgbe_ring *rx_ring;
1170 int r_idx;
1171 int i;
1172
1173 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1174 for (i = 0; i < q_vector->rxr_count; i++) {
1175 rx_ring = &(adapter->rx_ring[r_idx]);
1176 rx_ring->total_bytes = 0;
1177 rx_ring->total_packets = 0;
1178 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1179 r_idx + 1);
1180 }
1181
1182 if (!q_vector->rxr_count)
1183 return IRQ_HANDLED;
1184
1185 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1186 rx_ring = &(adapter->rx_ring[r_idx]);
1187 /* disable interrupts on this vector only */
1188 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1189 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1190 else if (rx_ring->v_idx & 0xFFFFFFFF)
1191 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx);
1192 else
1193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1),
1194 (rx_ring->v_idx >> 32));
1195 napi_schedule(&q_vector->napi);
1196
1197 return IRQ_HANDLED;
1198 }
1199
1200 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1201 {
1202 ixgbe_msix_clean_rx(irq, data);
1203 ixgbe_msix_clean_tx(irq, data);
1204
1205 return IRQ_HANDLED;
1206 }
1207
1208 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1209 u64 qmask)
1210 {
1211 u32 mask;
1212
1213 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1214 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1216 } else {
1217 mask = (qmask & 0xFFFFFFFF);
1218 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1219 mask = (qmask >> 32);
1220 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1221 }
1222 /* skip the flush */
1223 }
1224
1225 /**
1226 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1227 * @napi: napi struct with our devices info in it
1228 * @budget: amount of work driver is allowed to do this pass, in packets
1229 *
1230 * This function is optimized for cleaning one queue only on a single
1231 * q_vector!!!
1232 **/
1233 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1234 {
1235 struct ixgbe_q_vector *q_vector =
1236 container_of(napi, struct ixgbe_q_vector, napi);
1237 struct ixgbe_adapter *adapter = q_vector->adapter;
1238 struct ixgbe_ring *rx_ring = NULL;
1239 int work_done = 0;
1240 long r_idx;
1241
1242 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1243 rx_ring = &(adapter->rx_ring[r_idx]);
1244 #ifdef CONFIG_IXGBE_DCA
1245 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1246 ixgbe_update_rx_dca(adapter, rx_ring);
1247 #endif
1248
1249 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1250
1251 /* If all Rx work done, exit the polling mode */
1252 if (work_done < budget) {
1253 napi_complete(napi);
1254 if (adapter->itr_setting & 1)
1255 ixgbe_set_itr_msix(q_vector);
1256 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1257 ixgbe_irq_enable_queues(adapter, rx_ring->v_idx);
1258 }
1259
1260 return work_done;
1261 }
1262
1263 /**
1264 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1265 * @napi: napi struct with our devices info in it
1266 * @budget: amount of work driver is allowed to do this pass, in packets
1267 *
1268 * This function will clean more than one rx queue associated with a
1269 * q_vector.
1270 **/
1271 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1272 {
1273 struct ixgbe_q_vector *q_vector =
1274 container_of(napi, struct ixgbe_q_vector, napi);
1275 struct ixgbe_adapter *adapter = q_vector->adapter;
1276 struct ixgbe_ring *rx_ring = NULL;
1277 int work_done = 0, i;
1278 long r_idx;
1279 u64 enable_mask = 0;
1280
1281 /* attempt to distribute budget to each queue fairly, but don't allow
1282 * the budget to go below 1 because we'll exit polling */
1283 budget /= (q_vector->rxr_count ?: 1);
1284 budget = max(budget, 1);
1285 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1286 for (i = 0; i < q_vector->rxr_count; i++) {
1287 rx_ring = &(adapter->rx_ring[r_idx]);
1288 #ifdef CONFIG_IXGBE_DCA
1289 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1290 ixgbe_update_rx_dca(adapter, rx_ring);
1291 #endif
1292 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1293 enable_mask |= rx_ring->v_idx;
1294 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1295 r_idx + 1);
1296 }
1297
1298 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1299 rx_ring = &(adapter->rx_ring[r_idx]);
1300 /* If all Rx work done, exit the polling mode */
1301 if (work_done < budget) {
1302 napi_complete(napi);
1303 if (adapter->itr_setting & 1)
1304 ixgbe_set_itr_msix(q_vector);
1305 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1306 ixgbe_irq_enable_queues(adapter, enable_mask);
1307 return 0;
1308 }
1309
1310 return work_done;
1311 }
1312 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1313 int r_idx)
1314 {
1315 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1316
1317 set_bit(r_idx, q_vector->rxr_idx);
1318 q_vector->rxr_count++;
1319 a->rx_ring[r_idx].v_idx = (u64)1 << v_idx;
1320 }
1321
1322 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1323 int t_idx)
1324 {
1325 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1326
1327 set_bit(t_idx, q_vector->txr_idx);
1328 q_vector->txr_count++;
1329 a->tx_ring[t_idx].v_idx = (u64)1 << v_idx;
1330 }
1331
1332 /**
1333 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1334 * @adapter: board private structure to initialize
1335 * @vectors: allotted vector count for descriptor rings
1336 *
1337 * This function maps descriptor rings to the queue-specific vectors
1338 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1339 * one vector per ring/queue, but on a constrained vector budget, we
1340 * group the rings as "efficiently" as possible. You would add new
1341 * mapping configurations in here.
1342 **/
1343 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1344 int vectors)
1345 {
1346 int v_start = 0;
1347 int rxr_idx = 0, txr_idx = 0;
1348 int rxr_remaining = adapter->num_rx_queues;
1349 int txr_remaining = adapter->num_tx_queues;
1350 int i, j;
1351 int rqpv, tqpv;
1352 int err = 0;
1353
1354 /* No mapping required if MSI-X is disabled. */
1355 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1356 goto out;
1357
1358 /*
1359 * The ideal configuration...
1360 * We have enough vectors to map one per queue.
1361 */
1362 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1363 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1364 map_vector_to_rxq(adapter, v_start, rxr_idx);
1365
1366 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1367 map_vector_to_txq(adapter, v_start, txr_idx);
1368
1369 goto out;
1370 }
1371
1372 /*
1373 * If we don't have enough vectors for a 1-to-1
1374 * mapping, we'll have to group them so there are
1375 * multiple queues per vector.
1376 */
1377 /* Re-adjusting *qpv takes care of the remainder. */
1378 for (i = v_start; i < vectors; i++) {
1379 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1380 for (j = 0; j < rqpv; j++) {
1381 map_vector_to_rxq(adapter, i, rxr_idx);
1382 rxr_idx++;
1383 rxr_remaining--;
1384 }
1385 }
1386 for (i = v_start; i < vectors; i++) {
1387 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1388 for (j = 0; j < tqpv; j++) {
1389 map_vector_to_txq(adapter, i, txr_idx);
1390 txr_idx++;
1391 txr_remaining--;
1392 }
1393 }
1394
1395 out:
1396 return err;
1397 }
1398
1399 /**
1400 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1401 * @adapter: board private structure
1402 *
1403 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1404 * interrupts from the kernel.
1405 **/
1406 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1407 {
1408 struct net_device *netdev = adapter->netdev;
1409 irqreturn_t (*handler)(int, void *);
1410 int i, vector, q_vectors, err;
1411 int ri=0, ti=0;
1412
1413 /* Decrement for Other and TCP Timer vectors */
1414 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1415
1416 /* Map the Tx/Rx rings to the vectors we were allotted. */
1417 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1418 if (err)
1419 goto out;
1420
1421 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1422 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1423 &ixgbe_msix_clean_many)
1424 for (vector = 0; vector < q_vectors; vector++) {
1425 handler = SET_HANDLER(adapter->q_vector[vector]);
1426
1427 if(handler == &ixgbe_msix_clean_rx) {
1428 sprintf(adapter->name[vector], "%s-%s-%d",
1429 netdev->name, "rx", ri++);
1430 }
1431 else if(handler == &ixgbe_msix_clean_tx) {
1432 sprintf(adapter->name[vector], "%s-%s-%d",
1433 netdev->name, "tx", ti++);
1434 }
1435 else
1436 sprintf(adapter->name[vector], "%s-%s-%d",
1437 netdev->name, "TxRx", vector);
1438
1439 err = request_irq(adapter->msix_entries[vector].vector,
1440 handler, 0, adapter->name[vector],
1441 adapter->q_vector[vector]);
1442 if (err) {
1443 DPRINTK(PROBE, ERR,
1444 "request_irq failed for MSIX interrupt "
1445 "Error: %d\n", err);
1446 goto free_queue_irqs;
1447 }
1448 }
1449
1450 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1451 err = request_irq(adapter->msix_entries[vector].vector,
1452 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1453 if (err) {
1454 DPRINTK(PROBE, ERR,
1455 "request_irq for msix_lsc failed: %d\n", err);
1456 goto free_queue_irqs;
1457 }
1458
1459 return 0;
1460
1461 free_queue_irqs:
1462 for (i = vector - 1; i >= 0; i--)
1463 free_irq(adapter->msix_entries[--vector].vector,
1464 adapter->q_vector[i]);
1465 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1466 pci_disable_msix(adapter->pdev);
1467 kfree(adapter->msix_entries);
1468 adapter->msix_entries = NULL;
1469 out:
1470 return err;
1471 }
1472
1473 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1474 {
1475 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1476 u8 current_itr;
1477 u32 new_itr = q_vector->eitr;
1478 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1479 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1480
1481 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1482 q_vector->tx_itr,
1483 tx_ring->total_packets,
1484 tx_ring->total_bytes);
1485 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1486 q_vector->rx_itr,
1487 rx_ring->total_packets,
1488 rx_ring->total_bytes);
1489
1490 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1491
1492 switch (current_itr) {
1493 /* counts and packets in update_itr are dependent on these numbers */
1494 case lowest_latency:
1495 new_itr = 100000;
1496 break;
1497 case low_latency:
1498 new_itr = 20000; /* aka hwitr = ~200 */
1499 break;
1500 case bulk_latency:
1501 new_itr = 8000;
1502 break;
1503 default:
1504 break;
1505 }
1506
1507 if (new_itr != q_vector->eitr) {
1508 u32 itr_reg;
1509
1510 /* save the algorithm value here, not the smoothed one */
1511 q_vector->eitr = new_itr;
1512 /* do an exponential smoothing */
1513 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1514 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1515 ixgbe_write_eitr(adapter, 0, itr_reg);
1516 }
1517
1518 return;
1519 }
1520
1521 /**
1522 * ixgbe_irq_enable - Enable default interrupt generation settings
1523 * @adapter: board private structure
1524 **/
1525 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1526 {
1527 u32 mask;
1528
1529 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1530 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1531 mask |= IXGBE_EIMS_GPI_SDP1;
1532 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1533 mask |= IXGBE_EIMS_ECC;
1534 mask |= IXGBE_EIMS_GPI_SDP1;
1535 mask |= IXGBE_EIMS_GPI_SDP2;
1536 }
1537
1538 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1539 ixgbe_irq_enable_queues(adapter, ~0);
1540 IXGBE_WRITE_FLUSH(&adapter->hw);
1541 }
1542
1543 /**
1544 * ixgbe_intr - legacy mode Interrupt Handler
1545 * @irq: interrupt number
1546 * @data: pointer to a network interface device structure
1547 **/
1548 static irqreturn_t ixgbe_intr(int irq, void *data)
1549 {
1550 struct net_device *netdev = data;
1551 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1552 struct ixgbe_hw *hw = &adapter->hw;
1553 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1554 u32 eicr;
1555
1556 /*
1557 * Workaround for silicon errata. Mask the interrupts
1558 * before the read of EICR.
1559 */
1560 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1561
1562 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1563 * therefore no explict interrupt disable is necessary */
1564 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1565 if (!eicr) {
1566 /* shared interrupt alert!
1567 * make sure interrupts are enabled because the read will
1568 * have disabled interrupts due to EIAM */
1569 ixgbe_irq_enable(adapter);
1570 return IRQ_NONE; /* Not our interrupt */
1571 }
1572
1573 if (eicr & IXGBE_EICR_LSC)
1574 ixgbe_check_lsc(adapter);
1575
1576 if (hw->mac.type == ixgbe_mac_82599EB)
1577 ixgbe_check_sfp_event(adapter, eicr);
1578
1579 ixgbe_check_fan_failure(adapter, eicr);
1580
1581 if (napi_schedule_prep(&(q_vector->napi))) {
1582 adapter->tx_ring[0].total_packets = 0;
1583 adapter->tx_ring[0].total_bytes = 0;
1584 adapter->rx_ring[0].total_packets = 0;
1585 adapter->rx_ring[0].total_bytes = 0;
1586 /* would disable interrupts here but EIAM disabled it */
1587 __napi_schedule(&(q_vector->napi));
1588 }
1589
1590 return IRQ_HANDLED;
1591 }
1592
1593 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1594 {
1595 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1596
1597 for (i = 0; i < q_vectors; i++) {
1598 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1599 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1600 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1601 q_vector->rxr_count = 0;
1602 q_vector->txr_count = 0;
1603 }
1604 }
1605
1606 /**
1607 * ixgbe_request_irq - initialize interrupts
1608 * @adapter: board private structure
1609 *
1610 * Attempts to configure interrupts using the best available
1611 * capabilities of the hardware and kernel.
1612 **/
1613 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1614 {
1615 struct net_device *netdev = adapter->netdev;
1616 int err;
1617
1618 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1619 err = ixgbe_request_msix_irqs(adapter);
1620 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1621 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1622 netdev->name, netdev);
1623 } else {
1624 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1625 netdev->name, netdev);
1626 }
1627
1628 if (err)
1629 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1630
1631 return err;
1632 }
1633
1634 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1635 {
1636 struct net_device *netdev = adapter->netdev;
1637
1638 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1639 int i, q_vectors;
1640
1641 q_vectors = adapter->num_msix_vectors;
1642
1643 i = q_vectors - 1;
1644 free_irq(adapter->msix_entries[i].vector, netdev);
1645
1646 i--;
1647 for (; i >= 0; i--) {
1648 free_irq(adapter->msix_entries[i].vector,
1649 adapter->q_vector[i]);
1650 }
1651
1652 ixgbe_reset_q_vectors(adapter);
1653 } else {
1654 free_irq(adapter->pdev->irq, netdev);
1655 }
1656 }
1657
1658 /**
1659 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1660 * @adapter: board private structure
1661 **/
1662 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1663 {
1664 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1665 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1666 } else {
1667 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1668 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1669 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1670 }
1671 IXGBE_WRITE_FLUSH(&adapter->hw);
1672 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1673 int i;
1674 for (i = 0; i < adapter->num_msix_vectors; i++)
1675 synchronize_irq(adapter->msix_entries[i].vector);
1676 } else {
1677 synchronize_irq(adapter->pdev->irq);
1678 }
1679 }
1680
1681 /**
1682 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1683 *
1684 **/
1685 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1686 {
1687 struct ixgbe_hw *hw = &adapter->hw;
1688
1689 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1690 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1691
1692 ixgbe_set_ivar(adapter, 0, 0, 0);
1693 ixgbe_set_ivar(adapter, 1, 0, 0);
1694
1695 map_vector_to_rxq(adapter, 0, 0);
1696 map_vector_to_txq(adapter, 0, 0);
1697
1698 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1699 }
1700
1701 /**
1702 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1703 * @adapter: board private structure
1704 *
1705 * Configure the Tx unit of the MAC after a reset.
1706 **/
1707 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1708 {
1709 u64 tdba;
1710 struct ixgbe_hw *hw = &adapter->hw;
1711 u32 i, j, tdlen, txctrl;
1712
1713 /* Setup the HW Tx Head and Tail descriptor pointers */
1714 for (i = 0; i < adapter->num_tx_queues; i++) {
1715 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1716 j = ring->reg_idx;
1717 tdba = ring->dma;
1718 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1719 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1720 (tdba & DMA_BIT_MASK(32)));
1721 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1722 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1723 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1724 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1725 adapter->tx_ring[i].head = IXGBE_TDH(j);
1726 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1727 /* Disable Tx Head Writeback RO bit, since this hoses
1728 * bookkeeping if things aren't delivered in order.
1729 */
1730 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1731 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1732 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1733 }
1734 if (hw->mac.type == ixgbe_mac_82599EB) {
1735 /* We enable 8 traffic classes, DCB only */
1736 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1737 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1738 IXGBE_MTQC_8TC_8TQ));
1739 }
1740 }
1741
1742 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1743
1744 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1745 {
1746 struct ixgbe_ring *rx_ring;
1747 u32 srrctl;
1748 int queue0 = 0;
1749 unsigned long mask;
1750 struct ixgbe_ring_feature *feature = adapter->ring_feature;
1751
1752 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1753 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1754 int dcb_i = feature[RING_F_DCB].indices;
1755 if (dcb_i == 8)
1756 queue0 = index >> 4;
1757 else if (dcb_i == 4)
1758 queue0 = index >> 5;
1759 else
1760 dev_err(&adapter->pdev->dev, "Invalid DCB "
1761 "configuration\n");
1762 #ifdef IXGBE_FCOE
1763 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1764 struct ixgbe_ring_feature *f;
1765
1766 rx_ring = &adapter->rx_ring[queue0];
1767 f = &adapter->ring_feature[RING_F_FCOE];
1768 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1769 queue0 = f->mask + index -
1770 rx_ring->reg_idx - 1;
1771 }
1772 #endif /* IXGBE_FCOE */
1773 } else {
1774 queue0 = index;
1775 }
1776 } else {
1777 mask = (unsigned long) feature[RING_F_RSS].mask;
1778 queue0 = index & mask;
1779 index = index & mask;
1780 }
1781
1782 rx_ring = &adapter->rx_ring[queue0];
1783
1784 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1785
1786 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1787 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1788
1789 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1790 IXGBE_SRRCTL_BSIZEHDR_MASK;
1791
1792 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1793 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1794 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1795 #else
1796 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1797 #endif
1798 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1799 } else {
1800 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1801 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1802 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1803 }
1804
1805 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1806 }
1807
1808 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1809 {
1810 u32 mrqc = 0;
1811 int mask;
1812
1813 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1814 return mrqc;
1815
1816 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1817 #ifdef CONFIG_IXGBE_DCB
1818 | IXGBE_FLAG_DCB_ENABLED
1819 #endif
1820 );
1821
1822 switch (mask) {
1823 case (IXGBE_FLAG_RSS_ENABLED):
1824 mrqc = IXGBE_MRQC_RSSEN;
1825 break;
1826 #ifdef CONFIG_IXGBE_DCB
1827 case (IXGBE_FLAG_DCB_ENABLED):
1828 mrqc = IXGBE_MRQC_RT8TCEN;
1829 break;
1830 #endif /* CONFIG_IXGBE_DCB */
1831 default:
1832 break;
1833 }
1834
1835 return mrqc;
1836 }
1837
1838 /**
1839 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1840 * @adapter: board private structure
1841 *
1842 * Configure the Rx unit of the MAC after a reset.
1843 **/
1844 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1845 {
1846 u64 rdba;
1847 struct ixgbe_hw *hw = &adapter->hw;
1848 struct net_device *netdev = adapter->netdev;
1849 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1850 int i, j;
1851 u32 rdlen, rxctrl, rxcsum;
1852 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1853 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1854 0x6A3E67EA, 0x14364D17, 0x3BED200D};
1855 u32 fctrl, hlreg0;
1856 u32 reta = 0, mrqc = 0;
1857 u32 rdrxctl;
1858 u32 rscctrl;
1859 int rx_buf_len;
1860
1861 /* Decide whether to use packet split mode or not */
1862 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1863
1864 #ifdef IXGBE_FCOE
1865 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1866 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1867 #endif /* IXGBE_FCOE */
1868
1869 /* Set the RX buffer length according to the mode */
1870 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1871 rx_buf_len = IXGBE_RX_HDR_SIZE;
1872 if (hw->mac.type == ixgbe_mac_82599EB) {
1873 /* PSRTYPE must be initialized in 82599 */
1874 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1875 IXGBE_PSRTYPE_UDPHDR |
1876 IXGBE_PSRTYPE_IPV4HDR |
1877 IXGBE_PSRTYPE_IPV6HDR |
1878 IXGBE_PSRTYPE_L2HDR;
1879 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1880 }
1881 } else {
1882 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1883 (netdev->mtu <= ETH_DATA_LEN))
1884 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1885 else
1886 rx_buf_len = ALIGN(max_frame, 1024);
1887 }
1888
1889 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1890 fctrl |= IXGBE_FCTRL_BAM;
1891 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1892 fctrl |= IXGBE_FCTRL_PMCF;
1893 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1894
1895 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1896 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1897 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1898 else
1899 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1900 #ifdef IXGBE_FCOE
1901 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1902 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1903 #endif
1904 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1905
1906 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1907 /* disable receives while setting up the descriptors */
1908 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1909 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1910
1911 /*
1912 * Setup the HW Rx Head and Tail Descriptor Pointers and
1913 * the Base and Length of the Rx Descriptor Ring
1914 */
1915 for (i = 0; i < adapter->num_rx_queues; i++) {
1916 rdba = adapter->rx_ring[i].dma;
1917 j = adapter->rx_ring[i].reg_idx;
1918 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
1919 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1920 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1921 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1922 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1923 adapter->rx_ring[i].head = IXGBE_RDH(j);
1924 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1925 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1926
1927 #ifdef IXGBE_FCOE
1928 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1929 struct ixgbe_ring_feature *f;
1930 f = &adapter->ring_feature[RING_F_FCOE];
1931 if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
1932 (i >= f->mask) && (i < f->mask + f->indices))
1933 adapter->rx_ring[i].rx_buf_len =
1934 IXGBE_FCOE_JUMBO_FRAME_SIZE;
1935 }
1936
1937 #endif /* IXGBE_FCOE */
1938 ixgbe_configure_srrctl(adapter, j);
1939 }
1940
1941 if (hw->mac.type == ixgbe_mac_82598EB) {
1942 /*
1943 * For VMDq support of different descriptor types or
1944 * buffer sizes through the use of multiple SRRCTL
1945 * registers, RDRXCTL.MVMEN must be set to 1
1946 *
1947 * also, the manual doesn't mention it clearly but DCA hints
1948 * will only use queue 0's tags unless this bit is set. Side
1949 * effects of setting this bit are only that SRRCTL must be
1950 * fully programmed [0..15]
1951 */
1952 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1953 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1954 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1955 }
1956
1957 /* Program MRQC for the distribution of queues */
1958 mrqc = ixgbe_setup_mrqc(adapter);
1959
1960 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1961 /* Fill out redirection table */
1962 for (i = 0, j = 0; i < 128; i++, j++) {
1963 if (j == adapter->ring_feature[RING_F_RSS].indices)
1964 j = 0;
1965 /* reta = 4-byte sliding window of
1966 * 0x00..(indices-1)(indices-1)00..etc. */
1967 reta = (reta << 8) | (j * 0x11);
1968 if ((i & 3) == 3)
1969 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1970 }
1971
1972 /* Fill out hash function seeds */
1973 for (i = 0; i < 10; i++)
1974 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1975
1976 if (hw->mac.type == ixgbe_mac_82598EB)
1977 mrqc |= IXGBE_MRQC_RSSEN;
1978 /* Perform hash on these packet types */
1979 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1980 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1981 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1982 | IXGBE_MRQC_RSS_FIELD_IPV6
1983 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1984 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
1985 }
1986 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1987
1988 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1989
1990 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1991 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1992 /* Disable indicating checksum in descriptor, enables
1993 * RSS hash */
1994 rxcsum |= IXGBE_RXCSUM_PCSD;
1995 }
1996 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1997 /* Enable IPv4 payload checksum for UDP fragments
1998 * if PCSD is not set */
1999 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2000 }
2001
2002 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2003
2004 if (hw->mac.type == ixgbe_mac_82599EB) {
2005 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2006 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2007 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2008 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2009 }
2010
2011 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
2012 /* Enable 82599 HW-RSC */
2013 for (i = 0; i < adapter->num_rx_queues; i++) {
2014 j = adapter->rx_ring[i].reg_idx;
2015 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2016 rscctrl |= IXGBE_RSCCTL_RSCEN;
2017 /*
2018 * we must limit the number of descriptors so that the
2019 * total size of max desc * buf_len is not greater
2020 * than 65535
2021 */
2022 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2023 #if (MAX_SKB_FRAGS > 16)
2024 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2025 #elif (MAX_SKB_FRAGS > 8)
2026 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2027 #elif (MAX_SKB_FRAGS > 4)
2028 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2029 #else
2030 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2031 #endif
2032 } else {
2033 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2034 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2035 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2036 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2037 else
2038 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2039 }
2040 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2041 }
2042 /* Disable RSC for ACK packets */
2043 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2044 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2045 }
2046 }
2047
2048 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2049 {
2050 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2051 struct ixgbe_hw *hw = &adapter->hw;
2052
2053 /* add VID to filter table */
2054 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2055 }
2056
2057 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2058 {
2059 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2060 struct ixgbe_hw *hw = &adapter->hw;
2061
2062 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2063 ixgbe_irq_disable(adapter);
2064
2065 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2066
2067 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2068 ixgbe_irq_enable(adapter);
2069
2070 /* remove VID from filter table */
2071 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2072 }
2073
2074 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2075 struct vlan_group *grp)
2076 {
2077 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2078 u32 ctrl;
2079 int i, j;
2080
2081 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2082 ixgbe_irq_disable(adapter);
2083 adapter->vlgrp = grp;
2084
2085 /*
2086 * For a DCB driver, always enable VLAN tag stripping so we can
2087 * still receive traffic from a DCB-enabled host even if we're
2088 * not in DCB mode.
2089 */
2090 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2091 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2092 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2093 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2094 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2095 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2096 ctrl |= IXGBE_VLNCTRL_VFE;
2097 /* enable VLAN tag insert/strip */
2098 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2099 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2100 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2101 for (i = 0; i < adapter->num_rx_queues; i++) {
2102 j = adapter->rx_ring[i].reg_idx;
2103 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2104 ctrl |= IXGBE_RXDCTL_VME;
2105 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2106 }
2107 }
2108 ixgbe_vlan_rx_add_vid(netdev, 0);
2109
2110 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2111 ixgbe_irq_enable(adapter);
2112 }
2113
2114 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2115 {
2116 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2117
2118 if (adapter->vlgrp) {
2119 u16 vid;
2120 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2121 if (!vlan_group_get_device(adapter->vlgrp, vid))
2122 continue;
2123 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2124 }
2125 }
2126 }
2127
2128 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2129 {
2130 struct dev_mc_list *mc_ptr;
2131 u8 *addr = *mc_addr_ptr;
2132 *vmdq = 0;
2133
2134 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2135 if (mc_ptr->next)
2136 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2137 else
2138 *mc_addr_ptr = NULL;
2139
2140 return addr;
2141 }
2142
2143 /**
2144 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2145 * @netdev: network interface device structure
2146 *
2147 * The set_rx_method entry point is called whenever the unicast/multicast
2148 * address list or the network interface flags are updated. This routine is
2149 * responsible for configuring the hardware for proper unicast, multicast and
2150 * promiscuous mode.
2151 **/
2152 static void ixgbe_set_rx_mode(struct net_device *netdev)
2153 {
2154 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2155 struct ixgbe_hw *hw = &adapter->hw;
2156 u32 fctrl, vlnctrl;
2157 u8 *addr_list = NULL;
2158 int addr_count = 0;
2159
2160 /* Check for Promiscuous and All Multicast modes */
2161
2162 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2163 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2164
2165 if (netdev->flags & IFF_PROMISC) {
2166 hw->addr_ctrl.user_set_promisc = 1;
2167 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2168 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2169 } else {
2170 if (netdev->flags & IFF_ALLMULTI) {
2171 fctrl |= IXGBE_FCTRL_MPE;
2172 fctrl &= ~IXGBE_FCTRL_UPE;
2173 } else {
2174 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2175 }
2176 vlnctrl |= IXGBE_VLNCTRL_VFE;
2177 hw->addr_ctrl.user_set_promisc = 0;
2178 }
2179
2180 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2181 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2182
2183 /* reprogram secondary unicast list */
2184 addr_count = netdev->uc_count;
2185 if (addr_count)
2186 addr_list = netdev->uc_list->dmi_addr;
2187 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2188 ixgbe_addr_list_itr);
2189
2190 /* reprogram multicast list */
2191 addr_count = netdev->mc_count;
2192 if (addr_count)
2193 addr_list = netdev->mc_list->dmi_addr;
2194 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2195 ixgbe_addr_list_itr);
2196 }
2197
2198 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2199 {
2200 int q_idx;
2201 struct ixgbe_q_vector *q_vector;
2202 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2203
2204 /* legacy and MSI only use one vector */
2205 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2206 q_vectors = 1;
2207
2208 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2209 struct napi_struct *napi;
2210 q_vector = adapter->q_vector[q_idx];
2211 if (!q_vector->rxr_count)
2212 continue;
2213 napi = &q_vector->napi;
2214 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2215 (q_vector->rxr_count > 1))
2216 napi->poll = &ixgbe_clean_rxonly_many;
2217
2218 napi_enable(napi);
2219 }
2220 }
2221
2222 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2223 {
2224 int q_idx;
2225 struct ixgbe_q_vector *q_vector;
2226 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2227
2228 /* legacy and MSI only use one vector */
2229 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2230 q_vectors = 1;
2231
2232 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2233 q_vector = adapter->q_vector[q_idx];
2234 if (!q_vector->rxr_count)
2235 continue;
2236 napi_disable(&q_vector->napi);
2237 }
2238 }
2239
2240 #ifdef CONFIG_IXGBE_DCB
2241 /*
2242 * ixgbe_configure_dcb - Configure DCB hardware
2243 * @adapter: ixgbe adapter struct
2244 *
2245 * This is called by the driver on open to configure the DCB hardware.
2246 * This is also called by the gennetlink interface when reconfiguring
2247 * the DCB state.
2248 */
2249 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2250 {
2251 struct ixgbe_hw *hw = &adapter->hw;
2252 u32 txdctl, vlnctrl;
2253 int i, j;
2254
2255 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2256 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2257 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2258
2259 /* reconfigure the hardware */
2260 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2261
2262 for (i = 0; i < adapter->num_tx_queues; i++) {
2263 j = adapter->tx_ring[i].reg_idx;
2264 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2265 /* PThresh workaround for Tx hang with DFP enabled. */
2266 txdctl |= 32;
2267 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2268 }
2269 /* Enable VLAN tag insert/strip */
2270 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2271 if (hw->mac.type == ixgbe_mac_82598EB) {
2272 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2273 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2274 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2275 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2276 vlnctrl |= IXGBE_VLNCTRL_VFE;
2277 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2278 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2279 for (i = 0; i < adapter->num_rx_queues; i++) {
2280 j = adapter->rx_ring[i].reg_idx;
2281 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2282 vlnctrl |= IXGBE_RXDCTL_VME;
2283 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2284 }
2285 }
2286 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2287 }
2288
2289 #endif
2290 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2291 {
2292 struct net_device *netdev = adapter->netdev;
2293 int i;
2294
2295 ixgbe_set_rx_mode(netdev);
2296
2297 ixgbe_restore_vlan(adapter);
2298 #ifdef CONFIG_IXGBE_DCB
2299 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2300 netif_set_gso_max_size(netdev, 32768);
2301 ixgbe_configure_dcb(adapter);
2302 } else {
2303 netif_set_gso_max_size(netdev, 65536);
2304 }
2305 #else
2306 netif_set_gso_max_size(netdev, 65536);
2307 #endif
2308
2309 #ifdef IXGBE_FCOE
2310 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2311 ixgbe_configure_fcoe(adapter);
2312
2313 #endif /* IXGBE_FCOE */
2314 ixgbe_configure_tx(adapter);
2315 ixgbe_configure_rx(adapter);
2316 for (i = 0; i < adapter->num_rx_queues; i++)
2317 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2318 (adapter->rx_ring[i].count - 1));
2319 }
2320
2321 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2322 {
2323 switch (hw->phy.type) {
2324 case ixgbe_phy_sfp_avago:
2325 case ixgbe_phy_sfp_ftl:
2326 case ixgbe_phy_sfp_intel:
2327 case ixgbe_phy_sfp_unknown:
2328 case ixgbe_phy_tw_tyco:
2329 case ixgbe_phy_tw_unknown:
2330 return true;
2331 default:
2332 return false;
2333 }
2334 }
2335
2336 /**
2337 * ixgbe_sfp_link_config - set up SFP+ link
2338 * @adapter: pointer to private adapter struct
2339 **/
2340 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2341 {
2342 struct ixgbe_hw *hw = &adapter->hw;
2343
2344 if (hw->phy.multispeed_fiber) {
2345 /*
2346 * In multispeed fiber setups, the device may not have
2347 * had a physical connection when the driver loaded.
2348 * If that's the case, the initial link configuration
2349 * couldn't get the MAC into 10G or 1G mode, so we'll
2350 * never have a link status change interrupt fire.
2351 * We need to try and force an autonegotiation
2352 * session, then bring up link.
2353 */
2354 hw->mac.ops.setup_sfp(hw);
2355 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2356 schedule_work(&adapter->multispeed_fiber_task);
2357 } else {
2358 /*
2359 * Direct Attach Cu and non-multispeed fiber modules
2360 * still need to be configured properly prior to
2361 * attempting link.
2362 */
2363 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2364 schedule_work(&adapter->sfp_config_module_task);
2365 }
2366 }
2367
2368 /**
2369 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2370 * @hw: pointer to private hardware struct
2371 *
2372 * Returns 0 on success, negative on failure
2373 **/
2374 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2375 {
2376 u32 autoneg;
2377 bool link_up = false;
2378 u32 ret = IXGBE_ERR_LINK_SETUP;
2379
2380 if (hw->mac.ops.check_link)
2381 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2382
2383 if (ret)
2384 goto link_cfg_out;
2385
2386 if (hw->mac.ops.get_link_capabilities)
2387 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2388 &hw->mac.autoneg);
2389 if (ret)
2390 goto link_cfg_out;
2391
2392 if (hw->mac.ops.setup_link_speed)
2393 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2394 link_cfg_out:
2395 return ret;
2396 }
2397
2398 #define IXGBE_MAX_RX_DESC_POLL 10
2399 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2400 int rxr)
2401 {
2402 int j = adapter->rx_ring[rxr].reg_idx;
2403 int k;
2404
2405 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2406 if (IXGBE_READ_REG(&adapter->hw,
2407 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2408 break;
2409 else
2410 msleep(1);
2411 }
2412 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2413 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2414 "not set within the polling period\n", rxr);
2415 }
2416 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2417 (adapter->rx_ring[rxr].count - 1));
2418 }
2419
2420 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2421 {
2422 struct net_device *netdev = adapter->netdev;
2423 struct ixgbe_hw *hw = &adapter->hw;
2424 int i, j = 0;
2425 int num_rx_rings = adapter->num_rx_queues;
2426 int err;
2427 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2428 u32 txdctl, rxdctl, mhadd;
2429 u32 dmatxctl;
2430 u32 gpie;
2431
2432 ixgbe_get_hw_control(adapter);
2433
2434 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2435 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2436 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2437 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2438 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2439 } else {
2440 /* MSI only */
2441 gpie = 0;
2442 }
2443 /* XXX: to interrupt immediately for EICS writes, enable this */
2444 /* gpie |= IXGBE_GPIE_EIMEN; */
2445 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2446 }
2447
2448 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2449 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2450 * specifically only auto mask tx and rx interrupts */
2451 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2452 }
2453
2454 /* Enable fan failure interrupt if media type is copper */
2455 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2456 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2457 gpie |= IXGBE_SDP1_GPIEN;
2458 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2459 }
2460
2461 if (hw->mac.type == ixgbe_mac_82599EB) {
2462 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2463 gpie |= IXGBE_SDP1_GPIEN;
2464 gpie |= IXGBE_SDP2_GPIEN;
2465 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2466 }
2467
2468 #ifdef IXGBE_FCOE
2469 /* adjust max frame to be able to do baby jumbo for FCoE */
2470 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2471 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2472 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2473
2474 #endif /* IXGBE_FCOE */
2475 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2476 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2477 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2478 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2479
2480 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2481 }
2482
2483 for (i = 0; i < adapter->num_tx_queues; i++) {
2484 j = adapter->tx_ring[i].reg_idx;
2485 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2486 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2487 txdctl |= (8 << 16);
2488 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2489 }
2490
2491 if (hw->mac.type == ixgbe_mac_82599EB) {
2492 /* DMATXCTL.EN must be set after all Tx queue config is done */
2493 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2494 dmatxctl |= IXGBE_DMATXCTL_TE;
2495 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2496 }
2497 for (i = 0; i < adapter->num_tx_queues; i++) {
2498 j = adapter->tx_ring[i].reg_idx;
2499 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2500 txdctl |= IXGBE_TXDCTL_ENABLE;
2501 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2502 }
2503
2504 for (i = 0; i < num_rx_rings; i++) {
2505 j = adapter->rx_ring[i].reg_idx;
2506 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2507 /* enable PTHRESH=32 descriptors (half the internal cache)
2508 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2509 * this also removes a pesky rx_no_buffer_count increment */
2510 rxdctl |= 0x0020;
2511 rxdctl |= IXGBE_RXDCTL_ENABLE;
2512 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2513 if (hw->mac.type == ixgbe_mac_82599EB)
2514 ixgbe_rx_desc_queue_enable(adapter, i);
2515 }
2516 /* enable all receives */
2517 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2518 if (hw->mac.type == ixgbe_mac_82598EB)
2519 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2520 else
2521 rxdctl |= IXGBE_RXCTRL_RXEN;
2522 hw->mac.ops.enable_rx_dma(hw, rxdctl);
2523
2524 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2525 ixgbe_configure_msix(adapter);
2526 else
2527 ixgbe_configure_msi_and_legacy(adapter);
2528
2529 clear_bit(__IXGBE_DOWN, &adapter->state);
2530 ixgbe_napi_enable_all(adapter);
2531
2532 /* clear any pending interrupts, may auto mask */
2533 IXGBE_READ_REG(hw, IXGBE_EICR);
2534
2535 ixgbe_irq_enable(adapter);
2536
2537 /*
2538 * If this adapter has a fan, check to see if we had a failure
2539 * before we enabled the interrupt.
2540 */
2541 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2542 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2543 if (esdp & IXGBE_ESDP_SDP1)
2544 DPRINTK(DRV, CRIT,
2545 "Fan has stopped, replace the adapter\n");
2546 }
2547
2548 /*
2549 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2550 * arrived before interrupts were enabled. We need to kick off
2551 * the SFP+ module setup first, then try to bring up link.
2552 * If we're not hot-pluggable SFP+, we just need to configure link
2553 * and bring it up.
2554 */
2555 err = hw->phy.ops.identify(hw);
2556 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2557 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2558 ixgbe_down(adapter);
2559 return err;
2560 }
2561
2562 if (ixgbe_is_sfp(hw)) {
2563 ixgbe_sfp_link_config(adapter);
2564 } else {
2565 err = ixgbe_non_sfp_link_config(hw);
2566 if (err)
2567 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2568 }
2569
2570 /* enable transmits */
2571 netif_tx_start_all_queues(netdev);
2572
2573 /* bring the link up in the watchdog, this could race with our first
2574 * link up interrupt but shouldn't be a problem */
2575 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2576 adapter->link_check_timeout = jiffies;
2577 mod_timer(&adapter->watchdog_timer, jiffies);
2578 return 0;
2579 }
2580
2581 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2582 {
2583 WARN_ON(in_interrupt());
2584 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2585 msleep(1);
2586 ixgbe_down(adapter);
2587 ixgbe_up(adapter);
2588 clear_bit(__IXGBE_RESETTING, &adapter->state);
2589 }
2590
2591 int ixgbe_up(struct ixgbe_adapter *adapter)
2592 {
2593 /* hardware has been reset, we need to reload some things */
2594 ixgbe_configure(adapter);
2595
2596 return ixgbe_up_complete(adapter);
2597 }
2598
2599 void ixgbe_reset(struct ixgbe_adapter *adapter)
2600 {
2601 struct ixgbe_hw *hw = &adapter->hw;
2602 if (hw->mac.ops.init_hw(hw))
2603 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2604
2605 /* reprogram the RAR[0] in case user changed it. */
2606 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2607
2608 }
2609
2610 /**
2611 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2612 * @adapter: board private structure
2613 * @rx_ring: ring to free buffers from
2614 **/
2615 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2616 struct ixgbe_ring *rx_ring)
2617 {
2618 struct pci_dev *pdev = adapter->pdev;
2619 unsigned long size;
2620 unsigned int i;
2621
2622 /* Free all the Rx ring sk_buffs */
2623
2624 for (i = 0; i < rx_ring->count; i++) {
2625 struct ixgbe_rx_buffer *rx_buffer_info;
2626
2627 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2628 if (rx_buffer_info->dma) {
2629 pci_unmap_single(pdev, rx_buffer_info->dma,
2630 rx_ring->rx_buf_len,
2631 PCI_DMA_FROMDEVICE);
2632 rx_buffer_info->dma = 0;
2633 }
2634 if (rx_buffer_info->skb) {
2635 struct sk_buff *skb = rx_buffer_info->skb;
2636 rx_buffer_info->skb = NULL;
2637 do {
2638 struct sk_buff *this = skb;
2639 skb = skb->prev;
2640 dev_kfree_skb(this);
2641 } while (skb);
2642 }
2643 if (!rx_buffer_info->page)
2644 continue;
2645 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2646 PCI_DMA_FROMDEVICE);
2647 rx_buffer_info->page_dma = 0;
2648 put_page(rx_buffer_info->page);
2649 rx_buffer_info->page = NULL;
2650 rx_buffer_info->page_offset = 0;
2651 }
2652
2653 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2654 memset(rx_ring->rx_buffer_info, 0, size);
2655
2656 /* Zero out the descriptor ring */
2657 memset(rx_ring->desc, 0, rx_ring->size);
2658
2659 rx_ring->next_to_clean = 0;
2660 rx_ring->next_to_use = 0;
2661
2662 if (rx_ring->head)
2663 writel(0, adapter->hw.hw_addr + rx_ring->head);
2664 if (rx_ring->tail)
2665 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2666 }
2667
2668 /**
2669 * ixgbe_clean_tx_ring - Free Tx Buffers
2670 * @adapter: board private structure
2671 * @tx_ring: ring to be cleaned
2672 **/
2673 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2674 struct ixgbe_ring *tx_ring)
2675 {
2676 struct ixgbe_tx_buffer *tx_buffer_info;
2677 unsigned long size;
2678 unsigned int i;
2679
2680 /* Free all the Tx ring sk_buffs */
2681
2682 for (i = 0; i < tx_ring->count; i++) {
2683 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2684 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2685 }
2686
2687 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2688 memset(tx_ring->tx_buffer_info, 0, size);
2689
2690 /* Zero out the descriptor ring */
2691 memset(tx_ring->desc, 0, tx_ring->size);
2692
2693 tx_ring->next_to_use = 0;
2694 tx_ring->next_to_clean = 0;
2695
2696 if (tx_ring->head)
2697 writel(0, adapter->hw.hw_addr + tx_ring->head);
2698 if (tx_ring->tail)
2699 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2700 }
2701
2702 /**
2703 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2704 * @adapter: board private structure
2705 **/
2706 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2707 {
2708 int i;
2709
2710 for (i = 0; i < adapter->num_rx_queues; i++)
2711 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2712 }
2713
2714 /**
2715 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2716 * @adapter: board private structure
2717 **/
2718 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2719 {
2720 int i;
2721
2722 for (i = 0; i < adapter->num_tx_queues; i++)
2723 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2724 }
2725
2726 void ixgbe_down(struct ixgbe_adapter *adapter)
2727 {
2728 struct net_device *netdev = adapter->netdev;
2729 struct ixgbe_hw *hw = &adapter->hw;
2730 u32 rxctrl;
2731 u32 txdctl;
2732 int i, j;
2733
2734 /* signal that we are down to the interrupt handler */
2735 set_bit(__IXGBE_DOWN, &adapter->state);
2736
2737 /* disable receives */
2738 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2739 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2740
2741 netif_tx_disable(netdev);
2742
2743 IXGBE_WRITE_FLUSH(hw);
2744 msleep(10);
2745
2746 netif_tx_stop_all_queues(netdev);
2747
2748 ixgbe_irq_disable(adapter);
2749
2750 ixgbe_napi_disable_all(adapter);
2751
2752 del_timer_sync(&adapter->watchdog_timer);
2753 cancel_work_sync(&adapter->watchdog_task);
2754
2755 /* disable transmits in the hardware now that interrupts are off */
2756 for (i = 0; i < adapter->num_tx_queues; i++) {
2757 j = adapter->tx_ring[i].reg_idx;
2758 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2759 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2760 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2761 }
2762 /* Disable the Tx DMA engine on 82599 */
2763 if (hw->mac.type == ixgbe_mac_82599EB)
2764 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2765 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2766 ~IXGBE_DMATXCTL_TE));
2767
2768 netif_carrier_off(netdev);
2769
2770 if (!pci_channel_offline(adapter->pdev))
2771 ixgbe_reset(adapter);
2772 ixgbe_clean_all_tx_rings(adapter);
2773 ixgbe_clean_all_rx_rings(adapter);
2774
2775 #ifdef CONFIG_IXGBE_DCA
2776 /* since we reset the hardware DCA settings were cleared */
2777 ixgbe_setup_dca(adapter);
2778 #endif
2779 }
2780
2781 /**
2782 * ixgbe_poll - NAPI Rx polling callback
2783 * @napi: structure for representing this polling device
2784 * @budget: how many packets driver is allowed to clean
2785 *
2786 * This function is used for legacy and MSI, NAPI mode
2787 **/
2788 static int ixgbe_poll(struct napi_struct *napi, int budget)
2789 {
2790 struct ixgbe_q_vector *q_vector =
2791 container_of(napi, struct ixgbe_q_vector, napi);
2792 struct ixgbe_adapter *adapter = q_vector->adapter;
2793 int tx_clean_complete, work_done = 0;
2794
2795 #ifdef CONFIG_IXGBE_DCA
2796 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2797 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2798 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2799 }
2800 #endif
2801
2802 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2803 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2804
2805 if (!tx_clean_complete)
2806 work_done = budget;
2807
2808 /* If budget not fully consumed, exit the polling mode */
2809 if (work_done < budget) {
2810 napi_complete(napi);
2811 if (adapter->itr_setting & 1)
2812 ixgbe_set_itr(adapter);
2813 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2814 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
2815 }
2816 return work_done;
2817 }
2818
2819 /**
2820 * ixgbe_tx_timeout - Respond to a Tx Hang
2821 * @netdev: network interface device structure
2822 **/
2823 static void ixgbe_tx_timeout(struct net_device *netdev)
2824 {
2825 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2826
2827 /* Do the reset outside of interrupt context */
2828 schedule_work(&adapter->reset_task);
2829 }
2830
2831 static void ixgbe_reset_task(struct work_struct *work)
2832 {
2833 struct ixgbe_adapter *adapter;
2834 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2835
2836 /* If we're already down or resetting, just bail */
2837 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2838 test_bit(__IXGBE_RESETTING, &adapter->state))
2839 return;
2840
2841 adapter->tx_timeout_count++;
2842
2843 ixgbe_reinit_locked(adapter);
2844 }
2845
2846 #ifdef CONFIG_IXGBE_DCB
2847 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2848 {
2849 bool ret = false;
2850 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
2851
2852 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2853 return ret;
2854
2855 f->mask = 0x7 << 3;
2856 adapter->num_rx_queues = f->indices;
2857 adapter->num_tx_queues = f->indices;
2858 ret = true;
2859
2860 return ret;
2861 }
2862 #endif
2863
2864 /**
2865 * ixgbe_set_rss_queues: Allocate queues for RSS
2866 * @adapter: board private structure to initialize
2867 *
2868 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2869 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2870 *
2871 **/
2872 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2873 {
2874 bool ret = false;
2875 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
2876
2877 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2878 f->mask = 0xF;
2879 adapter->num_rx_queues = f->indices;
2880 adapter->num_tx_queues = f->indices;
2881 ret = true;
2882 } else {
2883 ret = false;
2884 }
2885
2886 return ret;
2887 }
2888
2889 #ifdef IXGBE_FCOE
2890 /**
2891 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
2892 * @adapter: board private structure to initialize
2893 *
2894 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
2895 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
2896 * rx queues out of the max number of rx queues, instead, it is used as the
2897 * index of the first rx queue used by FCoE.
2898 *
2899 **/
2900 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
2901 {
2902 bool ret = false;
2903 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
2904
2905 f->indices = min((int)num_online_cpus(), f->indices);
2906 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2907 #ifdef CONFIG_IXGBE_DCB
2908 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2909 DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
2910 ixgbe_set_dcb_queues(adapter);
2911 }
2912 #endif
2913 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2914 DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
2915 ixgbe_set_rss_queues(adapter);
2916 }
2917 /* adding FCoE rx rings to the end */
2918 f->mask = adapter->num_rx_queues;
2919 adapter->num_rx_queues += f->indices;
2920 if (adapter->num_tx_queues == 0)
2921 adapter->num_tx_queues = f->indices;
2922
2923 ret = true;
2924 }
2925
2926 return ret;
2927 }
2928
2929 #endif /* IXGBE_FCOE */
2930 /*
2931 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2932 * @adapter: board private structure to initialize
2933 *
2934 * This is the top level queue allocation routine. The order here is very
2935 * important, starting with the "most" number of features turned on at once,
2936 * and ending with the smallest set of features. This way large combinations
2937 * can be allocated if they're turned on, and smaller combinations are the
2938 * fallthrough conditions.
2939 *
2940 **/
2941 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2942 {
2943 #ifdef IXGBE_FCOE
2944 if (ixgbe_set_fcoe_queues(adapter))
2945 goto done;
2946
2947 #endif /* IXGBE_FCOE */
2948 #ifdef CONFIG_IXGBE_DCB
2949 if (ixgbe_set_dcb_queues(adapter))
2950 goto done;
2951
2952 #endif
2953 if (ixgbe_set_rss_queues(adapter))
2954 goto done;
2955
2956 /* fallback to base case */
2957 adapter->num_rx_queues = 1;
2958 adapter->num_tx_queues = 1;
2959
2960 done:
2961 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2962 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2963 }
2964
2965 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2966 int vectors)
2967 {
2968 int err, vector_threshold;
2969
2970 /* We'll want at least 3 (vector_threshold):
2971 * 1) TxQ[0] Cleanup
2972 * 2) RxQ[0] Cleanup
2973 * 3) Other (Link Status Change, etc.)
2974 * 4) TCP Timer (optional)
2975 */
2976 vector_threshold = MIN_MSIX_COUNT;
2977
2978 /* The more we get, the more we will assign to Tx/Rx Cleanup
2979 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2980 * Right now, we simply care about how many we'll get; we'll
2981 * set them up later while requesting irq's.
2982 */
2983 while (vectors >= vector_threshold) {
2984 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2985 vectors);
2986 if (!err) /* Success in acquiring all requested vectors. */
2987 break;
2988 else if (err < 0)
2989 vectors = 0; /* Nasty failure, quit now */
2990 else /* err == number of vectors we should try again with */
2991 vectors = err;
2992 }
2993
2994 if (vectors < vector_threshold) {
2995 /* Can't allocate enough MSI-X interrupts? Oh well.
2996 * This just means we'll go with either a single MSI
2997 * vector or fall back to legacy interrupts.
2998 */
2999 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3000 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3001 kfree(adapter->msix_entries);
3002 adapter->msix_entries = NULL;
3003 } else {
3004 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3005 /*
3006 * Adjust for only the vectors we'll use, which is minimum
3007 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3008 * vectors we were allocated.
3009 */
3010 adapter->num_msix_vectors = min(vectors,
3011 adapter->max_msix_q_vectors + NON_Q_VECTORS);
3012 }
3013 }
3014
3015 /**
3016 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3017 * @adapter: board private structure to initialize
3018 *
3019 * Cache the descriptor ring offsets for RSS to the assigned rings.
3020 *
3021 **/
3022 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3023 {
3024 int i;
3025 bool ret = false;
3026
3027 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3028 for (i = 0; i < adapter->num_rx_queues; i++)
3029 adapter->rx_ring[i].reg_idx = i;
3030 for (i = 0; i < adapter->num_tx_queues; i++)
3031 adapter->tx_ring[i].reg_idx = i;
3032 ret = true;
3033 } else {
3034 ret = false;
3035 }
3036
3037 return ret;
3038 }
3039
3040 #ifdef CONFIG_IXGBE_DCB
3041 /**
3042 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3043 * @adapter: board private structure to initialize
3044 *
3045 * Cache the descriptor ring offsets for DCB to the assigned rings.
3046 *
3047 **/
3048 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3049 {
3050 int i;
3051 bool ret = false;
3052 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3053
3054 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3055 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3056 /* the number of queues is assumed to be symmetric */
3057 for (i = 0; i < dcb_i; i++) {
3058 adapter->rx_ring[i].reg_idx = i << 3;
3059 adapter->tx_ring[i].reg_idx = i << 2;
3060 }
3061 ret = true;
3062 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3063 if (dcb_i == 8) {
3064 /*
3065 * Tx TC0 starts at: descriptor queue 0
3066 * Tx TC1 starts at: descriptor queue 32
3067 * Tx TC2 starts at: descriptor queue 64
3068 * Tx TC3 starts at: descriptor queue 80
3069 * Tx TC4 starts at: descriptor queue 96
3070 * Tx TC5 starts at: descriptor queue 104
3071 * Tx TC6 starts at: descriptor queue 112
3072 * Tx TC7 starts at: descriptor queue 120
3073 *
3074 * Rx TC0-TC7 are offset by 16 queues each
3075 */
3076 for (i = 0; i < 3; i++) {
3077 adapter->tx_ring[i].reg_idx = i << 5;
3078 adapter->rx_ring[i].reg_idx = i << 4;
3079 }
3080 for ( ; i < 5; i++) {
3081 adapter->tx_ring[i].reg_idx =
3082 ((i + 2) << 4);
3083 adapter->rx_ring[i].reg_idx = i << 4;
3084 }
3085 for ( ; i < dcb_i; i++) {
3086 adapter->tx_ring[i].reg_idx =
3087 ((i + 8) << 3);
3088 adapter->rx_ring[i].reg_idx = i << 4;
3089 }
3090
3091 ret = true;
3092 } else if (dcb_i == 4) {
3093 /*
3094 * Tx TC0 starts at: descriptor queue 0
3095 * Tx TC1 starts at: descriptor queue 64
3096 * Tx TC2 starts at: descriptor queue 96
3097 * Tx TC3 starts at: descriptor queue 112
3098 *
3099 * Rx TC0-TC3 are offset by 32 queues each
3100 */
3101 adapter->tx_ring[0].reg_idx = 0;
3102 adapter->tx_ring[1].reg_idx = 64;
3103 adapter->tx_ring[2].reg_idx = 96;
3104 adapter->tx_ring[3].reg_idx = 112;
3105 for (i = 0 ; i < dcb_i; i++)
3106 adapter->rx_ring[i].reg_idx = i << 5;
3107
3108 ret = true;
3109 } else {
3110 ret = false;
3111 }
3112 } else {
3113 ret = false;
3114 }
3115 } else {
3116 ret = false;
3117 }
3118
3119 return ret;
3120 }
3121 #endif
3122
3123 #ifdef IXGBE_FCOE
3124 /**
3125 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3126 * @adapter: board private structure to initialize
3127 *
3128 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3129 *
3130 */
3131 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3132 {
3133 int i, fcoe_i = 0;
3134 bool ret = false;
3135 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3136
3137 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3138 #ifdef CONFIG_IXGBE_DCB
3139 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3140 ixgbe_cache_ring_dcb(adapter);
3141 fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3142 }
3143 #endif /* CONFIG_IXGBE_DCB */
3144 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3145 ixgbe_cache_ring_rss(adapter);
3146 fcoe_i = f->mask;
3147 }
3148 for (i = 0; i < f->indices; i++, fcoe_i++)
3149 adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3150 ret = true;
3151 }
3152 return ret;
3153 }
3154
3155 #endif /* IXGBE_FCOE */
3156 /**
3157 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3158 * @adapter: board private structure to initialize
3159 *
3160 * Once we know the feature-set enabled for the device, we'll cache
3161 * the register offset the descriptor ring is assigned to.
3162 *
3163 * Note, the order the various feature calls is important. It must start with
3164 * the "most" features enabled at the same time, then trickle down to the
3165 * least amount of features turned on at once.
3166 **/
3167 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3168 {
3169 /* start with default case */
3170 adapter->rx_ring[0].reg_idx = 0;
3171 adapter->tx_ring[0].reg_idx = 0;
3172
3173 #ifdef IXGBE_FCOE
3174 if (ixgbe_cache_ring_fcoe(adapter))
3175 return;
3176
3177 #endif /* IXGBE_FCOE */
3178 #ifdef CONFIG_IXGBE_DCB
3179 if (ixgbe_cache_ring_dcb(adapter))
3180 return;
3181
3182 #endif
3183 if (ixgbe_cache_ring_rss(adapter))
3184 return;
3185 }
3186
3187 /**
3188 * ixgbe_alloc_queues - Allocate memory for all rings
3189 * @adapter: board private structure to initialize
3190 *
3191 * We allocate one ring per queue at run-time since we don't know the
3192 * number of queues at compile-time. The polling_netdev array is
3193 * intended for Multiqueue, but should work fine with a single queue.
3194 **/
3195 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3196 {
3197 int i;
3198
3199 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3200 sizeof(struct ixgbe_ring), GFP_KERNEL);
3201 if (!adapter->tx_ring)
3202 goto err_tx_ring_allocation;
3203
3204 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3205 sizeof(struct ixgbe_ring), GFP_KERNEL);
3206 if (!adapter->rx_ring)
3207 goto err_rx_ring_allocation;
3208
3209 for (i = 0; i < adapter->num_tx_queues; i++) {
3210 adapter->tx_ring[i].count = adapter->tx_ring_count;
3211 adapter->tx_ring[i].queue_index = i;
3212 }
3213
3214 for (i = 0; i < adapter->num_rx_queues; i++) {
3215 adapter->rx_ring[i].count = adapter->rx_ring_count;
3216 adapter->rx_ring[i].queue_index = i;
3217 }
3218
3219 ixgbe_cache_ring_register(adapter);
3220
3221 return 0;
3222
3223 err_rx_ring_allocation:
3224 kfree(adapter->tx_ring);
3225 err_tx_ring_allocation:
3226 return -ENOMEM;
3227 }
3228
3229 /**
3230 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3231 * @adapter: board private structure to initialize
3232 *
3233 * Attempt to configure the interrupts using the best available
3234 * capabilities of the hardware and the kernel.
3235 **/
3236 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3237 {
3238 struct ixgbe_hw *hw = &adapter->hw;
3239 int err = 0;
3240 int vector, v_budget;
3241
3242 /*
3243 * It's easy to be greedy for MSI-X vectors, but it really
3244 * doesn't do us much good if we have a lot more vectors
3245 * than CPU's. So let's be conservative and only ask for
3246 * (roughly) twice the number of vectors as there are CPU's.
3247 */
3248 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3249 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3250
3251 /*
3252 * At the same time, hardware can only support a maximum of
3253 * hw.mac->max_msix_vectors vectors. With features
3254 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3255 * descriptor queues supported by our device. Thus, we cap it off in
3256 * those rare cases where the cpu count also exceeds our vector limit.
3257 */
3258 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3259
3260 /* A failure in MSI-X entry allocation isn't fatal, but it does
3261 * mean we disable MSI-X capabilities of the adapter. */
3262 adapter->msix_entries = kcalloc(v_budget,
3263 sizeof(struct msix_entry), GFP_KERNEL);
3264 if (adapter->msix_entries) {
3265 for (vector = 0; vector < v_budget; vector++)
3266 adapter->msix_entries[vector].entry = vector;
3267
3268 ixgbe_acquire_msix_vectors(adapter, v_budget);
3269
3270 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3271 goto out;
3272 }
3273
3274 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3275 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3276 ixgbe_set_num_queues(adapter);
3277
3278 err = pci_enable_msi(adapter->pdev);
3279 if (!err) {
3280 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3281 } else {
3282 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3283 "falling back to legacy. Error: %d\n", err);
3284 /* reset err */
3285 err = 0;
3286 }
3287
3288 out:
3289 return err;
3290 }
3291
3292 /**
3293 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3294 * @adapter: board private structure to initialize
3295 *
3296 * We allocate one q_vector per queue interrupt. If allocation fails we
3297 * return -ENOMEM.
3298 **/
3299 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3300 {
3301 int q_idx, num_q_vectors;
3302 struct ixgbe_q_vector *q_vector;
3303 int napi_vectors;
3304 int (*poll)(struct napi_struct *, int);
3305
3306 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3307 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3308 napi_vectors = adapter->num_rx_queues;
3309 poll = &ixgbe_clean_rxonly;
3310 } else {
3311 num_q_vectors = 1;
3312 napi_vectors = 1;
3313 poll = &ixgbe_poll;
3314 }
3315
3316 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3317 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3318 if (!q_vector)
3319 goto err_out;
3320 q_vector->adapter = adapter;
3321 q_vector->v_idx = q_idx;
3322 q_vector->eitr = adapter->eitr_param;
3323 if (q_idx < napi_vectors)
3324 netif_napi_add(adapter->netdev, &q_vector->napi,
3325 (*poll), 64);
3326 adapter->q_vector[q_idx] = q_vector;
3327 }
3328
3329 return 0;
3330
3331 err_out:
3332 while (q_idx) {
3333 q_idx--;
3334 q_vector = adapter->q_vector[q_idx];
3335 netif_napi_del(&q_vector->napi);
3336 kfree(q_vector);
3337 adapter->q_vector[q_idx] = NULL;
3338 }
3339 return -ENOMEM;
3340 }
3341
3342 /**
3343 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3344 * @adapter: board private structure to initialize
3345 *
3346 * This function frees the memory allocated to the q_vectors. In addition if
3347 * NAPI is enabled it will delete any references to the NAPI struct prior
3348 * to freeing the q_vector.
3349 **/
3350 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3351 {
3352 int q_idx, num_q_vectors;
3353 int napi_vectors;
3354
3355 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3356 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3357 napi_vectors = adapter->num_rx_queues;
3358 } else {
3359 num_q_vectors = 1;
3360 napi_vectors = 1;
3361 }
3362
3363 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3364 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3365
3366 adapter->q_vector[q_idx] = NULL;
3367 if (q_idx < napi_vectors)
3368 netif_napi_del(&q_vector->napi);
3369 kfree(q_vector);
3370 }
3371 }
3372
3373 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3374 {
3375 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3376 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3377 pci_disable_msix(adapter->pdev);
3378 kfree(adapter->msix_entries);
3379 adapter->msix_entries = NULL;
3380 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3381 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3382 pci_disable_msi(adapter->pdev);
3383 }
3384 return;
3385 }
3386
3387 /**
3388 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3389 * @adapter: board private structure to initialize
3390 *
3391 * We determine which interrupt scheme to use based on...
3392 * - Kernel support (MSI, MSI-X)
3393 * - which can be user-defined (via MODULE_PARAM)
3394 * - Hardware queue count (num_*_queues)
3395 * - defined by miscellaneous hardware support/features (RSS, etc.)
3396 **/
3397 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3398 {
3399 int err;
3400
3401 /* Number of supported queues */
3402 ixgbe_set_num_queues(adapter);
3403
3404 err = ixgbe_set_interrupt_capability(adapter);
3405 if (err) {
3406 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3407 goto err_set_interrupt;
3408 }
3409
3410 err = ixgbe_alloc_q_vectors(adapter);
3411 if (err) {
3412 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3413 "vectors\n");
3414 goto err_alloc_q_vectors;
3415 }
3416
3417 err = ixgbe_alloc_queues(adapter);
3418 if (err) {
3419 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3420 goto err_alloc_queues;
3421 }
3422
3423 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3424 "Tx Queue count = %u\n",
3425 (adapter->num_rx_queues > 1) ? "Enabled" :
3426 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3427
3428 set_bit(__IXGBE_DOWN, &adapter->state);
3429
3430 return 0;
3431
3432 err_alloc_queues:
3433 ixgbe_free_q_vectors(adapter);
3434 err_alloc_q_vectors:
3435 ixgbe_reset_interrupt_capability(adapter);
3436 err_set_interrupt:
3437 return err;
3438 }
3439
3440 /**
3441 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3442 * @adapter: board private structure to clear interrupt scheme on
3443 *
3444 * We go through and clear interrupt specific resources and reset the structure
3445 * to pre-load conditions
3446 **/
3447 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3448 {
3449 kfree(adapter->tx_ring);
3450 kfree(adapter->rx_ring);
3451 adapter->tx_ring = NULL;
3452 adapter->rx_ring = NULL;
3453
3454 ixgbe_free_q_vectors(adapter);
3455 ixgbe_reset_interrupt_capability(adapter);
3456 }
3457
3458 /**
3459 * ixgbe_sfp_timer - worker thread to find a missing module
3460 * @data: pointer to our adapter struct
3461 **/
3462 static void ixgbe_sfp_timer(unsigned long data)
3463 {
3464 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3465
3466 /*
3467 * Do the sfp_timer outside of interrupt context due to the
3468 * delays that sfp+ detection requires
3469 */
3470 schedule_work(&adapter->sfp_task);
3471 }
3472
3473 /**
3474 * ixgbe_sfp_task - worker thread to find a missing module
3475 * @work: pointer to work_struct containing our data
3476 **/
3477 static void ixgbe_sfp_task(struct work_struct *work)
3478 {
3479 struct ixgbe_adapter *adapter = container_of(work,
3480 struct ixgbe_adapter,
3481 sfp_task);
3482 struct ixgbe_hw *hw = &adapter->hw;
3483
3484 if ((hw->phy.type == ixgbe_phy_nl) &&
3485 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3486 s32 ret = hw->phy.ops.identify_sfp(hw);
3487 if (ret)
3488 goto reschedule;
3489 ret = hw->phy.ops.reset(hw);
3490 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3491 DPRINTK(PROBE, ERR, "failed to initialize because an "
3492 "unsupported SFP+ module type was detected.\n"
3493 "Reload the driver after installing a "
3494 "supported module.\n");
3495 unregister_netdev(adapter->netdev);
3496 } else {
3497 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3498 hw->phy.sfp_type);
3499 }
3500 /* don't need this routine any more */
3501 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3502 }
3503 return;
3504 reschedule:
3505 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3506 mod_timer(&adapter->sfp_timer,
3507 round_jiffies(jiffies + (2 * HZ)));
3508 }
3509
3510 /**
3511 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3512 * @adapter: board private structure to initialize
3513 *
3514 * ixgbe_sw_init initializes the Adapter private data structure.
3515 * Fields are initialized based on PCI device information and
3516 * OS network device settings (MTU size).
3517 **/
3518 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3519 {
3520 struct ixgbe_hw *hw = &adapter->hw;
3521 struct pci_dev *pdev = adapter->pdev;
3522 unsigned int rss;
3523 #ifdef CONFIG_IXGBE_DCB
3524 int j;
3525 struct tc_configuration *tc;
3526 #endif
3527
3528 /* PCI config space info */
3529
3530 hw->vendor_id = pdev->vendor;
3531 hw->device_id = pdev->device;
3532 hw->revision_id = pdev->revision;
3533 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3534 hw->subsystem_device_id = pdev->subsystem_device;
3535
3536 /* Set capability flags */
3537 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3538 adapter->ring_feature[RING_F_RSS].indices = rss;
3539 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3540 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3541 if (hw->mac.type == ixgbe_mac_82598EB) {
3542 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3543 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3544 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3545 } else if (hw->mac.type == ixgbe_mac_82599EB) {
3546 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3547 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3548 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
3549 #ifdef IXGBE_FCOE
3550 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
3551 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
3552 #endif /* IXGBE_FCOE */
3553 }
3554
3555 #ifdef CONFIG_IXGBE_DCB
3556 /* Configure DCB traffic classes */
3557 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3558 tc = &adapter->dcb_cfg.tc_config[j];
3559 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3560 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3561 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3562 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3563 tc->dcb_pfc = pfc_disabled;
3564 }
3565 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3566 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3567 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3568 adapter->dcb_cfg.pfc_mode_enable = false;
3569 adapter->dcb_cfg.round_robin_enable = false;
3570 adapter->dcb_set_bitmap = 0x00;
3571 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3572 adapter->ring_feature[RING_F_DCB].indices);
3573
3574 #endif
3575
3576 /* default flow control settings */
3577 hw->fc.requested_mode = ixgbe_fc_full;
3578 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
3579 #ifdef CONFIG_DCB
3580 adapter->last_lfc_mode = hw->fc.current_mode;
3581 #endif
3582 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3583 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3584 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3585 hw->fc.send_xon = true;
3586 hw->fc.disable_fc_autoneg = false;
3587
3588 /* enable itr by default in dynamic mode */
3589 adapter->itr_setting = 1;
3590 adapter->eitr_param = 20000;
3591
3592 /* set defaults for eitr in MegaBytes */
3593 adapter->eitr_low = 10;
3594 adapter->eitr_high = 20;
3595
3596 /* set default ring sizes */
3597 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3598 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3599
3600 /* initialize eeprom parameters */
3601 if (ixgbe_init_eeprom_params_generic(hw)) {
3602 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3603 return -EIO;
3604 }
3605
3606 /* enable rx csum by default */
3607 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3608
3609 set_bit(__IXGBE_DOWN, &adapter->state);
3610
3611 return 0;
3612 }
3613
3614 /**
3615 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3616 * @adapter: board private structure
3617 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3618 *
3619 * Return 0 on success, negative on failure
3620 **/
3621 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3622 struct ixgbe_ring *tx_ring)
3623 {
3624 struct pci_dev *pdev = adapter->pdev;
3625 int size;
3626
3627 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3628 tx_ring->tx_buffer_info = vmalloc(size);
3629 if (!tx_ring->tx_buffer_info)
3630 goto err;
3631 memset(tx_ring->tx_buffer_info, 0, size);
3632
3633 /* round up to nearest 4K */
3634 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3635 tx_ring->size = ALIGN(tx_ring->size, 4096);
3636
3637 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3638 &tx_ring->dma);
3639 if (!tx_ring->desc)
3640 goto err;
3641
3642 tx_ring->next_to_use = 0;
3643 tx_ring->next_to_clean = 0;
3644 tx_ring->work_limit = tx_ring->count;
3645 return 0;
3646
3647 err:
3648 vfree(tx_ring->tx_buffer_info);
3649 tx_ring->tx_buffer_info = NULL;
3650 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3651 "descriptor ring\n");
3652 return -ENOMEM;
3653 }
3654
3655 /**
3656 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3657 * @adapter: board private structure
3658 *
3659 * If this function returns with an error, then it's possible one or
3660 * more of the rings is populated (while the rest are not). It is the
3661 * callers duty to clean those orphaned rings.
3662 *
3663 * Return 0 on success, negative on failure
3664 **/
3665 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3666 {
3667 int i, err = 0;
3668
3669 for (i = 0; i < adapter->num_tx_queues; i++) {
3670 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3671 if (!err)
3672 continue;
3673 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3674 break;
3675 }
3676
3677 return err;
3678 }
3679
3680 /**
3681 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3682 * @adapter: board private structure
3683 * @rx_ring: rx descriptor ring (for a specific queue) to setup
3684 *
3685 * Returns 0 on success, negative on failure
3686 **/
3687 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3688 struct ixgbe_ring *rx_ring)
3689 {
3690 struct pci_dev *pdev = adapter->pdev;
3691 int size;
3692
3693 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3694 rx_ring->rx_buffer_info = vmalloc(size);
3695 if (!rx_ring->rx_buffer_info) {
3696 DPRINTK(PROBE, ERR,
3697 "vmalloc allocation failed for the rx desc ring\n");
3698 goto alloc_failed;
3699 }
3700 memset(rx_ring->rx_buffer_info, 0, size);
3701
3702 /* Round up to nearest 4K */
3703 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3704 rx_ring->size = ALIGN(rx_ring->size, 4096);
3705
3706 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3707
3708 if (!rx_ring->desc) {
3709 DPRINTK(PROBE, ERR,
3710 "Memory allocation failed for the rx desc ring\n");
3711 vfree(rx_ring->rx_buffer_info);
3712 goto alloc_failed;
3713 }
3714
3715 rx_ring->next_to_clean = 0;
3716 rx_ring->next_to_use = 0;
3717
3718 return 0;
3719
3720 alloc_failed:
3721 return -ENOMEM;
3722 }
3723
3724 /**
3725 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3726 * @adapter: board private structure
3727 *
3728 * If this function returns with an error, then it's possible one or
3729 * more of the rings is populated (while the rest are not). It is the
3730 * callers duty to clean those orphaned rings.
3731 *
3732 * Return 0 on success, negative on failure
3733 **/
3734
3735 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3736 {
3737 int i, err = 0;
3738
3739 for (i = 0; i < adapter->num_rx_queues; i++) {
3740 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3741 if (!err)
3742 continue;
3743 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3744 break;
3745 }
3746
3747 return err;
3748 }
3749
3750 /**
3751 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3752 * @adapter: board private structure
3753 * @tx_ring: Tx descriptor ring for a specific queue
3754 *
3755 * Free all transmit software resources
3756 **/
3757 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3758 struct ixgbe_ring *tx_ring)
3759 {
3760 struct pci_dev *pdev = adapter->pdev;
3761
3762 ixgbe_clean_tx_ring(adapter, tx_ring);
3763
3764 vfree(tx_ring->tx_buffer_info);
3765 tx_ring->tx_buffer_info = NULL;
3766
3767 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3768
3769 tx_ring->desc = NULL;
3770 }
3771
3772 /**
3773 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3774 * @adapter: board private structure
3775 *
3776 * Free all transmit software resources
3777 **/
3778 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3779 {
3780 int i;
3781
3782 for (i = 0; i < adapter->num_tx_queues; i++)
3783 if (adapter->tx_ring[i].desc)
3784 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3785 }
3786
3787 /**
3788 * ixgbe_free_rx_resources - Free Rx Resources
3789 * @adapter: board private structure
3790 * @rx_ring: ring to clean the resources from
3791 *
3792 * Free all receive software resources
3793 **/
3794 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3795 struct ixgbe_ring *rx_ring)
3796 {
3797 struct pci_dev *pdev = adapter->pdev;
3798
3799 ixgbe_clean_rx_ring(adapter, rx_ring);
3800
3801 vfree(rx_ring->rx_buffer_info);
3802 rx_ring->rx_buffer_info = NULL;
3803
3804 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3805
3806 rx_ring->desc = NULL;
3807 }
3808
3809 /**
3810 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3811 * @adapter: board private structure
3812 *
3813 * Free all receive software resources
3814 **/
3815 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3816 {
3817 int i;
3818
3819 for (i = 0; i < adapter->num_rx_queues; i++)
3820 if (adapter->rx_ring[i].desc)
3821 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3822 }
3823
3824 /**
3825 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3826 * @netdev: network interface device structure
3827 * @new_mtu: new value for maximum frame size
3828 *
3829 * Returns 0 on success, negative on failure
3830 **/
3831 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3832 {
3833 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3834 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3835
3836 /* MTU < 68 is an error and causes problems on some kernels */
3837 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3838 return -EINVAL;
3839
3840 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3841 netdev->mtu, new_mtu);
3842 /* must set new MTU before calling down or up */
3843 netdev->mtu = new_mtu;
3844
3845 if (netif_running(netdev))
3846 ixgbe_reinit_locked(adapter);
3847
3848 return 0;
3849 }
3850
3851 /**
3852 * ixgbe_open - Called when a network interface is made active
3853 * @netdev: network interface device structure
3854 *
3855 * Returns 0 on success, negative value on failure
3856 *
3857 * The open entry point is called when a network interface is made
3858 * active by the system (IFF_UP). At this point all resources needed
3859 * for transmit and receive operations are allocated, the interrupt
3860 * handler is registered with the OS, the watchdog timer is started,
3861 * and the stack is notified that the interface is ready.
3862 **/
3863 static int ixgbe_open(struct net_device *netdev)
3864 {
3865 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3866 int err;
3867
3868 /* disallow open during test */
3869 if (test_bit(__IXGBE_TESTING, &adapter->state))
3870 return -EBUSY;
3871
3872 netif_carrier_off(netdev);
3873
3874 /* allocate transmit descriptors */
3875 err = ixgbe_setup_all_tx_resources(adapter);
3876 if (err)
3877 goto err_setup_tx;
3878
3879 /* allocate receive descriptors */
3880 err = ixgbe_setup_all_rx_resources(adapter);
3881 if (err)
3882 goto err_setup_rx;
3883
3884 ixgbe_configure(adapter);
3885
3886 err = ixgbe_request_irq(adapter);
3887 if (err)
3888 goto err_req_irq;
3889
3890 err = ixgbe_up_complete(adapter);
3891 if (err)
3892 goto err_up;
3893
3894 netif_tx_start_all_queues(netdev);
3895
3896 return 0;
3897
3898 err_up:
3899 ixgbe_release_hw_control(adapter);
3900 ixgbe_free_irq(adapter);
3901 err_req_irq:
3902 err_setup_rx:
3903 ixgbe_free_all_rx_resources(adapter);
3904 err_setup_tx:
3905 ixgbe_free_all_tx_resources(adapter);
3906 ixgbe_reset(adapter);
3907
3908 return err;
3909 }
3910
3911 /**
3912 * ixgbe_close - Disables a network interface
3913 * @netdev: network interface device structure
3914 *
3915 * Returns 0, this is not allowed to fail
3916 *
3917 * The close entry point is called when an interface is de-activated
3918 * by the OS. The hardware is still under the drivers control, but
3919 * needs to be disabled. A global MAC reset is issued to stop the
3920 * hardware, and all transmit and receive resources are freed.
3921 **/
3922 static int ixgbe_close(struct net_device *netdev)
3923 {
3924 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3925
3926 ixgbe_down(adapter);
3927 ixgbe_free_irq(adapter);
3928
3929 ixgbe_free_all_tx_resources(adapter);
3930 ixgbe_free_all_rx_resources(adapter);
3931
3932 ixgbe_release_hw_control(adapter);
3933
3934 return 0;
3935 }
3936
3937 #ifdef CONFIG_PM
3938 static int ixgbe_resume(struct pci_dev *pdev)
3939 {
3940 struct net_device *netdev = pci_get_drvdata(pdev);
3941 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3942 u32 err;
3943
3944 pci_set_power_state(pdev, PCI_D0);
3945 pci_restore_state(pdev);
3946
3947 err = pci_enable_device_mem(pdev);
3948 if (err) {
3949 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3950 "suspend\n");
3951 return err;
3952 }
3953 pci_set_master(pdev);
3954
3955 pci_wake_from_d3(pdev, false);
3956
3957 err = ixgbe_init_interrupt_scheme(adapter);
3958 if (err) {
3959 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3960 "device\n");
3961 return err;
3962 }
3963
3964 ixgbe_reset(adapter);
3965
3966 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
3967
3968 if (netif_running(netdev)) {
3969 err = ixgbe_open(adapter->netdev);
3970 if (err)
3971 return err;
3972 }
3973
3974 netif_device_attach(netdev);
3975
3976 return 0;
3977 }
3978 #endif /* CONFIG_PM */
3979
3980 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
3981 {
3982 struct net_device *netdev = pci_get_drvdata(pdev);
3983 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3984 struct ixgbe_hw *hw = &adapter->hw;
3985 u32 ctrl, fctrl;
3986 u32 wufc = adapter->wol;
3987 #ifdef CONFIG_PM
3988 int retval = 0;
3989 #endif
3990
3991 netif_device_detach(netdev);
3992
3993 if (netif_running(netdev)) {
3994 ixgbe_down(adapter);
3995 ixgbe_free_irq(adapter);
3996 ixgbe_free_all_tx_resources(adapter);
3997 ixgbe_free_all_rx_resources(adapter);
3998 }
3999 ixgbe_clear_interrupt_scheme(adapter);
4000
4001 #ifdef CONFIG_PM
4002 retval = pci_save_state(pdev);
4003 if (retval)
4004 return retval;
4005
4006 #endif
4007 if (wufc) {
4008 ixgbe_set_rx_mode(netdev);
4009
4010 /* turn on all-multi mode if wake on multicast is enabled */
4011 if (wufc & IXGBE_WUFC_MC) {
4012 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4013 fctrl |= IXGBE_FCTRL_MPE;
4014 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4015 }
4016
4017 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4018 ctrl |= IXGBE_CTRL_GIO_DIS;
4019 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4020
4021 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4022 } else {
4023 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4024 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4025 }
4026
4027 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4028 pci_wake_from_d3(pdev, true);
4029 else
4030 pci_wake_from_d3(pdev, false);
4031
4032 *enable_wake = !!wufc;
4033
4034 ixgbe_release_hw_control(adapter);
4035
4036 pci_disable_device(pdev);
4037
4038 return 0;
4039 }
4040
4041 #ifdef CONFIG_PM
4042 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4043 {
4044 int retval;
4045 bool wake;
4046
4047 retval = __ixgbe_shutdown(pdev, &wake);
4048 if (retval)
4049 return retval;
4050
4051 if (wake) {
4052 pci_prepare_to_sleep(pdev);
4053 } else {
4054 pci_wake_from_d3(pdev, false);
4055 pci_set_power_state(pdev, PCI_D3hot);
4056 }
4057
4058 return 0;
4059 }
4060 #endif /* CONFIG_PM */
4061
4062 static void ixgbe_shutdown(struct pci_dev *pdev)
4063 {
4064 bool wake;
4065
4066 __ixgbe_shutdown(pdev, &wake);
4067
4068 if (system_state == SYSTEM_POWER_OFF) {
4069 pci_wake_from_d3(pdev, wake);
4070 pci_set_power_state(pdev, PCI_D3hot);
4071 }
4072 }
4073
4074 /**
4075 * ixgbe_update_stats - Update the board statistics counters.
4076 * @adapter: board private structure
4077 **/
4078 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4079 {
4080 struct ixgbe_hw *hw = &adapter->hw;
4081 u64 total_mpc = 0;
4082 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4083
4084 if (hw->mac.type == ixgbe_mac_82599EB) {
4085 u64 rsc_count = 0;
4086 for (i = 0; i < 16; i++)
4087 adapter->hw_rx_no_dma_resources +=
4088 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4089 for (i = 0; i < adapter->num_rx_queues; i++)
4090 rsc_count += adapter->rx_ring[i].rsc_count;
4091 adapter->rsc_count = rsc_count;
4092 }
4093
4094 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4095 for (i = 0; i < 8; i++) {
4096 /* for packet buffers not used, the register should read 0 */
4097 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4098 missed_rx += mpc;
4099 adapter->stats.mpc[i] += mpc;
4100 total_mpc += adapter->stats.mpc[i];
4101 if (hw->mac.type == ixgbe_mac_82598EB)
4102 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4103 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4104 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4105 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4106 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4107 if (hw->mac.type == ixgbe_mac_82599EB) {
4108 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4109 IXGBE_PXONRXCNT(i));
4110 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4111 IXGBE_PXOFFRXCNT(i));
4112 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4113 } else {
4114 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4115 IXGBE_PXONRXC(i));
4116 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4117 IXGBE_PXOFFRXC(i));
4118 }
4119 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4120 IXGBE_PXONTXC(i));
4121 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4122 IXGBE_PXOFFTXC(i));
4123 }
4124 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4125 /* work around hardware counting issue */
4126 adapter->stats.gprc -= missed_rx;
4127
4128 /* 82598 hardware only has a 32 bit counter in the high register */
4129 if (hw->mac.type == ixgbe_mac_82599EB) {
4130 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4131 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4132 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4133 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4134 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4135 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4136 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4137 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4138 #ifdef IXGBE_FCOE
4139 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4140 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4141 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4142 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4143 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4144 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4145 #endif /* IXGBE_FCOE */
4146 } else {
4147 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4148 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4149 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4150 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4151 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4152 }
4153 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4154 adapter->stats.bprc += bprc;
4155 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4156 if (hw->mac.type == ixgbe_mac_82598EB)
4157 adapter->stats.mprc -= bprc;
4158 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4159 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4160 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4161 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4162 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4163 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4164 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4165 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4166 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4167 adapter->stats.lxontxc += lxon;
4168 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4169 adapter->stats.lxofftxc += lxoff;
4170 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4171 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4172 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4173 /*
4174 * 82598 errata - tx of flow control packets is included in tx counters
4175 */
4176 xon_off_tot = lxon + lxoff;
4177 adapter->stats.gptc -= xon_off_tot;
4178 adapter->stats.mptc -= xon_off_tot;
4179 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4180 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4181 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4182 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4183 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4184 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4185 adapter->stats.ptc64 -= xon_off_tot;
4186 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4187 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4188 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4189 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4190 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4191 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4192
4193 /* Fill out the OS statistics structure */
4194 adapter->net_stats.multicast = adapter->stats.mprc;
4195
4196 /* Rx Errors */
4197 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4198 adapter->stats.rlec;
4199 adapter->net_stats.rx_dropped = 0;
4200 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4201 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4202 adapter->net_stats.rx_missed_errors = total_mpc;
4203 }
4204
4205 /**
4206 * ixgbe_watchdog - Timer Call-back
4207 * @data: pointer to adapter cast into an unsigned long
4208 **/
4209 static void ixgbe_watchdog(unsigned long data)
4210 {
4211 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4212 struct ixgbe_hw *hw = &adapter->hw;
4213
4214 /* Do the watchdog outside of interrupt context due to the lovely
4215 * delays that some of the newer hardware requires */
4216 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
4217 u64 eics = 0;
4218 int i;
4219
4220 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
4221 eics |= ((u64)1 << i);
4222
4223 /* Cause software interrupt to ensure rx rings are cleaned */
4224 switch (hw->mac.type) {
4225 case ixgbe_mac_82598EB:
4226 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4227 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
4228 } else {
4229 /*
4230 * for legacy and MSI interrupts don't set any
4231 * bits that are enabled for EIAM, because this
4232 * operation would set *both* EIMS and EICS for
4233 * any bit in EIAM
4234 */
4235 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4236 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4237 }
4238 break;
4239 case ixgbe_mac_82599EB:
4240 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4241 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0),
4242 (u32)(eics & 0xFFFFFFFF));
4243 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
4244 (u32)(eics >> 32));
4245 } else {
4246 /*
4247 * for legacy and MSI interrupts don't set any
4248 * bits that are enabled for EIAM, because this
4249 * operation would set *both* EIMS and EICS for
4250 * any bit in EIAM
4251 */
4252 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4253 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4254 }
4255 break;
4256 default:
4257 break;
4258 }
4259 /* Reset the timer */
4260 mod_timer(&adapter->watchdog_timer,
4261 round_jiffies(jiffies + 2 * HZ));
4262 }
4263
4264 schedule_work(&adapter->watchdog_task);
4265 }
4266
4267 /**
4268 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4269 * @work: pointer to work_struct containing our data
4270 **/
4271 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4272 {
4273 struct ixgbe_adapter *adapter = container_of(work,
4274 struct ixgbe_adapter,
4275 multispeed_fiber_task);
4276 struct ixgbe_hw *hw = &adapter->hw;
4277 u32 autoneg;
4278
4279 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4280 if (hw->mac.ops.get_link_capabilities)
4281 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4282 &hw->mac.autoneg);
4283 if (hw->mac.ops.setup_link_speed)
4284 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4285 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4286 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4287 }
4288
4289 /**
4290 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4291 * @work: pointer to work_struct containing our data
4292 **/
4293 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4294 {
4295 struct ixgbe_adapter *adapter = container_of(work,
4296 struct ixgbe_adapter,
4297 sfp_config_module_task);
4298 struct ixgbe_hw *hw = &adapter->hw;
4299 u32 err;
4300
4301 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4302 err = hw->phy.ops.identify_sfp(hw);
4303 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4304 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4305 ixgbe_down(adapter);
4306 return;
4307 }
4308 hw->mac.ops.setup_sfp(hw);
4309
4310 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4311 /* This will also work for DA Twinax connections */
4312 schedule_work(&adapter->multispeed_fiber_task);
4313 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4314 }
4315
4316 /**
4317 * ixgbe_watchdog_task - worker thread to bring link up
4318 * @work: pointer to work_struct containing our data
4319 **/
4320 static void ixgbe_watchdog_task(struct work_struct *work)
4321 {
4322 struct ixgbe_adapter *adapter = container_of(work,
4323 struct ixgbe_adapter,
4324 watchdog_task);
4325 struct net_device *netdev = adapter->netdev;
4326 struct ixgbe_hw *hw = &adapter->hw;
4327 u32 link_speed = adapter->link_speed;
4328 bool link_up = adapter->link_up;
4329 int i;
4330 struct ixgbe_ring *tx_ring;
4331 int some_tx_pending = 0;
4332
4333 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4334
4335 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4336 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4337 if (link_up) {
4338 #ifdef CONFIG_DCB
4339 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4340 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4341 hw->mac.ops.setup_fc(hw, i);
4342 } else {
4343 hw->mac.ops.setup_fc(hw, 0);
4344 }
4345 #else
4346 hw->mac.ops.setup_fc(hw, 0);
4347 #endif
4348 }
4349
4350 if (link_up ||
4351 time_after(jiffies, (adapter->link_check_timeout +
4352 IXGBE_TRY_LINK_TIMEOUT))) {
4353 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4354 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4355 }
4356 adapter->link_up = link_up;
4357 adapter->link_speed = link_speed;
4358 }
4359
4360 if (link_up) {
4361 if (!netif_carrier_ok(netdev)) {
4362 bool flow_rx, flow_tx;
4363
4364 if (hw->mac.type == ixgbe_mac_82599EB) {
4365 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4366 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4367 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4368 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4369 } else {
4370 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4371 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4372 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4373 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4374 }
4375
4376 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4377 "Flow Control: %s\n",
4378 netdev->name,
4379 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4380 "10 Gbps" :
4381 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4382 "1 Gbps" : "unknown speed")),
4383 ((flow_rx && flow_tx) ? "RX/TX" :
4384 (flow_rx ? "RX" :
4385 (flow_tx ? "TX" : "None"))));
4386
4387 netif_carrier_on(netdev);
4388 } else {
4389 /* Force detection of hung controller */
4390 adapter->detect_tx_hung = true;
4391 }
4392 } else {
4393 adapter->link_up = false;
4394 adapter->link_speed = 0;
4395 if (netif_carrier_ok(netdev)) {
4396 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4397 netdev->name);
4398 netif_carrier_off(netdev);
4399 }
4400 }
4401
4402 if (!netif_carrier_ok(netdev)) {
4403 for (i = 0; i < adapter->num_tx_queues; i++) {
4404 tx_ring = &adapter->tx_ring[i];
4405 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4406 some_tx_pending = 1;
4407 break;
4408 }
4409 }
4410
4411 if (some_tx_pending) {
4412 /* We've lost link, so the controller stops DMA,
4413 * but we've got queued Tx work that's never going
4414 * to get done, so reset controller to flush Tx.
4415 * (Do the reset outside of interrupt context).
4416 */
4417 schedule_work(&adapter->reset_task);
4418 }
4419 }
4420
4421 ixgbe_update_stats(adapter);
4422 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4423 }
4424
4425 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4426 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4427 u32 tx_flags, u8 *hdr_len)
4428 {
4429 struct ixgbe_adv_tx_context_desc *context_desc;
4430 unsigned int i;
4431 int err;
4432 struct ixgbe_tx_buffer *tx_buffer_info;
4433 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4434 u32 mss_l4len_idx, l4len;
4435
4436 if (skb_is_gso(skb)) {
4437 if (skb_header_cloned(skb)) {
4438 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4439 if (err)
4440 return err;
4441 }
4442 l4len = tcp_hdrlen(skb);
4443 *hdr_len += l4len;
4444
4445 if (skb->protocol == htons(ETH_P_IP)) {
4446 struct iphdr *iph = ip_hdr(skb);
4447 iph->tot_len = 0;
4448 iph->check = 0;
4449 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4450 iph->daddr, 0,
4451 IPPROTO_TCP,
4452 0);
4453 adapter->hw_tso_ctxt++;
4454 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4455 ipv6_hdr(skb)->payload_len = 0;
4456 tcp_hdr(skb)->check =
4457 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4458 &ipv6_hdr(skb)->daddr,
4459 0, IPPROTO_TCP, 0);
4460 adapter->hw_tso6_ctxt++;
4461 }
4462
4463 i = tx_ring->next_to_use;
4464
4465 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4466 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4467
4468 /* VLAN MACLEN IPLEN */
4469 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4470 vlan_macip_lens |=
4471 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4472 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4473 IXGBE_ADVTXD_MACLEN_SHIFT);
4474 *hdr_len += skb_network_offset(skb);
4475 vlan_macip_lens |=
4476 (skb_transport_header(skb) - skb_network_header(skb));
4477 *hdr_len +=
4478 (skb_transport_header(skb) - skb_network_header(skb));
4479 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4480 context_desc->seqnum_seed = 0;
4481
4482 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4483 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4484 IXGBE_ADVTXD_DTYP_CTXT);
4485
4486 if (skb->protocol == htons(ETH_P_IP))
4487 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4488 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4489 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4490
4491 /* MSS L4LEN IDX */
4492 mss_l4len_idx =
4493 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4494 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4495 /* use index 1 for TSO */
4496 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4497 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4498
4499 tx_buffer_info->time_stamp = jiffies;
4500 tx_buffer_info->next_to_watch = i;
4501
4502 i++;
4503 if (i == tx_ring->count)
4504 i = 0;
4505 tx_ring->next_to_use = i;
4506
4507 return true;
4508 }
4509 return false;
4510 }
4511
4512 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4513 struct ixgbe_ring *tx_ring,
4514 struct sk_buff *skb, u32 tx_flags)
4515 {
4516 struct ixgbe_adv_tx_context_desc *context_desc;
4517 unsigned int i;
4518 struct ixgbe_tx_buffer *tx_buffer_info;
4519 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4520
4521 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4522 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4523 i = tx_ring->next_to_use;
4524 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4525 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4526
4527 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4528 vlan_macip_lens |=
4529 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4530 vlan_macip_lens |= (skb_network_offset(skb) <<
4531 IXGBE_ADVTXD_MACLEN_SHIFT);
4532 if (skb->ip_summed == CHECKSUM_PARTIAL)
4533 vlan_macip_lens |= (skb_transport_header(skb) -
4534 skb_network_header(skb));
4535
4536 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4537 context_desc->seqnum_seed = 0;
4538
4539 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4540 IXGBE_ADVTXD_DTYP_CTXT);
4541
4542 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4543 switch (skb->protocol) {
4544 case cpu_to_be16(ETH_P_IP):
4545 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4546 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4547 type_tucmd_mlhl |=
4548 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4549 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4550 type_tucmd_mlhl |=
4551 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4552 break;
4553 case cpu_to_be16(ETH_P_IPV6):
4554 /* XXX what about other V6 headers?? */
4555 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4556 type_tucmd_mlhl |=
4557 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4558 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4559 type_tucmd_mlhl |=
4560 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4561 break;
4562 default:
4563 if (unlikely(net_ratelimit())) {
4564 DPRINTK(PROBE, WARNING,
4565 "partial checksum but proto=%x!\n",
4566 skb->protocol);
4567 }
4568 break;
4569 }
4570 }
4571
4572 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4573 /* use index zero for tx checksum offload */
4574 context_desc->mss_l4len_idx = 0;
4575
4576 tx_buffer_info->time_stamp = jiffies;
4577 tx_buffer_info->next_to_watch = i;
4578
4579 adapter->hw_csum_tx_good++;
4580 i++;
4581 if (i == tx_ring->count)
4582 i = 0;
4583 tx_ring->next_to_use = i;
4584
4585 return true;
4586 }
4587
4588 return false;
4589 }
4590
4591 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4592 struct ixgbe_ring *tx_ring,
4593 struct sk_buff *skb, u32 tx_flags,
4594 unsigned int first)
4595 {
4596 struct ixgbe_tx_buffer *tx_buffer_info;
4597 unsigned int len;
4598 unsigned int total = skb->len;
4599 unsigned int offset = 0, size, count = 0, i;
4600 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4601 unsigned int f;
4602 dma_addr_t *map;
4603
4604 i = tx_ring->next_to_use;
4605
4606 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4607 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4608 return 0;
4609 }
4610
4611 map = skb_shinfo(skb)->dma_maps;
4612
4613 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4614 /* excluding fcoe_crc_eof for FCoE */
4615 total -= sizeof(struct fcoe_crc_eof);
4616
4617 len = min(skb_headlen(skb), total);
4618 while (len) {
4619 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4620 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4621
4622 tx_buffer_info->length = size;
4623 tx_buffer_info->dma = map[0] + offset;
4624 tx_buffer_info->time_stamp = jiffies;
4625 tx_buffer_info->next_to_watch = i;
4626
4627 len -= size;
4628 total -= size;
4629 offset += size;
4630 count++;
4631
4632 if (len) {
4633 i++;
4634 if (i == tx_ring->count)
4635 i = 0;
4636 }
4637 }
4638
4639 for (f = 0; f < nr_frags; f++) {
4640 struct skb_frag_struct *frag;
4641
4642 frag = &skb_shinfo(skb)->frags[f];
4643 len = min((unsigned int)frag->size, total);
4644 offset = 0;
4645
4646 while (len) {
4647 i++;
4648 if (i == tx_ring->count)
4649 i = 0;
4650
4651 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4652 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4653
4654 tx_buffer_info->length = size;
4655 tx_buffer_info->dma = map[f + 1] + offset;
4656 tx_buffer_info->time_stamp = jiffies;
4657 tx_buffer_info->next_to_watch = i;
4658
4659 len -= size;
4660 total -= size;
4661 offset += size;
4662 count++;
4663 }
4664 if (total == 0)
4665 break;
4666 }
4667
4668 tx_ring->tx_buffer_info[i].skb = skb;
4669 tx_ring->tx_buffer_info[first].next_to_watch = i;
4670
4671 return count;
4672 }
4673
4674 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4675 struct ixgbe_ring *tx_ring,
4676 int tx_flags, int count, u32 paylen, u8 hdr_len)
4677 {
4678 union ixgbe_adv_tx_desc *tx_desc = NULL;
4679 struct ixgbe_tx_buffer *tx_buffer_info;
4680 u32 olinfo_status = 0, cmd_type_len = 0;
4681 unsigned int i;
4682 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4683
4684 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4685
4686 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4687
4688 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4689 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4690
4691 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4692 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4693
4694 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4695 IXGBE_ADVTXD_POPTS_SHIFT;
4696
4697 /* use index 1 context for tso */
4698 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4699 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4700 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4701 IXGBE_ADVTXD_POPTS_SHIFT;
4702
4703 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4704 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4705 IXGBE_ADVTXD_POPTS_SHIFT;
4706
4707 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4708 olinfo_status |= IXGBE_ADVTXD_CC;
4709 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4710 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4711 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4712 }
4713
4714 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4715
4716 i = tx_ring->next_to_use;
4717 while (count--) {
4718 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4719 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4720 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4721 tx_desc->read.cmd_type_len =
4722 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4723 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4724 i++;
4725 if (i == tx_ring->count)
4726 i = 0;
4727 }
4728
4729 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4730
4731 /*
4732 * Force memory writes to complete before letting h/w
4733 * know there are new descriptors to fetch. (Only
4734 * applicable for weak-ordered memory model archs,
4735 * such as IA-64).
4736 */
4737 wmb();
4738
4739 tx_ring->next_to_use = i;
4740 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4741 }
4742
4743 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
4744 struct ixgbe_ring *tx_ring, int size)
4745 {
4746 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4747
4748 netif_stop_subqueue(netdev, tx_ring->queue_index);
4749 /* Herbert's original patch had:
4750 * smp_mb__after_netif_stop_queue();
4751 * but since that doesn't exist yet, just open code it. */
4752 smp_mb();
4753
4754 /* We need to check again in a case another CPU has just
4755 * made room available. */
4756 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4757 return -EBUSY;
4758
4759 /* A reprieve! - use start_queue because it doesn't call schedule */
4760 netif_start_subqueue(netdev, tx_ring->queue_index);
4761 ++adapter->restart_queue;
4762 return 0;
4763 }
4764
4765 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
4766 struct ixgbe_ring *tx_ring, int size)
4767 {
4768 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4769 return 0;
4770 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4771 }
4772
4773 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4774 {
4775 struct ixgbe_adapter *adapter = netdev_priv(dev);
4776
4777 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4778 return 0; /* All traffic should default to class 0 */
4779
4780 return skb_tx_hash(dev, skb);
4781 }
4782
4783 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4784 {
4785 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4786 struct ixgbe_ring *tx_ring;
4787 unsigned int first;
4788 unsigned int tx_flags = 0;
4789 u8 hdr_len = 0;
4790 int r_idx = 0, tso;
4791 int count = 0;
4792 unsigned int f;
4793
4794 r_idx = skb->queue_mapping;
4795 tx_ring = &adapter->tx_ring[r_idx];
4796
4797 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4798 tx_flags |= vlan_tx_tag_get(skb);
4799 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4800 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4801 tx_flags |= (skb->queue_mapping << 13);
4802 }
4803 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4804 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4805 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4806 tx_flags |= (skb->queue_mapping << 13);
4807 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4808 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4809 }
4810
4811 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4812 (skb->protocol == htons(ETH_P_FCOE)))
4813 tx_flags |= IXGBE_TX_FLAGS_FCOE;
4814
4815 /* four things can cause us to need a context descriptor */
4816 if (skb_is_gso(skb) ||
4817 (skb->ip_summed == CHECKSUM_PARTIAL) ||
4818 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
4819 (tx_flags & IXGBE_TX_FLAGS_FCOE))
4820 count++;
4821
4822 count += TXD_USE_COUNT(skb_headlen(skb));
4823 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4824 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4825
4826 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
4827 adapter->tx_busy++;
4828 return NETDEV_TX_BUSY;
4829 }
4830
4831 first = tx_ring->next_to_use;
4832 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4833 #ifdef IXGBE_FCOE
4834 /* setup tx offload for FCoE */
4835 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4836 if (tso < 0) {
4837 dev_kfree_skb_any(skb);
4838 return NETDEV_TX_OK;
4839 }
4840 if (tso)
4841 tx_flags |= IXGBE_TX_FLAGS_FSO;
4842 #endif /* IXGBE_FCOE */
4843 } else {
4844 if (skb->protocol == htons(ETH_P_IP))
4845 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4846 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4847 if (tso < 0) {
4848 dev_kfree_skb_any(skb);
4849 return NETDEV_TX_OK;
4850 }
4851
4852 if (tso)
4853 tx_flags |= IXGBE_TX_FLAGS_TSO;
4854 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4855 (skb->ip_summed == CHECKSUM_PARTIAL))
4856 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4857 }
4858
4859 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
4860 if (count) {
4861 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4862 hdr_len);
4863 netdev->trans_start = jiffies;
4864 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
4865
4866 } else {
4867 dev_kfree_skb_any(skb);
4868 tx_ring->tx_buffer_info[first].time_stamp = 0;
4869 tx_ring->next_to_use = first;
4870 }
4871
4872 return NETDEV_TX_OK;
4873 }
4874
4875 /**
4876 * ixgbe_get_stats - Get System Network Statistics
4877 * @netdev: network interface device structure
4878 *
4879 * Returns the address of the device statistics structure.
4880 * The statistics are actually updated from the timer callback.
4881 **/
4882 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4883 {
4884 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4885
4886 /* only return the current stats */
4887 return &adapter->net_stats;
4888 }
4889
4890 /**
4891 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4892 * @netdev: network interface device structure
4893 * @p: pointer to an address structure
4894 *
4895 * Returns 0 on success, negative on failure
4896 **/
4897 static int ixgbe_set_mac(struct net_device *netdev, void *p)
4898 {
4899 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4900 struct ixgbe_hw *hw = &adapter->hw;
4901 struct sockaddr *addr = p;
4902
4903 if (!is_valid_ether_addr(addr->sa_data))
4904 return -EADDRNOTAVAIL;
4905
4906 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4907 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4908
4909 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4910
4911 return 0;
4912 }
4913
4914 static int
4915 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
4916 {
4917 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4918 struct ixgbe_hw *hw = &adapter->hw;
4919 u16 value;
4920 int rc;
4921
4922 if (prtad != hw->phy.mdio.prtad)
4923 return -EINVAL;
4924 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
4925 if (!rc)
4926 rc = value;
4927 return rc;
4928 }
4929
4930 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
4931 u16 addr, u16 value)
4932 {
4933 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4934 struct ixgbe_hw *hw = &adapter->hw;
4935
4936 if (prtad != hw->phy.mdio.prtad)
4937 return -EINVAL;
4938 return hw->phy.ops.write_reg(hw, addr, devad, value);
4939 }
4940
4941 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
4942 {
4943 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4944
4945 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
4946 }
4947
4948 /**
4949 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
4950 * netdev->dev_addr_list
4951 * @netdev: network interface device structure
4952 *
4953 * Returns non-zero on failure
4954 **/
4955 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
4956 {
4957 int err = 0;
4958 struct ixgbe_adapter *adapter = netdev_priv(dev);
4959 struct ixgbe_mac_info *mac = &adapter->hw.mac;
4960
4961 if (is_valid_ether_addr(mac->san_addr)) {
4962 rtnl_lock();
4963 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
4964 rtnl_unlock();
4965 }
4966 return err;
4967 }
4968
4969 /**
4970 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
4971 * netdev->dev_addr_list
4972 * @netdev: network interface device structure
4973 *
4974 * Returns non-zero on failure
4975 **/
4976 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
4977 {
4978 int err = 0;
4979 struct ixgbe_adapter *adapter = netdev_priv(dev);
4980 struct ixgbe_mac_info *mac = &adapter->hw.mac;
4981
4982 if (is_valid_ether_addr(mac->san_addr)) {
4983 rtnl_lock();
4984 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
4985 rtnl_unlock();
4986 }
4987 return err;
4988 }
4989
4990 #ifdef CONFIG_NET_POLL_CONTROLLER
4991 /*
4992 * Polling 'interrupt' - used by things like netconsole to send skbs
4993 * without having to re-enable interrupts. It's not called while
4994 * the interrupt routine is executing.
4995 */
4996 static void ixgbe_netpoll(struct net_device *netdev)
4997 {
4998 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4999
5000 disable_irq(adapter->pdev->irq);
5001 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5002 ixgbe_intr(adapter->pdev->irq, netdev);
5003 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5004 enable_irq(adapter->pdev->irq);
5005 }
5006 #endif
5007
5008 static const struct net_device_ops ixgbe_netdev_ops = {
5009 .ndo_open = ixgbe_open,
5010 .ndo_stop = ixgbe_close,
5011 .ndo_start_xmit = ixgbe_xmit_frame,
5012 .ndo_select_queue = ixgbe_select_queue,
5013 .ndo_get_stats = ixgbe_get_stats,
5014 .ndo_set_rx_mode = ixgbe_set_rx_mode,
5015 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5016 .ndo_validate_addr = eth_validate_addr,
5017 .ndo_set_mac_address = ixgbe_set_mac,
5018 .ndo_change_mtu = ixgbe_change_mtu,
5019 .ndo_tx_timeout = ixgbe_tx_timeout,
5020 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5021 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5022 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
5023 .ndo_do_ioctl = ixgbe_ioctl,
5024 #ifdef CONFIG_NET_POLL_CONTROLLER
5025 .ndo_poll_controller = ixgbe_netpoll,
5026 #endif
5027 #ifdef IXGBE_FCOE
5028 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5029 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5030 #endif /* IXGBE_FCOE */
5031 };
5032
5033 /**
5034 * ixgbe_probe - Device Initialization Routine
5035 * @pdev: PCI device information struct
5036 * @ent: entry in ixgbe_pci_tbl
5037 *
5038 * Returns 0 on success, negative on failure
5039 *
5040 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5041 * The OS initialization, configuring of the adapter private structure,
5042 * and a hardware reset occur.
5043 **/
5044 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5045 const struct pci_device_id *ent)
5046 {
5047 struct net_device *netdev;
5048 struct ixgbe_adapter *adapter = NULL;
5049 struct ixgbe_hw *hw;
5050 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5051 static int cards_found;
5052 int i, err, pci_using_dac;
5053 #ifdef IXGBE_FCOE
5054 u16 device_caps;
5055 #endif
5056 u32 part_num, eec;
5057
5058 err = pci_enable_device_mem(pdev);
5059 if (err)
5060 return err;
5061
5062 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5063 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5064 pci_using_dac = 1;
5065 } else {
5066 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5067 if (err) {
5068 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5069 if (err) {
5070 dev_err(&pdev->dev, "No usable DMA "
5071 "configuration, aborting\n");
5072 goto err_dma;
5073 }
5074 }
5075 pci_using_dac = 0;
5076 }
5077
5078 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5079 IORESOURCE_MEM), ixgbe_driver_name);
5080 if (err) {
5081 dev_err(&pdev->dev,
5082 "pci_request_selected_regions failed 0x%x\n", err);
5083 goto err_pci_reg;
5084 }
5085
5086 err = pci_enable_pcie_error_reporting(pdev);
5087 if (err) {
5088 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5089 "0x%x\n", err);
5090 /* non-fatal, continue */
5091 }
5092
5093 pci_set_master(pdev);
5094 pci_save_state(pdev);
5095
5096 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5097 if (!netdev) {
5098 err = -ENOMEM;
5099 goto err_alloc_etherdev;
5100 }
5101
5102 SET_NETDEV_DEV(netdev, &pdev->dev);
5103
5104 pci_set_drvdata(pdev, netdev);
5105 adapter = netdev_priv(netdev);
5106
5107 adapter->netdev = netdev;
5108 adapter->pdev = pdev;
5109 hw = &adapter->hw;
5110 hw->back = adapter;
5111 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5112
5113 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5114 pci_resource_len(pdev, 0));
5115 if (!hw->hw_addr) {
5116 err = -EIO;
5117 goto err_ioremap;
5118 }
5119
5120 for (i = 1; i <= 5; i++) {
5121 if (pci_resource_len(pdev, i) == 0)
5122 continue;
5123 }
5124
5125 netdev->netdev_ops = &ixgbe_netdev_ops;
5126 ixgbe_set_ethtool_ops(netdev);
5127 netdev->watchdog_timeo = 5 * HZ;
5128 strcpy(netdev->name, pci_name(pdev));
5129
5130 adapter->bd_number = cards_found;
5131
5132 /* Setup hw api */
5133 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5134 hw->mac.type = ii->mac;
5135
5136 /* EEPROM */
5137 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5138 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5139 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5140 if (!(eec & (1 << 8)))
5141 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5142
5143 /* PHY */
5144 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5145 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5146 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5147 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5148 hw->phy.mdio.mmds = 0;
5149 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5150 hw->phy.mdio.dev = netdev;
5151 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5152 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5153
5154 /* set up this timer and work struct before calling get_invariants
5155 * which might start the timer
5156 */
5157 init_timer(&adapter->sfp_timer);
5158 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5159 adapter->sfp_timer.data = (unsigned long) adapter;
5160
5161 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5162
5163 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5164 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5165
5166 /* a new SFP+ module arrival, called from GPI SDP2 context */
5167 INIT_WORK(&adapter->sfp_config_module_task,
5168 ixgbe_sfp_config_module_task);
5169
5170 err = ii->get_invariants(hw);
5171 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5172 /* start a kernel thread to watch for a module to arrive */
5173 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5174 mod_timer(&adapter->sfp_timer,
5175 round_jiffies(jiffies + (2 * HZ)));
5176 err = 0;
5177 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5178 DPRINTK(PROBE, ERR, "failed to load because an "
5179 "unsupported SFP+ module type was detected.\n");
5180 goto err_hw_init;
5181 } else if (err) {
5182 goto err_hw_init;
5183 }
5184
5185 /* setup the private structure */
5186 err = ixgbe_sw_init(adapter);
5187 if (err)
5188 goto err_sw_init;
5189
5190 /*
5191 * If there is a fan on this device and it has failed log the
5192 * failure.
5193 */
5194 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5195 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5196 if (esdp & IXGBE_ESDP_SDP1)
5197 DPRINTK(PROBE, CRIT,
5198 "Fan has stopped, replace the adapter\n");
5199 }
5200
5201 /* reset_hw fills in the perm_addr as well */
5202 err = hw->mac.ops.reset_hw(hw);
5203 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5204 dev_err(&adapter->pdev->dev, "failed to load because an "
5205 "unsupported SFP+ module type was detected.\n");
5206 goto err_sw_init;
5207 } else if (err) {
5208 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5209 goto err_sw_init;
5210 }
5211
5212 netdev->features = NETIF_F_SG |
5213 NETIF_F_IP_CSUM |
5214 NETIF_F_HW_VLAN_TX |
5215 NETIF_F_HW_VLAN_RX |
5216 NETIF_F_HW_VLAN_FILTER;
5217
5218 netdev->features |= NETIF_F_IPV6_CSUM;
5219 netdev->features |= NETIF_F_TSO;
5220 netdev->features |= NETIF_F_TSO6;
5221 netdev->features |= NETIF_F_GRO;
5222
5223 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5224 netdev->features |= NETIF_F_SCTP_CSUM;
5225
5226 netdev->vlan_features |= NETIF_F_TSO;
5227 netdev->vlan_features |= NETIF_F_TSO6;
5228 netdev->vlan_features |= NETIF_F_IP_CSUM;
5229 netdev->vlan_features |= NETIF_F_SG;
5230
5231 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5232 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5233
5234 #ifdef CONFIG_IXGBE_DCB
5235 netdev->dcbnl_ops = &dcbnl_ops;
5236 #endif
5237
5238 #ifdef IXGBE_FCOE
5239 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5240 if (hw->mac.ops.get_device_caps) {
5241 hw->mac.ops.get_device_caps(hw, &device_caps);
5242 if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) {
5243 netdev->features |= NETIF_F_FCOE_CRC;
5244 netdev->features |= NETIF_F_FSO;
5245 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
5246 } else {
5247 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5248 }
5249 }
5250 }
5251 #endif /* IXGBE_FCOE */
5252 if (pci_using_dac)
5253 netdev->features |= NETIF_F_HIGHDMA;
5254
5255 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
5256 netdev->features |= NETIF_F_LRO;
5257
5258 /* make sure the EEPROM is good */
5259 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5260 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5261 err = -EIO;
5262 goto err_eeprom;
5263 }
5264
5265 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5266 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5267
5268 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5269 dev_err(&pdev->dev, "invalid MAC address\n");
5270 err = -EIO;
5271 goto err_eeprom;
5272 }
5273
5274 init_timer(&adapter->watchdog_timer);
5275 adapter->watchdog_timer.function = &ixgbe_watchdog;
5276 adapter->watchdog_timer.data = (unsigned long)adapter;
5277
5278 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5279 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5280
5281 err = ixgbe_init_interrupt_scheme(adapter);
5282 if (err)
5283 goto err_sw_init;
5284
5285 switch (pdev->device) {
5286 case IXGBE_DEV_ID_82599_KX4:
5287 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5288 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5289 break;
5290 default:
5291 adapter->wol = 0;
5292 break;
5293 }
5294 device_init_wakeup(&adapter->pdev->dev, true);
5295 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5296
5297 /* pick up the PCI bus settings for reporting later */
5298 hw->mac.ops.get_bus_info(hw);
5299
5300 /* print bus type/speed/width info */
5301 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5302 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5303 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5304 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5305 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5306 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5307 "Unknown"),
5308 netdev->dev_addr);
5309 ixgbe_read_pba_num_generic(hw, &part_num);
5310 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5311 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5312 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5313 (part_num >> 8), (part_num & 0xff));
5314 else
5315 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5316 hw->mac.type, hw->phy.type,
5317 (part_num >> 8), (part_num & 0xff));
5318
5319 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5320 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5321 "this card is not sufficient for optimal "
5322 "performance.\n");
5323 dev_warn(&pdev->dev, "For optimal performance a x8 "
5324 "PCI-Express slot is required.\n");
5325 }
5326
5327 /* save off EEPROM version number */
5328 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5329
5330 /* reset the hardware with the new settings */
5331 hw->mac.ops.start_hw(hw);
5332
5333 strcpy(netdev->name, "eth%d");
5334 err = register_netdev(netdev);
5335 if (err)
5336 goto err_register;
5337
5338 /* carrier off reporting is important to ethtool even BEFORE open */
5339 netif_carrier_off(netdev);
5340
5341 #ifdef CONFIG_IXGBE_DCA
5342 if (dca_add_requester(&pdev->dev) == 0) {
5343 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5344 ixgbe_setup_dca(adapter);
5345 }
5346 #endif
5347 /* add san mac addr to netdev */
5348 ixgbe_add_sanmac_netdev(netdev);
5349
5350 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5351 cards_found++;
5352 return 0;
5353
5354 err_register:
5355 ixgbe_release_hw_control(adapter);
5356 err_hw_init:
5357 ixgbe_clear_interrupt_scheme(adapter);
5358 err_sw_init:
5359 err_eeprom:
5360 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5361 del_timer_sync(&adapter->sfp_timer);
5362 cancel_work_sync(&adapter->sfp_task);
5363 cancel_work_sync(&adapter->multispeed_fiber_task);
5364 cancel_work_sync(&adapter->sfp_config_module_task);
5365 iounmap(hw->hw_addr);
5366 err_ioremap:
5367 free_netdev(netdev);
5368 err_alloc_etherdev:
5369 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5370 IORESOURCE_MEM));
5371 err_pci_reg:
5372 err_dma:
5373 pci_disable_device(pdev);
5374 return err;
5375 }
5376
5377 /**
5378 * ixgbe_remove - Device Removal Routine
5379 * @pdev: PCI device information struct
5380 *
5381 * ixgbe_remove is called by the PCI subsystem to alert the driver
5382 * that it should release a PCI device. The could be caused by a
5383 * Hot-Plug event, or because the driver is going to be removed from
5384 * memory.
5385 **/
5386 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5387 {
5388 struct net_device *netdev = pci_get_drvdata(pdev);
5389 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5390 int err;
5391
5392 set_bit(__IXGBE_DOWN, &adapter->state);
5393 /* clear the module not found bit to make sure the worker won't
5394 * reschedule
5395 */
5396 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5397 del_timer_sync(&adapter->watchdog_timer);
5398
5399 del_timer_sync(&adapter->sfp_timer);
5400 cancel_work_sync(&adapter->watchdog_task);
5401 cancel_work_sync(&adapter->sfp_task);
5402 cancel_work_sync(&adapter->multispeed_fiber_task);
5403 cancel_work_sync(&adapter->sfp_config_module_task);
5404 flush_scheduled_work();
5405
5406 #ifdef CONFIG_IXGBE_DCA
5407 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5408 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5409 dca_remove_requester(&pdev->dev);
5410 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5411 }
5412
5413 #endif
5414 #ifdef IXGBE_FCOE
5415 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5416 ixgbe_cleanup_fcoe(adapter);
5417
5418 #endif /* IXGBE_FCOE */
5419
5420 /* remove the added san mac */
5421 ixgbe_del_sanmac_netdev(netdev);
5422
5423 if (netdev->reg_state == NETREG_REGISTERED)
5424 unregister_netdev(netdev);
5425
5426 ixgbe_clear_interrupt_scheme(adapter);
5427
5428 ixgbe_release_hw_control(adapter);
5429
5430 iounmap(adapter->hw.hw_addr);
5431 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5432 IORESOURCE_MEM));
5433
5434 DPRINTK(PROBE, INFO, "complete\n");
5435
5436 free_netdev(netdev);
5437
5438 err = pci_disable_pcie_error_reporting(pdev);
5439 if (err)
5440 dev_err(&pdev->dev,
5441 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5442
5443 pci_disable_device(pdev);
5444 }
5445
5446 /**
5447 * ixgbe_io_error_detected - called when PCI error is detected
5448 * @pdev: Pointer to PCI device
5449 * @state: The current pci connection state
5450 *
5451 * This function is called after a PCI bus error affecting
5452 * this device has been detected.
5453 */
5454 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5455 pci_channel_state_t state)
5456 {
5457 struct net_device *netdev = pci_get_drvdata(pdev);
5458 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5459
5460 netif_device_detach(netdev);
5461
5462 if (state == pci_channel_io_perm_failure)
5463 return PCI_ERS_RESULT_DISCONNECT;
5464
5465 if (netif_running(netdev))
5466 ixgbe_down(adapter);
5467 pci_disable_device(pdev);
5468
5469 /* Request a slot reset. */
5470 return PCI_ERS_RESULT_NEED_RESET;
5471 }
5472
5473 /**
5474 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5475 * @pdev: Pointer to PCI device
5476 *
5477 * Restart the card from scratch, as if from a cold-boot.
5478 */
5479 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5480 {
5481 struct net_device *netdev = pci_get_drvdata(pdev);
5482 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5483 pci_ers_result_t result;
5484 int err;
5485
5486 if (pci_enable_device_mem(pdev)) {
5487 DPRINTK(PROBE, ERR,
5488 "Cannot re-enable PCI device after reset.\n");
5489 result = PCI_ERS_RESULT_DISCONNECT;
5490 } else {
5491 pci_set_master(pdev);
5492 pci_restore_state(pdev);
5493
5494 pci_wake_from_d3(pdev, false);
5495
5496 ixgbe_reset(adapter);
5497 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5498 result = PCI_ERS_RESULT_RECOVERED;
5499 }
5500
5501 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5502 if (err) {
5503 dev_err(&pdev->dev,
5504 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5505 /* non-fatal, continue */
5506 }
5507
5508 return result;
5509 }
5510
5511 /**
5512 * ixgbe_io_resume - called when traffic can start flowing again.
5513 * @pdev: Pointer to PCI device
5514 *
5515 * This callback is called when the error recovery driver tells us that
5516 * its OK to resume normal operation.
5517 */
5518 static void ixgbe_io_resume(struct pci_dev *pdev)
5519 {
5520 struct net_device *netdev = pci_get_drvdata(pdev);
5521 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5522
5523 if (netif_running(netdev)) {
5524 if (ixgbe_up(adapter)) {
5525 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5526 return;
5527 }
5528 }
5529
5530 netif_device_attach(netdev);
5531 }
5532
5533 static struct pci_error_handlers ixgbe_err_handler = {
5534 .error_detected = ixgbe_io_error_detected,
5535 .slot_reset = ixgbe_io_slot_reset,
5536 .resume = ixgbe_io_resume,
5537 };
5538
5539 static struct pci_driver ixgbe_driver = {
5540 .name = ixgbe_driver_name,
5541 .id_table = ixgbe_pci_tbl,
5542 .probe = ixgbe_probe,
5543 .remove = __devexit_p(ixgbe_remove),
5544 #ifdef CONFIG_PM
5545 .suspend = ixgbe_suspend,
5546 .resume = ixgbe_resume,
5547 #endif
5548 .shutdown = ixgbe_shutdown,
5549 .err_handler = &ixgbe_err_handler
5550 };
5551
5552 /**
5553 * ixgbe_init_module - Driver Registration Routine
5554 *
5555 * ixgbe_init_module is the first routine called when the driver is
5556 * loaded. All it does is register with the PCI subsystem.
5557 **/
5558 static int __init ixgbe_init_module(void)
5559 {
5560 int ret;
5561 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5562 ixgbe_driver_string, ixgbe_driver_version);
5563
5564 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5565
5566 #ifdef CONFIG_IXGBE_DCA
5567 dca_register_notify(&dca_notifier);
5568 #endif
5569
5570 ret = pci_register_driver(&ixgbe_driver);
5571 return ret;
5572 }
5573
5574 module_init(ixgbe_init_module);
5575
5576 /**
5577 * ixgbe_exit_module - Driver Exit Cleanup Routine
5578 *
5579 * ixgbe_exit_module is called just before the driver is removed
5580 * from memory.
5581 **/
5582 static void __exit ixgbe_exit_module(void)
5583 {
5584 #ifdef CONFIG_IXGBE_DCA
5585 dca_unregister_notify(&dca_notifier);
5586 #endif
5587 pci_unregister_driver(&ixgbe_driver);
5588 }
5589
5590 #ifdef CONFIG_IXGBE_DCA
5591 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5592 void *p)
5593 {
5594 int ret_val;
5595
5596 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5597 __ixgbe_notify_dca);
5598
5599 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5600 }
5601
5602 #endif /* CONFIG_IXGBE_DCA */
5603 #ifdef DEBUG
5604 /**
5605 * ixgbe_get_hw_dev_name - return device name string
5606 * used by hardware layer to print debugging information
5607 **/
5608 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5609 {
5610 struct ixgbe_adapter *adapter = hw->back;
5611 return adapter->netdev->name;
5612 }
5613
5614 #endif
5615 module_exit(ixgbe_exit_module);
5616
5617 /* ixgbe_main.c */
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