2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
5 * See LICENSE.qla4xxx for copyright and licensing details.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/module.h>
15 #include <linux/list.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/sched.h>
19 #include <linux/slab.h>
20 #include <linux/dmapool.h>
21 #include <linux/mempool.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/mutex.h>
27 #include <linux/aer.h>
28 #include <linux/bsg-lib.h>
31 #include <scsi/scsi.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/scsi_device.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <scsi/scsi_transport.h>
36 #include <scsi/scsi_transport_iscsi.h>
37 #include <scsi/scsi_bsg_iscsi.h>
38 #include <scsi/scsi_netlink.h>
39 #include <scsi/libiscsi.h>
44 #include "ql4_nvram.h"
47 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
48 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
51 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
52 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
55 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
56 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
59 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
60 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
63 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8324
64 #define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032
67 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8042
68 #define PCI_DEVICE_ID_QLOGIC_ISP8042 0x8042
71 #define ISP4XXX_PCI_FN_1 0x1
72 #define ISP4XXX_PCI_FN_2 0x3
78 * Data bit definitions
96 #define BIT_16 0x10000
97 #define BIT_17 0x20000
98 #define BIT_18 0x40000
99 #define BIT_19 0x80000
100 #define BIT_20 0x100000
101 #define BIT_21 0x200000
102 #define BIT_22 0x400000
103 #define BIT_23 0x800000
104 #define BIT_24 0x1000000
105 #define BIT_25 0x2000000
106 #define BIT_26 0x4000000
107 #define BIT_27 0x8000000
108 #define BIT_28 0x10000000
109 #define BIT_29 0x20000000
110 #define BIT_30 0x40000000
111 #define BIT_31 0x80000000
114 * Macros to help code, maintain, etc.
116 #define ql4_printk(level, ha, format, arg...) \
117 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
121 * Host adapter default definitions
122 ***********************************/
125 #define MAX_TARGETS MAX_DEV_DB_ENTRIES
126 #define MAX_LUNS 0xffff
127 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
128 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
129 #define MAX_PDU_ENTRIES 32
130 #define INVALID_ENTRY 0xFFFF
131 #define MAX_CMDS_TO_RISC 1024
132 #define MAX_SRBS MAX_CMDS_TO_RISC
133 #define MBOX_AEN_REG_COUNT 8
134 #define MAX_INIT_RETRIES 5
139 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
140 #define RESPONSE_QUEUE_DEPTH 64
141 #define QUEUE_SIZE 64
142 #define DMA_BUFFER_SIZE 512
143 #define IOCB_HIWAT_CUSHION 4
148 #define MAC_ADDR_LEN 6 /* in bytes */
149 #define IP_ADDR_LEN 4 /* in bytes */
150 #define IPv6_ADDR_LEN 16 /* IPv6 address size */
151 #define DRIVER_NAME "qla4xxx"
153 #define MAX_LINKED_CMDS_PER_LUN 3
154 #define MAX_REQS_SERVICED_PER_INTR 1
156 #define ISCSI_IPADDR_SIZE 4 /* IP address size */
157 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
158 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
160 #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */
161 /* recovery timeout */
163 #define LSDW(x) ((u32)((u64)(x)))
164 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
166 #define DEV_DB_NON_PERSISTENT 0
167 #define DEV_DB_PERSISTENT 1
169 #define COPY_ISID(dst_isid, src_isid) { \
171 for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;) \
172 dst_isid[i++] = src_isid[j--]; \
175 #define SET_BITVAL(o, n, v) { \
183 * Retry & Timeout Values
186 #define SOFT_RESET_TOV 30
187 #define RESET_INTR_TOV 3
188 #define SEMAPHORE_TOV 10
189 #define ADAPTER_INIT_TOV 30
190 #define ADAPTER_RESET_TOV 180
191 #define EXTEND_CMD_TOV 60
192 #define WAIT_CMD_TOV 30
193 #define EH_WAIT_CMD_TOV 120
194 #define FIRMWARE_UP_TOV 60
195 #define RESET_FIRMWARE_TOV 30
196 #define LOGOUT_TOV 10
197 #define IOCB_TOV_MARGIN 10
198 #define RELOGIN_TOV 18
199 #define ISNS_DEREG_TOV 5
200 #define HBA_ONLINE_TOV 30
201 #define DISABLE_ACB_TOV 30
202 #define IP_CONFIG_TOV 30
204 #define BOOT_LOGIN_RESP_TOV 60
206 #define MAX_RESET_HA_RETRIES 2
207 #define FW_ALIVE_WAIT_TOV 3
208 #define IDC_EXTEND_TOV 8
210 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
213 * SCSI Request Block structure (srb) that is placed
214 * on cmd->SCp location of every I/O [We have 22 bytes available]
217 struct list_head list
; /* (8) */
218 struct scsi_qla_host
*ha
; /* HA the SP is queued on */
219 struct ddb_entry
*ddb
;
220 uint16_t flags
; /* (1) Status flags. */
222 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
223 #define SRB_GOT_SENSE BIT_4 /* sense data received. */
224 uint8_t state
; /* (1) Status flags. */
226 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
227 #define SRB_FREE_STATE 1
228 #define SRB_ACTIVE_STATE 3
229 #define SRB_ACTIVE_TIMEOUT_STATE 4
230 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
232 struct scsi_cmnd
*cmd
; /* (4) SCSI command block */
233 dma_addr_t dma_handle
; /* (4) for unmap of single transfers */
234 struct kref srb_ref
; /* reference count for this srb */
235 uint8_t err_id
; /* error id */
236 #define SRB_ERR_PORT 1 /* Request failed because "port down" */
237 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
238 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
239 #define SRB_ERR_OTHER 4
243 uint16_t iocb_cnt
; /* Number of used iocbs */
246 /* Used for extended sense / status continuation */
247 uint8_t *req_sense_ptr
;
248 uint16_t req_sense_len
;
252 /* Mailbox request block structure */
254 struct scsi_qla_host
*ha
;
255 struct mbox_cmd_iocb
*mbox
;
257 uint16_t iocb_cnt
; /* Number of used iocbs */
262 * Asynchronous Event Queue structure
265 uint32_t mbox_sts
[MBOX_AEN_REG_COUNT
];
270 struct aen entry
[MAX_AEN_ENTRIES
];
274 * Device Database (DDB) structure
277 struct scsi_qla_host
*ha
;
278 struct iscsi_cls_session
*sess
;
279 struct iscsi_cls_conn
*conn
;
281 uint16_t fw_ddb_index
; /* DDB firmware index */
282 uint32_t fw_ddb_device_state
; /* F/W Device State -- see ql4_fw.h */
284 #define FLASH_DDB 0x01
286 struct dev_db_entry fw_ddb_entry
;
287 int (*unblock_sess
)(struct iscsi_cls_session
*cls_session
);
288 int (*ddb_change
)(struct scsi_qla_host
*ha
, uint32_t fw_ddb_index
,
289 struct ddb_entry
*ddb_entry
, uint32_t state
);
291 /* Driver Re-login */
292 unsigned long flags
; /* DDB Flags */
293 uint16_t default_relogin_timeout
; /* Max time to wait for
294 * relogin to complete */
295 atomic_t retry_relogin_timer
; /* Min Time between relogins
297 atomic_t relogin_timer
; /* Max Time to wait for
298 * relogin to complete */
299 atomic_t relogin_retry_count
; /* Num of times relogin has been
301 uint32_t default_time2wait
; /* Default Min time between
302 * relogins (+aens) */
303 uint16_t chap_tbl_idx
;
306 struct qla_ddb_index
{
307 struct list_head list
;
309 uint16_t flash_ddb_idx
;
310 struct dev_db_entry fw_ddb
;
311 uint8_t flash_isid
[6];
314 #define DDB_IPADDR_LEN 64
316 struct ql4_tuple_ddb
{
319 char ip_addr
[DDB_IPADDR_LEN
];
320 char iscsi_name
[ISCSI_NAME_SIZE
];
322 #define DDB_OPT_IPV6 0x0e0e
323 #define DDB_OPT_IPV4 0x0f0f
330 #define DDB_STATE_DEAD 0 /* We can no longer talk to
332 #define DDB_STATE_ONLINE 1 /* Device ready to accept
334 #define DDB_STATE_MISSING 2 /* Device logged off, trying
340 #define DF_RELOGIN 0 /* Relogin to device */
341 #define DF_BOOT_TGT 1 /* Boot target entry */
342 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
343 #define DF_FO_MASKED 3
344 #define DF_DISABLE_RELOGIN 4 /* Disable relogin to device */
346 enum qla4_work_type
{
348 QLA4_EVENT_PING_STATUS
,
351 struct qla4_work_evt
{
352 struct list_head list
;
353 enum qla4_work_type type
;
356 enum iscsi_host_event_code code
;
369 struct ql82xx_hw_data
{
370 /* Offsets for flash/nvram access (set to ~0 if not used). */
371 uint32_t flash_conf_off
;
372 uint32_t flash_data_off
;
374 uint32_t fdt_wrt_disable
;
375 uint32_t fdt_erase_cmd
;
376 uint32_t fdt_block_size
;
377 uint32_t fdt_unprotect_sec_cmd
;
378 uint32_t fdt_protect_sec_cmd
;
380 uint32_t flt_region_flt
;
381 uint32_t flt_region_fdt
;
382 uint32_t flt_region_boot
;
383 uint32_t flt_region_bootload
;
384 uint32_t flt_region_fw
;
386 uint32_t flt_iscsi_param
;
387 uint32_t flt_region_chap
;
388 uint32_t flt_chap_size
;
389 uint32_t flt_region_ddb
;
390 uint32_t flt_ddb_size
;
393 struct qla4_8xxx_legacy_intr_set
{
394 uint32_t int_vec_bit
;
395 uint32_t tgt_status_reg
;
396 uint32_t tgt_mask_reg
;
397 uint32_t pci_int_reg
;
402 #define QLA_MSIX_DEFAULT 0x00
403 #define QLA_MSIX_RSP_Q 0x01
405 #define QLA_MSIX_ENTRIES 2
406 #define QLA_MIDX_DEFAULT 0
407 #define QLA_MIDX_RSP_Q 1
409 struct ql4_msix_entry
{
411 uint16_t msix_vector
;
418 struct isp_operations
{
419 int (*iospace_config
) (struct scsi_qla_host
*ha
);
420 void (*pci_config
) (struct scsi_qla_host
*);
421 void (*disable_intrs
) (struct scsi_qla_host
*);
422 void (*enable_intrs
) (struct scsi_qla_host
*);
423 int (*start_firmware
) (struct scsi_qla_host
*);
424 int (*restart_firmware
) (struct scsi_qla_host
*);
425 irqreturn_t (*intr_handler
) (int , void *);
426 void (*interrupt_service_routine
) (struct scsi_qla_host
*, uint32_t);
427 int (*need_reset
) (struct scsi_qla_host
*);
428 int (*reset_chip
) (struct scsi_qla_host
*);
429 int (*reset_firmware
) (struct scsi_qla_host
*);
430 void (*queue_iocb
) (struct scsi_qla_host
*);
431 void (*complete_iocb
) (struct scsi_qla_host
*);
432 uint16_t (*rd_shdw_req_q_out
) (struct scsi_qla_host
*);
433 uint16_t (*rd_shdw_rsp_q_in
) (struct scsi_qla_host
*);
434 int (*get_sys_info
) (struct scsi_qla_host
*);
435 uint32_t (*rd_reg_direct
) (struct scsi_qla_host
*, ulong
);
436 void (*wr_reg_direct
) (struct scsi_qla_host
*, ulong
, uint32_t);
437 int (*rd_reg_indirect
) (struct scsi_qla_host
*, uint32_t, uint32_t *);
438 int (*wr_reg_indirect
) (struct scsi_qla_host
*, uint32_t, uint32_t);
439 int (*idc_lock
) (struct scsi_qla_host
*);
440 void (*idc_unlock
) (struct scsi_qla_host
*);
441 void (*rom_lock_recovery
) (struct scsi_qla_host
*);
442 void (*queue_mailbox_command
) (struct scsi_qla_host
*, uint32_t *, int);
443 void (*process_mailbox_interrupt
) (struct scsi_qla_host
*, int);
446 struct ql4_mdump_size_table
{
448 uint32_t size_cmask_02
;
449 uint32_t size_cmask_04
;
450 uint32_t size_cmask_08
;
451 uint32_t size_cmask_10
;
452 uint32_t size_cmask_FF
;
456 /*qla4xxx ipaddress configuration details */
457 struct ipaddress_config
{
458 uint16_t ipv4_options
;
459 uint16_t tcp_options
;
460 uint16_t ipv4_vlan_tag
;
461 uint8_t ipv4_addr_state
;
462 uint8_t ip_address
[IP_ADDR_LEN
];
463 uint8_t subnet_mask
[IP_ADDR_LEN
];
464 uint8_t gateway
[IP_ADDR_LEN
];
465 uint32_t ipv6_options
;
466 uint32_t ipv6_addl_options
;
467 uint8_t ipv6_link_local_state
;
468 uint8_t ipv6_addr0_state
;
469 uint8_t ipv6_addr1_state
;
470 uint8_t ipv6_default_router_state
;
471 uint16_t ipv6_vlan_tag
;
472 struct in6_addr ipv6_link_local_addr
;
473 struct in6_addr ipv6_addr0
;
474 struct in6_addr ipv6_addr1
;
475 struct in6_addr ipv6_default_router_addr
;
476 uint16_t eth_mtu_size
;
481 #define QL4_CHAP_MAX_NAME_LEN 256
482 #define QL4_CHAP_MAX_SECRET_LEN 100
486 struct ql4_chap_format
{
487 u8 intr_chap_name
[QL4_CHAP_MAX_NAME_LEN
];
488 u8 intr_secret
[QL4_CHAP_MAX_SECRET_LEN
];
489 u8 target_chap_name
[QL4_CHAP_MAX_NAME_LEN
];
490 u8 target_secret
[QL4_CHAP_MAX_SECRET_LEN
];
491 u16 intr_chap_name_length
;
492 u16 intr_secret_length
;
493 u16 target_chap_name_length
;
494 u16 target_secret_length
;
497 struct ip_address_format
{
502 struct ql4_conn_info
{
504 struct ip_address_format dest_ipaddr
;
505 struct ql4_chap_format chap
;
508 struct ql4_boot_session_info
{
510 struct ql4_conn_info conn_list
[1];
513 struct ql4_boot_tgt_info
{
514 struct ql4_boot_session_info boot_pri_sess
;
515 struct ql4_boot_session_info boot_sec_sess
;
519 * Linux Host Adapter structure
521 struct scsi_qla_host
{
522 /* Linux adapter configuration data */
525 #define AF_ONLINE 0 /* 0x00000001 */
526 #define AF_INIT_DONE 1 /* 0x00000002 */
527 #define AF_MBOX_COMMAND 2 /* 0x00000004 */
528 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
529 #define AF_ST_DISCOVERY_IN_PROGRESS 4 /* 0x00000010 */
530 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */
531 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
532 #define AF_LINK_UP 8 /* 0x00000100 */
533 #define AF_LOOPBACK 9 /* 0x00000200 */
534 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */
535 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
536 #define AF_HA_REMOVAL 12 /* 0x00001000 */
537 #define AF_INTx_ENABLED 15 /* 0x00008000 */
538 #define AF_MSI_ENABLED 16 /* 0x00010000 */
539 #define AF_MSIX_ENABLED 17 /* 0x00020000 */
540 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
541 #define AF_FW_RECOVERY 19 /* 0x00080000 */
542 #define AF_EEH_BUSY 20 /* 0x00100000 */
543 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
544 #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */
545 #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */
546 #define AF_8XXX_RST_OWNER 25 /* 0x02000000 */
547 #define AF_82XX_DUMP_READING 26 /* 0x04000000 */
548 #define AF_83XX_NO_FW_DUMP 27 /* 0x08000000 */
549 #define AF_83XX_IOCB_INTR_ON 28 /* 0x10000000 */
550 #define AF_83XX_MBOX_INTR_ON 29 /* 0x20000000 */
552 unsigned long dpc_flags
;
554 #define DPC_RESET_HA 1 /* 0x00000002 */
555 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
556 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
557 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
558 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */
559 #define DPC_ISNS_RESTART 7 /* 0x00000080 */
560 #define DPC_AEN 9 /* 0x00000200 */
561 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
562 #define DPC_LINK_CHANGED 18 /* 0x00040000 */
563 #define DPC_RESET_ACTIVE 20 /* 0x00040000 */
564 #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
565 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
566 #define DPC_POST_IDC_ACK 23 /* 0x00200000 */
567 #define DPC_RESTORE_ACB 24 /* 0x01000000 */
569 struct Scsi_Host
*host
; /* pointer to host data */
576 #define SRB_MIN_REQ 128
577 mempool_t
*srb_mempool
;
579 /* pci information */
580 struct pci_dev
*pdev
;
582 struct isp_reg __iomem
*reg
; /* Base I/O address */
583 unsigned long pio_address
;
584 unsigned long pio_length
;
585 #define MIN_IOBASE_LEN 0x100
587 uint16_t req_q_count
;
589 unsigned long host_no
;
591 /* NVRAM registers */
592 struct eeprom_data
*nvram
;
593 spinlock_t hardware_lock ____cacheline_aligned
;
594 uint32_t eeprom_cmd_data
;
596 /* Counters for general statistics */
598 uint64_t adapter_error_count
;
599 uint64_t device_error_count
;
600 uint64_t total_io_count
;
601 uint64_t total_mbytes_xferred
;
602 uint64_t link_failure_count
;
603 uint64_t invalid_crc_count
;
604 uint32_t bytes_xfered
;
605 uint32_t spurious_int_count
;
606 uint32_t aborted_io_count
;
607 uint32_t io_timeout_count
;
608 uint32_t mailbox_timeout_count
;
609 uint32_t seconds_since_last_intr
;
610 uint32_t seconds_since_last_heartbeat
;
613 /* Info Needed for Management App */
614 /* --- From GetFwVersion --- */
615 uint32_t firmware_version
[2];
616 uint32_t patch_number
;
617 uint32_t build_number
;
620 /* --- From Init_FW --- */
621 /* init_cb_t *init_cb; */
622 uint16_t firmware_options
;
624 uint8_t name_string
[256];
625 uint8_t heartbeat_interval
;
627 /* --- From FlashSysInfo --- */
628 uint8_t my_mac
[MAC_ADDR_LEN
];
629 uint8_t serial_number
[16];
631 /* --- From GetFwState --- */
632 uint32_t firmware_state
;
633 uint32_t addl_fw_state
;
635 /* Linux kernel thread */
636 struct workqueue_struct
*dpc_thread
;
637 struct work_struct dpc_work
;
639 /* Linux timer thread */
640 struct timer_list timer
;
641 uint32_t timer_active
;
643 /* Recovery Timers */
644 atomic_t check_relogin_timeouts
;
645 uint32_t retry_reset_ha_cnt
;
646 uint32_t isp_reset_timer
; /* reset test timer */
647 uint32_t nic_reset_timer
; /* simulated nic reset test timer */
649 struct list_head free_srb_q
;
650 uint16_t free_srb_q_count
;
651 uint16_t num_srbs_allocated
;
653 /* DMA Memory Block */
655 dma_addr_t queues_dma
;
656 unsigned long queues_len
;
658 #define MEM_ALIGN_VALUE \
659 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
660 sizeof(struct queue_entry))
661 /* request and response queue variables */
662 dma_addr_t request_dma
;
663 struct queue_entry
*request_ring
;
664 struct queue_entry
*request_ptr
;
665 dma_addr_t response_dma
;
666 struct queue_entry
*response_ring
;
667 struct queue_entry
*response_ptr
;
668 dma_addr_t shadow_regs_dma
;
669 struct shadow_regs
*shadow_regs
;
670 uint16_t request_in
; /* Current indexes. */
671 uint16_t request_out
;
672 uint16_t response_in
;
673 uint16_t response_out
;
675 /* aen queue variables */
676 uint16_t aen_q_count
; /* Number of available aen_q entries */
677 uint16_t aen_in
; /* Current indexes */
679 struct aen aen_q
[MAX_AEN_ENTRIES
];
681 struct ql4_aen_log aen_log
;/* tracks all aens */
683 /* This mutex protects several threads to do mailbox commands
686 struct mutex mbox_sem
;
688 /* temporary mailbox status registers */
689 volatile uint8_t mbox_status_count
;
690 volatile uint32_t mbox_status
[MBOX_REG_COUNT
];
692 /* FW ddb index map */
693 struct ddb_entry
*fw_ddb_index_map
[MAX_DDB_ENTRIES
];
695 /* Saved srb for status continuation entry processing */
696 struct srb
*status_srb
;
700 /* qla82xx specific fields */
701 struct device_reg_82xx __iomem
*qla4_82xx_reg
; /* Base I/O address */
702 unsigned long nx_pcibase
; /* Base I/O address */
703 uint8_t *nx_db_rd_ptr
; /* Doorbell read pointer */
704 unsigned long nx_db_wr_ptr
; /* Door bell write pointer */
705 unsigned long first_page_group_start
;
706 unsigned long first_page_group_end
;
709 uint32_t curr_window
;
710 uint32_t ddr_mn_window
;
711 unsigned long mn_win_crb
;
712 unsigned long ms_win_crb
;
718 struct qla4_8xxx_legacy_intr_set nx_legacy_intr
;
722 uint32_t fw_heartbeat_counter
;
724 struct isp_operations
*isp_ops
;
725 struct ql82xx_hw_data hw
;
727 struct ql4_msix_entry msix_entries
[QLA_MSIX_ENTRIES
];
729 uint32_t nx_dev_init_timeout
;
730 uint32_t nx_reset_timeout
;
732 uint32_t fw_dump_size
;
733 uint32_t fw_dump_capture_mask
;
734 void *fw_dump_tmplt_hdr
;
735 uint32_t fw_dump_tmplt_size
;
737 struct completion mbx_intr_comp
;
739 struct ipaddress_config ip_config
;
740 struct iscsi_iface
*iface_ipv4
;
741 struct iscsi_iface
*iface_ipv6_0
;
742 struct iscsi_iface
*iface_ipv6_1
;
744 /* --- From About Firmware --- */
745 struct about_fw_info fw_info
;
746 uint32_t fw_uptime_secs
; /* seconds elapsed since fw bootup */
747 uint32_t fw_uptime_msecs
; /* milliseconds beyond elapsed seconds */
748 uint16_t def_timeout
; /* Default login timeout */
750 uint32_t flash_state
;
751 #define QLFLASH_WAITING 0
752 #define QLFLASH_READING 1
753 #define QLFLASH_WRITING 2
754 struct dma_pool
*chap_dma_pool
;
755 uint8_t *chap_list
; /* CHAP table cache */
756 struct mutex chap_sem
;
758 #define CHAP_DMA_BLOCK_SIZE 512
759 struct workqueue_struct
*task_wq
;
760 unsigned long ddb_idx_map
[MAX_DDB_ENTRIES
/ BITS_PER_LONG
];
761 #define SYSFS_FLAG_FW_SEL_BOOT 2
762 struct iscsi_boot_kset
*boot_kset
;
763 struct ql4_boot_tgt_info boot_tgt
;
764 uint16_t phy_port_num
;
765 uint16_t phy_port_cnt
;
766 uint16_t iscsi_pci_func_cnt
;
767 uint8_t model_name
[16];
768 struct completion disable_acb_comp
;
769 struct dma_pool
*fw_ddb_dma_pool
;
770 #define DDB_DMA_BLOCK_SIZE 512
771 uint16_t pri_ddb_idx
;
772 uint16_t sec_ddb_idx
;
774 uint16_t temperature
;
776 /* event work list */
777 struct list_head work_list
;
778 spinlock_t work_lock
;
782 struct mrb
*active_mrb_array
[MAX_MRB
];
786 struct qla4_83xx_reset_template reset_tmplt
;
787 struct device_reg_83xx __iomem
*qla4_83xx_reg
; /* Base I/O address
791 struct qla4_83xx_idc_information idc_info
;
792 struct addr_ctrl_blk
*saved_acb
;
795 struct ql4_task_data
{
796 struct scsi_qla_host
*ha
;
797 uint8_t iocb_req_cnt
;
805 struct iscsi_task
*task
;
806 struct passthru_status sts
;
807 struct work_struct task_work
;
810 struct qla_endpoint
{
811 struct Scsi_Host
*host
;
812 struct sockaddr_storage dst_addr
;
816 struct qla_endpoint
*qla_ep
;
819 static inline int is_ipv4_enabled(struct scsi_qla_host
*ha
)
821 return ((ha
->ip_config
.ipv4_options
& IPOPT_IPV4_PROTOCOL_ENABLE
) != 0);
824 static inline int is_ipv6_enabled(struct scsi_qla_host
*ha
)
826 return ((ha
->ip_config
.ipv6_options
&
827 IPV6_OPT_IPV6_PROTOCOL_ENABLE
) != 0);
830 static inline int is_qla4010(struct scsi_qla_host
*ha
)
832 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP4010
;
835 static inline int is_qla4022(struct scsi_qla_host
*ha
)
837 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP4022
;
840 static inline int is_qla4032(struct scsi_qla_host
*ha
)
842 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP4032
;
845 static inline int is_qla40XX(struct scsi_qla_host
*ha
)
847 return is_qla4032(ha
) || is_qla4022(ha
) || is_qla4010(ha
);
850 static inline int is_qla8022(struct scsi_qla_host
*ha
)
852 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP8022
;
855 static inline int is_qla8032(struct scsi_qla_host
*ha
)
857 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP8324
;
860 static inline int is_qla8042(struct scsi_qla_host
*ha
)
862 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP8042
;
865 static inline int is_qla80XX(struct scsi_qla_host
*ha
)
867 return is_qla8022(ha
) || is_qla8032(ha
) || is_qla8042(ha
);
870 static inline int is_aer_supported(struct scsi_qla_host
*ha
)
872 return ((ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP8022
) ||
873 (ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP8324
));
876 static inline int adapter_up(struct scsi_qla_host
*ha
)
878 return (test_bit(AF_ONLINE
, &ha
->flags
) != 0) &&
879 (test_bit(AF_LINK_UP
, &ha
->flags
) != 0) &&
880 (!test_bit(AF_LOOPBACK
, &ha
->flags
));
883 static inline struct scsi_qla_host
* to_qla_host(struct Scsi_Host
*shost
)
885 return (struct scsi_qla_host
*)iscsi_host_priv(shost
);
888 static inline void __iomem
* isp_semaphore(struct scsi_qla_host
*ha
)
890 return (is_qla4010(ha
) ?
891 &ha
->reg
->u1
.isp4010
.nvram
:
892 &ha
->reg
->u1
.isp4022
.semaphore
);
895 static inline void __iomem
* isp_nvram(struct scsi_qla_host
*ha
)
897 return (is_qla4010(ha
) ?
898 &ha
->reg
->u1
.isp4010
.nvram
:
899 &ha
->reg
->u1
.isp4022
.nvram
);
902 static inline void __iomem
* isp_ext_hw_conf(struct scsi_qla_host
*ha
)
904 return (is_qla4010(ha
) ?
905 &ha
->reg
->u2
.isp4010
.ext_hw_conf
:
906 &ha
->reg
->u2
.isp4022
.p0
.ext_hw_conf
);
909 static inline void __iomem
* isp_port_status(struct scsi_qla_host
*ha
)
911 return (is_qla4010(ha
) ?
912 &ha
->reg
->u2
.isp4010
.port_status
:
913 &ha
->reg
->u2
.isp4022
.p0
.port_status
);
916 static inline void __iomem
* isp_port_ctrl(struct scsi_qla_host
*ha
)
918 return (is_qla4010(ha
) ?
919 &ha
->reg
->u2
.isp4010
.port_ctrl
:
920 &ha
->reg
->u2
.isp4022
.p0
.port_ctrl
);
923 static inline void __iomem
* isp_port_error_status(struct scsi_qla_host
*ha
)
925 return (is_qla4010(ha
) ?
926 &ha
->reg
->u2
.isp4010
.port_err_status
:
927 &ha
->reg
->u2
.isp4022
.p0
.port_err_status
);
930 static inline void __iomem
* isp_gp_out(struct scsi_qla_host
*ha
)
932 return (is_qla4010(ha
) ?
933 &ha
->reg
->u2
.isp4010
.gp_out
:
934 &ha
->reg
->u2
.isp4022
.p0
.gp_out
);
937 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host
*ha
)
939 return (is_qla4010(ha
) ?
940 offsetof(struct eeprom_data
, isp4010
.ext_hw_conf
) / 2 :
941 offsetof(struct eeprom_data
, isp4022
.ext_hw_conf
) / 2);
944 int ql4xxx_sem_spinlock(struct scsi_qla_host
* ha
, u32 sem_mask
, u32 sem_bits
);
945 void ql4xxx_sem_unlock(struct scsi_qla_host
* ha
, u32 sem_mask
);
946 int ql4xxx_sem_lock(struct scsi_qla_host
* ha
, u32 sem_mask
, u32 sem_bits
);
948 static inline int ql4xxx_lock_flash(struct scsi_qla_host
*a
)
951 return ql4xxx_sem_spinlock(a
, QL4010_FLASH_SEM_MASK
,
952 QL4010_FLASH_SEM_BITS
);
954 return ql4xxx_sem_spinlock(a
, QL4022_FLASH_SEM_MASK
,
955 (QL4022_RESOURCE_BITS_BASE_CODE
|
956 (a
->mac_index
)) << 13);
959 static inline void ql4xxx_unlock_flash(struct scsi_qla_host
*a
)
962 ql4xxx_sem_unlock(a
, QL4010_FLASH_SEM_MASK
);
964 ql4xxx_sem_unlock(a
, QL4022_FLASH_SEM_MASK
);
967 static inline int ql4xxx_lock_nvram(struct scsi_qla_host
*a
)
970 return ql4xxx_sem_spinlock(a
, QL4010_NVRAM_SEM_MASK
,
971 QL4010_NVRAM_SEM_BITS
);
973 return ql4xxx_sem_spinlock(a
, QL4022_NVRAM_SEM_MASK
,
974 (QL4022_RESOURCE_BITS_BASE_CODE
|
975 (a
->mac_index
)) << 10);
978 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host
*a
)
981 ql4xxx_sem_unlock(a
, QL4010_NVRAM_SEM_MASK
);
983 ql4xxx_sem_unlock(a
, QL4022_NVRAM_SEM_MASK
);
986 static inline int ql4xxx_lock_drvr(struct scsi_qla_host
*a
)
989 return ql4xxx_sem_lock(a
, QL4010_DRVR_SEM_MASK
,
990 QL4010_DRVR_SEM_BITS
);
992 return ql4xxx_sem_lock(a
, QL4022_DRVR_SEM_MASK
,
993 (QL4022_RESOURCE_BITS_BASE_CODE
|
994 (a
->mac_index
)) << 1);
997 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host
*a
)
1000 ql4xxx_sem_unlock(a
, QL4010_DRVR_SEM_MASK
);
1002 ql4xxx_sem_unlock(a
, QL4022_DRVR_SEM_MASK
);
1005 static inline int ql4xxx_reset_active(struct scsi_qla_host
*ha
)
1007 return test_bit(DPC_RESET_ACTIVE
, &ha
->dpc_flags
) ||
1008 test_bit(DPC_RESET_HA
, &ha
->dpc_flags
) ||
1009 test_bit(DPC_RETRY_RESET_HA
, &ha
->dpc_flags
) ||
1010 test_bit(DPC_RESET_HA_INTR
, &ha
->dpc_flags
) ||
1011 test_bit(DPC_RESET_HA_FW_CONTEXT
, &ha
->dpc_flags
) ||
1012 test_bit(DPC_HA_UNRECOVERABLE
, &ha
->dpc_flags
);
1016 static inline int qla4_8xxx_rd_direct(struct scsi_qla_host
*ha
,
1017 const uint32_t crb_reg
)
1019 return ha
->isp_ops
->rd_reg_direct(ha
, ha
->reg_tbl
[crb_reg
]);
1022 static inline void qla4_8xxx_wr_direct(struct scsi_qla_host
*ha
,
1023 const uint32_t crb_reg
,
1024 const uint32_t value
)
1026 ha
->isp_ops
->wr_reg_direct(ha
, ha
->reg_tbl
[crb_reg
], value
);
1029 /*---------------------------------------------------------------------------*/
1031 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
1033 #define INIT_ADAPTER 0
1034 #define RESET_ADAPTER 1
1036 #define PRESERVE_DDB_LIST 0
1037 #define REBUILD_DDB_LIST 1
1039 /* Defines for process_aen() */
1040 #define PROCESS_ALL_AENS 0
1041 #define FLUSH_DDB_CHANGED_AENS 1
1043 /* Defines for udev events */
1044 #define QL4_UEVENT_CODE_FW_DUMP 0
1046 #endif /*_QLA4XXX_H */