2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
33 #define DRIVER_NAME "sdhci"
35 #define DBG(f, x...) \
36 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
38 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
39 defined(CONFIG_MMC_SDHCI_MODULE))
40 #define SDHCI_USE_LEDS_CLASS
43 #define MAX_TUNING_LOOP 40
45 static unsigned int debug_quirks
= 0;
46 static unsigned int debug_quirks2
;
48 static void sdhci_finish_data(struct sdhci_host
*);
50 static void sdhci_send_command(struct sdhci_host
*, struct mmc_command
*);
51 static void sdhci_finish_command(struct sdhci_host
*);
52 static int sdhci_execute_tuning(struct mmc_host
*mmc
);
53 static void sdhci_tuning_timer(unsigned long data
);
55 #ifdef CONFIG_PM_RUNTIME
56 static int sdhci_runtime_pm_get(struct sdhci_host
*host
);
57 static int sdhci_runtime_pm_put(struct sdhci_host
*host
);
59 static inline int sdhci_runtime_pm_get(struct sdhci_host
*host
)
63 static inline int sdhci_runtime_pm_put(struct sdhci_host
*host
)
69 static void sdhci_dumpregs(struct sdhci_host
*host
)
71 pr_debug(DRIVER_NAME
": =========== REGISTER DUMP (%s)===========\n",
72 mmc_hostname(host
->mmc
));
74 pr_debug(DRIVER_NAME
": Sys addr: 0x%08x | Version: 0x%08x\n",
75 sdhci_readl(host
, SDHCI_DMA_ADDRESS
),
76 sdhci_readw(host
, SDHCI_HOST_VERSION
));
77 pr_debug(DRIVER_NAME
": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
78 sdhci_readw(host
, SDHCI_BLOCK_SIZE
),
79 sdhci_readw(host
, SDHCI_BLOCK_COUNT
));
80 pr_debug(DRIVER_NAME
": Argument: 0x%08x | Trn mode: 0x%08x\n",
81 sdhci_readl(host
, SDHCI_ARGUMENT
),
82 sdhci_readw(host
, SDHCI_TRANSFER_MODE
));
83 pr_debug(DRIVER_NAME
": Present: 0x%08x | Host ctl: 0x%08x\n",
84 sdhci_readl(host
, SDHCI_PRESENT_STATE
),
85 sdhci_readb(host
, SDHCI_HOST_CONTROL
));
86 pr_debug(DRIVER_NAME
": Power: 0x%08x | Blk gap: 0x%08x\n",
87 sdhci_readb(host
, SDHCI_POWER_CONTROL
),
88 sdhci_readb(host
, SDHCI_BLOCK_GAP_CONTROL
));
89 pr_debug(DRIVER_NAME
": Wake-up: 0x%08x | Clock: 0x%08x\n",
90 sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
),
91 sdhci_readw(host
, SDHCI_CLOCK_CONTROL
));
92 pr_debug(DRIVER_NAME
": Timeout: 0x%08x | Int stat: 0x%08x\n",
93 sdhci_readb(host
, SDHCI_TIMEOUT_CONTROL
),
94 sdhci_readl(host
, SDHCI_INT_STATUS
));
95 pr_debug(DRIVER_NAME
": Int enab: 0x%08x | Sig enab: 0x%08x\n",
96 sdhci_readl(host
, SDHCI_INT_ENABLE
),
97 sdhci_readl(host
, SDHCI_SIGNAL_ENABLE
));
98 pr_debug(DRIVER_NAME
": AC12 err: 0x%08x | Slot int: 0x%08x\n",
99 sdhci_readw(host
, SDHCI_ACMD12_ERR
),
100 sdhci_readw(host
, SDHCI_SLOT_INT_STATUS
));
101 pr_debug(DRIVER_NAME
": Caps: 0x%08x | Caps_1: 0x%08x\n",
102 sdhci_readl(host
, SDHCI_CAPABILITIES
),
103 sdhci_readl(host
, SDHCI_CAPABILITIES_1
));
104 pr_debug(DRIVER_NAME
": Cmd: 0x%08x | Max curr: 0x%08x\n",
105 sdhci_readw(host
, SDHCI_COMMAND
),
106 sdhci_readl(host
, SDHCI_MAX_CURRENT
));
107 pr_debug(DRIVER_NAME
": Host ctl2: 0x%08x\n",
108 sdhci_readw(host
, SDHCI_HOST_CONTROL2
));
110 if (host
->flags
& SDHCI_USE_ADMA
)
111 pr_debug(DRIVER_NAME
": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
112 readl(host
->ioaddr
+ SDHCI_ADMA_ERROR
),
113 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS
));
115 pr_debug(DRIVER_NAME
": ===========================================\n");
118 /*****************************************************************************\
120 * Low level functions *
122 \*****************************************************************************/
124 static void sdhci_clear_set_irqs(struct sdhci_host
*host
, u32 clear
, u32 set
)
128 ier
= sdhci_readl(host
, SDHCI_INT_ENABLE
);
131 sdhci_writel(host
, ier
, SDHCI_INT_ENABLE
);
132 sdhci_writel(host
, ier
, SDHCI_SIGNAL_ENABLE
);
135 static void sdhci_unmask_irqs(struct sdhci_host
*host
, u32 irqs
)
137 sdhci_clear_set_irqs(host
, 0, irqs
);
140 static void sdhci_mask_irqs(struct sdhci_host
*host
, u32 irqs
)
142 sdhci_clear_set_irqs(host
, irqs
, 0);
145 static void sdhci_set_card_detection(struct sdhci_host
*host
, bool enable
)
149 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) ||
150 !mmc_card_is_removable(host
->mmc
))
153 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
155 irqs
= present
? SDHCI_INT_CARD_REMOVE
: SDHCI_INT_CARD_INSERT
;
158 sdhci_unmask_irqs(host
, irqs
);
160 sdhci_mask_irqs(host
, irqs
);
163 static void sdhci_enable_card_detection(struct sdhci_host
*host
)
165 sdhci_set_card_detection(host
, true);
168 static void sdhci_disable_card_detection(struct sdhci_host
*host
)
170 sdhci_set_card_detection(host
, false);
173 static void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
175 unsigned long timeout
;
176 u32
uninitialized_var(ier
);
178 if (host
->quirks
& SDHCI_QUIRK_NO_CARD_NO_RESET
) {
179 if (!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
184 if (host
->quirks
& SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET
)
185 ier
= sdhci_readl(host
, SDHCI_INT_ENABLE
);
187 if (host
->ops
->platform_reset_enter
)
188 host
->ops
->platform_reset_enter(host
, mask
);
190 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
192 if (mask
& SDHCI_RESET_ALL
)
195 /* Wait max 100 ms */
198 /* hw clears the bit when it's done */
199 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
201 pr_err("%s: Reset 0x%x never completed.\n",
202 mmc_hostname(host
->mmc
), (int)mask
);
203 sdhci_dumpregs(host
);
210 if (host
->ops
->platform_reset_exit
)
211 host
->ops
->platform_reset_exit(host
, mask
);
213 if (host
->quirks
& SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET
)
214 sdhci_clear_set_irqs(host
, SDHCI_INT_ALL_MASK
, ier
);
217 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
);
219 static void sdhci_init(struct sdhci_host
*host
, int soft
)
222 sdhci_reset(host
, SDHCI_RESET_CMD
|SDHCI_RESET_DATA
);
224 sdhci_reset(host
, SDHCI_RESET_ALL
);
226 sdhci_clear_set_irqs(host
, SDHCI_INT_ALL_MASK
,
227 SDHCI_INT_BUS_POWER
| SDHCI_INT_DATA_END_BIT
|
228 SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_TIMEOUT
| SDHCI_INT_INDEX
|
229 SDHCI_INT_END_BIT
| SDHCI_INT_CRC
| SDHCI_INT_TIMEOUT
|
230 SDHCI_INT_DATA_END
| SDHCI_INT_RESPONSE
);
233 /* force clock reconfiguration */
235 sdhci_set_ios(host
->mmc
, &host
->mmc
->ios
);
239 static void sdhci_reinit(struct sdhci_host
*host
)
242 sdhci_enable_card_detection(host
);
245 static void sdhci_activate_led(struct sdhci_host
*host
)
249 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
250 ctrl
|= SDHCI_CTRL_LED
;
251 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
254 static void sdhci_deactivate_led(struct sdhci_host
*host
)
258 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
259 ctrl
&= ~SDHCI_CTRL_LED
;
260 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
263 #ifdef SDHCI_USE_LEDS_CLASS
264 static void sdhci_led_control(struct led_classdev
*led
,
265 enum led_brightness brightness
)
267 struct sdhci_host
*host
= container_of(led
, struct sdhci_host
, led
);
270 spin_lock_irqsave(&host
->lock
, flags
);
272 if (host
->runtime_suspended
)
275 if (brightness
== LED_OFF
)
276 sdhci_deactivate_led(host
);
278 sdhci_activate_led(host
);
280 spin_unlock_irqrestore(&host
->lock
, flags
);
284 /*****************************************************************************\
288 \*****************************************************************************/
290 static void sdhci_read_block_pio(struct sdhci_host
*host
)
293 size_t blksize
, len
, chunk
;
294 u32
uninitialized_var(scratch
);
297 DBG("PIO reading\n");
299 blksize
= host
->data
->blksz
;
302 local_irq_save(flags
);
305 if (!sg_miter_next(&host
->sg_miter
))
308 len
= min(host
->sg_miter
.length
, blksize
);
311 host
->sg_miter
.consumed
= len
;
313 buf
= host
->sg_miter
.addr
;
317 scratch
= sdhci_readl(host
, SDHCI_BUFFER
);
321 *buf
= scratch
& 0xFF;
330 sg_miter_stop(&host
->sg_miter
);
332 local_irq_restore(flags
);
335 static void sdhci_write_block_pio(struct sdhci_host
*host
)
338 size_t blksize
, len
, chunk
;
342 DBG("PIO writing\n");
344 blksize
= host
->data
->blksz
;
348 local_irq_save(flags
);
351 if (!sg_miter_next(&host
->sg_miter
))
354 len
= min(host
->sg_miter
.length
, blksize
);
357 host
->sg_miter
.consumed
= len
;
359 buf
= host
->sg_miter
.addr
;
362 scratch
|= (u32
)*buf
<< (chunk
* 8);
368 if ((chunk
== 4) || ((len
== 0) && (blksize
== 0))) {
369 sdhci_writel(host
, scratch
, SDHCI_BUFFER
);
376 sg_miter_stop(&host
->sg_miter
);
378 local_irq_restore(flags
);
381 static void sdhci_transfer_pio(struct sdhci_host
*host
)
387 if (host
->blocks
== 0)
390 if (host
->data
->flags
& MMC_DATA_READ
)
391 mask
= SDHCI_DATA_AVAILABLE
;
393 mask
= SDHCI_SPACE_AVAILABLE
;
396 * Some controllers (JMicron JMB38x) mess up the buffer bits
397 * for transfers < 4 bytes. As long as it is just one block,
398 * we can ignore the bits.
400 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_SMALL_PIO
) &&
401 (host
->data
->blocks
== 1))
404 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
405 if (host
->quirks
& SDHCI_QUIRK_PIO_NEEDS_DELAY
)
408 if (host
->data
->flags
& MMC_DATA_READ
)
409 sdhci_read_block_pio(host
);
411 sdhci_write_block_pio(host
);
414 if (host
->blocks
== 0)
418 DBG("PIO transfer complete.\n");
421 static char *sdhci_kmap_atomic(struct scatterlist
*sg
, unsigned long *flags
)
423 local_irq_save(*flags
);
424 return kmap_atomic(sg_page(sg
)) + sg
->offset
;
427 static void sdhci_kunmap_atomic(void *buffer
, unsigned long *flags
)
429 kunmap_atomic(buffer
);
430 local_irq_restore(*flags
);
433 static void sdhci_set_adma_desc(u8
*desc
, u32 addr
, int len
, unsigned cmd
)
435 __le32
*dataddr
= (__le32 __force
*)(desc
+ 4);
436 __le16
*cmdlen
= (__le16 __force
*)desc
;
438 /* SDHCI specification says ADMA descriptors should be 4 byte
439 * aligned, so using 16 or 32bit operations should be safe. */
441 cmdlen
[0] = cpu_to_le16(cmd
);
442 cmdlen
[1] = cpu_to_le16(len
);
444 dataddr
[0] = cpu_to_le32(addr
);
447 static int sdhci_adma_table_pre(struct sdhci_host
*host
,
448 struct mmc_data
*data
)
455 dma_addr_t align_addr
;
458 struct scatterlist
*sg
;
464 * The spec does not specify endianness of descriptor table.
465 * We currently guess that it is LE.
468 if (data
->flags
& MMC_DATA_READ
)
469 direction
= DMA_FROM_DEVICE
;
471 direction
= DMA_TO_DEVICE
;
474 * The ADMA descriptor table is mapped further down as we
475 * need to fill it with data first.
478 host
->align_addr
= dma_map_single(mmc_dev(host
->mmc
),
479 host
->align_buffer
, 128 * 4, direction
);
480 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->align_addr
))
482 BUG_ON(host
->align_addr
& 0x3);
484 host
->sg_count
= dma_map_sg(mmc_dev(host
->mmc
),
485 data
->sg
, data
->sg_len
, direction
);
486 if (host
->sg_count
== 0)
489 desc
= host
->adma_desc
;
490 align
= host
->align_buffer
;
492 align_addr
= host
->align_addr
;
494 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
495 addr
= sg_dma_address(sg
);
496 len
= sg_dma_len(sg
);
499 * The SDHCI specification states that ADMA
500 * addresses must be 32-bit aligned. If they
501 * aren't, then we use a bounce buffer for
502 * the (up to three) bytes that screw up the
505 offset
= (4 - (addr
& 0x3)) & 0x3;
507 if (data
->flags
& MMC_DATA_WRITE
) {
508 buffer
= sdhci_kmap_atomic(sg
, &flags
);
509 WARN_ON(((long)buffer
& PAGE_MASK
) > (PAGE_SIZE
- 3));
510 memcpy(align
, buffer
, offset
);
511 sdhci_kunmap_atomic(buffer
, &flags
);
515 sdhci_set_adma_desc(desc
, align_addr
, offset
, 0x21);
517 BUG_ON(offset
> 65536);
531 sdhci_set_adma_desc(desc
, addr
, len
, 0x21);
535 * If this triggers then we have a calculation bug
538 WARN_ON((desc
- host
->adma_desc
) > (128 * 2 + 1) * 4);
541 if (host
->quirks
& SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
) {
543 * Mark the last descriptor as the terminating descriptor
545 if (desc
!= host
->adma_desc
) {
547 desc
[0] |= 0x2; /* end */
551 * Add a terminating entry.
554 /* nop, end, valid */
555 sdhci_set_adma_desc(desc
, 0, 0, 0x3);
559 * Resync align buffer as we might have changed it.
561 if (data
->flags
& MMC_DATA_WRITE
) {
562 dma_sync_single_for_device(mmc_dev(host
->mmc
),
563 host
->align_addr
, 128 * 4, direction
);
566 host
->adma_addr
= dma_map_single(mmc_dev(host
->mmc
),
567 host
->adma_desc
, (128 * 2 + 1) * 4, DMA_TO_DEVICE
);
568 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->adma_addr
))
570 BUG_ON(host
->adma_addr
& 0x3);
575 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
576 data
->sg_len
, direction
);
578 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
584 static void sdhci_adma_table_post(struct sdhci_host
*host
,
585 struct mmc_data
*data
)
589 struct scatterlist
*sg
;
595 if (data
->flags
& MMC_DATA_READ
)
596 direction
= DMA_FROM_DEVICE
;
598 direction
= DMA_TO_DEVICE
;
600 dma_unmap_single(mmc_dev(host
->mmc
), host
->adma_addr
,
601 (128 * 2 + 1) * 4, DMA_TO_DEVICE
);
603 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
606 if (data
->flags
& MMC_DATA_READ
) {
607 dma_sync_sg_for_cpu(mmc_dev(host
->mmc
), data
->sg
,
608 data
->sg_len
, direction
);
610 align
= host
->align_buffer
;
612 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
613 if (sg_dma_address(sg
) & 0x3) {
614 size
= 4 - (sg_dma_address(sg
) & 0x3);
616 buffer
= sdhci_kmap_atomic(sg
, &flags
);
617 WARN_ON(((long)buffer
& PAGE_MASK
) > (PAGE_SIZE
- 3));
618 memcpy(buffer
, align
, size
);
619 sdhci_kunmap_atomic(buffer
, &flags
);
626 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
627 data
->sg_len
, direction
);
630 static u8
sdhci_calc_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
633 struct mmc_data
*data
= cmd
->data
;
634 unsigned target_timeout
, current_timeout
;
637 * If the host controller provides us with an incorrect timeout
638 * value, just skip the check and use 0xE. The hardware may take
639 * longer to time out, but that's much better than having a too-short
642 if (host
->quirks
& SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)
645 /* Unspecified timeout, assume max */
646 if (!data
&& !cmd
->cmd_timeout_ms
)
651 target_timeout
= cmd
->cmd_timeout_ms
* 1000;
653 target_timeout
= data
->timeout_ns
/ 1000;
655 target_timeout
+= data
->timeout_clks
/ host
->clock
;
659 * Figure out needed cycles.
660 * We do this in steps in order to fit inside a 32 bit int.
661 * The first step is the minimum timeout, which will have a
662 * minimum resolution of 6 bits:
663 * (1) 2^13*1000 > 2^22,
664 * (2) host->timeout_clk < 2^16
669 current_timeout
= (1 << 13) * 1000 / host
->timeout_clk
;
670 while (current_timeout
< target_timeout
) {
672 current_timeout
<<= 1;
678 pr_warning("%s: Too large timeout requested for CMD%d!\n",
679 mmc_hostname(host
->mmc
), cmd
->opcode
);
686 static void sdhci_set_transfer_irqs(struct sdhci_host
*host
)
688 u32 pio_irqs
= SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
;
689 u32 dma_irqs
= SDHCI_INT_DMA_END
| SDHCI_INT_ADMA_ERROR
;
691 if (host
->flags
& SDHCI_REQ_USE_DMA
)
692 sdhci_clear_set_irqs(host
, pio_irqs
, dma_irqs
);
694 sdhci_clear_set_irqs(host
, dma_irqs
, pio_irqs
);
697 static void sdhci_prepare_data(struct sdhci_host
*host
, struct mmc_command
*cmd
)
701 struct mmc_data
*data
= cmd
->data
;
706 if (data
|| (cmd
->flags
& MMC_RSP_BUSY
)) {
707 count
= sdhci_calc_timeout(host
, cmd
);
708 sdhci_writeb(host
, count
, SDHCI_TIMEOUT_CONTROL
);
715 BUG_ON(data
->blksz
* data
->blocks
> 524288);
716 BUG_ON(data
->blksz
> host
->mmc
->max_blk_size
);
717 BUG_ON(data
->blocks
> 65535);
720 host
->data_early
= 0;
721 host
->data
->bytes_xfered
= 0;
723 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))
724 host
->flags
|= SDHCI_REQ_USE_DMA
;
727 * FIXME: This doesn't account for merging when mapping the
730 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
732 struct scatterlist
*sg
;
735 if (host
->flags
& SDHCI_USE_ADMA
) {
736 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
739 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_SIZE
)
743 if (unlikely(broken
)) {
744 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
745 if (sg
->length
& 0x3) {
746 DBG("Reverting to PIO because of "
747 "transfer size (%d)\n",
749 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
757 * The assumption here being that alignment is the same after
758 * translation to device address space.
760 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
762 struct scatterlist
*sg
;
765 if (host
->flags
& SDHCI_USE_ADMA
) {
767 * As we use 3 byte chunks to work around
768 * alignment problems, we need to check this
771 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
774 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
)
778 if (unlikely(broken
)) {
779 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
780 if (sg
->offset
& 0x3) {
781 DBG("Reverting to PIO because of "
783 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
790 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
791 if (host
->flags
& SDHCI_USE_ADMA
) {
792 ret
= sdhci_adma_table_pre(host
, data
);
795 * This only happens when someone fed
796 * us an invalid request.
799 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
801 sdhci_writel(host
, host
->adma_addr
,
807 sg_cnt
= dma_map_sg(mmc_dev(host
->mmc
),
808 data
->sg
, data
->sg_len
,
809 (data
->flags
& MMC_DATA_READ
) ?
814 * This only happens when someone fed
815 * us an invalid request.
818 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
820 WARN_ON(sg_cnt
!= 1);
821 sdhci_writel(host
, sg_dma_address(data
->sg
),
828 * Always adjust the DMA selection as some controllers
829 * (e.g. JMicron) can't do PIO properly when the selection
832 if (host
->version
>= SDHCI_SPEC_200
) {
833 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
834 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
835 if ((host
->flags
& SDHCI_REQ_USE_DMA
) &&
836 (host
->flags
& SDHCI_USE_ADMA
))
837 ctrl
|= SDHCI_CTRL_ADMA32
;
839 ctrl
|= SDHCI_CTRL_SDMA
;
840 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
843 if (!(host
->flags
& SDHCI_REQ_USE_DMA
)) {
846 flags
= SG_MITER_ATOMIC
;
847 if (host
->data
->flags
& MMC_DATA_READ
)
848 flags
|= SG_MITER_TO_SG
;
850 flags
|= SG_MITER_FROM_SG
;
851 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
852 host
->blocks
= data
->blocks
;
855 sdhci_set_transfer_irqs(host
);
857 /* Set the DMA boundary value and block size */
858 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG
,
859 data
->blksz
), SDHCI_BLOCK_SIZE
);
860 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
863 static void sdhci_set_transfer_mode(struct sdhci_host
*host
,
864 struct mmc_command
*cmd
)
867 struct mmc_data
*data
= cmd
->data
;
872 WARN_ON(!host
->data
);
874 mode
= SDHCI_TRNS_BLK_CNT_EN
;
875 if (mmc_op_multi(cmd
->opcode
) || data
->blocks
> 1) {
876 mode
|= SDHCI_TRNS_MULTI
;
878 * If we are sending CMD23, CMD12 never gets sent
879 * on successful completion (so no Auto-CMD12).
881 if (!host
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
))
882 mode
|= SDHCI_TRNS_AUTO_CMD12
;
883 else if (host
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD23
)) {
884 mode
|= SDHCI_TRNS_AUTO_CMD23
;
885 sdhci_writel(host
, host
->mrq
->sbc
->arg
, SDHCI_ARGUMENT2
);
889 if (data
->flags
& MMC_DATA_READ
)
890 mode
|= SDHCI_TRNS_READ
;
891 if (host
->flags
& SDHCI_REQ_USE_DMA
)
892 mode
|= SDHCI_TRNS_DMA
;
894 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
897 static void sdhci_finish_data(struct sdhci_host
*host
)
899 struct mmc_data
*data
;
906 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
907 if (host
->flags
& SDHCI_USE_ADMA
)
908 sdhci_adma_table_post(host
, data
);
910 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
911 data
->sg_len
, (data
->flags
& MMC_DATA_READ
) ?
912 DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
917 * The specification states that the block count register must
918 * be updated, but it does not specify at what point in the
919 * data flow. That makes the register entirely useless to read
920 * back so we have to assume that nothing made it to the card
921 * in the event of an error.
924 data
->bytes_xfered
= 0;
926 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
929 * Need to send CMD12 if -
930 * a) open-ended multiblock transfer (no CMD23)
931 * b) error in multiblock transfer
938 * The controller needs a reset of internal state machines
939 * upon error conditions.
942 sdhci_reset(host
, SDHCI_RESET_CMD
);
943 sdhci_reset(host
, SDHCI_RESET_DATA
);
946 sdhci_send_command(host
, data
->stop
);
948 tasklet_schedule(&host
->finish_tasklet
);
951 static void sdhci_send_command(struct sdhci_host
*host
, struct mmc_command
*cmd
)
955 unsigned long timeout
;
962 mask
= SDHCI_CMD_INHIBIT
;
963 if ((cmd
->data
!= NULL
) || (cmd
->flags
& MMC_RSP_BUSY
))
964 mask
|= SDHCI_DATA_INHIBIT
;
966 /* We shouldn't wait for data inihibit for stop commands, even
967 though they might use busy signaling */
968 if (host
->mrq
->data
&& (cmd
== host
->mrq
->data
->stop
))
969 mask
&= ~SDHCI_DATA_INHIBIT
;
971 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
973 pr_err("%s: Controller never released "
974 "inhibit bit(s).\n", mmc_hostname(host
->mmc
));
975 sdhci_dumpregs(host
);
977 tasklet_schedule(&host
->finish_tasklet
);
984 mod_timer(&host
->timer
, jiffies
+ 10 * HZ
);
988 sdhci_prepare_data(host
, cmd
);
990 sdhci_writel(host
, cmd
->arg
, SDHCI_ARGUMENT
);
992 sdhci_set_transfer_mode(host
, cmd
);
994 if ((cmd
->flags
& MMC_RSP_136
) && (cmd
->flags
& MMC_RSP_BUSY
)) {
995 pr_err("%s: Unsupported response type!\n",
996 mmc_hostname(host
->mmc
));
997 cmd
->error
= -EINVAL
;
998 tasklet_schedule(&host
->finish_tasklet
);
1002 if (!(cmd
->flags
& MMC_RSP_PRESENT
))
1003 flags
= SDHCI_CMD_RESP_NONE
;
1004 else if (cmd
->flags
& MMC_RSP_136
)
1005 flags
= SDHCI_CMD_RESP_LONG
;
1006 else if (cmd
->flags
& MMC_RSP_BUSY
)
1007 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
1009 flags
= SDHCI_CMD_RESP_SHORT
;
1011 if (cmd
->flags
& MMC_RSP_CRC
)
1012 flags
|= SDHCI_CMD_CRC
;
1013 if (cmd
->flags
& MMC_RSP_OPCODE
)
1014 flags
|= SDHCI_CMD_INDEX
;
1016 /* CMD19 is special in that the Data Present Select should be set */
1017 if (cmd
->data
|| (cmd
->opcode
== MMC_SEND_TUNING_BLOCK
))
1018 flags
|= SDHCI_CMD_DATA
;
1020 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->opcode
, flags
), SDHCI_COMMAND
);
1023 static void sdhci_finish_command(struct sdhci_host
*host
)
1027 BUG_ON(host
->cmd
== NULL
);
1029 if (host
->cmd
->flags
& MMC_RSP_PRESENT
) {
1030 if (host
->cmd
->flags
& MMC_RSP_136
) {
1031 /* CRC is stripped so we need to do some shifting. */
1032 for (i
= 0;i
< 4;i
++) {
1033 host
->cmd
->resp
[i
] = sdhci_readl(host
,
1034 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
1036 host
->cmd
->resp
[i
] |=
1038 SDHCI_RESPONSE
+ (3-i
)*4-1);
1041 host
->cmd
->resp
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
1045 host
->cmd
->error
= 0;
1047 /* Finished CMD23, now send actual command. */
1048 if (host
->cmd
== host
->mrq
->sbc
) {
1050 sdhci_send_command(host
, host
->mrq
->cmd
);
1053 /* Processed actual command. */
1054 if (host
->data
&& host
->data_early
)
1055 sdhci_finish_data(host
);
1057 if (!host
->cmd
->data
)
1058 tasklet_schedule(&host
->finish_tasklet
);
1064 static void sdhci_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1066 int div
= 0; /* Initialized for compiler warning */
1067 int real_div
= div
, clk_mul
= 1;
1069 unsigned long timeout
;
1071 if (clock
== host
->clock
)
1074 host
->mmc
->actual_clock
= 0;
1076 if (host
->ops
->set_clock
) {
1077 host
->ops
->set_clock(host
, clock
);
1078 if (host
->quirks
& SDHCI_QUIRK_NONSTANDARD_CLOCK
)
1082 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
1087 if (host
->version
>= SDHCI_SPEC_300
) {
1089 * Check if the Host Controller supports Programmable Clock
1092 if (host
->clk_mul
) {
1096 * We need to figure out whether the Host Driver needs
1097 * to select Programmable Clock Mode, or the value can
1098 * be set automatically by the Host Controller based on
1099 * the Preset Value registers.
1101 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1102 if (!(ctrl
& SDHCI_CTRL_PRESET_VAL_ENABLE
)) {
1103 for (div
= 1; div
<= 1024; div
++) {
1104 if (((host
->max_clk
* host
->clk_mul
) /
1109 * Set Programmable Clock Mode in the Clock
1112 clk
= SDHCI_PROG_CLOCK_MODE
;
1114 clk_mul
= host
->clk_mul
;
1118 /* Version 3.00 divisors must be a multiple of 2. */
1119 if (host
->max_clk
<= clock
)
1122 for (div
= 2; div
< SDHCI_MAX_DIV_SPEC_300
;
1124 if ((host
->max_clk
/ div
) <= clock
)
1132 /* Version 2.00 divisors must be a power of 2. */
1133 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
1134 if ((host
->max_clk
/ div
) <= clock
)
1142 host
->mmc
->actual_clock
= (host
->max_clk
* clk_mul
) / real_div
;
1144 clk
|= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
1145 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
1146 << SDHCI_DIVIDER_HI_SHIFT
;
1147 clk
|= SDHCI_CLOCK_INT_EN
;
1148 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1150 /* Wait max 20 ms */
1152 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
1153 & SDHCI_CLOCK_INT_STABLE
)) {
1155 pr_err("%s: Internal clock never "
1156 "stabilised.\n", mmc_hostname(host
->mmc
));
1157 sdhci_dumpregs(host
);
1164 clk
|= SDHCI_CLOCK_CARD_EN
;
1165 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1168 host
->clock
= clock
;
1171 static int sdhci_set_power(struct sdhci_host
*host
, unsigned short power
)
1175 if (power
!= (unsigned short)-1) {
1176 switch (1 << power
) {
1177 case MMC_VDD_165_195
:
1178 pwr
= SDHCI_POWER_180
;
1182 pwr
= SDHCI_POWER_300
;
1186 pwr
= SDHCI_POWER_330
;
1193 if (host
->pwr
== pwr
)
1199 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1204 * Spec says that we should clear the power reg before setting
1205 * a new value. Some controllers don't seem to like this though.
1207 if (!(host
->quirks
& SDHCI_QUIRK_SINGLE_POWER_WRITE
))
1208 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1211 * At least the Marvell CaFe chip gets confused if we set the voltage
1212 * and set turn on power at the same time, so set the voltage first.
1214 if (host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
)
1215 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1217 pwr
|= SDHCI_POWER_ON
;
1219 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1222 * Some controllers need an extra 10ms delay of 10ms before they
1223 * can apply clock after applying power
1225 if (host
->quirks
& SDHCI_QUIRK_DELAY_AFTER_POWER
)
1231 /*****************************************************************************\
1235 \*****************************************************************************/
1237 static void sdhci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1239 struct sdhci_host
*host
;
1241 unsigned long flags
;
1243 host
= mmc_priv(mmc
);
1245 sdhci_runtime_pm_get(host
);
1247 spin_lock_irqsave(&host
->lock
, flags
);
1249 WARN_ON(host
->mrq
!= NULL
);
1251 #ifndef SDHCI_USE_LEDS_CLASS
1252 sdhci_activate_led(host
);
1256 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1257 * requests if Auto-CMD12 is enabled.
1259 if (!mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
)) {
1261 mrq
->data
->stop
= NULL
;
1268 /* If polling, assume that the card is always present. */
1269 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
1272 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
1275 if (!present
|| host
->flags
& SDHCI_DEVICE_DEAD
) {
1276 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1277 tasklet_schedule(&host
->finish_tasklet
);
1281 present_state
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
1283 * Check if the re-tuning timer has already expired and there
1284 * is no on-going data transfer. If so, we need to execute
1285 * tuning procedure before sending command.
1287 if ((host
->flags
& SDHCI_NEEDS_RETUNING
) &&
1288 !(present_state
& (SDHCI_DOING_WRITE
| SDHCI_DOING_READ
))) {
1289 spin_unlock_irqrestore(&host
->lock
, flags
);
1290 sdhci_execute_tuning(mmc
);
1291 spin_lock_irqsave(&host
->lock
, flags
);
1293 /* Restore original mmc_request structure */
1297 if (mrq
->sbc
&& !(host
->flags
& SDHCI_AUTO_CMD23
))
1298 sdhci_send_command(host
, mrq
->sbc
);
1300 sdhci_send_command(host
, mrq
->cmd
);
1304 spin_unlock_irqrestore(&host
->lock
, flags
);
1307 static void sdhci_do_set_ios(struct sdhci_host
*host
, struct mmc_ios
*ios
)
1309 unsigned long flags
;
1313 spin_lock_irqsave(&host
->lock
, flags
);
1315 if (host
->flags
& SDHCI_DEVICE_DEAD
) {
1316 spin_unlock_irqrestore(&host
->lock
, flags
);
1317 if (host
->vmmc
&& ios
->power_mode
== MMC_POWER_OFF
)
1318 mmc_regulator_set_ocr(host
->mmc
, host
->vmmc
, 0);
1323 * Reset the chip on each power off.
1324 * Should clear out any weird states.
1326 if (ios
->power_mode
== MMC_POWER_OFF
) {
1327 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
1331 sdhci_set_clock(host
, ios
->clock
);
1333 if (ios
->power_mode
== MMC_POWER_OFF
)
1334 vdd_bit
= sdhci_set_power(host
, -1);
1336 vdd_bit
= sdhci_set_power(host
, ios
->vdd
);
1338 if (host
->vmmc
&& vdd_bit
!= -1) {
1339 spin_unlock_irqrestore(&host
->lock
, flags
);
1340 mmc_regulator_set_ocr(host
->mmc
, host
->vmmc
, vdd_bit
);
1341 spin_lock_irqsave(&host
->lock
, flags
);
1344 if (host
->ops
->platform_send_init_74_clocks
)
1345 host
->ops
->platform_send_init_74_clocks(host
, ios
->power_mode
);
1348 * If your platform has 8-bit width support but is not a v3 controller,
1349 * or if it requires special setup code, you should implement that in
1350 * platform_8bit_width().
1352 if (host
->ops
->platform_8bit_width
)
1353 host
->ops
->platform_8bit_width(host
, ios
->bus_width
);
1355 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1356 if (ios
->bus_width
== MMC_BUS_WIDTH_8
) {
1357 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1358 if (host
->version
>= SDHCI_SPEC_300
)
1359 ctrl
|= SDHCI_CTRL_8BITBUS
;
1361 if (host
->version
>= SDHCI_SPEC_300
)
1362 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
1363 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
1364 ctrl
|= SDHCI_CTRL_4BITBUS
;
1366 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1368 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1371 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1373 if ((ios
->timing
== MMC_TIMING_SD_HS
||
1374 ios
->timing
== MMC_TIMING_MMC_HS
)
1375 && !(host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
))
1376 ctrl
|= SDHCI_CTRL_HISPD
;
1378 ctrl
&= ~SDHCI_CTRL_HISPD
;
1380 if (host
->version
>= SDHCI_SPEC_300
) {
1384 /* In case of UHS-I modes, set High Speed Enable */
1385 if ((ios
->timing
== MMC_TIMING_UHS_SDR50
) ||
1386 (ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1387 (ios
->timing
== MMC_TIMING_UHS_DDR50
) ||
1388 (ios
->timing
== MMC_TIMING_UHS_SDR25
) ||
1389 (ios
->timing
== MMC_TIMING_UHS_SDR12
))
1390 ctrl
|= SDHCI_CTRL_HISPD
;
1392 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1393 if (!(ctrl_2
& SDHCI_CTRL_PRESET_VAL_ENABLE
)) {
1394 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1396 * We only need to set Driver Strength if the
1397 * preset value enable is not set.
1399 ctrl_2
&= ~SDHCI_CTRL_DRV_TYPE_MASK
;
1400 if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_A
)
1401 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_A
;
1402 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_C
)
1403 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_C
;
1405 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1408 * According to SDHC Spec v3.00, if the Preset Value
1409 * Enable in the Host Control 2 register is set, we
1410 * need to reset SD Clock Enable before changing High
1411 * Speed Enable to avoid generating clock gliches.
1414 /* Reset SD Clock Enable */
1415 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1416 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1417 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1419 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1421 /* Re-enable SD Clock */
1422 clock
= host
->clock
;
1424 sdhci_set_clock(host
, clock
);
1428 /* Reset SD Clock Enable */
1429 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1430 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1431 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1433 if (host
->ops
->set_uhs_signaling
)
1434 host
->ops
->set_uhs_signaling(host
, ios
->timing
);
1436 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1437 /* Select Bus Speed Mode for host */
1438 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
1439 if (ios
->timing
== MMC_TIMING_UHS_SDR12
)
1440 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
1441 else if (ios
->timing
== MMC_TIMING_UHS_SDR25
)
1442 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
1443 else if (ios
->timing
== MMC_TIMING_UHS_SDR50
)
1444 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
1445 else if (ios
->timing
== MMC_TIMING_UHS_SDR104
)
1446 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
1447 else if (ios
->timing
== MMC_TIMING_UHS_DDR50
)
1448 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
1449 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1452 /* Re-enable SD Clock */
1453 clock
= host
->clock
;
1455 sdhci_set_clock(host
, clock
);
1457 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1460 * Some (ENE) controllers go apeshit on some ios operation,
1461 * signalling timeout and CRC errors even on CMD0. Resetting
1462 * it on each ios seems to solve the problem.
1464 if(host
->quirks
& SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
)
1465 sdhci_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
1468 spin_unlock_irqrestore(&host
->lock
, flags
);
1471 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1473 struct sdhci_host
*host
= mmc_priv(mmc
);
1475 sdhci_runtime_pm_get(host
);
1476 sdhci_do_set_ios(host
, ios
);
1477 sdhci_runtime_pm_put(host
);
1480 static int sdhci_check_ro(struct sdhci_host
*host
)
1482 unsigned long flags
;
1485 spin_lock_irqsave(&host
->lock
, flags
);
1487 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1489 else if (host
->ops
->get_ro
)
1490 is_readonly
= host
->ops
->get_ro(host
);
1492 is_readonly
= !(sdhci_readl(host
, SDHCI_PRESENT_STATE
)
1493 & SDHCI_WRITE_PROTECT
);
1495 spin_unlock_irqrestore(&host
->lock
, flags
);
1497 /* This quirk needs to be replaced by a callback-function later */
1498 return host
->quirks
& SDHCI_QUIRK_INVERTED_WRITE_PROTECT
?
1499 !is_readonly
: is_readonly
;
1502 #define SAMPLE_COUNT 5
1504 static int sdhci_do_get_ro(struct sdhci_host
*host
)
1508 if (!(host
->quirks
& SDHCI_QUIRK_UNSTABLE_RO_DETECT
))
1509 return sdhci_check_ro(host
);
1512 for (i
= 0; i
< SAMPLE_COUNT
; i
++) {
1513 if (sdhci_check_ro(host
)) {
1514 if (++ro_count
> SAMPLE_COUNT
/ 2)
1522 static void sdhci_hw_reset(struct mmc_host
*mmc
)
1524 struct sdhci_host
*host
= mmc_priv(mmc
);
1526 if (host
->ops
&& host
->ops
->hw_reset
)
1527 host
->ops
->hw_reset(host
);
1530 static int sdhci_get_ro(struct mmc_host
*mmc
)
1532 struct sdhci_host
*host
= mmc_priv(mmc
);
1535 sdhci_runtime_pm_get(host
);
1536 ret
= sdhci_do_get_ro(host
);
1537 sdhci_runtime_pm_put(host
);
1541 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host
*host
, int enable
)
1543 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1547 host
->flags
|= SDHCI_SDIO_IRQ_ENABLED
;
1549 host
->flags
&= ~SDHCI_SDIO_IRQ_ENABLED
;
1551 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1552 if (host
->runtime_suspended
)
1556 sdhci_unmask_irqs(host
, SDHCI_INT_CARD_INT
);
1558 sdhci_mask_irqs(host
, SDHCI_INT_CARD_INT
);
1563 static void sdhci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1565 struct sdhci_host
*host
= mmc_priv(mmc
);
1566 unsigned long flags
;
1568 spin_lock_irqsave(&host
->lock
, flags
);
1569 sdhci_enable_sdio_irq_nolock(host
, enable
);
1570 spin_unlock_irqrestore(&host
->lock
, flags
);
1573 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host
*host
,
1574 struct mmc_ios
*ios
)
1581 * Signal Voltage Switching is only applicable for Host Controllers
1584 if (host
->version
< SDHCI_SPEC_300
)
1588 * We first check whether the request is to set signalling voltage
1589 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1591 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1592 if (ios
->signal_voltage
== MMC_SIGNAL_VOLTAGE_330
) {
1593 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1594 ctrl
&= ~SDHCI_CTRL_VDD_180
;
1595 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1598 usleep_range(5000, 5500);
1600 /* 3.3V regulator output should be stable within 5 ms */
1601 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1602 if (!(ctrl
& SDHCI_CTRL_VDD_180
))
1605 pr_info(DRIVER_NAME
": Switching to 3.3V "
1606 "signalling voltage failed\n");
1609 } else if (!(ctrl
& SDHCI_CTRL_VDD_180
) &&
1610 (ios
->signal_voltage
== MMC_SIGNAL_VOLTAGE_180
)) {
1612 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1613 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1614 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1616 /* Check whether DAT[3:0] is 0000 */
1617 present_state
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
1618 if (!((present_state
& SDHCI_DATA_LVL_MASK
) >>
1619 SDHCI_DATA_LVL_SHIFT
)) {
1621 * Enable 1.8V Signal Enable in the Host Control2
1624 ctrl
|= SDHCI_CTRL_VDD_180
;
1625 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1628 usleep_range(5000, 5500);
1630 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1631 if (ctrl
& SDHCI_CTRL_VDD_180
) {
1632 /* Provide SDCLK again and wait for 1ms*/
1633 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1634 clk
|= SDHCI_CLOCK_CARD_EN
;
1635 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1636 usleep_range(1000, 1500);
1639 * If DAT[3:0] level is 1111b, then the card
1640 * was successfully switched to 1.8V signaling.
1642 present_state
= sdhci_readl(host
,
1643 SDHCI_PRESENT_STATE
);
1644 if ((present_state
& SDHCI_DATA_LVL_MASK
) ==
1645 SDHCI_DATA_LVL_MASK
)
1651 * If we are here, that means the switch to 1.8V signaling
1652 * failed. We power cycle the card, and retry initialization
1653 * sequence by setting S18R to 0.
1655 pwr
= sdhci_readb(host
, SDHCI_POWER_CONTROL
);
1656 pwr
&= ~SDHCI_POWER_ON
;
1657 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1659 /* Wait for 1ms as per the spec */
1660 usleep_range(1000, 1500);
1661 pwr
|= SDHCI_POWER_ON
;
1662 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1664 pr_info(DRIVER_NAME
": Switching to 1.8V signalling "
1665 "voltage failed, retrying with S18R set to 0\n");
1668 /* No signal voltage switch required */
1672 static int sdhci_start_signal_voltage_switch(struct mmc_host
*mmc
,
1673 struct mmc_ios
*ios
)
1675 struct sdhci_host
*host
= mmc_priv(mmc
);
1678 if (host
->version
< SDHCI_SPEC_300
)
1680 sdhci_runtime_pm_get(host
);
1681 err
= sdhci_do_start_signal_voltage_switch(host
, ios
);
1682 sdhci_runtime_pm_put(host
);
1686 static int sdhci_execute_tuning(struct mmc_host
*mmc
)
1688 struct sdhci_host
*host
;
1691 int tuning_loop_counter
= MAX_TUNING_LOOP
;
1692 unsigned long timeout
;
1695 host
= mmc_priv(mmc
);
1697 sdhci_runtime_pm_get(host
);
1698 disable_irq(host
->irq
);
1699 spin_lock(&host
->lock
);
1701 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1704 * Host Controller needs tuning only in case of SDR104 mode
1705 * and for SDR50 mode when Use Tuning for SDR50 is set in
1706 * Capabilities register.
1708 if (((ctrl
& SDHCI_CTRL_UHS_MASK
) == SDHCI_CTRL_UHS_SDR104
) ||
1709 (((ctrl
& SDHCI_CTRL_UHS_MASK
) == SDHCI_CTRL_UHS_SDR50
) &&
1710 (host
->flags
& SDHCI_SDR50_NEEDS_TUNING
)))
1711 ctrl
|= SDHCI_CTRL_EXEC_TUNING
;
1713 spin_unlock(&host
->lock
);
1714 enable_irq(host
->irq
);
1715 sdhci_runtime_pm_put(host
);
1719 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1722 * As per the Host Controller spec v3.00, tuning command
1723 * generates Buffer Read Ready interrupt, so enable that.
1725 * Note: The spec clearly says that when tuning sequence
1726 * is being performed, the controller does not generate
1727 * interrupts other than Buffer Read Ready interrupt. But
1728 * to make sure we don't hit a controller bug, we _only_
1729 * enable Buffer Read Ready interrupt here.
1731 ier
= sdhci_readl(host
, SDHCI_INT_ENABLE
);
1732 sdhci_clear_set_irqs(host
, ier
, SDHCI_INT_DATA_AVAIL
);
1735 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1736 * of loops reaches 40 times or a timeout of 150ms occurs.
1740 struct mmc_command cmd
= {0};
1741 struct mmc_request mrq
= {NULL
};
1743 if (!tuning_loop_counter
&& !timeout
)
1746 cmd
.opcode
= MMC_SEND_TUNING_BLOCK
;
1748 cmd
.flags
= MMC_RSP_R1
| MMC_CMD_ADTC
;
1757 * In response to CMD19, the card sends 64 bytes of tuning
1758 * block to the Host Controller. So we set the block size
1761 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE
);
1764 * The tuning block is sent by the card to the host controller.
1765 * So we set the TRNS_READ bit in the Transfer Mode register.
1766 * This also takes care of setting DMA Enable and Multi Block
1767 * Select in the same register to 0.
1769 sdhci_writew(host
, SDHCI_TRNS_READ
, SDHCI_TRANSFER_MODE
);
1771 sdhci_send_command(host
, &cmd
);
1776 spin_unlock(&host
->lock
);
1777 enable_irq(host
->irq
);
1779 /* Wait for Buffer Read Ready interrupt */
1780 wait_event_interruptible_timeout(host
->buf_ready_int
,
1781 (host
->tuning_done
== 1),
1782 msecs_to_jiffies(50));
1783 disable_irq(host
->irq
);
1784 spin_lock(&host
->lock
);
1786 if (!host
->tuning_done
) {
1787 pr_info(DRIVER_NAME
": Timeout waiting for "
1788 "Buffer Read Ready interrupt during tuning "
1789 "procedure, falling back to fixed sampling "
1791 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1792 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
1793 ctrl
&= ~SDHCI_CTRL_EXEC_TUNING
;
1794 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1800 host
->tuning_done
= 0;
1802 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1803 tuning_loop_counter
--;
1806 } while (ctrl
& SDHCI_CTRL_EXEC_TUNING
);
1809 * The Host Driver has exhausted the maximum number of loops allowed,
1810 * so use fixed sampling frequency.
1812 if (!tuning_loop_counter
|| !timeout
) {
1813 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
1814 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1816 if (!(ctrl
& SDHCI_CTRL_TUNED_CLK
)) {
1817 pr_info(DRIVER_NAME
": Tuning procedure"
1818 " failed, falling back to fixed sampling"
1826 * If this is the very first time we are here, we start the retuning
1827 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1828 * flag won't be set, we check this condition before actually starting
1831 if (!(host
->flags
& SDHCI_NEEDS_RETUNING
) && host
->tuning_count
&&
1832 (host
->tuning_mode
== SDHCI_TUNING_MODE_1
)) {
1833 mod_timer(&host
->tuning_timer
, jiffies
+
1834 host
->tuning_count
* HZ
);
1835 /* Tuning mode 1 limits the maximum data length to 4MB */
1836 mmc
->max_blk_count
= (4 * 1024 * 1024) / mmc
->max_blk_size
;
1838 host
->flags
&= ~SDHCI_NEEDS_RETUNING
;
1839 /* Reload the new initial value for timer */
1840 if (host
->tuning_mode
== SDHCI_TUNING_MODE_1
)
1841 mod_timer(&host
->tuning_timer
, jiffies
+
1842 host
->tuning_count
* HZ
);
1846 * In case tuning fails, host controllers which support re-tuning can
1847 * try tuning again at a later time, when the re-tuning timer expires.
1848 * So for these controllers, we return 0. Since there might be other
1849 * controllers who do not have this capability, we return error for
1852 if (err
&& host
->tuning_count
&&
1853 host
->tuning_mode
== SDHCI_TUNING_MODE_1
)
1856 sdhci_clear_set_irqs(host
, SDHCI_INT_DATA_AVAIL
, ier
);
1857 spin_unlock(&host
->lock
);
1858 enable_irq(host
->irq
);
1859 sdhci_runtime_pm_put(host
);
1864 static void sdhci_do_enable_preset_value(struct sdhci_host
*host
, bool enable
)
1867 unsigned long flags
;
1869 /* Host Controller v3.00 defines preset value registers */
1870 if (host
->version
< SDHCI_SPEC_300
)
1873 spin_lock_irqsave(&host
->lock
, flags
);
1875 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1878 * We only enable or disable Preset Value if they are not already
1879 * enabled or disabled respectively. Otherwise, we bail out.
1881 if (enable
&& !(ctrl
& SDHCI_CTRL_PRESET_VAL_ENABLE
)) {
1882 ctrl
|= SDHCI_CTRL_PRESET_VAL_ENABLE
;
1883 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1884 host
->flags
|= SDHCI_PV_ENABLED
;
1885 } else if (!enable
&& (ctrl
& SDHCI_CTRL_PRESET_VAL_ENABLE
)) {
1886 ctrl
&= ~SDHCI_CTRL_PRESET_VAL_ENABLE
;
1887 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1888 host
->flags
&= ~SDHCI_PV_ENABLED
;
1891 spin_unlock_irqrestore(&host
->lock
, flags
);
1894 static void sdhci_enable_preset_value(struct mmc_host
*mmc
, bool enable
)
1896 struct sdhci_host
*host
= mmc_priv(mmc
);
1898 sdhci_runtime_pm_get(host
);
1899 sdhci_do_enable_preset_value(host
, enable
);
1900 sdhci_runtime_pm_put(host
);
1903 static const struct mmc_host_ops sdhci_ops
= {
1904 .request
= sdhci_request
,
1905 .set_ios
= sdhci_set_ios
,
1906 .get_ro
= sdhci_get_ro
,
1907 .hw_reset
= sdhci_hw_reset
,
1908 .enable_sdio_irq
= sdhci_enable_sdio_irq
,
1909 .start_signal_voltage_switch
= sdhci_start_signal_voltage_switch
,
1910 .execute_tuning
= sdhci_execute_tuning
,
1911 .enable_preset_value
= sdhci_enable_preset_value
,
1914 /*****************************************************************************\
1918 \*****************************************************************************/
1920 static void sdhci_tasklet_card(unsigned long param
)
1922 struct sdhci_host
*host
;
1923 unsigned long flags
;
1925 host
= (struct sdhci_host
*)param
;
1927 spin_lock_irqsave(&host
->lock
, flags
);
1929 /* Check host->mrq first in case we are runtime suspended */
1931 !(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
)) {
1932 pr_err("%s: Card removed during transfer!\n",
1933 mmc_hostname(host
->mmc
));
1934 pr_err("%s: Resetting controller.\n",
1935 mmc_hostname(host
->mmc
));
1937 sdhci_reset(host
, SDHCI_RESET_CMD
);
1938 sdhci_reset(host
, SDHCI_RESET_DATA
);
1940 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1941 tasklet_schedule(&host
->finish_tasklet
);
1944 spin_unlock_irqrestore(&host
->lock
, flags
);
1946 mmc_detect_change(host
->mmc
, msecs_to_jiffies(200));
1949 static void sdhci_tasklet_finish(unsigned long param
)
1951 struct sdhci_host
*host
;
1952 unsigned long flags
;
1953 struct mmc_request
*mrq
;
1955 host
= (struct sdhci_host
*)param
;
1957 spin_lock_irqsave(&host
->lock
, flags
);
1960 * If this tasklet gets rescheduled while running, it will
1961 * be run again afterwards but without any active request.
1964 spin_unlock_irqrestore(&host
->lock
, flags
);
1968 del_timer(&host
->timer
);
1973 * The controller needs a reset of internal state machines
1974 * upon error conditions.
1976 if (!(host
->flags
& SDHCI_DEVICE_DEAD
) &&
1977 ((mrq
->cmd
&& mrq
->cmd
->error
) ||
1978 (mrq
->data
&& (mrq
->data
->error
||
1979 (mrq
->data
->stop
&& mrq
->data
->stop
->error
))) ||
1980 (host
->quirks
& SDHCI_QUIRK_RESET_AFTER_REQUEST
))) {
1982 /* Some controllers need this kick or reset won't work here */
1983 if (host
->quirks
& SDHCI_QUIRK_CLOCK_BEFORE_RESET
) {
1986 /* This is to force an update */
1987 clock
= host
->clock
;
1989 sdhci_set_clock(host
, clock
);
1992 /* Spec says we should do both at the same time, but Ricoh
1993 controllers do not like that. */
1994 sdhci_reset(host
, SDHCI_RESET_CMD
);
1995 sdhci_reset(host
, SDHCI_RESET_DATA
);
2002 #ifndef SDHCI_USE_LEDS_CLASS
2003 sdhci_deactivate_led(host
);
2007 spin_unlock_irqrestore(&host
->lock
, flags
);
2009 mmc_request_done(host
->mmc
, mrq
);
2010 sdhci_runtime_pm_put(host
);
2013 static void sdhci_timeout_timer(unsigned long data
)
2015 struct sdhci_host
*host
;
2016 unsigned long flags
;
2018 host
= (struct sdhci_host
*)data
;
2020 spin_lock_irqsave(&host
->lock
, flags
);
2023 pr_err("%s: Timeout waiting for hardware "
2024 "interrupt.\n", mmc_hostname(host
->mmc
));
2025 sdhci_dumpregs(host
);
2028 host
->data
->error
= -ETIMEDOUT
;
2029 sdhci_finish_data(host
);
2032 host
->cmd
->error
= -ETIMEDOUT
;
2034 host
->mrq
->cmd
->error
= -ETIMEDOUT
;
2036 tasklet_schedule(&host
->finish_tasklet
);
2041 spin_unlock_irqrestore(&host
->lock
, flags
);
2044 static void sdhci_tuning_timer(unsigned long data
)
2046 struct sdhci_host
*host
;
2047 unsigned long flags
;
2049 host
= (struct sdhci_host
*)data
;
2051 spin_lock_irqsave(&host
->lock
, flags
);
2053 host
->flags
|= SDHCI_NEEDS_RETUNING
;
2055 spin_unlock_irqrestore(&host
->lock
, flags
);
2058 /*****************************************************************************\
2060 * Interrupt handling *
2062 \*****************************************************************************/
2064 static void sdhci_cmd_irq(struct sdhci_host
*host
, u32 intmask
)
2066 BUG_ON(intmask
== 0);
2069 pr_err("%s: Got command interrupt 0x%08x even "
2070 "though no command operation was in progress.\n",
2071 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2072 sdhci_dumpregs(host
);
2076 if (intmask
& SDHCI_INT_TIMEOUT
)
2077 host
->cmd
->error
= -ETIMEDOUT
;
2078 else if (intmask
& (SDHCI_INT_CRC
| SDHCI_INT_END_BIT
|
2080 host
->cmd
->error
= -EILSEQ
;
2082 if (host
->cmd
->error
) {
2083 tasklet_schedule(&host
->finish_tasklet
);
2088 * The host can send and interrupt when the busy state has
2089 * ended, allowing us to wait without wasting CPU cycles.
2090 * Unfortunately this is overloaded on the "data complete"
2091 * interrupt, so we need to take some care when handling
2094 * Note: The 1.0 specification is a bit ambiguous about this
2095 * feature so there might be some problems with older
2098 if (host
->cmd
->flags
& MMC_RSP_BUSY
) {
2099 if (host
->cmd
->data
)
2100 DBG("Cannot wait for busy signal when also "
2101 "doing a data transfer");
2102 else if (!(host
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
))
2105 /* The controller does not support the end-of-busy IRQ,
2106 * fall through and take the SDHCI_INT_RESPONSE */
2109 if (intmask
& SDHCI_INT_RESPONSE
)
2110 sdhci_finish_command(host
);
2113 #ifdef CONFIG_MMC_DEBUG
2114 static void sdhci_show_adma_error(struct sdhci_host
*host
)
2116 const char *name
= mmc_hostname(host
->mmc
);
2117 u8
*desc
= host
->adma_desc
;
2122 sdhci_dumpregs(host
);
2125 dma
= (__le32
*)(desc
+ 4);
2126 len
= (__le16
*)(desc
+ 2);
2129 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2130 name
, desc
, le32_to_cpu(*dma
), le16_to_cpu(*len
), attr
);
2139 static void sdhci_show_adma_error(struct sdhci_host
*host
) { }
2142 static void sdhci_data_irq(struct sdhci_host
*host
, u32 intmask
)
2144 BUG_ON(intmask
== 0);
2146 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2147 if (intmask
& SDHCI_INT_DATA_AVAIL
) {
2148 if (SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
)) ==
2149 MMC_SEND_TUNING_BLOCK
) {
2150 host
->tuning_done
= 1;
2151 wake_up(&host
->buf_ready_int
);
2158 * The "data complete" interrupt is also used to
2159 * indicate that a busy state has ended. See comment
2160 * above in sdhci_cmd_irq().
2162 if (host
->cmd
&& (host
->cmd
->flags
& MMC_RSP_BUSY
)) {
2163 if (intmask
& SDHCI_INT_DATA_END
) {
2164 sdhci_finish_command(host
);
2169 pr_err("%s: Got data interrupt 0x%08x even "
2170 "though no data operation was in progress.\n",
2171 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2172 sdhci_dumpregs(host
);
2177 if (intmask
& SDHCI_INT_DATA_TIMEOUT
)
2178 host
->data
->error
= -ETIMEDOUT
;
2179 else if (intmask
& SDHCI_INT_DATA_END_BIT
)
2180 host
->data
->error
= -EILSEQ
;
2181 else if ((intmask
& SDHCI_INT_DATA_CRC
) &&
2182 SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
))
2184 host
->data
->error
= -EILSEQ
;
2185 else if (intmask
& SDHCI_INT_ADMA_ERROR
) {
2186 pr_err("%s: ADMA error\n", mmc_hostname(host
->mmc
));
2187 sdhci_show_adma_error(host
);
2188 host
->data
->error
= -EIO
;
2191 if (host
->data
->error
)
2192 sdhci_finish_data(host
);
2194 if (intmask
& (SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
))
2195 sdhci_transfer_pio(host
);
2198 * We currently don't do anything fancy with DMA
2199 * boundaries, but as we can't disable the feature
2200 * we need to at least restart the transfer.
2202 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2203 * should return a valid address to continue from, but as
2204 * some controllers are faulty, don't trust them.
2206 if (intmask
& SDHCI_INT_DMA_END
) {
2207 u32 dmastart
, dmanow
;
2208 dmastart
= sg_dma_address(host
->data
->sg
);
2209 dmanow
= dmastart
+ host
->data
->bytes_xfered
;
2211 * Force update to the next DMA block boundary.
2214 ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1)) +
2215 SDHCI_DEFAULT_BOUNDARY_SIZE
;
2216 host
->data
->bytes_xfered
= dmanow
- dmastart
;
2217 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2219 mmc_hostname(host
->mmc
), dmastart
,
2220 host
->data
->bytes_xfered
, dmanow
);
2221 sdhci_writel(host
, dmanow
, SDHCI_DMA_ADDRESS
);
2224 if (intmask
& SDHCI_INT_DATA_END
) {
2227 * Data managed to finish before the
2228 * command completed. Make sure we do
2229 * things in the proper order.
2231 host
->data_early
= 1;
2233 sdhci_finish_data(host
);
2239 static irqreturn_t
sdhci_irq(int irq
, void *dev_id
)
2242 struct sdhci_host
*host
= dev_id
;
2246 spin_lock(&host
->lock
);
2248 if (host
->runtime_suspended
) {
2249 spin_unlock(&host
->lock
);
2250 pr_warning("%s: got irq while runtime suspended\n",
2251 mmc_hostname(host
->mmc
));
2255 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2257 if (!intmask
|| intmask
== 0xffffffff) {
2262 DBG("*** %s got interrupt: 0x%08x\n",
2263 mmc_hostname(host
->mmc
), intmask
);
2265 if (intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2266 u32 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
2270 * There is a observation on i.mx esdhc. INSERT bit will be
2271 * immediately set again when it gets cleared, if a card is
2272 * inserted. We have to mask the irq to prevent interrupt
2273 * storm which will freeze the system. And the REMOVE gets
2274 * the same situation.
2276 * More testing are needed here to ensure it works for other
2279 sdhci_mask_irqs(host
, present
? SDHCI_INT_CARD_INSERT
:
2280 SDHCI_INT_CARD_REMOVE
);
2281 sdhci_unmask_irqs(host
, present
? SDHCI_INT_CARD_REMOVE
:
2282 SDHCI_INT_CARD_INSERT
);
2284 sdhci_writel(host
, intmask
& (SDHCI_INT_CARD_INSERT
|
2285 SDHCI_INT_CARD_REMOVE
), SDHCI_INT_STATUS
);
2286 intmask
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
);
2287 tasklet_schedule(&host
->card_tasklet
);
2290 if (intmask
& SDHCI_INT_CMD_MASK
) {
2291 sdhci_writel(host
, intmask
& SDHCI_INT_CMD_MASK
,
2293 sdhci_cmd_irq(host
, intmask
& SDHCI_INT_CMD_MASK
);
2296 if (intmask
& SDHCI_INT_DATA_MASK
) {
2297 sdhci_writel(host
, intmask
& SDHCI_INT_DATA_MASK
,
2299 sdhci_data_irq(host
, intmask
& SDHCI_INT_DATA_MASK
);
2302 intmask
&= ~(SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
);
2304 intmask
&= ~SDHCI_INT_ERROR
;
2306 if (intmask
& SDHCI_INT_BUS_POWER
) {
2307 pr_err("%s: Card is consuming too much power!\n",
2308 mmc_hostname(host
->mmc
));
2309 sdhci_writel(host
, SDHCI_INT_BUS_POWER
, SDHCI_INT_STATUS
);
2312 intmask
&= ~SDHCI_INT_BUS_POWER
;
2314 if (intmask
& SDHCI_INT_CARD_INT
)
2317 intmask
&= ~SDHCI_INT_CARD_INT
;
2320 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2321 mmc_hostname(host
->mmc
), intmask
);
2322 sdhci_dumpregs(host
);
2324 sdhci_writel(host
, intmask
, SDHCI_INT_STATUS
);
2327 result
= IRQ_HANDLED
;
2331 spin_unlock(&host
->lock
);
2334 * We have to delay this as it calls back into the driver.
2337 mmc_signal_sdio_irq(host
->mmc
);
2342 /*****************************************************************************\
2346 \*****************************************************************************/
2350 int sdhci_suspend_host(struct sdhci_host
*host
)
2354 sdhci_disable_card_detection(host
);
2356 /* Disable tuning since we are suspending */
2357 if (host
->version
>= SDHCI_SPEC_300
&& host
->tuning_count
&&
2358 host
->tuning_mode
== SDHCI_TUNING_MODE_1
) {
2359 host
->flags
&= ~SDHCI_NEEDS_RETUNING
;
2360 mod_timer(&host
->tuning_timer
, jiffies
+
2361 host
->tuning_count
* HZ
);
2364 ret
= mmc_suspend_host(host
->mmc
);
2368 free_irq(host
->irq
, host
);
2373 EXPORT_SYMBOL_GPL(sdhci_suspend_host
);
2375 int sdhci_resume_host(struct sdhci_host
*host
)
2379 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2380 if (host
->ops
->enable_dma
)
2381 host
->ops
->enable_dma(host
);
2384 ret
= request_irq(host
->irq
, sdhci_irq
, IRQF_SHARED
,
2385 mmc_hostname(host
->mmc
), host
);
2389 sdhci_init(host
, (host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
));
2392 ret
= mmc_resume_host(host
->mmc
);
2393 sdhci_enable_card_detection(host
);
2395 /* Set the re-tuning expiration flag */
2396 if ((host
->version
>= SDHCI_SPEC_300
) && host
->tuning_count
&&
2397 (host
->tuning_mode
== SDHCI_TUNING_MODE_1
))
2398 host
->flags
|= SDHCI_NEEDS_RETUNING
;
2403 EXPORT_SYMBOL_GPL(sdhci_resume_host
);
2405 void sdhci_enable_irq_wakeups(struct sdhci_host
*host
)
2408 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2409 val
|= SDHCI_WAKE_ON_INT
;
2410 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2413 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups
);
2415 #endif /* CONFIG_PM */
2417 #ifdef CONFIG_PM_RUNTIME
2419 static int sdhci_runtime_pm_get(struct sdhci_host
*host
)
2421 return pm_runtime_get_sync(host
->mmc
->parent
);
2424 static int sdhci_runtime_pm_put(struct sdhci_host
*host
)
2426 pm_runtime_mark_last_busy(host
->mmc
->parent
);
2427 return pm_runtime_put_autosuspend(host
->mmc
->parent
);
2430 int sdhci_runtime_suspend_host(struct sdhci_host
*host
)
2432 unsigned long flags
;
2435 /* Disable tuning since we are suspending */
2436 if (host
->version
>= SDHCI_SPEC_300
&&
2437 host
->tuning_mode
== SDHCI_TUNING_MODE_1
) {
2438 del_timer_sync(&host
->tuning_timer
);
2439 host
->flags
&= ~SDHCI_NEEDS_RETUNING
;
2442 spin_lock_irqsave(&host
->lock
, flags
);
2443 sdhci_mask_irqs(host
, SDHCI_INT_ALL_MASK
);
2444 spin_unlock_irqrestore(&host
->lock
, flags
);
2446 synchronize_irq(host
->irq
);
2448 spin_lock_irqsave(&host
->lock
, flags
);
2449 host
->runtime_suspended
= true;
2450 spin_unlock_irqrestore(&host
->lock
, flags
);
2454 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host
);
2456 int sdhci_runtime_resume_host(struct sdhci_host
*host
)
2458 unsigned long flags
;
2459 int ret
= 0, host_flags
= host
->flags
;
2461 if (host_flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2462 if (host
->ops
->enable_dma
)
2463 host
->ops
->enable_dma(host
);
2466 sdhci_init(host
, 0);
2468 /* Force clock and power re-program */
2471 sdhci_do_set_ios(host
, &host
->mmc
->ios
);
2473 sdhci_do_start_signal_voltage_switch(host
, &host
->mmc
->ios
);
2474 if (host_flags
& SDHCI_PV_ENABLED
)
2475 sdhci_do_enable_preset_value(host
, true);
2477 /* Set the re-tuning expiration flag */
2478 if ((host
->version
>= SDHCI_SPEC_300
) && host
->tuning_count
&&
2479 (host
->tuning_mode
== SDHCI_TUNING_MODE_1
))
2480 host
->flags
|= SDHCI_NEEDS_RETUNING
;
2482 spin_lock_irqsave(&host
->lock
, flags
);
2484 host
->runtime_suspended
= false;
2486 /* Enable SDIO IRQ */
2487 if ((host
->flags
& SDHCI_SDIO_IRQ_ENABLED
))
2488 sdhci_enable_sdio_irq_nolock(host
, true);
2490 /* Enable Card Detection */
2491 sdhci_enable_card_detection(host
);
2493 spin_unlock_irqrestore(&host
->lock
, flags
);
2497 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host
);
2501 /*****************************************************************************\
2503 * Device allocation/registration *
2505 \*****************************************************************************/
2507 struct sdhci_host
*sdhci_alloc_host(struct device
*dev
,
2510 struct mmc_host
*mmc
;
2511 struct sdhci_host
*host
;
2513 WARN_ON(dev
== NULL
);
2515 mmc
= mmc_alloc_host(sizeof(struct sdhci_host
) + priv_size
, dev
);
2517 return ERR_PTR(-ENOMEM
);
2519 host
= mmc_priv(mmc
);
2525 EXPORT_SYMBOL_GPL(sdhci_alloc_host
);
2527 int sdhci_add_host(struct sdhci_host
*host
)
2529 struct mmc_host
*mmc
;
2531 u32 max_current_caps
;
2532 unsigned int ocr_avail
;
2535 WARN_ON(host
== NULL
);
2542 host
->quirks
= debug_quirks
;
2544 host
->quirks2
= debug_quirks2
;
2546 sdhci_reset(host
, SDHCI_RESET_ALL
);
2548 host
->version
= sdhci_readw(host
, SDHCI_HOST_VERSION
);
2549 host
->version
= (host
->version
& SDHCI_SPEC_VER_MASK
)
2550 >> SDHCI_SPEC_VER_SHIFT
;
2551 if (host
->version
> SDHCI_SPEC_300
) {
2552 pr_err("%s: Unknown controller version (%d). "
2553 "You may experience problems.\n", mmc_hostname(mmc
),
2557 caps
[0] = (host
->quirks
& SDHCI_QUIRK_MISSING_CAPS
) ? host
->caps
:
2558 sdhci_readl(host
, SDHCI_CAPABILITIES
);
2560 caps
[1] = (host
->version
>= SDHCI_SPEC_300
) ?
2561 sdhci_readl(host
, SDHCI_CAPABILITIES_1
) : 0;
2563 if (host
->quirks
& SDHCI_QUIRK_FORCE_DMA
)
2564 host
->flags
|= SDHCI_USE_SDMA
;
2565 else if (!(caps
[0] & SDHCI_CAN_DO_SDMA
))
2566 DBG("Controller doesn't have SDMA capability\n");
2568 host
->flags
|= SDHCI_USE_SDMA
;
2570 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_DMA
) &&
2571 (host
->flags
& SDHCI_USE_SDMA
)) {
2572 DBG("Disabling DMA as it is marked broken\n");
2573 host
->flags
&= ~SDHCI_USE_SDMA
;
2576 if ((host
->version
>= SDHCI_SPEC_200
) &&
2577 (caps
[0] & SDHCI_CAN_DO_ADMA2
))
2578 host
->flags
|= SDHCI_USE_ADMA
;
2580 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA
) &&
2581 (host
->flags
& SDHCI_USE_ADMA
)) {
2582 DBG("Disabling ADMA as it is marked broken\n");
2583 host
->flags
&= ~SDHCI_USE_ADMA
;
2586 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2587 if (host
->ops
->enable_dma
) {
2588 if (host
->ops
->enable_dma(host
)) {
2589 pr_warning("%s: No suitable DMA "
2590 "available. Falling back to PIO.\n",
2593 ~(SDHCI_USE_SDMA
| SDHCI_USE_ADMA
);
2598 if (host
->flags
& SDHCI_USE_ADMA
) {
2600 * We need to allocate descriptors for all sg entries
2601 * (128) and potentially one alignment transfer for
2602 * each of those entries.
2604 host
->adma_desc
= kmalloc((128 * 2 + 1) * 4, GFP_KERNEL
);
2605 host
->align_buffer
= kmalloc(128 * 4, GFP_KERNEL
);
2606 if (!host
->adma_desc
|| !host
->align_buffer
) {
2607 kfree(host
->adma_desc
);
2608 kfree(host
->align_buffer
);
2609 pr_warning("%s: Unable to allocate ADMA "
2610 "buffers. Falling back to standard DMA.\n",
2612 host
->flags
&= ~SDHCI_USE_ADMA
;
2617 * If we use DMA, then it's up to the caller to set the DMA
2618 * mask, but PIO does not need the hw shim so we set a new
2619 * mask here in that case.
2621 if (!(host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))) {
2622 host
->dma_mask
= DMA_BIT_MASK(64);
2623 mmc_dev(host
->mmc
)->dma_mask
= &host
->dma_mask
;
2626 if (host
->version
>= SDHCI_SPEC_300
)
2627 host
->max_clk
= (caps
[0] & SDHCI_CLOCK_V3_BASE_MASK
)
2628 >> SDHCI_CLOCK_BASE_SHIFT
;
2630 host
->max_clk
= (caps
[0] & SDHCI_CLOCK_BASE_MASK
)
2631 >> SDHCI_CLOCK_BASE_SHIFT
;
2633 host
->max_clk
*= 1000000;
2634 if (host
->max_clk
== 0 || host
->quirks
&
2635 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
) {
2636 if (!host
->ops
->get_max_clock
) {
2637 pr_err("%s: Hardware doesn't specify base clock "
2638 "frequency.\n", mmc_hostname(mmc
));
2641 host
->max_clk
= host
->ops
->get_max_clock(host
);
2645 * In case of Host Controller v3.00, find out whether clock
2646 * multiplier is supported.
2648 host
->clk_mul
= (caps
[1] & SDHCI_CLOCK_MUL_MASK
) >>
2649 SDHCI_CLOCK_MUL_SHIFT
;
2652 * In case the value in Clock Multiplier is 0, then programmable
2653 * clock mode is not supported, otherwise the actual clock
2654 * multiplier is one more than the value of Clock Multiplier
2655 * in the Capabilities Register.
2661 * Set host parameters.
2663 mmc
->ops
= &sdhci_ops
;
2664 mmc
->f_max
= host
->max_clk
;
2665 if (host
->ops
->get_min_clock
)
2666 mmc
->f_min
= host
->ops
->get_min_clock(host
);
2667 else if (host
->version
>= SDHCI_SPEC_300
) {
2668 if (host
->clk_mul
) {
2669 mmc
->f_min
= (host
->max_clk
* host
->clk_mul
) / 1024;
2670 mmc
->f_max
= host
->max_clk
* host
->clk_mul
;
2672 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_300
;
2674 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_200
;
2677 (caps
[0] & SDHCI_TIMEOUT_CLK_MASK
) >> SDHCI_TIMEOUT_CLK_SHIFT
;
2678 if (host
->timeout_clk
== 0) {
2679 if (host
->ops
->get_timeout_clock
) {
2680 host
->timeout_clk
= host
->ops
->get_timeout_clock(host
);
2681 } else if (!(host
->quirks
&
2682 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
)) {
2683 pr_err("%s: Hardware doesn't specify timeout clock "
2684 "frequency.\n", mmc_hostname(mmc
));
2688 if (caps
[0] & SDHCI_TIMEOUT_CLK_UNIT
)
2689 host
->timeout_clk
*= 1000;
2691 if (host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
)
2692 host
->timeout_clk
= mmc
->f_max
/ 1000;
2694 mmc
->max_discard_to
= (1 << 27) / host
->timeout_clk
;
2696 mmc
->caps
|= MMC_CAP_SDIO_IRQ
| MMC_CAP_ERASE
| MMC_CAP_CMD23
;
2698 if (host
->quirks
& SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12
)
2699 host
->flags
|= SDHCI_AUTO_CMD12
;
2701 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2702 if ((host
->version
>= SDHCI_SPEC_300
) &&
2703 ((host
->flags
& SDHCI_USE_ADMA
) ||
2704 !(host
->flags
& SDHCI_USE_SDMA
))) {
2705 host
->flags
|= SDHCI_AUTO_CMD23
;
2706 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc
));
2708 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc
));
2712 * A controller may support 8-bit width, but the board itself
2713 * might not have the pins brought out. Boards that support
2714 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2715 * their platform code before calling sdhci_add_host(), and we
2716 * won't assume 8-bit width for hosts without that CAP.
2718 if (!(host
->quirks
& SDHCI_QUIRK_FORCE_1_BIT_DATA
))
2719 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
2721 if (caps
[0] & SDHCI_CAN_DO_HISPD
)
2722 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
;
2724 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) &&
2725 mmc_card_is_removable(mmc
))
2726 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
2728 /* UHS-I mode(s) supported by the host controller. */
2729 if (host
->version
>= SDHCI_SPEC_300
)
2730 mmc
->caps
|= MMC_CAP_UHS_SDR12
| MMC_CAP_UHS_SDR25
;
2732 /* SDR104 supports also implies SDR50 support */
2733 if (caps
[1] & SDHCI_SUPPORT_SDR104
)
2734 mmc
->caps
|= MMC_CAP_UHS_SDR104
| MMC_CAP_UHS_SDR50
;
2735 else if (caps
[1] & SDHCI_SUPPORT_SDR50
)
2736 mmc
->caps
|= MMC_CAP_UHS_SDR50
;
2738 if (caps
[1] & SDHCI_SUPPORT_DDR50
)
2739 mmc
->caps
|= MMC_CAP_UHS_DDR50
;
2741 /* Does the host needs tuning for SDR50? */
2742 if (caps
[1] & SDHCI_USE_SDR50_TUNING
)
2743 host
->flags
|= SDHCI_SDR50_NEEDS_TUNING
;
2745 /* Driver Type(s) (A, C, D) supported by the host */
2746 if (caps
[1] & SDHCI_DRIVER_TYPE_A
)
2747 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_A
;
2748 if (caps
[1] & SDHCI_DRIVER_TYPE_C
)
2749 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_C
;
2750 if (caps
[1] & SDHCI_DRIVER_TYPE_D
)
2751 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_D
;
2754 * If Power Off Notify capability is enabled by the host,
2755 * set notify to short power off notify timeout value.
2757 if (mmc
->caps2
& MMC_CAP2_POWEROFF_NOTIFY
)
2758 mmc
->power_notify_type
= MMC_HOST_PW_NOTIFY_SHORT
;
2760 mmc
->power_notify_type
= MMC_HOST_PW_NOTIFY_NONE
;
2762 /* Initial value for re-tuning timer count */
2763 host
->tuning_count
= (caps
[1] & SDHCI_RETUNING_TIMER_COUNT_MASK
) >>
2764 SDHCI_RETUNING_TIMER_COUNT_SHIFT
;
2767 * In case Re-tuning Timer is not disabled, the actual value of
2768 * re-tuning timer will be 2 ^ (n - 1).
2770 if (host
->tuning_count
)
2771 host
->tuning_count
= 1 << (host
->tuning_count
- 1);
2773 /* Re-tuning mode supported by the Host Controller */
2774 host
->tuning_mode
= (caps
[1] & SDHCI_RETUNING_MODE_MASK
) >>
2775 SDHCI_RETUNING_MODE_SHIFT
;
2779 * According to SD Host Controller spec v3.00, if the Host System
2780 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2781 * the value is meaningful only if Voltage Support in the Capabilities
2782 * register is set. The actual current value is 4 times the register
2785 max_current_caps
= sdhci_readl(host
, SDHCI_MAX_CURRENT
);
2787 if (caps
[0] & SDHCI_CAN_VDD_330
) {
2788 int max_current_330
;
2790 ocr_avail
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
2792 max_current_330
= ((max_current_caps
&
2793 SDHCI_MAX_CURRENT_330_MASK
) >>
2794 SDHCI_MAX_CURRENT_330_SHIFT
) *
2795 SDHCI_MAX_CURRENT_MULTIPLIER
;
2797 if (max_current_330
> 150)
2798 mmc
->caps
|= MMC_CAP_SET_XPC_330
;
2800 if (caps
[0] & SDHCI_CAN_VDD_300
) {
2801 int max_current_300
;
2803 ocr_avail
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
2805 max_current_300
= ((max_current_caps
&
2806 SDHCI_MAX_CURRENT_300_MASK
) >>
2807 SDHCI_MAX_CURRENT_300_SHIFT
) *
2808 SDHCI_MAX_CURRENT_MULTIPLIER
;
2810 if (max_current_300
> 150)
2811 mmc
->caps
|= MMC_CAP_SET_XPC_300
;
2813 if (caps
[0] & SDHCI_CAN_VDD_180
) {
2814 int max_current_180
;
2816 ocr_avail
|= MMC_VDD_165_195
;
2818 max_current_180
= ((max_current_caps
&
2819 SDHCI_MAX_CURRENT_180_MASK
) >>
2820 SDHCI_MAX_CURRENT_180_SHIFT
) *
2821 SDHCI_MAX_CURRENT_MULTIPLIER
;
2823 if (max_current_180
> 150)
2824 mmc
->caps
|= MMC_CAP_SET_XPC_180
;
2826 /* Maximum current capabilities of the host at 1.8V */
2827 if (max_current_180
>= 800)
2828 mmc
->caps
|= MMC_CAP_MAX_CURRENT_800
;
2829 else if (max_current_180
>= 600)
2830 mmc
->caps
|= MMC_CAP_MAX_CURRENT_600
;
2831 else if (max_current_180
>= 400)
2832 mmc
->caps
|= MMC_CAP_MAX_CURRENT_400
;
2834 mmc
->caps
|= MMC_CAP_MAX_CURRENT_200
;
2837 mmc
->ocr_avail
= ocr_avail
;
2838 mmc
->ocr_avail_sdio
= ocr_avail
;
2839 if (host
->ocr_avail_sdio
)
2840 mmc
->ocr_avail_sdio
&= host
->ocr_avail_sdio
;
2841 mmc
->ocr_avail_sd
= ocr_avail
;
2842 if (host
->ocr_avail_sd
)
2843 mmc
->ocr_avail_sd
&= host
->ocr_avail_sd
;
2844 else /* normal SD controllers don't support 1.8V */
2845 mmc
->ocr_avail_sd
&= ~MMC_VDD_165_195
;
2846 mmc
->ocr_avail_mmc
= ocr_avail
;
2847 if (host
->ocr_avail_mmc
)
2848 mmc
->ocr_avail_mmc
&= host
->ocr_avail_mmc
;
2850 if (mmc
->ocr_avail
== 0) {
2851 pr_err("%s: Hardware doesn't report any "
2852 "support voltages.\n", mmc_hostname(mmc
));
2856 spin_lock_init(&host
->lock
);
2859 * Maximum number of segments. Depends on if the hardware
2860 * can do scatter/gather or not.
2862 if (host
->flags
& SDHCI_USE_ADMA
)
2863 mmc
->max_segs
= 128;
2864 else if (host
->flags
& SDHCI_USE_SDMA
)
2867 mmc
->max_segs
= 128;
2870 * Maximum number of sectors in one transfer. Limited by DMA boundary
2873 mmc
->max_req_size
= 524288;
2876 * Maximum segment size. Could be one segment with the maximum number
2877 * of bytes. When doing hardware scatter/gather, each entry cannot
2878 * be larger than 64 KiB though.
2880 if (host
->flags
& SDHCI_USE_ADMA
) {
2881 if (host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
)
2882 mmc
->max_seg_size
= 65535;
2884 mmc
->max_seg_size
= 65536;
2886 mmc
->max_seg_size
= mmc
->max_req_size
;
2890 * Maximum block size. This varies from controller to controller and
2891 * is specified in the capabilities register.
2893 if (host
->quirks
& SDHCI_QUIRK_FORCE_BLK_SZ_2048
) {
2894 mmc
->max_blk_size
= 2;
2896 mmc
->max_blk_size
= (caps
[0] & SDHCI_MAX_BLOCK_MASK
) >>
2897 SDHCI_MAX_BLOCK_SHIFT
;
2898 if (mmc
->max_blk_size
>= 3) {
2899 pr_warning("%s: Invalid maximum block size, "
2900 "assuming 512 bytes\n", mmc_hostname(mmc
));
2901 mmc
->max_blk_size
= 0;
2905 mmc
->max_blk_size
= 512 << mmc
->max_blk_size
;
2908 * Maximum block count.
2910 mmc
->max_blk_count
= (host
->quirks
& SDHCI_QUIRK_NO_MULTIBLOCK
) ? 1 : 65535;
2915 tasklet_init(&host
->card_tasklet
,
2916 sdhci_tasklet_card
, (unsigned long)host
);
2917 tasklet_init(&host
->finish_tasklet
,
2918 sdhci_tasklet_finish
, (unsigned long)host
);
2920 setup_timer(&host
->timer
, sdhci_timeout_timer
, (unsigned long)host
);
2922 if (host
->version
>= SDHCI_SPEC_300
) {
2923 init_waitqueue_head(&host
->buf_ready_int
);
2925 /* Initialize re-tuning timer */
2926 init_timer(&host
->tuning_timer
);
2927 host
->tuning_timer
.data
= (unsigned long)host
;
2928 host
->tuning_timer
.function
= sdhci_tuning_timer
;
2931 ret
= request_irq(host
->irq
, sdhci_irq
, IRQF_SHARED
,
2932 mmc_hostname(mmc
), host
);
2936 host
->vmmc
= regulator_get(mmc_dev(mmc
), "vmmc");
2937 if (IS_ERR(host
->vmmc
)) {
2938 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc
));
2942 sdhci_init(host
, 0);
2944 #ifdef CONFIG_MMC_DEBUG
2945 sdhci_dumpregs(host
);
2948 #ifdef SDHCI_USE_LEDS_CLASS
2949 snprintf(host
->led_name
, sizeof(host
->led_name
),
2950 "%s::", mmc_hostname(mmc
));
2951 host
->led
.name
= host
->led_name
;
2952 host
->led
.brightness
= LED_OFF
;
2953 host
->led
.default_trigger
= mmc_hostname(mmc
);
2954 host
->led
.brightness_set
= sdhci_led_control
;
2956 ret
= led_classdev_register(mmc_dev(mmc
), &host
->led
);
2965 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
2966 mmc_hostname(mmc
), host
->hw_name
, dev_name(mmc_dev(mmc
)),
2967 (host
->flags
& SDHCI_USE_ADMA
) ? "ADMA" :
2968 (host
->flags
& SDHCI_USE_SDMA
) ? "DMA" : "PIO");
2970 sdhci_enable_card_detection(host
);
2974 #ifdef SDHCI_USE_LEDS_CLASS
2976 sdhci_reset(host
, SDHCI_RESET_ALL
);
2977 free_irq(host
->irq
, host
);
2980 tasklet_kill(&host
->card_tasklet
);
2981 tasklet_kill(&host
->finish_tasklet
);
2986 EXPORT_SYMBOL_GPL(sdhci_add_host
);
2988 void sdhci_remove_host(struct sdhci_host
*host
, int dead
)
2990 unsigned long flags
;
2993 spin_lock_irqsave(&host
->lock
, flags
);
2995 host
->flags
|= SDHCI_DEVICE_DEAD
;
2998 pr_err("%s: Controller removed during "
2999 " transfer!\n", mmc_hostname(host
->mmc
));
3001 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
3002 tasklet_schedule(&host
->finish_tasklet
);
3005 spin_unlock_irqrestore(&host
->lock
, flags
);
3008 sdhci_disable_card_detection(host
);
3010 mmc_remove_host(host
->mmc
);
3012 #ifdef SDHCI_USE_LEDS_CLASS
3013 led_classdev_unregister(&host
->led
);
3017 sdhci_reset(host
, SDHCI_RESET_ALL
);
3019 free_irq(host
->irq
, host
);
3021 del_timer_sync(&host
->timer
);
3022 if (host
->version
>= SDHCI_SPEC_300
)
3023 del_timer_sync(&host
->tuning_timer
);
3025 tasklet_kill(&host
->card_tasklet
);
3026 tasklet_kill(&host
->finish_tasklet
);
3029 regulator_put(host
->vmmc
);
3031 kfree(host
->adma_desc
);
3032 kfree(host
->align_buffer
);
3034 host
->adma_desc
= NULL
;
3035 host
->align_buffer
= NULL
;
3038 EXPORT_SYMBOL_GPL(sdhci_remove_host
);
3040 void sdhci_free_host(struct sdhci_host
*host
)
3042 mmc_free_host(host
->mmc
);
3045 EXPORT_SYMBOL_GPL(sdhci_free_host
);
3047 /*****************************************************************************\
3049 * Driver init/exit *
3051 \*****************************************************************************/
3053 static int __init
sdhci_drv_init(void)
3056 ": Secure Digital Host Controller Interface driver\n");
3057 pr_info(DRIVER_NAME
": Copyright(c) Pierre Ossman\n");
3062 static void __exit
sdhci_drv_exit(void)
3066 module_init(sdhci_drv_init
);
3067 module_exit(sdhci_drv_exit
);
3069 module_param(debug_quirks
, uint
, 0444);
3070 module_param(debug_quirks2
, uint
, 0444);
3072 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3073 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3074 MODULE_LICENSE("GPL");
3076 MODULE_PARM_DESC(debug_quirks
, "Force certain quirks.");
3077 MODULE_PARM_DESC(debug_quirks2
, "Force certain other quirks.");