3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
6 * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
7 * driver to function correctly on these systems.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/fsl_devices.h>
18 #include <linux/platform_device.h>
20 #include <mach/hardware.h>
22 static struct clk
*mxc_ahb_clk
;
23 static struct clk
*mxc_usb_clk
;
25 /* workaround ENGcm09152 for i.MX35 */
26 #define USBPHYCTRL_OTGBASE_OFFSET 0x608
27 #define USBPHYCTRL_EVDO (1 << 23)
29 int fsl_udc_clk_init(struct platform_device
*pdev
)
31 struct fsl_usb2_platform_data
*pdata
;
35 pdata
= pdev
->dev
.platform_data
;
37 if (!cpu_is_mx35() && !cpu_is_mx25()) {
38 mxc_ahb_clk
= clk_get(&pdev
->dev
, "usb_ahb");
39 if (IS_ERR(mxc_ahb_clk
))
40 return PTR_ERR(mxc_ahb_clk
);
42 ret
= clk_enable(mxc_ahb_clk
);
44 dev_err(&pdev
->dev
, "clk_enable(\"usb_ahb\") failed\n");
49 /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
50 mxc_usb_clk
= clk_get(&pdev
->dev
, "usb");
51 if (IS_ERR(mxc_usb_clk
)) {
52 dev_err(&pdev
->dev
, "clk_get(\"usb\") failed\n");
53 ret
= PTR_ERR(mxc_usb_clk
);
58 freq
= clk_get_rate(mxc_usb_clk
);
59 if (pdata
->phy_mode
!= FSL_USB2_PHY_ULPI
&&
60 (freq
< 59999000 || freq
> 60001000)) {
61 dev_err(&pdev
->dev
, "USB_CLK=%lu, should be 60MHz\n", freq
);
67 ret
= clk_enable(mxc_usb_clk
);
69 dev_err(&pdev
->dev
, "clk_enable(\"usb_clk\") failed\n");
81 clk_disable(mxc_ahb_clk
);
88 void fsl_udc_clk_finalize(struct platform_device
*pdev
)
90 struct fsl_usb2_platform_data
*pdata
= pdev
->dev
.platform_data
;
91 #if defined(CONFIG_ARCH_MX35)
94 /* workaround ENGcm09152 for i.MX35 */
95 if (pdata
->workaround
& FLS_USB2_WORKAROUND_ENGCM09152
) {
96 v
= readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR
+
97 USBPHYCTRL_OTGBASE_OFFSET
));
98 writel(v
| USBPHYCTRL_EVDO
, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR
+
99 USBPHYCTRL_OTGBASE_OFFSET
));
103 /* ULPI transceivers don't need usbpll */
104 if (pdata
->phy_mode
== FSL_USB2_PHY_ULPI
) {
105 clk_disable(mxc_usb_clk
);
106 clk_put(mxc_usb_clk
);
111 void fsl_udc_clk_release(void)
114 clk_disable(mxc_usb_clk
);
115 clk_put(mxc_usb_clk
);
117 if (!cpu_is_mx35()) {
118 clk_disable(mxc_ahb_clk
);
119 clk_put(mxc_ahb_clk
);