2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
42 #include "en_accel/ipsec.h"
43 #include "en_accel/ipsec_rxtx.h"
44 #include "accel/ipsec.h"
47 struct mlx5e_rq_param
{
48 u32 rqc
[MLX5_ST_SZ_DW(rqc
)];
49 struct mlx5_wq_param wq
;
52 struct mlx5e_sq_param
{
53 u32 sqc
[MLX5_ST_SZ_DW(sqc
)];
54 struct mlx5_wq_param wq
;
57 struct mlx5e_cq_param
{
58 u32 cqc
[MLX5_ST_SZ_DW(cqc
)];
59 struct mlx5_wq_param wq
;
64 struct mlx5e_channel_param
{
65 struct mlx5e_rq_param rq
;
66 struct mlx5e_sq_param sq
;
67 struct mlx5e_sq_param xdp_sq
;
68 struct mlx5e_sq_param icosq
;
69 struct mlx5e_cq_param rx_cq
;
70 struct mlx5e_cq_param tx_cq
;
71 struct mlx5e_cq_param icosq_cq
;
74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev
*mdev
)
76 return MLX5_CAP_GEN(mdev
, striding_rq
) &&
77 MLX5_CAP_GEN(mdev
, umr_ptr_rlky
) &&
78 MLX5_CAP_ETH(mdev
, reg_umr_sq
);
81 void mlx5e_init_rq_type_params(struct mlx5_core_dev
*mdev
,
82 struct mlx5e_params
*params
, u8 rq_type
)
84 params
->rq_wq_type
= rq_type
;
85 params
->lro_wqe_sz
= MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ
;
86 switch (params
->rq_wq_type
) {
87 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
88 params
->log_rq_size
= is_kdump_kernel() ?
89 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW
:
90 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW
;
91 params
->mpwqe_log_stride_sz
= MLX5E_MPWQE_STRIDE_SZ(mdev
,
92 MLX5E_GET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_COMPRESS
));
93 params
->mpwqe_log_num_strides
= MLX5_MPWRQ_LOG_WQE_SZ
-
94 params
->mpwqe_log_stride_sz
;
96 default: /* MLX5_WQ_TYPE_LINKED_LIST */
97 params
->log_rq_size
= is_kdump_kernel() ?
98 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE
:
99 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE
;
100 params
->rq_headroom
= params
->xdp_prog
?
101 XDP_PACKET_HEADROOM
: MLX5_RX_HEADROOM
;
102 params
->rq_headroom
+= NET_IP_ALIGN
;
104 /* Extra room needed for build_skb */
105 params
->lro_wqe_sz
-= params
->rq_headroom
+
106 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
109 mlx5_core_info(mdev
, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
110 params
->rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
,
111 BIT(params
->log_rq_size
),
112 BIT(params
->mpwqe_log_stride_sz
),
113 MLX5E_GET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_COMPRESS
));
116 static void mlx5e_set_rq_params(struct mlx5_core_dev
*mdev
,
117 struct mlx5e_params
*params
)
119 u8 rq_type
= mlx5e_check_fragmented_striding_rq_cap(mdev
) &&
120 !params
->xdp_prog
&& !MLX5_IPSEC_DEV(mdev
) ?
121 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
122 MLX5_WQ_TYPE_LINKED_LIST
;
123 mlx5e_init_rq_type_params(mdev
, params
, rq_type
);
126 static void mlx5e_update_carrier(struct mlx5e_priv
*priv
)
128 struct mlx5_core_dev
*mdev
= priv
->mdev
;
131 port_state
= mlx5_query_vport_state(mdev
,
132 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
,
135 if (port_state
== VPORT_STATE_UP
) {
136 netdev_info(priv
->netdev
, "Link up\n");
137 netif_carrier_on(priv
->netdev
);
139 netdev_info(priv
->netdev
, "Link down\n");
140 netif_carrier_off(priv
->netdev
);
144 static void mlx5e_update_carrier_work(struct work_struct
*work
)
146 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
147 update_carrier_work
);
149 mutex_lock(&priv
->state_lock
);
150 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
151 if (priv
->profile
->update_carrier
)
152 priv
->profile
->update_carrier(priv
);
153 mutex_unlock(&priv
->state_lock
);
156 static void mlx5e_tx_timeout_work(struct work_struct
*work
)
158 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
163 mutex_lock(&priv
->state_lock
);
164 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
166 mlx5e_close_locked(priv
->netdev
);
167 err
= mlx5e_open_locked(priv
->netdev
);
169 netdev_err(priv
->netdev
, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
172 mutex_unlock(&priv
->state_lock
);
176 static void mlx5e_update_sw_counters(struct mlx5e_priv
*priv
)
178 struct mlx5e_sw_stats temp
, *s
= &temp
;
179 struct mlx5e_rq_stats
*rq_stats
;
180 struct mlx5e_sq_stats
*sq_stats
;
183 memset(s
, 0, sizeof(*s
));
184 for (i
= 0; i
< priv
->channels
.num
; i
++) {
185 struct mlx5e_channel
*c
= priv
->channels
.c
[i
];
187 rq_stats
= &c
->rq
.stats
;
189 s
->rx_packets
+= rq_stats
->packets
;
190 s
->rx_bytes
+= rq_stats
->bytes
;
191 s
->rx_lro_packets
+= rq_stats
->lro_packets
;
192 s
->rx_lro_bytes
+= rq_stats
->lro_bytes
;
193 s
->rx_removed_vlan_packets
+= rq_stats
->removed_vlan_packets
;
194 s
->rx_csum_none
+= rq_stats
->csum_none
;
195 s
->rx_csum_complete
+= rq_stats
->csum_complete
;
196 s
->rx_csum_unnecessary
+= rq_stats
->csum_unnecessary
;
197 s
->rx_csum_unnecessary_inner
+= rq_stats
->csum_unnecessary_inner
;
198 s
->rx_xdp_drop
+= rq_stats
->xdp_drop
;
199 s
->rx_xdp_tx
+= rq_stats
->xdp_tx
;
200 s
->rx_xdp_tx_full
+= rq_stats
->xdp_tx_full
;
201 s
->rx_wqe_err
+= rq_stats
->wqe_err
;
202 s
->rx_mpwqe_filler
+= rq_stats
->mpwqe_filler
;
203 s
->rx_buff_alloc_err
+= rq_stats
->buff_alloc_err
;
204 s
->rx_cqe_compress_blks
+= rq_stats
->cqe_compress_blks
;
205 s
->rx_cqe_compress_pkts
+= rq_stats
->cqe_compress_pkts
;
206 s
->rx_page_reuse
+= rq_stats
->page_reuse
;
207 s
->rx_cache_reuse
+= rq_stats
->cache_reuse
;
208 s
->rx_cache_full
+= rq_stats
->cache_full
;
209 s
->rx_cache_empty
+= rq_stats
->cache_empty
;
210 s
->rx_cache_busy
+= rq_stats
->cache_busy
;
211 s
->rx_cache_waive
+= rq_stats
->cache_waive
;
213 for (j
= 0; j
< priv
->channels
.params
.num_tc
; j
++) {
214 sq_stats
= &c
->sq
[j
].stats
;
216 s
->tx_packets
+= sq_stats
->packets
;
217 s
->tx_bytes
+= sq_stats
->bytes
;
218 s
->tx_tso_packets
+= sq_stats
->tso_packets
;
219 s
->tx_tso_bytes
+= sq_stats
->tso_bytes
;
220 s
->tx_tso_inner_packets
+= sq_stats
->tso_inner_packets
;
221 s
->tx_tso_inner_bytes
+= sq_stats
->tso_inner_bytes
;
222 s
->tx_added_vlan_packets
+= sq_stats
->added_vlan_packets
;
223 s
->tx_queue_stopped
+= sq_stats
->stopped
;
224 s
->tx_queue_wake
+= sq_stats
->wake
;
225 s
->tx_queue_dropped
+= sq_stats
->dropped
;
226 s
->tx_xmit_more
+= sq_stats
->xmit_more
;
227 s
->tx_csum_partial_inner
+= sq_stats
->csum_partial_inner
;
228 s
->tx_csum_none
+= sq_stats
->csum_none
;
229 s
->tx_csum_partial
+= sq_stats
->csum_partial
;
233 s
->link_down_events_phy
= MLX5_GET(ppcnt_reg
,
234 priv
->stats
.pport
.phy_counters
,
235 counter_set
.phys_layer_cntrs
.link_down_events
);
236 memcpy(&priv
->stats
.sw
, s
, sizeof(*s
));
239 static void mlx5e_update_vport_counters(struct mlx5e_priv
*priv
)
241 int outlen
= MLX5_ST_SZ_BYTES(query_vport_counter_out
);
242 u32
*out
= (u32
*)priv
->stats
.vport
.query_vport_out
;
243 u32 in
[MLX5_ST_SZ_DW(query_vport_counter_in
)] = {0};
244 struct mlx5_core_dev
*mdev
= priv
->mdev
;
246 MLX5_SET(query_vport_counter_in
, in
, opcode
,
247 MLX5_CMD_OP_QUERY_VPORT_COUNTER
);
248 MLX5_SET(query_vport_counter_in
, in
, op_mod
, 0);
249 MLX5_SET(query_vport_counter_in
, in
, other_vport
, 0);
251 mlx5_cmd_exec(mdev
, in
, sizeof(in
), out
, outlen
);
254 static void mlx5e_update_pport_counters(struct mlx5e_priv
*priv
, bool full
)
256 struct mlx5e_pport_stats
*pstats
= &priv
->stats
.pport
;
257 struct mlx5_core_dev
*mdev
= priv
->mdev
;
258 u32 in
[MLX5_ST_SZ_DW(ppcnt_reg
)] = {0};
259 int sz
= MLX5_ST_SZ_BYTES(ppcnt_reg
);
263 MLX5_SET(ppcnt_reg
, in
, local_port
, 1);
265 out
= pstats
->IEEE_802_3_counters
;
266 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_IEEE_802_3_COUNTERS_GROUP
);
267 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
272 out
= pstats
->RFC_2863_counters
;
273 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2863_COUNTERS_GROUP
);
274 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
276 out
= pstats
->RFC_2819_counters
;
277 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2819_COUNTERS_GROUP
);
278 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
280 out
= pstats
->phy_counters
;
281 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP
);
282 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
284 if (MLX5_CAP_PCAM_FEATURE(mdev
, ppcnt_statistical_group
)) {
285 out
= pstats
->phy_statistical_counters
;
286 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP
);
287 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
290 if (MLX5_CAP_PCAM_FEATURE(mdev
, rx_buffer_fullness_counters
)) {
291 out
= pstats
->eth_ext_counters
;
292 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP
);
293 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
296 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PER_PRIORITY_COUNTERS_GROUP
);
297 for (prio
= 0; prio
< NUM_PPORT_PRIO
; prio
++) {
298 out
= pstats
->per_prio_counters
[prio
];
299 MLX5_SET(ppcnt_reg
, in
, prio_tc
, prio
);
300 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
,
301 MLX5_REG_PPCNT
, 0, 0);
305 static void mlx5e_update_q_counter(struct mlx5e_priv
*priv
)
307 struct mlx5e_qcounter_stats
*qcnt
= &priv
->stats
.qcnt
;
308 u32 out
[MLX5_ST_SZ_DW(query_q_counter_out
)];
311 if (!priv
->q_counter
)
314 err
= mlx5_core_query_q_counter(priv
->mdev
, priv
->q_counter
, 0, out
, sizeof(out
));
318 qcnt
->rx_out_of_buffer
= MLX5_GET(query_q_counter_out
, out
, out_of_buffer
);
321 static void mlx5e_update_pcie_counters(struct mlx5e_priv
*priv
)
323 struct mlx5e_pcie_stats
*pcie_stats
= &priv
->stats
.pcie
;
324 struct mlx5_core_dev
*mdev
= priv
->mdev
;
325 u32 in
[MLX5_ST_SZ_DW(mpcnt_reg
)] = {0};
326 int sz
= MLX5_ST_SZ_BYTES(mpcnt_reg
);
329 if (!MLX5_CAP_MCAM_FEATURE(mdev
, pcie_performance_group
))
332 out
= pcie_stats
->pcie_perf_counters
;
333 MLX5_SET(mpcnt_reg
, in
, grp
, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP
);
334 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_MPCNT
, 0, 0);
337 void mlx5e_update_stats(struct mlx5e_priv
*priv
, bool full
)
340 mlx5e_update_pcie_counters(priv
);
341 mlx5e_ipsec_update_stats(priv
);
343 mlx5e_update_pport_counters(priv
, full
);
344 mlx5e_update_vport_counters(priv
);
345 mlx5e_update_q_counter(priv
);
346 mlx5e_update_sw_counters(priv
);
349 static void mlx5e_update_ndo_stats(struct mlx5e_priv
*priv
)
351 mlx5e_update_stats(priv
, false);
354 void mlx5e_update_stats_work(struct work_struct
*work
)
356 struct delayed_work
*dwork
= to_delayed_work(work
);
357 struct mlx5e_priv
*priv
= container_of(dwork
, struct mlx5e_priv
,
359 mutex_lock(&priv
->state_lock
);
360 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
)) {
361 priv
->profile
->update_stats(priv
);
362 queue_delayed_work(priv
->wq
, dwork
,
363 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL
));
365 mutex_unlock(&priv
->state_lock
);
368 static void mlx5e_async_event(struct mlx5_core_dev
*mdev
, void *vpriv
,
369 enum mlx5_dev_event event
, unsigned long param
)
371 struct mlx5e_priv
*priv
= vpriv
;
373 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
))
377 case MLX5_DEV_EVENT_PORT_UP
:
378 case MLX5_DEV_EVENT_PORT_DOWN
:
379 queue_work(priv
->wq
, &priv
->update_carrier_work
);
386 static void mlx5e_enable_async_events(struct mlx5e_priv
*priv
)
388 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
);
391 static void mlx5e_disable_async_events(struct mlx5e_priv
*priv
)
393 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
);
394 synchronize_irq(pci_irq_vector(priv
->mdev
->pdev
, MLX5_EQ_VEC_ASYNC
));
397 static inline int mlx5e_get_wqe_mtt_sz(void)
399 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
400 * To avoid copying garbage after the mtt array, we allocate
403 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE
* sizeof(__be64
),
404 MLX5_UMR_MTT_ALIGNMENT
);
407 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq
*rq
,
408 struct mlx5e_icosq
*sq
,
409 struct mlx5e_umr_wqe
*wqe
,
412 struct mlx5_wqe_ctrl_seg
*cseg
= &wqe
->ctrl
;
413 struct mlx5_wqe_umr_ctrl_seg
*ucseg
= &wqe
->uctrl
;
414 struct mlx5_wqe_data_seg
*dseg
= &wqe
->data
;
415 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
416 u8 ds_cnt
= DIV_ROUND_UP(sizeof(*wqe
), MLX5_SEND_WQE_DS
);
417 u32 umr_wqe_mtt_offset
= mlx5e_get_wqe_mtt_offset(rq
, ix
);
419 cseg
->qpn_ds
= cpu_to_be32((sq
->sqn
<< MLX5_WQE_CTRL_QPN_SHIFT
) |
421 cseg
->fm_ce_se
= MLX5_WQE_CTRL_CQ_UPDATE
;
422 cseg
->imm
= rq
->mkey_be
;
424 ucseg
->flags
= MLX5_UMR_TRANSLATION_OFFSET_EN
;
425 ucseg
->xlt_octowords
=
426 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE
));
427 ucseg
->bsf_octowords
=
428 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset
));
429 ucseg
->mkey_mask
= cpu_to_be64(MLX5_MKEY_MASK_FREE
);
431 dseg
->lkey
= sq
->mkey_be
;
432 dseg
->addr
= cpu_to_be64(wi
->umr
.mtt_addr
);
435 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq
*rq
,
436 struct mlx5e_channel
*c
)
438 int wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
439 int mtt_sz
= mlx5e_get_wqe_mtt_sz();
440 int mtt_alloc
= mtt_sz
+ MLX5_UMR_ALIGN
- 1;
443 rq
->mpwqe
.info
= kzalloc_node(wq_sz
* sizeof(*rq
->mpwqe
.info
),
444 GFP_KERNEL
, cpu_to_node(c
->cpu
));
448 /* We allocate more than mtt_sz as we will align the pointer */
449 rq
->mpwqe
.mtt_no_align
= kzalloc_node(mtt_alloc
* wq_sz
, GFP_KERNEL
,
450 cpu_to_node(c
->cpu
));
451 if (unlikely(!rq
->mpwqe
.mtt_no_align
))
452 goto err_free_wqe_info
;
454 for (i
= 0; i
< wq_sz
; i
++) {
455 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[i
];
457 wi
->umr
.mtt
= PTR_ALIGN(rq
->mpwqe
.mtt_no_align
+ i
* mtt_alloc
,
459 wi
->umr
.mtt_addr
= dma_map_single(c
->pdev
, wi
->umr
.mtt
, mtt_sz
,
461 if (unlikely(dma_mapping_error(c
->pdev
, wi
->umr
.mtt_addr
)))
464 mlx5e_build_umr_wqe(rq
, &c
->icosq
, &wi
->umr
.wqe
, i
);
471 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[i
];
473 dma_unmap_single(c
->pdev
, wi
->umr
.mtt_addr
, mtt_sz
,
476 kfree(rq
->mpwqe
.mtt_no_align
);
478 kfree(rq
->mpwqe
.info
);
484 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq
*rq
)
486 int wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
487 int mtt_sz
= mlx5e_get_wqe_mtt_sz();
490 for (i
= 0; i
< wq_sz
; i
++) {
491 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[i
];
493 dma_unmap_single(rq
->pdev
, wi
->umr
.mtt_addr
, mtt_sz
,
496 kfree(rq
->mpwqe
.mtt_no_align
);
497 kfree(rq
->mpwqe
.info
);
500 static int mlx5e_create_umr_mkey(struct mlx5_core_dev
*mdev
,
501 u64 npages
, u8 page_shift
,
502 struct mlx5_core_mkey
*umr_mkey
)
504 int inlen
= MLX5_ST_SZ_BYTES(create_mkey_in
);
509 if (!MLX5E_VALID_NUM_MTTS(npages
))
512 in
= kvzalloc(inlen
, GFP_KERNEL
);
516 mkc
= MLX5_ADDR_OF(create_mkey_in
, in
, memory_key_mkey_entry
);
518 MLX5_SET(mkc
, mkc
, free
, 1);
519 MLX5_SET(mkc
, mkc
, umr_en
, 1);
520 MLX5_SET(mkc
, mkc
, lw
, 1);
521 MLX5_SET(mkc
, mkc
, lr
, 1);
522 MLX5_SET(mkc
, mkc
, access_mode
, MLX5_MKC_ACCESS_MODE_MTT
);
524 MLX5_SET(mkc
, mkc
, qpn
, 0xffffff);
525 MLX5_SET(mkc
, mkc
, pd
, mdev
->mlx5e_res
.pdn
);
526 MLX5_SET64(mkc
, mkc
, len
, npages
<< page_shift
);
527 MLX5_SET(mkc
, mkc
, translations_octword_size
,
528 MLX5_MTT_OCTW(npages
));
529 MLX5_SET(mkc
, mkc
, log_page_size
, page_shift
);
531 err
= mlx5_core_create_mkey(mdev
, umr_mkey
, in
, inlen
);
537 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev
*mdev
, struct mlx5e_rq
*rq
)
539 u64 num_mtts
= MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq
->wq
));
541 return mlx5e_create_umr_mkey(mdev
, num_mtts
, PAGE_SHIFT
, &rq
->umr_mkey
);
544 static int mlx5e_alloc_rq(struct mlx5e_channel
*c
,
545 struct mlx5e_params
*params
,
546 struct mlx5e_rq_param
*rqp
,
549 struct mlx5_core_dev
*mdev
= c
->mdev
;
550 void *rqc
= rqp
->rqc
;
551 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
558 rqp
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
560 err
= mlx5_wq_ll_create(mdev
, &rqp
->wq
, rqc_wq
, &rq
->wq
,
565 rq
->wq
.db
= &rq
->wq
.db
[MLX5_RCV_DBR
];
567 wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
569 rq
->wq_type
= params
->rq_wq_type
;
571 rq
->netdev
= c
->netdev
;
572 rq
->tstamp
= c
->tstamp
;
573 rq
->clock
= &mdev
->clock
;
578 rq
->xdp_prog
= params
->xdp_prog
? bpf_prog_inc(params
->xdp_prog
) : NULL
;
579 if (IS_ERR(rq
->xdp_prog
)) {
580 err
= PTR_ERR(rq
->xdp_prog
);
582 goto err_rq_wq_destroy
;
585 err
= xdp_rxq_info_reg(&rq
->xdp_rxq
, rq
->netdev
, rq
->ix
);
587 goto err_rq_wq_destroy
;
589 rq
->buff
.map_dir
= rq
->xdp_prog
? DMA_BIDIRECTIONAL
: DMA_FROM_DEVICE
;
590 rq
->buff
.headroom
= params
->rq_headroom
;
592 switch (rq
->wq_type
) {
593 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
595 rq
->post_wqes
= mlx5e_post_rx_mpwqes
;
596 rq
->dealloc_wqe
= mlx5e_dealloc_rx_mpwqe
;
598 rq
->handle_rx_cqe
= c
->priv
->profile
->rx_handlers
.handle_rx_cqe_mpwqe
;
599 #ifdef CONFIG_MLX5_EN_IPSEC
600 if (MLX5_IPSEC_DEV(mdev
)) {
602 netdev_err(c
->netdev
, "MPWQE RQ with IPSec offload not supported\n");
603 goto err_rq_wq_destroy
;
606 if (!rq
->handle_rx_cqe
) {
608 netdev_err(c
->netdev
, "RX handler of MPWQE RQ is not set, err %d\n", err
);
609 goto err_rq_wq_destroy
;
612 rq
->mpwqe
.log_stride_sz
= params
->mpwqe_log_stride_sz
;
613 rq
->mpwqe
.num_strides
= BIT(params
->mpwqe_log_num_strides
);
615 byte_count
= rq
->mpwqe
.num_strides
<< rq
->mpwqe
.log_stride_sz
;
617 err
= mlx5e_create_rq_umr_mkey(mdev
, rq
);
619 goto err_rq_wq_destroy
;
620 rq
->mkey_be
= cpu_to_be32(rq
->umr_mkey
.key
);
622 err
= mlx5e_rq_alloc_mpwqe_info(rq
, c
);
624 goto err_destroy_umr_mkey
;
626 default: /* MLX5_WQ_TYPE_LINKED_LIST */
628 kzalloc_node(wq_sz
* sizeof(*rq
->wqe
.frag_info
),
629 GFP_KERNEL
, cpu_to_node(c
->cpu
));
630 if (!rq
->wqe
.frag_info
) {
632 goto err_rq_wq_destroy
;
634 rq
->post_wqes
= mlx5e_post_rx_wqes
;
635 rq
->dealloc_wqe
= mlx5e_dealloc_rx_wqe
;
637 #ifdef CONFIG_MLX5_EN_IPSEC
639 rq
->handle_rx_cqe
= mlx5e_ipsec_handle_rx_cqe
;
642 rq
->handle_rx_cqe
= c
->priv
->profile
->rx_handlers
.handle_rx_cqe
;
643 if (!rq
->handle_rx_cqe
) {
644 kfree(rq
->wqe
.frag_info
);
646 netdev_err(c
->netdev
, "RX handler of RQ is not set, err %d\n", err
);
647 goto err_rq_wq_destroy
;
650 byte_count
= params
->lro_en
?
652 MLX5E_SW2HW_MTU(c
->priv
, c
->netdev
->mtu
);
653 #ifdef CONFIG_MLX5_EN_IPSEC
654 if (MLX5_IPSEC_DEV(mdev
))
655 byte_count
+= MLX5E_METADATA_ETHER_LEN
;
657 rq
->wqe
.page_reuse
= !params
->xdp_prog
&& !params
->lro_en
;
659 /* calc the required page order */
660 rq
->wqe
.frag_sz
= MLX5_SKB_FRAG_SZ(rq
->buff
.headroom
+ byte_count
);
661 npages
= DIV_ROUND_UP(rq
->wqe
.frag_sz
, PAGE_SIZE
);
662 rq
->buff
.page_order
= order_base_2(npages
);
664 byte_count
|= MLX5_HW_START_PADDING
;
665 rq
->mkey_be
= c
->mkey_be
;
668 for (i
= 0; i
< wq_sz
; i
++) {
669 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, i
);
671 if (rq
->wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
) {
672 u64 dma_offset
= (u64
)mlx5e_get_wqe_mtt_offset(rq
, i
) << PAGE_SHIFT
;
674 wqe
->data
.addr
= cpu_to_be64(dma_offset
);
677 wqe
->data
.byte_count
= cpu_to_be32(byte_count
);
678 wqe
->data
.lkey
= rq
->mkey_be
;
681 INIT_WORK(&rq
->dim
.work
, mlx5e_rx_dim_work
);
683 switch (params
->rx_cq_moderation
.cq_period_mode
) {
684 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE
:
685 rq
->dim
.mode
= NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE
;
687 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE
:
689 rq
->dim
.mode
= NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE
;
692 rq
->page_cache
.head
= 0;
693 rq
->page_cache
.tail
= 0;
697 err_destroy_umr_mkey
:
698 mlx5_core_destroy_mkey(mdev
, &rq
->umr_mkey
);
702 bpf_prog_put(rq
->xdp_prog
);
703 xdp_rxq_info_unreg(&rq
->xdp_rxq
);
704 mlx5_wq_destroy(&rq
->wq_ctrl
);
709 static void mlx5e_free_rq(struct mlx5e_rq
*rq
)
714 bpf_prog_put(rq
->xdp_prog
);
716 xdp_rxq_info_unreg(&rq
->xdp_rxq
);
718 switch (rq
->wq_type
) {
719 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
720 mlx5e_rq_free_mpwqe_info(rq
);
721 mlx5_core_destroy_mkey(rq
->mdev
, &rq
->umr_mkey
);
723 default: /* MLX5_WQ_TYPE_LINKED_LIST */
724 kfree(rq
->wqe
.frag_info
);
727 for (i
= rq
->page_cache
.head
; i
!= rq
->page_cache
.tail
;
728 i
= (i
+ 1) & (MLX5E_CACHE_SIZE
- 1)) {
729 struct mlx5e_dma_info
*dma_info
= &rq
->page_cache
.page_cache
[i
];
731 mlx5e_page_release(rq
, dma_info
, false);
733 mlx5_wq_destroy(&rq
->wq_ctrl
);
736 static int mlx5e_create_rq(struct mlx5e_rq
*rq
,
737 struct mlx5e_rq_param
*param
)
739 struct mlx5_core_dev
*mdev
= rq
->mdev
;
747 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) +
748 sizeof(u64
) * rq
->wq_ctrl
.buf
.npages
;
749 in
= kvzalloc(inlen
, GFP_KERNEL
);
753 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
754 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
756 memcpy(rqc
, param
->rqc
, sizeof(param
->rqc
));
758 MLX5_SET(rqc
, rqc
, cqn
, rq
->cq
.mcq
.cqn
);
759 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
760 MLX5_SET(wq
, wq
, log_wq_pg_sz
, rq
->wq_ctrl
.buf
.page_shift
-
761 MLX5_ADAPTER_PAGE_SHIFT
);
762 MLX5_SET64(wq
, wq
, dbr_addr
, rq
->wq_ctrl
.db
.dma
);
764 mlx5_fill_page_array(&rq
->wq_ctrl
.buf
,
765 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
767 err
= mlx5_core_create_rq(mdev
, in
, inlen
, &rq
->rqn
);
774 static int mlx5e_modify_rq_state(struct mlx5e_rq
*rq
, int curr_state
,
777 struct mlx5e_channel
*c
= rq
->channel
;
778 struct mlx5_core_dev
*mdev
= c
->mdev
;
785 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
786 in
= kvzalloc(inlen
, GFP_KERNEL
);
790 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
792 MLX5_SET(modify_rq_in
, in
, rq_state
, curr_state
);
793 MLX5_SET(rqc
, rqc
, state
, next_state
);
795 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
802 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq
*rq
, bool enable
)
804 struct mlx5e_channel
*c
= rq
->channel
;
805 struct mlx5e_priv
*priv
= c
->priv
;
806 struct mlx5_core_dev
*mdev
= priv
->mdev
;
813 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
814 in
= kvzalloc(inlen
, GFP_KERNEL
);
818 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
820 MLX5_SET(modify_rq_in
, in
, rq_state
, MLX5_RQC_STATE_RDY
);
821 MLX5_SET64(modify_rq_in
, in
, modify_bitmask
,
822 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS
);
823 MLX5_SET(rqc
, rqc
, scatter_fcs
, enable
);
824 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RDY
);
826 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
833 static int mlx5e_modify_rq_vsd(struct mlx5e_rq
*rq
, bool vsd
)
835 struct mlx5e_channel
*c
= rq
->channel
;
836 struct mlx5_core_dev
*mdev
= c
->mdev
;
842 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
843 in
= kvzalloc(inlen
, GFP_KERNEL
);
847 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
849 MLX5_SET(modify_rq_in
, in
, rq_state
, MLX5_RQC_STATE_RDY
);
850 MLX5_SET64(modify_rq_in
, in
, modify_bitmask
,
851 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD
);
852 MLX5_SET(rqc
, rqc
, vsd
, vsd
);
853 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RDY
);
855 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
862 static void mlx5e_destroy_rq(struct mlx5e_rq
*rq
)
864 mlx5_core_destroy_rq(rq
->mdev
, rq
->rqn
);
867 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq
*rq
)
869 unsigned long exp_time
= jiffies
+ msecs_to_jiffies(20000);
870 struct mlx5e_channel
*c
= rq
->channel
;
872 struct mlx5_wq_ll
*wq
= &rq
->wq
;
873 u16 min_wqes
= mlx5_min_rx_wqes(rq
->wq_type
, mlx5_wq_ll_get_size(wq
));
875 while (time_before(jiffies
, exp_time
)) {
876 if (wq
->cur_sz
>= min_wqes
)
882 netdev_warn(c
->netdev
, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
883 rq
->rqn
, wq
->cur_sz
, min_wqes
);
887 static void mlx5e_free_rx_descs(struct mlx5e_rq
*rq
)
889 struct mlx5_wq_ll
*wq
= &rq
->wq
;
890 struct mlx5e_rx_wqe
*wqe
;
894 /* UMR WQE (if in progress) is always at wq->head */
895 if (rq
->wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
&&
896 rq
->mpwqe
.umr_in_progress
)
897 mlx5e_free_rx_mpwqe(rq
, &rq
->mpwqe
.info
[wq
->head
]);
899 while (!mlx5_wq_ll_is_empty(wq
)) {
900 wqe_ix_be
= *wq
->tail_next
;
901 wqe_ix
= be16_to_cpu(wqe_ix_be
);
902 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_ix
);
903 rq
->dealloc_wqe(rq
, wqe_ix
);
904 mlx5_wq_ll_pop(&rq
->wq
, wqe_ix_be
,
905 &wqe
->next
.next_wqe_index
);
908 if (rq
->wq_type
== MLX5_WQ_TYPE_LINKED_LIST
&& rq
->wqe
.page_reuse
) {
909 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
910 * but yet to be re-posted.
912 int wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
914 for (wqe_ix
= 0; wqe_ix
< wq_sz
; wqe_ix
++)
915 rq
->dealloc_wqe(rq
, wqe_ix
);
919 static int mlx5e_open_rq(struct mlx5e_channel
*c
,
920 struct mlx5e_params
*params
,
921 struct mlx5e_rq_param
*param
,
926 err
= mlx5e_alloc_rq(c
, params
, param
, rq
);
930 err
= mlx5e_create_rq(rq
, param
);
934 err
= mlx5e_modify_rq_state(rq
, MLX5_RQC_STATE_RST
, MLX5_RQC_STATE_RDY
);
938 if (params
->rx_dim_enabled
)
939 c
->rq
.state
|= BIT(MLX5E_RQ_STATE_AM
);
944 mlx5e_destroy_rq(rq
);
951 static void mlx5e_activate_rq(struct mlx5e_rq
*rq
)
953 struct mlx5e_icosq
*sq
= &rq
->channel
->icosq
;
954 u16 pi
= sq
->pc
& sq
->wq
.sz_m1
;
955 struct mlx5e_tx_wqe
*nopwqe
;
957 set_bit(MLX5E_RQ_STATE_ENABLED
, &rq
->state
);
958 sq
->db
.ico_wqe
[pi
].opcode
= MLX5_OPCODE_NOP
;
959 nopwqe
= mlx5e_post_nop(&sq
->wq
, sq
->sqn
, &sq
->pc
);
960 mlx5e_notify_hw(&sq
->wq
, sq
->pc
, sq
->uar_map
, &nopwqe
->ctrl
);
963 static void mlx5e_deactivate_rq(struct mlx5e_rq
*rq
)
965 clear_bit(MLX5E_RQ_STATE_ENABLED
, &rq
->state
);
966 napi_synchronize(&rq
->channel
->napi
); /* prevent mlx5e_post_rx_wqes */
969 static void mlx5e_close_rq(struct mlx5e_rq
*rq
)
971 cancel_work_sync(&rq
->dim
.work
);
972 mlx5e_destroy_rq(rq
);
973 mlx5e_free_rx_descs(rq
);
977 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq
*sq
)
982 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq
*sq
, int numa
)
984 int wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
986 sq
->db
.di
= kzalloc_node(sizeof(*sq
->db
.di
) * wq_sz
,
989 mlx5e_free_xdpsq_db(sq
);
996 static int mlx5e_alloc_xdpsq(struct mlx5e_channel
*c
,
997 struct mlx5e_params
*params
,
998 struct mlx5e_sq_param
*param
,
999 struct mlx5e_xdpsq
*sq
)
1001 void *sqc_wq
= MLX5_ADDR_OF(sqc
, param
->sqc
, wq
);
1002 struct mlx5_core_dev
*mdev
= c
->mdev
;
1006 sq
->mkey_be
= c
->mkey_be
;
1008 sq
->uar_map
= mdev
->mlx5e_res
.bfreg
.map
;
1009 sq
->min_inline_mode
= params
->tx_min_inline_mode
;
1011 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
1012 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
, &sq
->wq_ctrl
);
1015 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
1017 err
= mlx5e_alloc_xdpsq_db(sq
, cpu_to_node(c
->cpu
));
1019 goto err_sq_wq_destroy
;
1024 mlx5_wq_destroy(&sq
->wq_ctrl
);
1029 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq
*sq
)
1031 mlx5e_free_xdpsq_db(sq
);
1032 mlx5_wq_destroy(&sq
->wq_ctrl
);
1035 static void mlx5e_free_icosq_db(struct mlx5e_icosq
*sq
)
1037 kfree(sq
->db
.ico_wqe
);
1040 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq
*sq
, int numa
)
1042 u8 wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
1044 sq
->db
.ico_wqe
= kzalloc_node(sizeof(*sq
->db
.ico_wqe
) * wq_sz
,
1046 if (!sq
->db
.ico_wqe
)
1052 static int mlx5e_alloc_icosq(struct mlx5e_channel
*c
,
1053 struct mlx5e_sq_param
*param
,
1054 struct mlx5e_icosq
*sq
)
1056 void *sqc_wq
= MLX5_ADDR_OF(sqc
, param
->sqc
, wq
);
1057 struct mlx5_core_dev
*mdev
= c
->mdev
;
1060 sq
->mkey_be
= c
->mkey_be
;
1062 sq
->uar_map
= mdev
->mlx5e_res
.bfreg
.map
;
1064 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
1065 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
, &sq
->wq_ctrl
);
1068 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
1070 err
= mlx5e_alloc_icosq_db(sq
, cpu_to_node(c
->cpu
));
1072 goto err_sq_wq_destroy
;
1074 sq
->edge
= (sq
->wq
.sz_m1
+ 1) - MLX5E_ICOSQ_MAX_WQEBBS
;
1079 mlx5_wq_destroy(&sq
->wq_ctrl
);
1084 static void mlx5e_free_icosq(struct mlx5e_icosq
*sq
)
1086 mlx5e_free_icosq_db(sq
);
1087 mlx5_wq_destroy(&sq
->wq_ctrl
);
1090 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq
*sq
)
1092 kfree(sq
->db
.wqe_info
);
1093 kfree(sq
->db
.dma_fifo
);
1096 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq
*sq
, int numa
)
1098 int wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
1099 int df_sz
= wq_sz
* MLX5_SEND_WQEBB_NUM_DS
;
1101 sq
->db
.dma_fifo
= kzalloc_node(df_sz
* sizeof(*sq
->db
.dma_fifo
),
1103 sq
->db
.wqe_info
= kzalloc_node(wq_sz
* sizeof(*sq
->db
.wqe_info
),
1105 if (!sq
->db
.dma_fifo
|| !sq
->db
.wqe_info
) {
1106 mlx5e_free_txqsq_db(sq
);
1110 sq
->dma_fifo_mask
= df_sz
- 1;
1115 static int mlx5e_alloc_txqsq(struct mlx5e_channel
*c
,
1117 struct mlx5e_params
*params
,
1118 struct mlx5e_sq_param
*param
,
1119 struct mlx5e_txqsq
*sq
)
1121 void *sqc_wq
= MLX5_ADDR_OF(sqc
, param
->sqc
, wq
);
1122 struct mlx5_core_dev
*mdev
= c
->mdev
;
1126 sq
->tstamp
= c
->tstamp
;
1127 sq
->clock
= &mdev
->clock
;
1128 sq
->mkey_be
= c
->mkey_be
;
1130 sq
->txq_ix
= txq_ix
;
1131 sq
->uar_map
= mdev
->mlx5e_res
.bfreg
.map
;
1132 sq
->max_inline
= params
->tx_max_inline
;
1133 sq
->min_inline_mode
= params
->tx_min_inline_mode
;
1134 if (MLX5_IPSEC_DEV(c
->priv
->mdev
))
1135 set_bit(MLX5E_SQ_STATE_IPSEC
, &sq
->state
);
1137 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
1138 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
, &sq
->wq_ctrl
);
1141 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
1143 err
= mlx5e_alloc_txqsq_db(sq
, cpu_to_node(c
->cpu
));
1145 goto err_sq_wq_destroy
;
1147 sq
->edge
= (sq
->wq
.sz_m1
+ 1) - MLX5_SEND_WQE_MAX_WQEBBS
;
1152 mlx5_wq_destroy(&sq
->wq_ctrl
);
1157 static void mlx5e_free_txqsq(struct mlx5e_txqsq
*sq
)
1159 mlx5e_free_txqsq_db(sq
);
1160 mlx5_wq_destroy(&sq
->wq_ctrl
);
1163 struct mlx5e_create_sq_param
{
1164 struct mlx5_wq_ctrl
*wq_ctrl
;
1171 static int mlx5e_create_sq(struct mlx5_core_dev
*mdev
,
1172 struct mlx5e_sq_param
*param
,
1173 struct mlx5e_create_sq_param
*csp
,
1182 inlen
= MLX5_ST_SZ_BYTES(create_sq_in
) +
1183 sizeof(u64
) * csp
->wq_ctrl
->buf
.npages
;
1184 in
= kvzalloc(inlen
, GFP_KERNEL
);
1188 sqc
= MLX5_ADDR_OF(create_sq_in
, in
, ctx
);
1189 wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1191 memcpy(sqc
, param
->sqc
, sizeof(param
->sqc
));
1192 MLX5_SET(sqc
, sqc
, tis_lst_sz
, csp
->tis_lst_sz
);
1193 MLX5_SET(sqc
, sqc
, tis_num_0
, csp
->tisn
);
1194 MLX5_SET(sqc
, sqc
, cqn
, csp
->cqn
);
1196 if (MLX5_CAP_ETH(mdev
, wqe_inline_mode
) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT
)
1197 MLX5_SET(sqc
, sqc
, min_wqe_inline_mode
, csp
->min_inline_mode
);
1199 MLX5_SET(sqc
, sqc
, state
, MLX5_SQC_STATE_RST
);
1201 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
1202 MLX5_SET(wq
, wq
, uar_page
, mdev
->mlx5e_res
.bfreg
.index
);
1203 MLX5_SET(wq
, wq
, log_wq_pg_sz
, csp
->wq_ctrl
->buf
.page_shift
-
1204 MLX5_ADAPTER_PAGE_SHIFT
);
1205 MLX5_SET64(wq
, wq
, dbr_addr
, csp
->wq_ctrl
->db
.dma
);
1207 mlx5_fill_page_array(&csp
->wq_ctrl
->buf
, (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
1209 err
= mlx5_core_create_sq(mdev
, in
, inlen
, sqn
);
1216 struct mlx5e_modify_sq_param
{
1223 static int mlx5e_modify_sq(struct mlx5_core_dev
*mdev
, u32 sqn
,
1224 struct mlx5e_modify_sq_param
*p
)
1231 inlen
= MLX5_ST_SZ_BYTES(modify_sq_in
);
1232 in
= kvzalloc(inlen
, GFP_KERNEL
);
1236 sqc
= MLX5_ADDR_OF(modify_sq_in
, in
, ctx
);
1238 MLX5_SET(modify_sq_in
, in
, sq_state
, p
->curr_state
);
1239 MLX5_SET(sqc
, sqc
, state
, p
->next_state
);
1240 if (p
->rl_update
&& p
->next_state
== MLX5_SQC_STATE_RDY
) {
1241 MLX5_SET64(modify_sq_in
, in
, modify_bitmask
, 1);
1242 MLX5_SET(sqc
, sqc
, packet_pacing_rate_limit_index
, p
->rl_index
);
1245 err
= mlx5_core_modify_sq(mdev
, sqn
, in
, inlen
);
1252 static void mlx5e_destroy_sq(struct mlx5_core_dev
*mdev
, u32 sqn
)
1254 mlx5_core_destroy_sq(mdev
, sqn
);
1257 static int mlx5e_create_sq_rdy(struct mlx5_core_dev
*mdev
,
1258 struct mlx5e_sq_param
*param
,
1259 struct mlx5e_create_sq_param
*csp
,
1262 struct mlx5e_modify_sq_param msp
= {0};
1265 err
= mlx5e_create_sq(mdev
, param
, csp
, sqn
);
1269 msp
.curr_state
= MLX5_SQC_STATE_RST
;
1270 msp
.next_state
= MLX5_SQC_STATE_RDY
;
1271 err
= mlx5e_modify_sq(mdev
, *sqn
, &msp
);
1273 mlx5e_destroy_sq(mdev
, *sqn
);
1278 static int mlx5e_set_sq_maxrate(struct net_device
*dev
,
1279 struct mlx5e_txqsq
*sq
, u32 rate
);
1281 static int mlx5e_open_txqsq(struct mlx5e_channel
*c
,
1284 struct mlx5e_params
*params
,
1285 struct mlx5e_sq_param
*param
,
1286 struct mlx5e_txqsq
*sq
)
1288 struct mlx5e_create_sq_param csp
= {};
1292 err
= mlx5e_alloc_txqsq(c
, txq_ix
, params
, param
, sq
);
1298 csp
.cqn
= sq
->cq
.mcq
.cqn
;
1299 csp
.wq_ctrl
= &sq
->wq_ctrl
;
1300 csp
.min_inline_mode
= sq
->min_inline_mode
;
1301 err
= mlx5e_create_sq_rdy(c
->mdev
, param
, &csp
, &sq
->sqn
);
1303 goto err_free_txqsq
;
1305 tx_rate
= c
->priv
->tx_rates
[sq
->txq_ix
];
1307 mlx5e_set_sq_maxrate(c
->netdev
, sq
, tx_rate
);
1312 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1313 mlx5e_free_txqsq(sq
);
1318 static void mlx5e_activate_txqsq(struct mlx5e_txqsq
*sq
)
1320 sq
->txq
= netdev_get_tx_queue(sq
->channel
->netdev
, sq
->txq_ix
);
1321 set_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1322 netdev_tx_reset_queue(sq
->txq
);
1323 netif_tx_start_queue(sq
->txq
);
1326 static inline void netif_tx_disable_queue(struct netdev_queue
*txq
)
1328 __netif_tx_lock_bh(txq
);
1329 netif_tx_stop_queue(txq
);
1330 __netif_tx_unlock_bh(txq
);
1333 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq
*sq
)
1335 struct mlx5e_channel
*c
= sq
->channel
;
1337 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1338 /* prevent netif_tx_wake_queue */
1339 napi_synchronize(&c
->napi
);
1341 netif_tx_disable_queue(sq
->txq
);
1343 /* last doorbell out, godspeed .. */
1344 if (mlx5e_wqc_has_room_for(&sq
->wq
, sq
->cc
, sq
->pc
, 1)) {
1345 struct mlx5e_tx_wqe
*nop
;
1347 sq
->db
.wqe_info
[(sq
->pc
& sq
->wq
.sz_m1
)].skb
= NULL
;
1348 nop
= mlx5e_post_nop(&sq
->wq
, sq
->sqn
, &sq
->pc
);
1349 mlx5e_notify_hw(&sq
->wq
, sq
->pc
, sq
->uar_map
, &nop
->ctrl
);
1353 static void mlx5e_close_txqsq(struct mlx5e_txqsq
*sq
)
1355 struct mlx5e_channel
*c
= sq
->channel
;
1356 struct mlx5_core_dev
*mdev
= c
->mdev
;
1358 mlx5e_destroy_sq(mdev
, sq
->sqn
);
1360 mlx5_rl_remove_rate(mdev
, sq
->rate_limit
);
1361 mlx5e_free_txqsq_descs(sq
);
1362 mlx5e_free_txqsq(sq
);
1365 static int mlx5e_open_icosq(struct mlx5e_channel
*c
,
1366 struct mlx5e_params
*params
,
1367 struct mlx5e_sq_param
*param
,
1368 struct mlx5e_icosq
*sq
)
1370 struct mlx5e_create_sq_param csp
= {};
1373 err
= mlx5e_alloc_icosq(c
, param
, sq
);
1377 csp
.cqn
= sq
->cq
.mcq
.cqn
;
1378 csp
.wq_ctrl
= &sq
->wq_ctrl
;
1379 csp
.min_inline_mode
= params
->tx_min_inline_mode
;
1380 set_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1381 err
= mlx5e_create_sq_rdy(c
->mdev
, param
, &csp
, &sq
->sqn
);
1383 goto err_free_icosq
;
1388 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1389 mlx5e_free_icosq(sq
);
1394 static void mlx5e_close_icosq(struct mlx5e_icosq
*sq
)
1396 struct mlx5e_channel
*c
= sq
->channel
;
1398 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1399 napi_synchronize(&c
->napi
);
1401 mlx5e_destroy_sq(c
->mdev
, sq
->sqn
);
1402 mlx5e_free_icosq(sq
);
1405 static int mlx5e_open_xdpsq(struct mlx5e_channel
*c
,
1406 struct mlx5e_params
*params
,
1407 struct mlx5e_sq_param
*param
,
1408 struct mlx5e_xdpsq
*sq
)
1410 unsigned int ds_cnt
= MLX5E_XDP_TX_DS_COUNT
;
1411 struct mlx5e_create_sq_param csp
= {};
1412 unsigned int inline_hdr_sz
= 0;
1416 err
= mlx5e_alloc_xdpsq(c
, params
, param
, sq
);
1421 csp
.tisn
= c
->priv
->tisn
[0]; /* tc = 0 */
1422 csp
.cqn
= sq
->cq
.mcq
.cqn
;
1423 csp
.wq_ctrl
= &sq
->wq_ctrl
;
1424 csp
.min_inline_mode
= sq
->min_inline_mode
;
1425 set_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1426 err
= mlx5e_create_sq_rdy(c
->mdev
, param
, &csp
, &sq
->sqn
);
1428 goto err_free_xdpsq
;
1430 if (sq
->min_inline_mode
!= MLX5_INLINE_MODE_NONE
) {
1431 inline_hdr_sz
= MLX5E_XDP_MIN_INLINE
;
1435 /* Pre initialize fixed WQE fields */
1436 for (i
= 0; i
< mlx5_wq_cyc_get_size(&sq
->wq
); i
++) {
1437 struct mlx5e_tx_wqe
*wqe
= mlx5_wq_cyc_get_wqe(&sq
->wq
, i
);
1438 struct mlx5_wqe_ctrl_seg
*cseg
= &wqe
->ctrl
;
1439 struct mlx5_wqe_eth_seg
*eseg
= &wqe
->eth
;
1440 struct mlx5_wqe_data_seg
*dseg
;
1442 cseg
->qpn_ds
= cpu_to_be32((sq
->sqn
<< 8) | ds_cnt
);
1443 eseg
->inline_hdr
.sz
= cpu_to_be16(inline_hdr_sz
);
1445 dseg
= (struct mlx5_wqe_data_seg
*)cseg
+ (ds_cnt
- 1);
1446 dseg
->lkey
= sq
->mkey_be
;
1452 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1453 mlx5e_free_xdpsq(sq
);
1458 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq
*sq
)
1460 struct mlx5e_channel
*c
= sq
->channel
;
1462 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1463 napi_synchronize(&c
->napi
);
1465 mlx5e_destroy_sq(c
->mdev
, sq
->sqn
);
1466 mlx5e_free_xdpsq_descs(sq
);
1467 mlx5e_free_xdpsq(sq
);
1470 static int mlx5e_alloc_cq_common(struct mlx5_core_dev
*mdev
,
1471 struct mlx5e_cq_param
*param
,
1472 struct mlx5e_cq
*cq
)
1474 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
1480 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
1485 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
1488 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
1489 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
1490 *mcq
->set_ci_db
= 0;
1492 mcq
->vector
= param
->eq_ix
;
1493 mcq
->comp
= mlx5e_completion_event
;
1494 mcq
->event
= mlx5e_cq_error_event
;
1497 for (i
= 0; i
< mlx5_cqwq_get_size(&cq
->wq
); i
++) {
1498 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, i
);
1508 static int mlx5e_alloc_cq(struct mlx5e_channel
*c
,
1509 struct mlx5e_cq_param
*param
,
1510 struct mlx5e_cq
*cq
)
1512 struct mlx5_core_dev
*mdev
= c
->priv
->mdev
;
1515 param
->wq
.buf_numa_node
= cpu_to_node(c
->cpu
);
1516 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
1517 param
->eq_ix
= c
->ix
;
1519 err
= mlx5e_alloc_cq_common(mdev
, param
, cq
);
1521 cq
->napi
= &c
->napi
;
1527 static void mlx5e_free_cq(struct mlx5e_cq
*cq
)
1529 mlx5_cqwq_destroy(&cq
->wq_ctrl
);
1532 static int mlx5e_create_cq(struct mlx5e_cq
*cq
, struct mlx5e_cq_param
*param
)
1534 struct mlx5_core_dev
*mdev
= cq
->mdev
;
1535 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
1540 unsigned int irqn_not_used
;
1544 inlen
= MLX5_ST_SZ_BYTES(create_cq_in
) +
1545 sizeof(u64
) * cq
->wq_ctrl
.frag_buf
.npages
;
1546 in
= kvzalloc(inlen
, GFP_KERNEL
);
1550 cqc
= MLX5_ADDR_OF(create_cq_in
, in
, cq_context
);
1552 memcpy(cqc
, param
->cqc
, sizeof(param
->cqc
));
1554 mlx5_fill_page_frag_array(&cq
->wq_ctrl
.frag_buf
,
1555 (__be64
*)MLX5_ADDR_OF(create_cq_in
, in
, pas
));
1557 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn
, &irqn_not_used
);
1559 MLX5_SET(cqc
, cqc
, cq_period_mode
, param
->cq_period_mode
);
1560 MLX5_SET(cqc
, cqc
, c_eqn
, eqn
);
1561 MLX5_SET(cqc
, cqc
, uar_page
, mdev
->priv
.uar
->index
);
1562 MLX5_SET(cqc
, cqc
, log_page_size
, cq
->wq_ctrl
.frag_buf
.page_shift
-
1563 MLX5_ADAPTER_PAGE_SHIFT
);
1564 MLX5_SET64(cqc
, cqc
, dbr_addr
, cq
->wq_ctrl
.db
.dma
);
1566 err
= mlx5_core_create_cq(mdev
, mcq
, in
, inlen
);
1578 static void mlx5e_destroy_cq(struct mlx5e_cq
*cq
)
1580 mlx5_core_destroy_cq(cq
->mdev
, &cq
->mcq
);
1583 static int mlx5e_open_cq(struct mlx5e_channel
*c
,
1584 struct net_dim_cq_moder moder
,
1585 struct mlx5e_cq_param
*param
,
1586 struct mlx5e_cq
*cq
)
1588 struct mlx5_core_dev
*mdev
= c
->mdev
;
1591 err
= mlx5e_alloc_cq(c
, param
, cq
);
1595 err
= mlx5e_create_cq(cq
, param
);
1599 if (MLX5_CAP_GEN(mdev
, cq_moderation
))
1600 mlx5_core_modify_cq_moderation(mdev
, &cq
->mcq
, moder
.usec
, moder
.pkts
);
1609 static void mlx5e_close_cq(struct mlx5e_cq
*cq
)
1611 mlx5e_destroy_cq(cq
);
1615 static int mlx5e_get_cpu(struct mlx5e_priv
*priv
, int ix
)
1617 return cpumask_first(priv
->mdev
->priv
.irq_info
[ix
].mask
);
1620 static int mlx5e_open_tx_cqs(struct mlx5e_channel
*c
,
1621 struct mlx5e_params
*params
,
1622 struct mlx5e_channel_param
*cparam
)
1627 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
1628 err
= mlx5e_open_cq(c
, params
->tx_cq_moderation
,
1629 &cparam
->tx_cq
, &c
->sq
[tc
].cq
);
1631 goto err_close_tx_cqs
;
1637 for (tc
--; tc
>= 0; tc
--)
1638 mlx5e_close_cq(&c
->sq
[tc
].cq
);
1643 static void mlx5e_close_tx_cqs(struct mlx5e_channel
*c
)
1647 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1648 mlx5e_close_cq(&c
->sq
[tc
].cq
);
1651 static int mlx5e_open_sqs(struct mlx5e_channel
*c
,
1652 struct mlx5e_params
*params
,
1653 struct mlx5e_channel_param
*cparam
)
1658 for (tc
= 0; tc
< params
->num_tc
; tc
++) {
1659 int txq_ix
= c
->ix
+ tc
* params
->num_channels
;
1661 err
= mlx5e_open_txqsq(c
, c
->priv
->tisn
[tc
], txq_ix
,
1662 params
, &cparam
->sq
, &c
->sq
[tc
]);
1670 for (tc
--; tc
>= 0; tc
--)
1671 mlx5e_close_txqsq(&c
->sq
[tc
]);
1676 static void mlx5e_close_sqs(struct mlx5e_channel
*c
)
1680 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1681 mlx5e_close_txqsq(&c
->sq
[tc
]);
1684 static int mlx5e_set_sq_maxrate(struct net_device
*dev
,
1685 struct mlx5e_txqsq
*sq
, u32 rate
)
1687 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1688 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1689 struct mlx5e_modify_sq_param msp
= {0};
1693 if (rate
== sq
->rate_limit
)
1698 /* remove current rl index to free space to next ones */
1699 mlx5_rl_remove_rate(mdev
, sq
->rate_limit
);
1704 err
= mlx5_rl_add_rate(mdev
, rate
, &rl_index
);
1706 netdev_err(dev
, "Failed configuring rate %u: %d\n",
1712 msp
.curr_state
= MLX5_SQC_STATE_RDY
;
1713 msp
.next_state
= MLX5_SQC_STATE_RDY
;
1714 msp
.rl_index
= rl_index
;
1715 msp
.rl_update
= true;
1716 err
= mlx5e_modify_sq(mdev
, sq
->sqn
, &msp
);
1718 netdev_err(dev
, "Failed configuring rate %u: %d\n",
1720 /* remove the rate from the table */
1722 mlx5_rl_remove_rate(mdev
, rate
);
1726 sq
->rate_limit
= rate
;
1730 static int mlx5e_set_tx_maxrate(struct net_device
*dev
, int index
, u32 rate
)
1732 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1733 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1734 struct mlx5e_txqsq
*sq
= priv
->txq2sq
[index
];
1737 if (!mlx5_rl_is_supported(mdev
)) {
1738 netdev_err(dev
, "Rate limiting is not supported on this device\n");
1742 /* rate is given in Mb/sec, HW config is in Kb/sec */
1745 /* Check whether rate in valid range, 0 is always valid */
1746 if (rate
&& !mlx5_rl_is_in_range(mdev
, rate
)) {
1747 netdev_err(dev
, "TX rate %u, is not in range\n", rate
);
1751 mutex_lock(&priv
->state_lock
);
1752 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
1753 err
= mlx5e_set_sq_maxrate(dev
, sq
, rate
);
1755 priv
->tx_rates
[index
] = rate
;
1756 mutex_unlock(&priv
->state_lock
);
1761 static int mlx5e_open_channel(struct mlx5e_priv
*priv
, int ix
,
1762 struct mlx5e_params
*params
,
1763 struct mlx5e_channel_param
*cparam
,
1764 struct mlx5e_channel
**cp
)
1766 struct net_dim_cq_moder icocq_moder
= {0, 0};
1767 struct net_device
*netdev
= priv
->netdev
;
1768 int cpu
= mlx5e_get_cpu(priv
, ix
);
1769 struct mlx5e_channel
*c
;
1774 c
= kzalloc_node(sizeof(*c
), GFP_KERNEL
, cpu_to_node(cpu
));
1779 c
->mdev
= priv
->mdev
;
1780 c
->tstamp
= &priv
->tstamp
;
1783 c
->pdev
= &priv
->mdev
->pdev
->dev
;
1784 c
->netdev
= priv
->netdev
;
1785 c
->mkey_be
= cpu_to_be32(priv
->mdev
->mlx5e_res
.mkey
.key
);
1786 c
->num_tc
= params
->num_tc
;
1787 c
->xdp
= !!params
->xdp_prog
;
1789 mlx5_vector2eqn(priv
->mdev
, ix
, &eqn
, &irq
);
1790 c
->irq_desc
= irq_to_desc(irq
);
1792 netif_napi_add(netdev
, &c
->napi
, mlx5e_napi_poll
, 64);
1794 err
= mlx5e_open_cq(c
, icocq_moder
, &cparam
->icosq_cq
, &c
->icosq
.cq
);
1798 err
= mlx5e_open_tx_cqs(c
, params
, cparam
);
1800 goto err_close_icosq_cq
;
1802 err
= mlx5e_open_cq(c
, params
->rx_cq_moderation
, &cparam
->rx_cq
, &c
->rq
.cq
);
1804 goto err_close_tx_cqs
;
1806 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1807 err
= c
->xdp
? mlx5e_open_cq(c
, params
->tx_cq_moderation
,
1808 &cparam
->tx_cq
, &c
->rq
.xdpsq
.cq
) : 0;
1810 goto err_close_rx_cq
;
1812 napi_enable(&c
->napi
);
1814 err
= mlx5e_open_icosq(c
, params
, &cparam
->icosq
, &c
->icosq
);
1816 goto err_disable_napi
;
1818 err
= mlx5e_open_sqs(c
, params
, cparam
);
1820 goto err_close_icosq
;
1822 err
= c
->xdp
? mlx5e_open_xdpsq(c
, params
, &cparam
->xdp_sq
, &c
->rq
.xdpsq
) : 0;
1826 err
= mlx5e_open_rq(c
, params
, &cparam
->rq
, &c
->rq
);
1828 goto err_close_xdp_sq
;
1835 mlx5e_close_xdpsq(&c
->rq
.xdpsq
);
1841 mlx5e_close_icosq(&c
->icosq
);
1844 napi_disable(&c
->napi
);
1846 mlx5e_close_cq(&c
->rq
.xdpsq
.cq
);
1849 mlx5e_close_cq(&c
->rq
.cq
);
1852 mlx5e_close_tx_cqs(c
);
1855 mlx5e_close_cq(&c
->icosq
.cq
);
1858 netif_napi_del(&c
->napi
);
1864 static void mlx5e_activate_channel(struct mlx5e_channel
*c
)
1868 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1869 mlx5e_activate_txqsq(&c
->sq
[tc
]);
1870 mlx5e_activate_rq(&c
->rq
);
1871 netif_set_xps_queue(c
->netdev
, get_cpu_mask(c
->cpu
), c
->ix
);
1874 static void mlx5e_deactivate_channel(struct mlx5e_channel
*c
)
1878 mlx5e_deactivate_rq(&c
->rq
);
1879 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1880 mlx5e_deactivate_txqsq(&c
->sq
[tc
]);
1883 static void mlx5e_close_channel(struct mlx5e_channel
*c
)
1885 mlx5e_close_rq(&c
->rq
);
1887 mlx5e_close_xdpsq(&c
->rq
.xdpsq
);
1889 mlx5e_close_icosq(&c
->icosq
);
1890 napi_disable(&c
->napi
);
1892 mlx5e_close_cq(&c
->rq
.xdpsq
.cq
);
1893 mlx5e_close_cq(&c
->rq
.cq
);
1894 mlx5e_close_tx_cqs(c
);
1895 mlx5e_close_cq(&c
->icosq
.cq
);
1896 netif_napi_del(&c
->napi
);
1901 static void mlx5e_build_rq_param(struct mlx5e_priv
*priv
,
1902 struct mlx5e_params
*params
,
1903 struct mlx5e_rq_param
*param
)
1905 void *rqc
= param
->rqc
;
1906 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1908 switch (params
->rq_wq_type
) {
1909 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
1910 MLX5_SET(wq
, wq
, log_wqe_num_of_strides
, params
->mpwqe_log_num_strides
- 9);
1911 MLX5_SET(wq
, wq
, log_wqe_stride_size
, params
->mpwqe_log_stride_sz
- 6);
1912 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
);
1914 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1915 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1918 MLX5_SET(wq
, wq
, end_padding_mode
, MLX5_WQ_END_PAD_MODE_ALIGN
);
1919 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1920 MLX5_SET(wq
, wq
, log_wq_sz
, params
->log_rq_size
);
1921 MLX5_SET(wq
, wq
, pd
, priv
->mdev
->mlx5e_res
.pdn
);
1922 MLX5_SET(rqc
, rqc
, counter_set_id
, priv
->q_counter
);
1923 MLX5_SET(rqc
, rqc
, vsd
, params
->vlan_strip_disable
);
1924 MLX5_SET(rqc
, rqc
, scatter_fcs
, params
->scatter_fcs_en
);
1926 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1927 param
->wq
.linear
= 1;
1930 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param
*param
)
1932 void *rqc
= param
->rqc
;
1933 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1935 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1936 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1939 static void mlx5e_build_sq_param_common(struct mlx5e_priv
*priv
,
1940 struct mlx5e_sq_param
*param
)
1942 void *sqc
= param
->sqc
;
1943 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1945 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(MLX5_SEND_WQE_BB
));
1946 MLX5_SET(wq
, wq
, pd
, priv
->mdev
->mlx5e_res
.pdn
);
1948 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1951 static void mlx5e_build_sq_param(struct mlx5e_priv
*priv
,
1952 struct mlx5e_params
*params
,
1953 struct mlx5e_sq_param
*param
)
1955 void *sqc
= param
->sqc
;
1956 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1958 mlx5e_build_sq_param_common(priv
, param
);
1959 MLX5_SET(wq
, wq
, log_wq_sz
, params
->log_sq_size
);
1960 MLX5_SET(sqc
, sqc
, allow_swp
, !!MLX5_IPSEC_DEV(priv
->mdev
));
1963 static void mlx5e_build_common_cq_param(struct mlx5e_priv
*priv
,
1964 struct mlx5e_cq_param
*param
)
1966 void *cqc
= param
->cqc
;
1968 MLX5_SET(cqc
, cqc
, uar_page
, priv
->mdev
->priv
.uar
->index
);
1971 static void mlx5e_build_rx_cq_param(struct mlx5e_priv
*priv
,
1972 struct mlx5e_params
*params
,
1973 struct mlx5e_cq_param
*param
)
1975 void *cqc
= param
->cqc
;
1978 switch (params
->rq_wq_type
) {
1979 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
1980 log_cq_size
= params
->log_rq_size
+ params
->mpwqe_log_num_strides
;
1982 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1983 log_cq_size
= params
->log_rq_size
;
1986 MLX5_SET(cqc
, cqc
, log_cq_size
, log_cq_size
);
1987 if (MLX5E_GET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_COMPRESS
)) {
1988 MLX5_SET(cqc
, cqc
, mini_cqe_res_format
, MLX5_CQE_FORMAT_CSUM
);
1989 MLX5_SET(cqc
, cqc
, cqe_comp_en
, 1);
1992 mlx5e_build_common_cq_param(priv
, param
);
1993 param
->cq_period_mode
= params
->rx_cq_moderation
.cq_period_mode
;
1996 static void mlx5e_build_tx_cq_param(struct mlx5e_priv
*priv
,
1997 struct mlx5e_params
*params
,
1998 struct mlx5e_cq_param
*param
)
2000 void *cqc
= param
->cqc
;
2002 MLX5_SET(cqc
, cqc
, log_cq_size
, params
->log_sq_size
);
2004 mlx5e_build_common_cq_param(priv
, param
);
2005 param
->cq_period_mode
= params
->tx_cq_moderation
.cq_period_mode
;
2008 static void mlx5e_build_ico_cq_param(struct mlx5e_priv
*priv
,
2010 struct mlx5e_cq_param
*param
)
2012 void *cqc
= param
->cqc
;
2014 MLX5_SET(cqc
, cqc
, log_cq_size
, log_wq_size
);
2016 mlx5e_build_common_cq_param(priv
, param
);
2018 param
->cq_period_mode
= NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE
;
2021 static void mlx5e_build_icosq_param(struct mlx5e_priv
*priv
,
2023 struct mlx5e_sq_param
*param
)
2025 void *sqc
= param
->sqc
;
2026 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
2028 mlx5e_build_sq_param_common(priv
, param
);
2030 MLX5_SET(wq
, wq
, log_wq_sz
, log_wq_size
);
2031 MLX5_SET(sqc
, sqc
, reg_umr
, MLX5_CAP_ETH(priv
->mdev
, reg_umr_sq
));
2034 static void mlx5e_build_xdpsq_param(struct mlx5e_priv
*priv
,
2035 struct mlx5e_params
*params
,
2036 struct mlx5e_sq_param
*param
)
2038 void *sqc
= param
->sqc
;
2039 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
2041 mlx5e_build_sq_param_common(priv
, param
);
2042 MLX5_SET(wq
, wq
, log_wq_sz
, params
->log_sq_size
);
2045 static void mlx5e_build_channel_param(struct mlx5e_priv
*priv
,
2046 struct mlx5e_params
*params
,
2047 struct mlx5e_channel_param
*cparam
)
2049 u8 icosq_log_wq_sz
= MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE
;
2051 mlx5e_build_rq_param(priv
, params
, &cparam
->rq
);
2052 mlx5e_build_sq_param(priv
, params
, &cparam
->sq
);
2053 mlx5e_build_xdpsq_param(priv
, params
, &cparam
->xdp_sq
);
2054 mlx5e_build_icosq_param(priv
, icosq_log_wq_sz
, &cparam
->icosq
);
2055 mlx5e_build_rx_cq_param(priv
, params
, &cparam
->rx_cq
);
2056 mlx5e_build_tx_cq_param(priv
, params
, &cparam
->tx_cq
);
2057 mlx5e_build_ico_cq_param(priv
, icosq_log_wq_sz
, &cparam
->icosq_cq
);
2060 int mlx5e_open_channels(struct mlx5e_priv
*priv
,
2061 struct mlx5e_channels
*chs
)
2063 struct mlx5e_channel_param
*cparam
;
2067 chs
->num
= chs
->params
.num_channels
;
2069 chs
->c
= kcalloc(chs
->num
, sizeof(struct mlx5e_channel
*), GFP_KERNEL
);
2070 cparam
= kzalloc(sizeof(struct mlx5e_channel_param
), GFP_KERNEL
);
2071 if (!chs
->c
|| !cparam
)
2074 mlx5e_build_channel_param(priv
, &chs
->params
, cparam
);
2075 for (i
= 0; i
< chs
->num
; i
++) {
2076 err
= mlx5e_open_channel(priv
, i
, &chs
->params
, cparam
, &chs
->c
[i
]);
2078 goto err_close_channels
;
2085 for (i
--; i
>= 0; i
--)
2086 mlx5e_close_channel(chs
->c
[i
]);
2095 static void mlx5e_activate_channels(struct mlx5e_channels
*chs
)
2099 for (i
= 0; i
< chs
->num
; i
++)
2100 mlx5e_activate_channel(chs
->c
[i
]);
2103 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels
*chs
)
2108 for (i
= 0; i
< chs
->num
; i
++) {
2109 err
= mlx5e_wait_for_min_rx_wqes(&chs
->c
[i
]->rq
);
2117 static void mlx5e_deactivate_channels(struct mlx5e_channels
*chs
)
2121 for (i
= 0; i
< chs
->num
; i
++)
2122 mlx5e_deactivate_channel(chs
->c
[i
]);
2125 void mlx5e_close_channels(struct mlx5e_channels
*chs
)
2129 for (i
= 0; i
< chs
->num
; i
++)
2130 mlx5e_close_channel(chs
->c
[i
]);
2137 mlx5e_create_rqt(struct mlx5e_priv
*priv
, int sz
, struct mlx5e_rqt
*rqt
)
2139 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2146 inlen
= MLX5_ST_SZ_BYTES(create_rqt_in
) + sizeof(u32
) * sz
;
2147 in
= kvzalloc(inlen
, GFP_KERNEL
);
2151 rqtc
= MLX5_ADDR_OF(create_rqt_in
, in
, rqt_context
);
2153 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
2154 MLX5_SET(rqtc
, rqtc
, rqt_max_size
, sz
);
2156 for (i
= 0; i
< sz
; i
++)
2157 MLX5_SET(rqtc
, rqtc
, rq_num
[i
], priv
->drop_rq
.rqn
);
2159 err
= mlx5_core_create_rqt(mdev
, in
, inlen
, &rqt
->rqtn
);
2161 rqt
->enabled
= true;
2167 void mlx5e_destroy_rqt(struct mlx5e_priv
*priv
, struct mlx5e_rqt
*rqt
)
2169 rqt
->enabled
= false;
2170 mlx5_core_destroy_rqt(priv
->mdev
, rqt
->rqtn
);
2173 int mlx5e_create_indirect_rqt(struct mlx5e_priv
*priv
)
2175 struct mlx5e_rqt
*rqt
= &priv
->indir_rqt
;
2178 err
= mlx5e_create_rqt(priv
, MLX5E_INDIR_RQT_SIZE
, rqt
);
2180 mlx5_core_warn(priv
->mdev
, "create indirect rqts failed, %d\n", err
);
2184 int mlx5e_create_direct_rqts(struct mlx5e_priv
*priv
)
2186 struct mlx5e_rqt
*rqt
;
2190 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
2191 rqt
= &priv
->direct_tir
[ix
].rqt
;
2192 err
= mlx5e_create_rqt(priv
, 1 /*size */, rqt
);
2194 goto err_destroy_rqts
;
2200 mlx5_core_warn(priv
->mdev
, "create direct rqts failed, %d\n", err
);
2201 for (ix
--; ix
>= 0; ix
--)
2202 mlx5e_destroy_rqt(priv
, &priv
->direct_tir
[ix
].rqt
);
2207 void mlx5e_destroy_direct_rqts(struct mlx5e_priv
*priv
)
2211 for (i
= 0; i
< priv
->profile
->max_nch(priv
->mdev
); i
++)
2212 mlx5e_destroy_rqt(priv
, &priv
->direct_tir
[i
].rqt
);
2215 static int mlx5e_rx_hash_fn(int hfunc
)
2217 return (hfunc
== ETH_RSS_HASH_TOP
) ?
2218 MLX5_RX_HASH_FN_TOEPLITZ
:
2219 MLX5_RX_HASH_FN_INVERTED_XOR8
;
2222 static int mlx5e_bits_invert(unsigned long a
, int size
)
2227 for (i
= 0; i
< size
; i
++)
2228 inv
|= (test_bit(size
- i
- 1, &a
) ? 1 : 0) << i
;
2233 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv
*priv
, int sz
,
2234 struct mlx5e_redirect_rqt_param rrp
, void *rqtc
)
2238 for (i
= 0; i
< sz
; i
++) {
2244 if (rrp
.rss
.hfunc
== ETH_RSS_HASH_XOR
)
2245 ix
= mlx5e_bits_invert(i
, ilog2(sz
));
2247 ix
= priv
->channels
.params
.indirection_rqt
[ix
];
2248 rqn
= rrp
.rss
.channels
->c
[ix
]->rq
.rqn
;
2252 MLX5_SET(rqtc
, rqtc
, rq_num
[i
], rqn
);
2256 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, u32 rqtn
, int sz
,
2257 struct mlx5e_redirect_rqt_param rrp
)
2259 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2265 inlen
= MLX5_ST_SZ_BYTES(modify_rqt_in
) + sizeof(u32
) * sz
;
2266 in
= kvzalloc(inlen
, GFP_KERNEL
);
2270 rqtc
= MLX5_ADDR_OF(modify_rqt_in
, in
, ctx
);
2272 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
2273 MLX5_SET(modify_rqt_in
, in
, bitmask
.rqn_list
, 1);
2274 mlx5e_fill_rqt_rqns(priv
, sz
, rrp
, rqtc
);
2275 err
= mlx5_core_modify_rqt(mdev
, rqtn
, in
, inlen
);
2281 static u32
mlx5e_get_direct_rqn(struct mlx5e_priv
*priv
, int ix
,
2282 struct mlx5e_redirect_rqt_param rrp
)
2287 if (ix
>= rrp
.rss
.channels
->num
)
2288 return priv
->drop_rq
.rqn
;
2290 return rrp
.rss
.channels
->c
[ix
]->rq
.rqn
;
2293 static void mlx5e_redirect_rqts(struct mlx5e_priv
*priv
,
2294 struct mlx5e_redirect_rqt_param rrp
)
2299 if (priv
->indir_rqt
.enabled
) {
2301 rqtn
= priv
->indir_rqt
.rqtn
;
2302 mlx5e_redirect_rqt(priv
, rqtn
, MLX5E_INDIR_RQT_SIZE
, rrp
);
2305 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
2306 struct mlx5e_redirect_rqt_param direct_rrp
= {
2309 .rqn
= mlx5e_get_direct_rqn(priv
, ix
, rrp
)
2313 /* Direct RQ Tables */
2314 if (!priv
->direct_tir
[ix
].rqt
.enabled
)
2317 rqtn
= priv
->direct_tir
[ix
].rqt
.rqtn
;
2318 mlx5e_redirect_rqt(priv
, rqtn
, 1, direct_rrp
);
2322 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv
*priv
,
2323 struct mlx5e_channels
*chs
)
2325 struct mlx5e_redirect_rqt_param rrp
= {
2330 .hfunc
= chs
->params
.rss_hfunc
,
2335 mlx5e_redirect_rqts(priv
, rrp
);
2338 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv
*priv
)
2340 struct mlx5e_redirect_rqt_param drop_rrp
= {
2343 .rqn
= priv
->drop_rq
.rqn
,
2347 mlx5e_redirect_rqts(priv
, drop_rrp
);
2350 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params
*params
, void *tirc
)
2352 if (!params
->lro_en
)
2355 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2357 MLX5_SET(tirc
, tirc
, lro_enable_mask
,
2358 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
|
2359 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
);
2360 MLX5_SET(tirc
, tirc
, lro_max_ip_payload_size
,
2361 (params
->lro_wqe_sz
- ROUGH_MAX_L2_L3_HDR_SZ
) >> 8);
2362 MLX5_SET(tirc
, tirc
, lro_timeout_period_usecs
, params
->lro_timeout
);
2365 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params
*params
,
2366 enum mlx5e_traffic_types tt
,
2367 void *tirc
, bool inner
)
2369 void *hfso
= inner
? MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_inner
) :
2370 MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_outer
);
2372 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2373 MLX5_HASH_FIELD_SEL_DST_IP)
2375 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2376 MLX5_HASH_FIELD_SEL_DST_IP |\
2377 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2378 MLX5_HASH_FIELD_SEL_L4_DPORT)
2380 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2381 MLX5_HASH_FIELD_SEL_DST_IP |\
2382 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2384 MLX5_SET(tirc
, tirc
, rx_hash_fn
, mlx5e_rx_hash_fn(params
->rss_hfunc
));
2385 if (params
->rss_hfunc
== ETH_RSS_HASH_TOP
) {
2386 void *rss_key
= MLX5_ADDR_OF(tirc
, tirc
,
2387 rx_hash_toeplitz_key
);
2388 size_t len
= MLX5_FLD_SZ_BYTES(tirc
,
2389 rx_hash_toeplitz_key
);
2391 MLX5_SET(tirc
, tirc
, rx_hash_symmetric
, 1);
2392 memcpy(rss_key
, params
->toeplitz_hash_key
, len
);
2396 case MLX5E_TT_IPV4_TCP
:
2397 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2398 MLX5_L3_PROT_TYPE_IPV4
);
2399 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2400 MLX5_L4_PROT_TYPE_TCP
);
2401 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2402 MLX5_HASH_IP_L4PORTS
);
2405 case MLX5E_TT_IPV6_TCP
:
2406 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2407 MLX5_L3_PROT_TYPE_IPV6
);
2408 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2409 MLX5_L4_PROT_TYPE_TCP
);
2410 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2411 MLX5_HASH_IP_L4PORTS
);
2414 case MLX5E_TT_IPV4_UDP
:
2415 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2416 MLX5_L3_PROT_TYPE_IPV4
);
2417 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2418 MLX5_L4_PROT_TYPE_UDP
);
2419 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2420 MLX5_HASH_IP_L4PORTS
);
2423 case MLX5E_TT_IPV6_UDP
:
2424 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2425 MLX5_L3_PROT_TYPE_IPV6
);
2426 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2427 MLX5_L4_PROT_TYPE_UDP
);
2428 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2429 MLX5_HASH_IP_L4PORTS
);
2432 case MLX5E_TT_IPV4_IPSEC_AH
:
2433 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2434 MLX5_L3_PROT_TYPE_IPV4
);
2435 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2436 MLX5_HASH_IP_IPSEC_SPI
);
2439 case MLX5E_TT_IPV6_IPSEC_AH
:
2440 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2441 MLX5_L3_PROT_TYPE_IPV6
);
2442 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2443 MLX5_HASH_IP_IPSEC_SPI
);
2446 case MLX5E_TT_IPV4_IPSEC_ESP
:
2447 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2448 MLX5_L3_PROT_TYPE_IPV4
);
2449 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2450 MLX5_HASH_IP_IPSEC_SPI
);
2453 case MLX5E_TT_IPV6_IPSEC_ESP
:
2454 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2455 MLX5_L3_PROT_TYPE_IPV6
);
2456 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2457 MLX5_HASH_IP_IPSEC_SPI
);
2461 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2462 MLX5_L3_PROT_TYPE_IPV4
);
2463 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2468 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2469 MLX5_L3_PROT_TYPE_IPV6
);
2470 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2474 WARN_ONCE(true, "%s: bad traffic type!\n", __func__
);
2478 static int mlx5e_modify_tirs_lro(struct mlx5e_priv
*priv
)
2480 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2489 inlen
= MLX5_ST_SZ_BYTES(modify_tir_in
);
2490 in
= kvzalloc(inlen
, GFP_KERNEL
);
2494 MLX5_SET(modify_tir_in
, in
, bitmask
.lro
, 1);
2495 tirc
= MLX5_ADDR_OF(modify_tir_in
, in
, ctx
);
2497 mlx5e_build_tir_ctx_lro(&priv
->channels
.params
, tirc
);
2499 for (tt
= 0; tt
< MLX5E_NUM_INDIR_TIRS
; tt
++) {
2500 err
= mlx5_core_modify_tir(mdev
, priv
->indir_tir
[tt
].tirn
, in
,
2506 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
2507 err
= mlx5_core_modify_tir(mdev
, priv
->direct_tir
[ix
].tirn
,
2519 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv
*priv
,
2520 enum mlx5e_traffic_types tt
,
2523 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2525 mlx5e_build_tir_ctx_lro(&priv
->channels
.params
, tirc
);
2527 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2528 MLX5_SET(tirc
, tirc
, indirect_table
, priv
->indir_rqt
.rqtn
);
2529 MLX5_SET(tirc
, tirc
, tunneled_offload_en
, 0x1);
2531 mlx5e_build_indir_tir_ctx_hash(&priv
->channels
.params
, tt
, tirc
, true);
2534 static int mlx5e_set_mtu(struct mlx5e_priv
*priv
, u16 mtu
)
2536 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2537 u16 hw_mtu
= MLX5E_SW2HW_MTU(priv
, mtu
);
2540 err
= mlx5_set_port_mtu(mdev
, hw_mtu
, 1);
2544 /* Update vport context MTU */
2545 mlx5_modify_nic_vport_mtu(mdev
, hw_mtu
);
2549 static void mlx5e_query_mtu(struct mlx5e_priv
*priv
, u16
*mtu
)
2551 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2555 err
= mlx5_query_nic_vport_mtu(mdev
, &hw_mtu
);
2556 if (err
|| !hw_mtu
) /* fallback to port oper mtu */
2557 mlx5_query_port_oper_mtu(mdev
, &hw_mtu
, 1);
2559 *mtu
= MLX5E_HW2SW_MTU(priv
, hw_mtu
);
2562 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv
*priv
)
2564 struct net_device
*netdev
= priv
->netdev
;
2568 err
= mlx5e_set_mtu(priv
, netdev
->mtu
);
2572 mlx5e_query_mtu(priv
, &mtu
);
2573 if (mtu
!= netdev
->mtu
)
2574 netdev_warn(netdev
, "%s: VPort MTU %d is different than netdev mtu %d\n",
2575 __func__
, mtu
, netdev
->mtu
);
2581 static void mlx5e_netdev_set_tcs(struct net_device
*netdev
)
2583 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2584 int nch
= priv
->channels
.params
.num_channels
;
2585 int ntc
= priv
->channels
.params
.num_tc
;
2588 netdev_reset_tc(netdev
);
2593 netdev_set_num_tc(netdev
, ntc
);
2595 /* Map netdev TCs to offset 0
2596 * We have our own UP to TXQ mapping for QoS
2598 for (tc
= 0; tc
< ntc
; tc
++)
2599 netdev_set_tc_queue(netdev
, tc
, nch
, 0);
2602 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv
*priv
)
2604 struct mlx5e_channel
*c
;
2605 struct mlx5e_txqsq
*sq
;
2608 for (i
= 0; i
< priv
->channels
.num
; i
++)
2609 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++)
2610 priv
->channel_tc2txq
[i
][tc
] = i
+ tc
* priv
->channels
.num
;
2612 for (i
= 0; i
< priv
->channels
.num
; i
++) {
2613 c
= priv
->channels
.c
[i
];
2614 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
2616 priv
->txq2sq
[sq
->txq_ix
] = sq
;
2621 void mlx5e_activate_priv_channels(struct mlx5e_priv
*priv
)
2623 int num_txqs
= priv
->channels
.num
* priv
->channels
.params
.num_tc
;
2624 struct net_device
*netdev
= priv
->netdev
;
2626 mlx5e_netdev_set_tcs(netdev
);
2627 netif_set_real_num_tx_queues(netdev
, num_txqs
);
2628 netif_set_real_num_rx_queues(netdev
, priv
->channels
.num
);
2630 mlx5e_build_channels_tx_maps(priv
);
2631 mlx5e_activate_channels(&priv
->channels
);
2632 netif_tx_start_all_queues(priv
->netdev
);
2634 if (MLX5_VPORT_MANAGER(priv
->mdev
))
2635 mlx5e_add_sqs_fwd_rules(priv
);
2637 mlx5e_wait_channels_min_rx_wqes(&priv
->channels
);
2638 mlx5e_redirect_rqts_to_channels(priv
, &priv
->channels
);
2641 void mlx5e_deactivate_priv_channels(struct mlx5e_priv
*priv
)
2643 mlx5e_redirect_rqts_to_drop(priv
);
2645 if (MLX5_VPORT_MANAGER(priv
->mdev
))
2646 mlx5e_remove_sqs_fwd_rules(priv
);
2648 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2649 * polling for inactive tx queues.
2651 netif_tx_stop_all_queues(priv
->netdev
);
2652 netif_tx_disable(priv
->netdev
);
2653 mlx5e_deactivate_channels(&priv
->channels
);
2656 void mlx5e_switch_priv_channels(struct mlx5e_priv
*priv
,
2657 struct mlx5e_channels
*new_chs
,
2658 mlx5e_fp_hw_modify hw_modify
)
2660 struct net_device
*netdev
= priv
->netdev
;
2663 new_num_txqs
= new_chs
->num
* new_chs
->params
.num_tc
;
2665 carrier_ok
= netif_carrier_ok(netdev
);
2666 netif_carrier_off(netdev
);
2668 if (new_num_txqs
< netdev
->real_num_tx_queues
)
2669 netif_set_real_num_tx_queues(netdev
, new_num_txqs
);
2671 mlx5e_deactivate_priv_channels(priv
);
2672 mlx5e_close_channels(&priv
->channels
);
2674 priv
->channels
= *new_chs
;
2676 /* New channels are ready to roll, modify HW settings if needed */
2680 mlx5e_refresh_tirs(priv
, false);
2681 mlx5e_activate_priv_channels(priv
);
2683 /* return carrier back if needed */
2685 netif_carrier_on(netdev
);
2688 void mlx5e_timestamp_set(struct mlx5e_priv
*priv
)
2690 priv
->tstamp
.tx_type
= HWTSTAMP_TX_OFF
;
2691 priv
->tstamp
.rx_filter
= HWTSTAMP_FILTER_NONE
;
2694 int mlx5e_open_locked(struct net_device
*netdev
)
2696 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2699 set_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2701 err
= mlx5e_open_channels(priv
, &priv
->channels
);
2703 goto err_clear_state_opened_flag
;
2705 mlx5e_refresh_tirs(priv
, false);
2706 mlx5e_activate_priv_channels(priv
);
2707 if (priv
->profile
->update_carrier
)
2708 priv
->profile
->update_carrier(priv
);
2709 mlx5e_timestamp_set(priv
);
2711 if (priv
->profile
->update_stats
)
2712 queue_delayed_work(priv
->wq
, &priv
->update_stats_work
, 0);
2716 err_clear_state_opened_flag
:
2717 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2721 int mlx5e_open(struct net_device
*netdev
)
2723 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2726 mutex_lock(&priv
->state_lock
);
2727 err
= mlx5e_open_locked(netdev
);
2729 mlx5_set_port_admin_status(priv
->mdev
, MLX5_PORT_UP
);
2730 mutex_unlock(&priv
->state_lock
);
2735 int mlx5e_close_locked(struct net_device
*netdev
)
2737 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2739 /* May already be CLOSED in case a previous configuration operation
2740 * (e.g RX/TX queue size change) that involves close&open failed.
2742 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
2745 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2747 netif_carrier_off(priv
->netdev
);
2748 mlx5e_deactivate_priv_channels(priv
);
2749 mlx5e_close_channels(&priv
->channels
);
2754 int mlx5e_close(struct net_device
*netdev
)
2756 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2759 if (!netif_device_present(netdev
))
2762 mutex_lock(&priv
->state_lock
);
2763 mlx5_set_port_admin_status(priv
->mdev
, MLX5_PORT_DOWN
);
2764 err
= mlx5e_close_locked(netdev
);
2765 mutex_unlock(&priv
->state_lock
);
2770 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev
*mdev
,
2771 struct mlx5e_rq
*rq
,
2772 struct mlx5e_rq_param
*param
)
2774 void *rqc
= param
->rqc
;
2775 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
2778 param
->wq
.db_numa_node
= param
->wq
.buf_numa_node
;
2780 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
2785 /* Mark as unused given "Drop-RQ" packets never reach XDP */
2786 xdp_rxq_info_unused(&rq
->xdp_rxq
);
2793 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev
*mdev
,
2794 struct mlx5e_cq
*cq
,
2795 struct mlx5e_cq_param
*param
)
2797 return mlx5e_alloc_cq_common(mdev
, param
, cq
);
2800 static int mlx5e_open_drop_rq(struct mlx5_core_dev
*mdev
,
2801 struct mlx5e_rq
*drop_rq
)
2803 struct mlx5e_cq_param cq_param
= {};
2804 struct mlx5e_rq_param rq_param
= {};
2805 struct mlx5e_cq
*cq
= &drop_rq
->cq
;
2808 mlx5e_build_drop_rq_param(&rq_param
);
2810 err
= mlx5e_alloc_drop_cq(mdev
, cq
, &cq_param
);
2814 err
= mlx5e_create_cq(cq
, &cq_param
);
2818 err
= mlx5e_alloc_drop_rq(mdev
, drop_rq
, &rq_param
);
2820 goto err_destroy_cq
;
2822 err
= mlx5e_create_rq(drop_rq
, &rq_param
);
2829 mlx5e_free_rq(drop_rq
);
2832 mlx5e_destroy_cq(cq
);
2840 static void mlx5e_close_drop_rq(struct mlx5e_rq
*drop_rq
)
2842 mlx5e_destroy_rq(drop_rq
);
2843 mlx5e_free_rq(drop_rq
);
2844 mlx5e_destroy_cq(&drop_rq
->cq
);
2845 mlx5e_free_cq(&drop_rq
->cq
);
2848 int mlx5e_create_tis(struct mlx5_core_dev
*mdev
, int tc
,
2849 u32 underlay_qpn
, u32
*tisn
)
2851 u32 in
[MLX5_ST_SZ_DW(create_tis_in
)] = {0};
2852 void *tisc
= MLX5_ADDR_OF(create_tis_in
, in
, ctx
);
2854 MLX5_SET(tisc
, tisc
, prio
, tc
<< 1);
2855 MLX5_SET(tisc
, tisc
, underlay_qpn
, underlay_qpn
);
2856 MLX5_SET(tisc
, tisc
, transport_domain
, mdev
->mlx5e_res
.td
.tdn
);
2858 if (mlx5_lag_is_lacp_owner(mdev
))
2859 MLX5_SET(tisc
, tisc
, strict_lag_tx_port_affinity
, 1);
2861 return mlx5_core_create_tis(mdev
, in
, sizeof(in
), tisn
);
2864 void mlx5e_destroy_tis(struct mlx5_core_dev
*mdev
, u32 tisn
)
2866 mlx5_core_destroy_tis(mdev
, tisn
);
2869 int mlx5e_create_tises(struct mlx5e_priv
*priv
)
2874 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++) {
2875 err
= mlx5e_create_tis(priv
->mdev
, tc
, 0, &priv
->tisn
[tc
]);
2877 goto err_close_tises
;
2883 for (tc
--; tc
>= 0; tc
--)
2884 mlx5e_destroy_tis(priv
->mdev
, priv
->tisn
[tc
]);
2889 void mlx5e_cleanup_nic_tx(struct mlx5e_priv
*priv
)
2893 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++)
2894 mlx5e_destroy_tis(priv
->mdev
, priv
->tisn
[tc
]);
2897 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv
*priv
,
2898 enum mlx5e_traffic_types tt
,
2901 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2903 mlx5e_build_tir_ctx_lro(&priv
->channels
.params
, tirc
);
2905 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2906 MLX5_SET(tirc
, tirc
, indirect_table
, priv
->indir_rqt
.rqtn
);
2907 mlx5e_build_indir_tir_ctx_hash(&priv
->channels
.params
, tt
, tirc
, false);
2910 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv
*priv
, u32 rqtn
, u32
*tirc
)
2912 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2914 mlx5e_build_tir_ctx_lro(&priv
->channels
.params
, tirc
);
2916 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2917 MLX5_SET(tirc
, tirc
, indirect_table
, rqtn
);
2918 MLX5_SET(tirc
, tirc
, rx_hash_fn
, MLX5_RX_HASH_FN_INVERTED_XOR8
);
2921 int mlx5e_create_indirect_tirs(struct mlx5e_priv
*priv
)
2923 struct mlx5e_tir
*tir
;
2931 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
2932 in
= kvzalloc(inlen
, GFP_KERNEL
);
2936 for (tt
= 0; tt
< MLX5E_NUM_INDIR_TIRS
; tt
++) {
2937 memset(in
, 0, inlen
);
2938 tir
= &priv
->indir_tir
[tt
];
2939 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2940 mlx5e_build_indir_tir_ctx(priv
, tt
, tirc
);
2941 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
2943 mlx5_core_warn(priv
->mdev
, "create indirect tirs failed, %d\n", err
);
2944 goto err_destroy_inner_tirs
;
2948 if (!mlx5e_tunnel_inner_ft_supported(priv
->mdev
))
2951 for (i
= 0; i
< MLX5E_NUM_INDIR_TIRS
; i
++) {
2952 memset(in
, 0, inlen
);
2953 tir
= &priv
->inner_indir_tir
[i
];
2954 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2955 mlx5e_build_inner_indir_tir_ctx(priv
, i
, tirc
);
2956 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
2958 mlx5_core_warn(priv
->mdev
, "create inner indirect tirs failed, %d\n", err
);
2959 goto err_destroy_inner_tirs
;
2968 err_destroy_inner_tirs
:
2969 for (i
--; i
>= 0; i
--)
2970 mlx5e_destroy_tir(priv
->mdev
, &priv
->inner_indir_tir
[i
]);
2972 for (tt
--; tt
>= 0; tt
--)
2973 mlx5e_destroy_tir(priv
->mdev
, &priv
->indir_tir
[tt
]);
2980 int mlx5e_create_direct_tirs(struct mlx5e_priv
*priv
)
2982 int nch
= priv
->profile
->max_nch(priv
->mdev
);
2983 struct mlx5e_tir
*tir
;
2990 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
2991 in
= kvzalloc(inlen
, GFP_KERNEL
);
2995 for (ix
= 0; ix
< nch
; ix
++) {
2996 memset(in
, 0, inlen
);
2997 tir
= &priv
->direct_tir
[ix
];
2998 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2999 mlx5e_build_direct_tir_ctx(priv
, priv
->direct_tir
[ix
].rqt
.rqtn
, tirc
);
3000 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
3002 goto err_destroy_ch_tirs
;
3009 err_destroy_ch_tirs
:
3010 mlx5_core_warn(priv
->mdev
, "create direct tirs failed, %d\n", err
);
3011 for (ix
--; ix
>= 0; ix
--)
3012 mlx5e_destroy_tir(priv
->mdev
, &priv
->direct_tir
[ix
]);
3019 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv
*priv
)
3023 for (i
= 0; i
< MLX5E_NUM_INDIR_TIRS
; i
++)
3024 mlx5e_destroy_tir(priv
->mdev
, &priv
->indir_tir
[i
]);
3026 if (!mlx5e_tunnel_inner_ft_supported(priv
->mdev
))
3029 for (i
= 0; i
< MLX5E_NUM_INDIR_TIRS
; i
++)
3030 mlx5e_destroy_tir(priv
->mdev
, &priv
->inner_indir_tir
[i
]);
3033 void mlx5e_destroy_direct_tirs(struct mlx5e_priv
*priv
)
3035 int nch
= priv
->profile
->max_nch(priv
->mdev
);
3038 for (i
= 0; i
< nch
; i
++)
3039 mlx5e_destroy_tir(priv
->mdev
, &priv
->direct_tir
[i
]);
3042 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels
*chs
, bool enable
)
3047 for (i
= 0; i
< chs
->num
; i
++) {
3048 err
= mlx5e_modify_rq_scatter_fcs(&chs
->c
[i
]->rq
, enable
);
3056 static int mlx5e_modify_channels_vsd(struct mlx5e_channels
*chs
, bool vsd
)
3061 for (i
= 0; i
< chs
->num
; i
++) {
3062 err
= mlx5e_modify_rq_vsd(&chs
->c
[i
]->rq
, vsd
);
3070 static int mlx5e_setup_tc_mqprio(struct net_device
*netdev
,
3071 struct tc_mqprio_qopt
*mqprio
)
3073 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3074 struct mlx5e_channels new_channels
= {};
3075 u8 tc
= mqprio
->num_tc
;
3078 mqprio
->hw
= TC_MQPRIO_HW_OFFLOAD_TCS
;
3080 if (tc
&& tc
!= MLX5E_MAX_NUM_TC
)
3083 mutex_lock(&priv
->state_lock
);
3085 new_channels
.params
= priv
->channels
.params
;
3086 new_channels
.params
.num_tc
= tc
? tc
: 1;
3088 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
)) {
3089 priv
->channels
.params
= new_channels
.params
;
3093 err
= mlx5e_open_channels(priv
, &new_channels
);
3097 mlx5e_switch_priv_channels(priv
, &new_channels
, NULL
);
3099 mutex_unlock(&priv
->state_lock
);
3103 #ifdef CONFIG_MLX5_ESWITCH
3104 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv
*priv
,
3105 struct tc_cls_flower_offload
*cls_flower
)
3107 if (cls_flower
->common
.chain_index
)
3110 switch (cls_flower
->command
) {
3111 case TC_CLSFLOWER_REPLACE
:
3112 return mlx5e_configure_flower(priv
, cls_flower
);
3113 case TC_CLSFLOWER_DESTROY
:
3114 return mlx5e_delete_flower(priv
, cls_flower
);
3115 case TC_CLSFLOWER_STATS
:
3116 return mlx5e_stats_flower(priv
, cls_flower
);
3122 int mlx5e_setup_tc_block_cb(enum tc_setup_type type
, void *type_data
,
3125 struct mlx5e_priv
*priv
= cb_priv
;
3127 if (!tc_can_offload(priv
->netdev
))
3131 case TC_SETUP_CLSFLOWER
:
3132 return mlx5e_setup_tc_cls_flower(priv
, type_data
);
3138 static int mlx5e_setup_tc_block(struct net_device
*dev
,
3139 struct tc_block_offload
*f
)
3141 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3143 if (f
->binder_type
!= TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS
)
3146 switch (f
->command
) {
3148 return tcf_block_cb_register(f
->block
, mlx5e_setup_tc_block_cb
,
3150 case TC_BLOCK_UNBIND
:
3151 tcf_block_cb_unregister(f
->block
, mlx5e_setup_tc_block_cb
,
3160 int mlx5e_setup_tc(struct net_device
*dev
, enum tc_setup_type type
,
3164 #ifdef CONFIG_MLX5_ESWITCH
3165 case TC_SETUP_BLOCK
:
3166 return mlx5e_setup_tc_block(dev
, type_data
);
3168 case TC_SETUP_QDISC_MQPRIO
:
3169 return mlx5e_setup_tc_mqprio(dev
, type_data
);
3176 mlx5e_get_stats(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
3178 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3179 struct mlx5e_sw_stats
*sstats
= &priv
->stats
.sw
;
3180 struct mlx5e_vport_stats
*vstats
= &priv
->stats
.vport
;
3181 struct mlx5e_pport_stats
*pstats
= &priv
->stats
.pport
;
3183 if (mlx5e_is_uplink_rep(priv
)) {
3184 stats
->rx_packets
= PPORT_802_3_GET(pstats
, a_frames_received_ok
);
3185 stats
->rx_bytes
= PPORT_802_3_GET(pstats
, a_octets_received_ok
);
3186 stats
->tx_packets
= PPORT_802_3_GET(pstats
, a_frames_transmitted_ok
);
3187 stats
->tx_bytes
= PPORT_802_3_GET(pstats
, a_octets_transmitted_ok
);
3189 stats
->rx_packets
= sstats
->rx_packets
;
3190 stats
->rx_bytes
= sstats
->rx_bytes
;
3191 stats
->tx_packets
= sstats
->tx_packets
;
3192 stats
->tx_bytes
= sstats
->tx_bytes
;
3193 stats
->tx_dropped
= sstats
->tx_queue_dropped
;
3196 stats
->rx_dropped
= priv
->stats
.qcnt
.rx_out_of_buffer
;
3198 stats
->rx_length_errors
=
3199 PPORT_802_3_GET(pstats
, a_in_range_length_errors
) +
3200 PPORT_802_3_GET(pstats
, a_out_of_range_length_field
) +
3201 PPORT_802_3_GET(pstats
, a_frame_too_long_errors
);
3202 stats
->rx_crc_errors
=
3203 PPORT_802_3_GET(pstats
, a_frame_check_sequence_errors
);
3204 stats
->rx_frame_errors
= PPORT_802_3_GET(pstats
, a_alignment_errors
);
3205 stats
->tx_aborted_errors
= PPORT_2863_GET(pstats
, if_out_discards
);
3206 stats
->rx_errors
= stats
->rx_length_errors
+ stats
->rx_crc_errors
+
3207 stats
->rx_frame_errors
;
3208 stats
->tx_errors
= stats
->tx_aborted_errors
+ stats
->tx_carrier_errors
;
3210 /* vport multicast also counts packets that are dropped due to steering
3211 * or rx out of buffer
3214 VPORT_COUNTER_GET(vstats
, received_eth_multicast
.packets
);
3217 static void mlx5e_set_rx_mode(struct net_device
*dev
)
3219 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3221 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
3224 static int mlx5e_set_mac(struct net_device
*netdev
, void *addr
)
3226 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3227 struct sockaddr
*saddr
= addr
;
3229 if (!is_valid_ether_addr(saddr
->sa_data
))
3230 return -EADDRNOTAVAIL
;
3232 netif_addr_lock_bh(netdev
);
3233 ether_addr_copy(netdev
->dev_addr
, saddr
->sa_data
);
3234 netif_addr_unlock_bh(netdev
);
3236 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
3241 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
3244 netdev->features |= feature; \
3246 netdev->features &= ~feature; \
3249 typedef int (*mlx5e_feature_handler
)(struct net_device
*netdev
, bool enable
);
3251 static int set_feature_lro(struct net_device
*netdev
, bool enable
)
3253 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3254 struct mlx5e_channels new_channels
= {};
3258 mutex_lock(&priv
->state_lock
);
3260 reset
= (priv
->channels
.params
.rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST
);
3261 reset
= reset
&& test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
3263 new_channels
.params
= priv
->channels
.params
;
3264 new_channels
.params
.lro_en
= enable
;
3267 priv
->channels
.params
= new_channels
.params
;
3268 err
= mlx5e_modify_tirs_lro(priv
);
3272 err
= mlx5e_open_channels(priv
, &new_channels
);
3276 mlx5e_switch_priv_channels(priv
, &new_channels
, mlx5e_modify_tirs_lro
);
3278 mutex_unlock(&priv
->state_lock
);
3282 static int set_feature_cvlan_filter(struct net_device
*netdev
, bool enable
)
3284 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3287 mlx5e_enable_cvlan_filter(priv
);
3289 mlx5e_disable_cvlan_filter(priv
);
3294 static int set_feature_tc_num_filters(struct net_device
*netdev
, bool enable
)
3296 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3298 if (!enable
&& mlx5e_tc_num_filters(priv
)) {
3300 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3307 static int set_feature_rx_all(struct net_device
*netdev
, bool enable
)
3309 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3310 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3312 return mlx5_set_port_fcs(mdev
, !enable
);
3315 static int set_feature_rx_fcs(struct net_device
*netdev
, bool enable
)
3317 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3320 mutex_lock(&priv
->state_lock
);
3322 priv
->channels
.params
.scatter_fcs_en
= enable
;
3323 err
= mlx5e_modify_channels_scatter_fcs(&priv
->channels
, enable
);
3325 priv
->channels
.params
.scatter_fcs_en
= !enable
;
3327 mutex_unlock(&priv
->state_lock
);
3332 static int set_feature_rx_vlan(struct net_device
*netdev
, bool enable
)
3334 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3337 mutex_lock(&priv
->state_lock
);
3339 priv
->channels
.params
.vlan_strip_disable
= !enable
;
3340 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
3343 err
= mlx5e_modify_channels_vsd(&priv
->channels
, !enable
);
3345 priv
->channels
.params
.vlan_strip_disable
= enable
;
3348 mutex_unlock(&priv
->state_lock
);
3353 #ifdef CONFIG_RFS_ACCEL
3354 static int set_feature_arfs(struct net_device
*netdev
, bool enable
)
3356 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3360 err
= mlx5e_arfs_enable(priv
);
3362 err
= mlx5e_arfs_disable(priv
);
3368 static int mlx5e_handle_feature(struct net_device
*netdev
,
3369 netdev_features_t wanted_features
,
3370 netdev_features_t feature
,
3371 mlx5e_feature_handler feature_handler
)
3373 netdev_features_t changes
= wanted_features
^ netdev
->features
;
3374 bool enable
= !!(wanted_features
& feature
);
3377 if (!(changes
& feature
))
3380 err
= feature_handler(netdev
, enable
);
3382 netdev_err(netdev
, "%s feature %pNF failed, err %d\n",
3383 enable
? "Enable" : "Disable", &feature
, err
);
3387 MLX5E_SET_FEATURE(netdev
, feature
, enable
);
3391 static int mlx5e_set_features(struct net_device
*netdev
,
3392 netdev_features_t features
)
3396 err
= mlx5e_handle_feature(netdev
, features
, NETIF_F_LRO
,
3398 err
|= mlx5e_handle_feature(netdev
, features
,
3399 NETIF_F_HW_VLAN_CTAG_FILTER
,
3400 set_feature_cvlan_filter
);
3401 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_HW_TC
,
3402 set_feature_tc_num_filters
);
3403 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_RXALL
,
3404 set_feature_rx_all
);
3405 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_RXFCS
,
3406 set_feature_rx_fcs
);
3407 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_HW_VLAN_CTAG_RX
,
3408 set_feature_rx_vlan
);
3409 #ifdef CONFIG_RFS_ACCEL
3410 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_NTUPLE
,
3414 return err
? -EINVAL
: 0;
3417 static netdev_features_t
mlx5e_fix_features(struct net_device
*netdev
,
3418 netdev_features_t features
)
3420 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3422 mutex_lock(&priv
->state_lock
);
3423 if (!bitmap_empty(priv
->fs
.vlan
.active_svlans
, VLAN_N_VID
)) {
3424 /* HW strips the outer C-tag header, this is a problem
3425 * for S-tag traffic.
3427 features
&= ~NETIF_F_HW_VLAN_CTAG_RX
;
3428 if (!priv
->channels
.params
.vlan_strip_disable
)
3429 netdev_warn(netdev
, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3431 mutex_unlock(&priv
->state_lock
);
3436 static int mlx5e_change_mtu(struct net_device
*netdev
, int new_mtu
)
3438 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3439 struct mlx5e_channels new_channels
= {};
3444 mutex_lock(&priv
->state_lock
);
3446 reset
= !priv
->channels
.params
.lro_en
&&
3447 (priv
->channels
.params
.rq_wq_type
!=
3448 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
);
3450 reset
= reset
&& test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
3452 curr_mtu
= netdev
->mtu
;
3453 netdev
->mtu
= new_mtu
;
3456 mlx5e_set_dev_port_mtu(priv
);
3460 new_channels
.params
= priv
->channels
.params
;
3461 err
= mlx5e_open_channels(priv
, &new_channels
);
3463 netdev
->mtu
= curr_mtu
;
3467 mlx5e_switch_priv_channels(priv
, &new_channels
, mlx5e_set_dev_port_mtu
);
3470 mutex_unlock(&priv
->state_lock
);
3474 int mlx5e_hwstamp_set(struct mlx5e_priv
*priv
, struct ifreq
*ifr
)
3476 struct hwtstamp_config config
;
3479 if (!MLX5_CAP_GEN(priv
->mdev
, device_frequency_khz
))
3482 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
3485 /* TX HW timestamp */
3486 switch (config
.tx_type
) {
3487 case HWTSTAMP_TX_OFF
:
3488 case HWTSTAMP_TX_ON
:
3494 mutex_lock(&priv
->state_lock
);
3495 /* RX HW timestamp */
3496 switch (config
.rx_filter
) {
3497 case HWTSTAMP_FILTER_NONE
:
3498 /* Reset CQE compression to Admin default */
3499 mlx5e_modify_rx_cqe_compression_locked(priv
, priv
->channels
.params
.rx_cqe_compress_def
);
3501 case HWTSTAMP_FILTER_ALL
:
3502 case HWTSTAMP_FILTER_SOME
:
3503 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
3504 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
3505 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
3506 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
3507 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
3508 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
3509 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
3510 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
3511 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
3512 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
3513 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
3514 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
3515 case HWTSTAMP_FILTER_NTP_ALL
:
3516 /* Disable CQE compression */
3517 netdev_warn(priv
->netdev
, "Disabling cqe compression");
3518 err
= mlx5e_modify_rx_cqe_compression_locked(priv
, false);
3520 netdev_err(priv
->netdev
, "Failed disabling cqe compression err=%d\n", err
);
3521 mutex_unlock(&priv
->state_lock
);
3524 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
3527 mutex_unlock(&priv
->state_lock
);
3531 memcpy(&priv
->tstamp
, &config
, sizeof(config
));
3532 mutex_unlock(&priv
->state_lock
);
3534 return copy_to_user(ifr
->ifr_data
, &config
,
3535 sizeof(config
)) ? -EFAULT
: 0;
3538 int mlx5e_hwstamp_get(struct mlx5e_priv
*priv
, struct ifreq
*ifr
)
3540 struct hwtstamp_config
*cfg
= &priv
->tstamp
;
3542 if (!MLX5_CAP_GEN(priv
->mdev
, device_frequency_khz
))
3545 return copy_to_user(ifr
->ifr_data
, cfg
, sizeof(*cfg
)) ? -EFAULT
: 0;
3548 static int mlx5e_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3550 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3554 return mlx5e_hwstamp_set(priv
, ifr
);
3556 return mlx5e_hwstamp_get(priv
, ifr
);
3562 #ifdef CONFIG_MLX5_ESWITCH
3563 static int mlx5e_set_vf_mac(struct net_device
*dev
, int vf
, u8
*mac
)
3565 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3566 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3568 return mlx5_eswitch_set_vport_mac(mdev
->priv
.eswitch
, vf
+ 1, mac
);
3571 static int mlx5e_set_vf_vlan(struct net_device
*dev
, int vf
, u16 vlan
, u8 qos
,
3574 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3575 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3577 if (vlan_proto
!= htons(ETH_P_8021Q
))
3578 return -EPROTONOSUPPORT
;
3580 return mlx5_eswitch_set_vport_vlan(mdev
->priv
.eswitch
, vf
+ 1,
3584 static int mlx5e_set_vf_spoofchk(struct net_device
*dev
, int vf
, bool setting
)
3586 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3587 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3589 return mlx5_eswitch_set_vport_spoofchk(mdev
->priv
.eswitch
, vf
+ 1, setting
);
3592 static int mlx5e_set_vf_trust(struct net_device
*dev
, int vf
, bool setting
)
3594 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3595 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3597 return mlx5_eswitch_set_vport_trust(mdev
->priv
.eswitch
, vf
+ 1, setting
);
3600 static int mlx5e_set_vf_rate(struct net_device
*dev
, int vf
, int min_tx_rate
,
3603 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3604 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3606 return mlx5_eswitch_set_vport_rate(mdev
->priv
.eswitch
, vf
+ 1,
3607 max_tx_rate
, min_tx_rate
);
3610 static int mlx5_vport_link2ifla(u8 esw_link
)
3613 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN
:
3614 return IFLA_VF_LINK_STATE_DISABLE
;
3615 case MLX5_ESW_VPORT_ADMIN_STATE_UP
:
3616 return IFLA_VF_LINK_STATE_ENABLE
;
3618 return IFLA_VF_LINK_STATE_AUTO
;
3621 static int mlx5_ifla_link2vport(u8 ifla_link
)
3623 switch (ifla_link
) {
3624 case IFLA_VF_LINK_STATE_DISABLE
:
3625 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN
;
3626 case IFLA_VF_LINK_STATE_ENABLE
:
3627 return MLX5_ESW_VPORT_ADMIN_STATE_UP
;
3629 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO
;
3632 static int mlx5e_set_vf_link_state(struct net_device
*dev
, int vf
,
3635 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3636 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3638 return mlx5_eswitch_set_vport_state(mdev
->priv
.eswitch
, vf
+ 1,
3639 mlx5_ifla_link2vport(link_state
));
3642 static int mlx5e_get_vf_config(struct net_device
*dev
,
3643 int vf
, struct ifla_vf_info
*ivi
)
3645 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3646 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3649 err
= mlx5_eswitch_get_vport_config(mdev
->priv
.eswitch
, vf
+ 1, ivi
);
3652 ivi
->linkstate
= mlx5_vport_link2ifla(ivi
->linkstate
);
3656 static int mlx5e_get_vf_stats(struct net_device
*dev
,
3657 int vf
, struct ifla_vf_stats
*vf_stats
)
3659 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3660 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3662 return mlx5_eswitch_get_vport_stats(mdev
->priv
.eswitch
, vf
+ 1,
3667 static void mlx5e_add_vxlan_port(struct net_device
*netdev
,
3668 struct udp_tunnel_info
*ti
)
3670 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3672 if (ti
->type
!= UDP_TUNNEL_TYPE_VXLAN
)
3675 if (!mlx5e_vxlan_allowed(priv
->mdev
))
3678 mlx5e_vxlan_queue_work(priv
, ti
->sa_family
, be16_to_cpu(ti
->port
), 1);
3681 static void mlx5e_del_vxlan_port(struct net_device
*netdev
,
3682 struct udp_tunnel_info
*ti
)
3684 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3686 if (ti
->type
!= UDP_TUNNEL_TYPE_VXLAN
)
3689 if (!mlx5e_vxlan_allowed(priv
->mdev
))
3692 mlx5e_vxlan_queue_work(priv
, ti
->sa_family
, be16_to_cpu(ti
->port
), 0);
3695 static netdev_features_t
mlx5e_tunnel_features_check(struct mlx5e_priv
*priv
,
3696 struct sk_buff
*skb
,
3697 netdev_features_t features
)
3699 unsigned int offset
= 0;
3700 struct udphdr
*udph
;
3704 switch (vlan_get_protocol(skb
)) {
3705 case htons(ETH_P_IP
):
3706 proto
= ip_hdr(skb
)->protocol
;
3708 case htons(ETH_P_IPV6
):
3709 proto
= ipv6_find_hdr(skb
, &offset
, -1, NULL
, NULL
);
3719 udph
= udp_hdr(skb
);
3720 port
= be16_to_cpu(udph
->dest
);
3722 /* Verify if UDP port is being offloaded by HW */
3723 if (mlx5e_vxlan_lookup_port(priv
, port
))
3728 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3729 return features
& ~(NETIF_F_CSUM_MASK
| NETIF_F_GSO_MASK
);
3732 static netdev_features_t
mlx5e_features_check(struct sk_buff
*skb
,
3733 struct net_device
*netdev
,
3734 netdev_features_t features
)
3736 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3738 features
= vlan_features_check(skb
, features
);
3739 features
= vxlan_features_check(skb
, features
);
3741 #ifdef CONFIG_MLX5_EN_IPSEC
3742 if (mlx5e_ipsec_feature_check(skb
, netdev
, features
))
3746 /* Validate if the tunneled packet is being offloaded by HW */
3747 if (skb
->encapsulation
&&
3748 (features
& NETIF_F_CSUM_MASK
|| features
& NETIF_F_GSO_MASK
))
3749 return mlx5e_tunnel_features_check(priv
, skb
, features
);
3754 static void mlx5e_tx_timeout(struct net_device
*dev
)
3756 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3757 bool sched_work
= false;
3760 netdev_err(dev
, "TX timeout detected\n");
3762 for (i
= 0; i
< priv
->channels
.num
* priv
->channels
.params
.num_tc
; i
++) {
3763 struct mlx5e_txqsq
*sq
= priv
->txq2sq
[i
];
3765 if (!netif_xmit_stopped(netdev_get_tx_queue(dev
, i
)))
3768 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
3769 netdev_err(dev
, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3770 i
, sq
->sqn
, sq
->cq
.mcq
.cqn
, sq
->cc
, sq
->pc
);
3773 if (sched_work
&& test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
3774 schedule_work(&priv
->tx_timeout_work
);
3777 static int mlx5e_xdp_set(struct net_device
*netdev
, struct bpf_prog
*prog
)
3779 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3780 struct bpf_prog
*old_prog
;
3782 bool reset
, was_opened
;
3785 mutex_lock(&priv
->state_lock
);
3787 if ((netdev
->features
& NETIF_F_LRO
) && prog
) {
3788 netdev_warn(netdev
, "can't set XDP while LRO is on, disable LRO first\n");
3793 if ((netdev
->features
& NETIF_F_HW_ESP
) && prog
) {
3794 netdev_warn(netdev
, "can't set XDP with IPSec offload\n");
3799 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
3800 /* no need for full reset when exchanging programs */
3801 reset
= (!priv
->channels
.params
.xdp_prog
|| !prog
);
3803 if (was_opened
&& reset
)
3804 mlx5e_close_locked(netdev
);
3805 if (was_opened
&& !reset
) {
3806 /* num_channels is invariant here, so we can take the
3807 * batched reference right upfront.
3809 prog
= bpf_prog_add(prog
, priv
->channels
.num
);
3811 err
= PTR_ERR(prog
);
3816 /* exchange programs, extra prog reference we got from caller
3817 * as long as we don't fail from this point onwards.
3819 old_prog
= xchg(&priv
->channels
.params
.xdp_prog
, prog
);
3821 bpf_prog_put(old_prog
);
3823 if (reset
) /* change RQ type according to priv->xdp_prog */
3824 mlx5e_set_rq_params(priv
->mdev
, &priv
->channels
.params
);
3826 if (was_opened
&& reset
)
3827 mlx5e_open_locked(netdev
);
3829 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
) || reset
)
3832 /* exchanging programs w/o reset, we update ref counts on behalf
3833 * of the channels RQs here.
3835 for (i
= 0; i
< priv
->channels
.num
; i
++) {
3836 struct mlx5e_channel
*c
= priv
->channels
.c
[i
];
3838 clear_bit(MLX5E_RQ_STATE_ENABLED
, &c
->rq
.state
);
3839 napi_synchronize(&c
->napi
);
3840 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3842 old_prog
= xchg(&c
->rq
.xdp_prog
, prog
);
3844 set_bit(MLX5E_RQ_STATE_ENABLED
, &c
->rq
.state
);
3845 /* napi_schedule in case we have missed anything */
3846 napi_schedule(&c
->napi
);
3849 bpf_prog_put(old_prog
);
3853 mutex_unlock(&priv
->state_lock
);
3857 static u32
mlx5e_xdp_query(struct net_device
*dev
)
3859 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3860 const struct bpf_prog
*xdp_prog
;
3863 mutex_lock(&priv
->state_lock
);
3864 xdp_prog
= priv
->channels
.params
.xdp_prog
;
3866 prog_id
= xdp_prog
->aux
->id
;
3867 mutex_unlock(&priv
->state_lock
);
3872 static int mlx5e_xdp(struct net_device
*dev
, struct netdev_bpf
*xdp
)
3874 switch (xdp
->command
) {
3875 case XDP_SETUP_PROG
:
3876 return mlx5e_xdp_set(dev
, xdp
->prog
);
3877 case XDP_QUERY_PROG
:
3878 xdp
->prog_id
= mlx5e_xdp_query(dev
);
3879 xdp
->prog_attached
= !!xdp
->prog_id
;
3886 #ifdef CONFIG_NET_POLL_CONTROLLER
3887 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3888 * reenabling interrupts.
3890 static void mlx5e_netpoll(struct net_device
*dev
)
3892 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3893 struct mlx5e_channels
*chs
= &priv
->channels
;
3897 for (i
= 0; i
< chs
->num
; i
++)
3898 napi_schedule(&chs
->c
[i
]->napi
);
3902 static const struct net_device_ops mlx5e_netdev_ops
= {
3903 .ndo_open
= mlx5e_open
,
3904 .ndo_stop
= mlx5e_close
,
3905 .ndo_start_xmit
= mlx5e_xmit
,
3906 .ndo_setup_tc
= mlx5e_setup_tc
,
3907 .ndo_select_queue
= mlx5e_select_queue
,
3908 .ndo_get_stats64
= mlx5e_get_stats
,
3909 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
3910 .ndo_set_mac_address
= mlx5e_set_mac
,
3911 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
3912 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
3913 .ndo_set_features
= mlx5e_set_features
,
3914 .ndo_fix_features
= mlx5e_fix_features
,
3915 .ndo_change_mtu
= mlx5e_change_mtu
,
3916 .ndo_do_ioctl
= mlx5e_ioctl
,
3917 .ndo_set_tx_maxrate
= mlx5e_set_tx_maxrate
,
3918 .ndo_udp_tunnel_add
= mlx5e_add_vxlan_port
,
3919 .ndo_udp_tunnel_del
= mlx5e_del_vxlan_port
,
3920 .ndo_features_check
= mlx5e_features_check
,
3921 #ifdef CONFIG_RFS_ACCEL
3922 .ndo_rx_flow_steer
= mlx5e_rx_flow_steer
,
3924 .ndo_tx_timeout
= mlx5e_tx_timeout
,
3925 .ndo_bpf
= mlx5e_xdp
,
3926 #ifdef CONFIG_NET_POLL_CONTROLLER
3927 .ndo_poll_controller
= mlx5e_netpoll
,
3929 #ifdef CONFIG_MLX5_ESWITCH
3930 /* SRIOV E-Switch NDOs */
3931 .ndo_set_vf_mac
= mlx5e_set_vf_mac
,
3932 .ndo_set_vf_vlan
= mlx5e_set_vf_vlan
,
3933 .ndo_set_vf_spoofchk
= mlx5e_set_vf_spoofchk
,
3934 .ndo_set_vf_trust
= mlx5e_set_vf_trust
,
3935 .ndo_set_vf_rate
= mlx5e_set_vf_rate
,
3936 .ndo_get_vf_config
= mlx5e_get_vf_config
,
3937 .ndo_set_vf_link_state
= mlx5e_set_vf_link_state
,
3938 .ndo_get_vf_stats
= mlx5e_get_vf_stats
,
3939 .ndo_has_offload_stats
= mlx5e_has_offload_stats
,
3940 .ndo_get_offload_stats
= mlx5e_get_offload_stats
,
3944 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev
*mdev
)
3946 if (MLX5_CAP_GEN(mdev
, port_type
) != MLX5_CAP_PORT_TYPE_ETH
)
3948 if (!MLX5_CAP_GEN(mdev
, eth_net_offloads
) ||
3949 !MLX5_CAP_GEN(mdev
, nic_flow_table
) ||
3950 !MLX5_CAP_ETH(mdev
, csum_cap
) ||
3951 !MLX5_CAP_ETH(mdev
, max_lso_cap
) ||
3952 !MLX5_CAP_ETH(mdev
, vlan_cap
) ||
3953 !MLX5_CAP_ETH(mdev
, rss_ind_tbl_cap
) ||
3954 MLX5_CAP_FLOWTABLE(mdev
,
3955 flow_table_properties_nic_receive
.max_ft_level
)
3957 mlx5_core_warn(mdev
,
3958 "Not creating net device, some required device capabilities are missing\n");
3961 if (!MLX5_CAP_ETH(mdev
, self_lb_en_modifiable
))
3962 mlx5_core_warn(mdev
, "Self loop back prevention is not supported\n");
3963 if (!MLX5_CAP_GEN(mdev
, cq_moderation
))
3964 mlx5_core_warn(mdev
, "CQ moderation is not supported\n");
3969 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
)
3971 int bf_buf_size
= (1 << MLX5_CAP_GEN(mdev
, log_bf_reg_size
)) / 2;
3973 return bf_buf_size
-
3974 sizeof(struct mlx5e_tx_wqe
) +
3975 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3978 void mlx5e_build_default_indir_rqt(u32
*indirection_rqt
, int len
,
3983 for (i
= 0; i
< len
; i
++)
3984 indirection_rqt
[i
] = i
% num_channels
;
3987 static int mlx5e_get_pci_bw(struct mlx5_core_dev
*mdev
, u32
*pci_bw
)
3989 enum pcie_link_width width
;
3990 enum pci_bus_speed speed
;
3993 err
= pcie_get_minimum_link(mdev
->pdev
, &speed
, &width
);
3997 if (speed
== PCI_SPEED_UNKNOWN
|| width
== PCIE_LNK_WIDTH_UNKNOWN
)
4001 case PCIE_SPEED_2_5GT
:
4002 *pci_bw
= 2500 * width
;
4004 case PCIE_SPEED_5_0GT
:
4005 *pci_bw
= 5000 * width
;
4007 case PCIE_SPEED_8_0GT
:
4008 *pci_bw
= 8000 * width
;
4017 static bool cqe_compress_heuristic(u32 link_speed
, u32 pci_bw
)
4019 return (link_speed
&& pci_bw
&&
4020 (pci_bw
< 40000) && (pci_bw
< link_speed
));
4023 static bool hw_lro_heuristic(u32 link_speed
, u32 pci_bw
)
4025 return !(link_speed
&& pci_bw
&&
4026 (pci_bw
<= 16000) && (pci_bw
< link_speed
));
4029 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params
*params
, u8 cq_period_mode
)
4031 params
->tx_cq_moderation
.cq_period_mode
= cq_period_mode
;
4033 params
->tx_cq_moderation
.pkts
=
4034 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS
;
4035 params
->tx_cq_moderation
.usec
=
4036 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC
;
4038 if (cq_period_mode
== MLX5_CQ_PERIOD_MODE_START_FROM_CQE
)
4039 params
->tx_cq_moderation
.usec
=
4040 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE
;
4042 MLX5E_SET_PFLAG(params
, MLX5E_PFLAG_TX_CQE_BASED_MODER
,
4043 params
->tx_cq_moderation
.cq_period_mode
==
4044 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
);
4047 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params
*params
, u8 cq_period_mode
)
4049 params
->rx_cq_moderation
.cq_period_mode
= cq_period_mode
;
4051 params
->rx_cq_moderation
.pkts
=
4052 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS
;
4053 params
->rx_cq_moderation
.usec
=
4054 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC
;
4056 if (cq_period_mode
== MLX5_CQ_PERIOD_MODE_START_FROM_CQE
)
4057 params
->rx_cq_moderation
.usec
=
4058 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE
;
4060 if (params
->rx_dim_enabled
) {
4061 switch (cq_period_mode
) {
4062 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE
:
4063 params
->rx_cq_moderation
=
4064 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE
);
4066 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE
:
4068 params
->rx_cq_moderation
=
4069 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE
);
4073 MLX5E_SET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_BASED_MODER
,
4074 params
->rx_cq_moderation
.cq_period_mode
==
4075 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
);
4078 u32
mlx5e_choose_lro_timeout(struct mlx5_core_dev
*mdev
, u32 wanted_timeout
)
4082 /* The supported periods are organized in ascending order */
4083 for (i
= 0; i
< MLX5E_LRO_TIMEOUT_ARR_SIZE
- 1; i
++)
4084 if (MLX5_CAP_ETH(mdev
, lro_timer_supported_periods
[i
]) >= wanted_timeout
)
4087 return MLX5_CAP_ETH(mdev
, lro_timer_supported_periods
[i
]);
4090 void mlx5e_build_nic_params(struct mlx5_core_dev
*mdev
,
4091 struct mlx5e_params
*params
,
4094 u8 cq_period_mode
= 0;
4098 params
->num_channels
= max_channels
;
4101 mlx5e_get_max_linkspeed(mdev
, &link_speed
);
4102 mlx5e_get_pci_bw(mdev
, &pci_bw
);
4103 mlx5_core_dbg(mdev
, "Max link speed = %d, PCI BW = %d\n",
4104 link_speed
, pci_bw
);
4107 params
->log_sq_size
= is_kdump_kernel() ?
4108 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE
:
4109 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE
;
4111 /* set CQE compression */
4112 params
->rx_cqe_compress_def
= false;
4113 if (MLX5_CAP_GEN(mdev
, cqe_compression
) &&
4114 MLX5_CAP_GEN(mdev
, vport_group_manager
))
4115 params
->rx_cqe_compress_def
= cqe_compress_heuristic(link_speed
, pci_bw
);
4117 MLX5E_SET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_COMPRESS
, params
->rx_cqe_compress_def
);
4120 mlx5e_set_rq_params(mdev
, params
);
4124 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4125 if (params
->rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
)
4126 params
->lro_en
= hw_lro_heuristic(link_speed
, pci_bw
);
4127 params
->lro_timeout
= mlx5e_choose_lro_timeout(mdev
, MLX5E_DEFAULT_LRO_TIMEOUT
);
4129 /* CQ moderation params */
4130 cq_period_mode
= MLX5_CAP_GEN(mdev
, cq_period_start_from_cqe
) ?
4131 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
:
4132 MLX5_CQ_PERIOD_MODE_START_FROM_EQE
;
4133 params
->rx_dim_enabled
= MLX5_CAP_GEN(mdev
, cq_moderation
);
4134 mlx5e_set_rx_cq_mode_params(params
, cq_period_mode
);
4135 mlx5e_set_tx_cq_mode_params(params
, cq_period_mode
);
4138 params
->tx_max_inline
= mlx5e_get_max_inline_cap(mdev
);
4139 params
->tx_min_inline_mode
= mlx5e_params_calculate_tx_min_inline(mdev
);
4142 params
->rss_hfunc
= ETH_RSS_HASH_XOR
;
4143 netdev_rss_key_fill(params
->toeplitz_hash_key
, sizeof(params
->toeplitz_hash_key
));
4144 mlx5e_build_default_indir_rqt(params
->indirection_rqt
,
4145 MLX5E_INDIR_RQT_SIZE
, max_channels
);
4148 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev
*mdev
,
4149 struct net_device
*netdev
,
4150 const struct mlx5e_profile
*profile
,
4153 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
4156 priv
->netdev
= netdev
;
4157 priv
->profile
= profile
;
4158 priv
->ppriv
= ppriv
;
4159 priv
->msglevel
= MLX5E_MSG_LEVEL
;
4160 priv
->hard_mtu
= MLX5E_ETH_HARD_MTU
;
4162 mlx5e_build_nic_params(mdev
, &priv
->channels
.params
, profile
->max_nch(mdev
));
4164 mutex_init(&priv
->state_lock
);
4166 INIT_WORK(&priv
->update_carrier_work
, mlx5e_update_carrier_work
);
4167 INIT_WORK(&priv
->set_rx_mode_work
, mlx5e_set_rx_mode_work
);
4168 INIT_WORK(&priv
->tx_timeout_work
, mlx5e_tx_timeout_work
);
4169 INIT_DELAYED_WORK(&priv
->update_stats_work
, mlx5e_update_stats_work
);
4172 static void mlx5e_set_netdev_dev_addr(struct net_device
*netdev
)
4174 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
4176 mlx5_query_nic_vport_mac_address(priv
->mdev
, 0, netdev
->dev_addr
);
4177 if (is_zero_ether_addr(netdev
->dev_addr
) &&
4178 !MLX5_CAP_GEN(priv
->mdev
, vport_group_manager
)) {
4179 eth_hw_addr_random(netdev
);
4180 mlx5_core_info(priv
->mdev
, "Assigned random MAC address %pM\n", netdev
->dev_addr
);
4184 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4185 static const struct switchdev_ops mlx5e_switchdev_ops
= {
4186 .switchdev_port_attr_get
= mlx5e_attr_get
,
4190 static void mlx5e_build_nic_netdev(struct net_device
*netdev
)
4192 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
4193 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4197 SET_NETDEV_DEV(netdev
, &mdev
->pdev
->dev
);
4199 netdev
->netdev_ops
= &mlx5e_netdev_ops
;
4201 #ifdef CONFIG_MLX5_CORE_EN_DCB
4202 if (MLX5_CAP_GEN(mdev
, vport_group_manager
) && MLX5_CAP_GEN(mdev
, qos
))
4203 netdev
->dcbnl_ops
= &mlx5e_dcbnl_ops
;
4206 netdev
->watchdog_timeo
= 15 * HZ
;
4208 netdev
->ethtool_ops
= &mlx5e_ethtool_ops
;
4210 netdev
->vlan_features
|= NETIF_F_SG
;
4211 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
4212 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
4213 netdev
->vlan_features
|= NETIF_F_GRO
;
4214 netdev
->vlan_features
|= NETIF_F_TSO
;
4215 netdev
->vlan_features
|= NETIF_F_TSO6
;
4216 netdev
->vlan_features
|= NETIF_F_RXCSUM
;
4217 netdev
->vlan_features
|= NETIF_F_RXHASH
;
4219 if (!!MLX5_CAP_ETH(mdev
, lro_cap
))
4220 netdev
->vlan_features
|= NETIF_F_LRO
;
4222 netdev
->hw_features
= netdev
->vlan_features
;
4223 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_TX
;
4224 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
;
4225 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
4226 netdev
->hw_features
|= NETIF_F_HW_VLAN_STAG_TX
;
4228 if (mlx5e_vxlan_allowed(mdev
) || MLX5_CAP_ETH(mdev
, tunnel_stateless_gre
)) {
4229 netdev
->hw_features
|= NETIF_F_GSO_PARTIAL
;
4230 netdev
->hw_enc_features
|= NETIF_F_IP_CSUM
;
4231 netdev
->hw_enc_features
|= NETIF_F_IPV6_CSUM
;
4232 netdev
->hw_enc_features
|= NETIF_F_TSO
;
4233 netdev
->hw_enc_features
|= NETIF_F_TSO6
;
4234 netdev
->hw_enc_features
|= NETIF_F_GSO_PARTIAL
;
4237 if (mlx5e_vxlan_allowed(mdev
)) {
4238 netdev
->hw_features
|= NETIF_F_GSO_UDP_TUNNEL
|
4239 NETIF_F_GSO_UDP_TUNNEL_CSUM
;
4240 netdev
->hw_enc_features
|= NETIF_F_GSO_UDP_TUNNEL
|
4241 NETIF_F_GSO_UDP_TUNNEL_CSUM
;
4242 netdev
->gso_partial_features
= NETIF_F_GSO_UDP_TUNNEL_CSUM
;
4245 if (MLX5_CAP_ETH(mdev
, tunnel_stateless_gre
)) {
4246 netdev
->hw_features
|= NETIF_F_GSO_GRE
|
4247 NETIF_F_GSO_GRE_CSUM
;
4248 netdev
->hw_enc_features
|= NETIF_F_GSO_GRE
|
4249 NETIF_F_GSO_GRE_CSUM
;
4250 netdev
->gso_partial_features
|= NETIF_F_GSO_GRE
|
4251 NETIF_F_GSO_GRE_CSUM
;
4254 mlx5_query_port_fcs(mdev
, &fcs_supported
, &fcs_enabled
);
4257 netdev
->hw_features
|= NETIF_F_RXALL
;
4259 if (MLX5_CAP_ETH(mdev
, scatter_fcs
))
4260 netdev
->hw_features
|= NETIF_F_RXFCS
;
4262 netdev
->features
= netdev
->hw_features
;
4263 if (!priv
->channels
.params
.lro_en
)
4264 netdev
->features
&= ~NETIF_F_LRO
;
4267 netdev
->features
&= ~NETIF_F_RXALL
;
4269 if (!priv
->channels
.params
.scatter_fcs_en
)
4270 netdev
->features
&= ~NETIF_F_RXFCS
;
4272 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4273 if (FT_CAP(flow_modify_en
) &&
4274 FT_CAP(modify_root
) &&
4275 FT_CAP(identified_miss_table_mode
) &&
4276 FT_CAP(flow_table_modify
)) {
4277 netdev
->hw_features
|= NETIF_F_HW_TC
;
4278 #ifdef CONFIG_RFS_ACCEL
4279 netdev
->hw_features
|= NETIF_F_NTUPLE
;
4283 netdev
->features
|= NETIF_F_HIGHDMA
;
4284 netdev
->features
|= NETIF_F_HW_VLAN_STAG_FILTER
;
4286 netdev
->priv_flags
|= IFF_UNICAST_FLT
;
4288 mlx5e_set_netdev_dev_addr(netdev
);
4290 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4291 if (MLX5_VPORT_MANAGER(mdev
))
4292 netdev
->switchdev_ops
= &mlx5e_switchdev_ops
;
4295 mlx5e_ipsec_build_netdev(priv
);
4298 static void mlx5e_create_q_counter(struct mlx5e_priv
*priv
)
4300 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4303 err
= mlx5_core_alloc_q_counter(mdev
, &priv
->q_counter
);
4305 mlx5_core_warn(mdev
, "alloc queue counter failed, %d\n", err
);
4306 priv
->q_counter
= 0;
4310 static void mlx5e_destroy_q_counter(struct mlx5e_priv
*priv
)
4312 if (!priv
->q_counter
)
4315 mlx5_core_dealloc_q_counter(priv
->mdev
, priv
->q_counter
);
4318 static void mlx5e_nic_init(struct mlx5_core_dev
*mdev
,
4319 struct net_device
*netdev
,
4320 const struct mlx5e_profile
*profile
,
4323 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
4326 mlx5e_build_nic_netdev_priv(mdev
, netdev
, profile
, ppriv
);
4327 err
= mlx5e_ipsec_init(priv
);
4329 mlx5_core_err(mdev
, "IPSec initialization failed, %d\n", err
);
4330 mlx5e_build_nic_netdev(netdev
);
4331 mlx5e_vxlan_init(priv
);
4334 static void mlx5e_nic_cleanup(struct mlx5e_priv
*priv
)
4336 mlx5e_ipsec_cleanup(priv
);
4337 mlx5e_vxlan_cleanup(priv
);
4340 static int mlx5e_init_nic_rx(struct mlx5e_priv
*priv
)
4342 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4345 err
= mlx5e_create_indirect_rqt(priv
);
4349 err
= mlx5e_create_direct_rqts(priv
);
4351 goto err_destroy_indirect_rqts
;
4353 err
= mlx5e_create_indirect_tirs(priv
);
4355 goto err_destroy_direct_rqts
;
4357 err
= mlx5e_create_direct_tirs(priv
);
4359 goto err_destroy_indirect_tirs
;
4361 err
= mlx5e_create_flow_steering(priv
);
4363 mlx5_core_warn(mdev
, "create flow steering failed, %d\n", err
);
4364 goto err_destroy_direct_tirs
;
4367 err
= mlx5e_tc_init(priv
);
4369 goto err_destroy_flow_steering
;
4373 err_destroy_flow_steering
:
4374 mlx5e_destroy_flow_steering(priv
);
4375 err_destroy_direct_tirs
:
4376 mlx5e_destroy_direct_tirs(priv
);
4377 err_destroy_indirect_tirs
:
4378 mlx5e_destroy_indirect_tirs(priv
);
4379 err_destroy_direct_rqts
:
4380 mlx5e_destroy_direct_rqts(priv
);
4381 err_destroy_indirect_rqts
:
4382 mlx5e_destroy_rqt(priv
, &priv
->indir_rqt
);
4386 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv
*priv
)
4388 mlx5e_tc_cleanup(priv
);
4389 mlx5e_destroy_flow_steering(priv
);
4390 mlx5e_destroy_direct_tirs(priv
);
4391 mlx5e_destroy_indirect_tirs(priv
);
4392 mlx5e_destroy_direct_rqts(priv
);
4393 mlx5e_destroy_rqt(priv
, &priv
->indir_rqt
);
4396 static int mlx5e_init_nic_tx(struct mlx5e_priv
*priv
)
4400 err
= mlx5e_create_tises(priv
);
4402 mlx5_core_warn(priv
->mdev
, "create tises failed, %d\n", err
);
4406 #ifdef CONFIG_MLX5_CORE_EN_DCB
4407 mlx5e_dcbnl_initialize(priv
);
4412 static void mlx5e_nic_enable(struct mlx5e_priv
*priv
)
4414 struct net_device
*netdev
= priv
->netdev
;
4415 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4418 mlx5e_init_l2_addr(priv
);
4420 /* Marking the link as currently not needed by the Driver */
4421 if (!netif_running(netdev
))
4422 mlx5_set_port_admin_status(mdev
, MLX5_PORT_DOWN
);
4424 /* MTU range: 68 - hw-specific max */
4425 netdev
->min_mtu
= ETH_MIN_MTU
;
4426 mlx5_query_port_max_mtu(priv
->mdev
, &max_mtu
, 1);
4427 netdev
->max_mtu
= MLX5E_HW2SW_MTU(priv
, max_mtu
);
4428 mlx5e_set_dev_port_mtu(priv
);
4430 mlx5_lag_add(mdev
, netdev
);
4432 mlx5e_enable_async_events(priv
);
4434 if (MLX5_VPORT_MANAGER(priv
->mdev
))
4435 mlx5e_register_vport_reps(priv
);
4437 if (netdev
->reg_state
!= NETREG_REGISTERED
)
4439 #ifdef CONFIG_MLX5_CORE_EN_DCB
4440 mlx5e_dcbnl_init_app(priv
);
4442 /* Device already registered: sync netdev system state */
4443 if (mlx5e_vxlan_allowed(mdev
)) {
4445 udp_tunnel_get_rx_info(netdev
);
4449 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
4452 if (netif_running(netdev
))
4454 netif_device_attach(netdev
);
4458 static void mlx5e_nic_disable(struct mlx5e_priv
*priv
)
4460 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4462 #ifdef CONFIG_MLX5_CORE_EN_DCB
4463 if (priv
->netdev
->reg_state
== NETREG_REGISTERED
)
4464 mlx5e_dcbnl_delete_app(priv
);
4468 if (netif_running(priv
->netdev
))
4469 mlx5e_close(priv
->netdev
);
4470 netif_device_detach(priv
->netdev
);
4473 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
4475 if (MLX5_VPORT_MANAGER(priv
->mdev
))
4476 mlx5e_unregister_vport_reps(priv
);
4478 mlx5e_disable_async_events(priv
);
4479 mlx5_lag_remove(mdev
);
4482 static const struct mlx5e_profile mlx5e_nic_profile
= {
4483 .init
= mlx5e_nic_init
,
4484 .cleanup
= mlx5e_nic_cleanup
,
4485 .init_rx
= mlx5e_init_nic_rx
,
4486 .cleanup_rx
= mlx5e_cleanup_nic_rx
,
4487 .init_tx
= mlx5e_init_nic_tx
,
4488 .cleanup_tx
= mlx5e_cleanup_nic_tx
,
4489 .enable
= mlx5e_nic_enable
,
4490 .disable
= mlx5e_nic_disable
,
4491 .update_stats
= mlx5e_update_ndo_stats
,
4492 .max_nch
= mlx5e_get_max_num_channels
,
4493 .update_carrier
= mlx5e_update_carrier
,
4494 .rx_handlers
.handle_rx_cqe
= mlx5e_handle_rx_cqe
,
4495 .rx_handlers
.handle_rx_cqe_mpwqe
= mlx5e_handle_rx_cqe_mpwrq
,
4496 .max_tc
= MLX5E_MAX_NUM_TC
,
4499 /* mlx5e generic netdev management API (move to en_common.c) */
4501 struct net_device
*mlx5e_create_netdev(struct mlx5_core_dev
*mdev
,
4502 const struct mlx5e_profile
*profile
,
4505 int nch
= profile
->max_nch(mdev
);
4506 struct net_device
*netdev
;
4507 struct mlx5e_priv
*priv
;
4509 netdev
= alloc_etherdev_mqs(sizeof(struct mlx5e_priv
),
4510 nch
* profile
->max_tc
,
4513 mlx5_core_err(mdev
, "alloc_etherdev_mqs() failed\n");
4517 #ifdef CONFIG_RFS_ACCEL
4518 netdev
->rx_cpu_rmap
= mdev
->rmap
;
4521 profile
->init(mdev
, netdev
, profile
, ppriv
);
4523 netif_carrier_off(netdev
);
4525 priv
= netdev_priv(netdev
);
4527 priv
->wq
= create_singlethread_workqueue("mlx5e");
4529 goto err_cleanup_nic
;
4534 if (profile
->cleanup
)
4535 profile
->cleanup(priv
);
4536 free_netdev(netdev
);
4541 int mlx5e_attach_netdev(struct mlx5e_priv
*priv
)
4543 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4544 const struct mlx5e_profile
*profile
;
4547 profile
= priv
->profile
;
4548 clear_bit(MLX5E_STATE_DESTROYING
, &priv
->state
);
4550 err
= profile
->init_tx(priv
);
4554 err
= mlx5e_open_drop_rq(mdev
, &priv
->drop_rq
);
4556 mlx5_core_err(mdev
, "open drop rq failed, %d\n", err
);
4557 goto err_cleanup_tx
;
4560 err
= profile
->init_rx(priv
);
4562 goto err_close_drop_rq
;
4564 mlx5e_create_q_counter(priv
);
4566 if (profile
->enable
)
4567 profile
->enable(priv
);
4572 mlx5e_close_drop_rq(&priv
->drop_rq
);
4575 profile
->cleanup_tx(priv
);
4581 void mlx5e_detach_netdev(struct mlx5e_priv
*priv
)
4583 const struct mlx5e_profile
*profile
= priv
->profile
;
4585 set_bit(MLX5E_STATE_DESTROYING
, &priv
->state
);
4587 if (profile
->disable
)
4588 profile
->disable(priv
);
4589 flush_workqueue(priv
->wq
);
4591 mlx5e_destroy_q_counter(priv
);
4592 profile
->cleanup_rx(priv
);
4593 mlx5e_close_drop_rq(&priv
->drop_rq
);
4594 profile
->cleanup_tx(priv
);
4595 cancel_delayed_work_sync(&priv
->update_stats_work
);
4598 void mlx5e_destroy_netdev(struct mlx5e_priv
*priv
)
4600 const struct mlx5e_profile
*profile
= priv
->profile
;
4601 struct net_device
*netdev
= priv
->netdev
;
4603 destroy_workqueue(priv
->wq
);
4604 if (profile
->cleanup
)
4605 profile
->cleanup(priv
);
4606 free_netdev(netdev
);
4609 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4610 * hardware contexts and to connect it to the current netdev.
4612 static int mlx5e_attach(struct mlx5_core_dev
*mdev
, void *vpriv
)
4614 struct mlx5e_priv
*priv
= vpriv
;
4615 struct net_device
*netdev
= priv
->netdev
;
4618 if (netif_device_present(netdev
))
4621 err
= mlx5e_create_mdev_resources(mdev
);
4625 err
= mlx5e_attach_netdev(priv
);
4627 mlx5e_destroy_mdev_resources(mdev
);
4634 static void mlx5e_detach(struct mlx5_core_dev
*mdev
, void *vpriv
)
4636 struct mlx5e_priv
*priv
= vpriv
;
4637 struct net_device
*netdev
= priv
->netdev
;
4639 if (!netif_device_present(netdev
))
4642 mlx5e_detach_netdev(priv
);
4643 mlx5e_destroy_mdev_resources(mdev
);
4646 static void *mlx5e_add(struct mlx5_core_dev
*mdev
)
4648 struct net_device
*netdev
;
4653 err
= mlx5e_check_required_hca_cap(mdev
);
4657 #ifdef CONFIG_MLX5_ESWITCH
4658 if (MLX5_VPORT_MANAGER(mdev
)) {
4659 rpriv
= mlx5e_alloc_nic_rep_priv(mdev
);
4661 mlx5_core_warn(mdev
, "Failed to alloc NIC rep priv data\n");
4667 netdev
= mlx5e_create_netdev(mdev
, &mlx5e_nic_profile
, rpriv
);
4669 mlx5_core_err(mdev
, "mlx5e_create_netdev failed\n");
4670 goto err_free_rpriv
;
4673 priv
= netdev_priv(netdev
);
4675 err
= mlx5e_attach(mdev
, priv
);
4677 mlx5_core_err(mdev
, "mlx5e_attach failed, %d\n", err
);
4678 goto err_destroy_netdev
;
4681 err
= register_netdev(netdev
);
4683 mlx5_core_err(mdev
, "register_netdev failed, %d\n", err
);
4687 #ifdef CONFIG_MLX5_CORE_EN_DCB
4688 mlx5e_dcbnl_init_app(priv
);
4693 mlx5e_detach(mdev
, priv
);
4695 mlx5e_destroy_netdev(priv
);
4701 static void mlx5e_remove(struct mlx5_core_dev
*mdev
, void *vpriv
)
4703 struct mlx5e_priv
*priv
= vpriv
;
4704 void *ppriv
= priv
->ppriv
;
4706 #ifdef CONFIG_MLX5_CORE_EN_DCB
4707 mlx5e_dcbnl_delete_app(priv
);
4709 unregister_netdev(priv
->netdev
);
4710 mlx5e_detach(mdev
, vpriv
);
4711 mlx5e_destroy_netdev(priv
);
4715 static void *mlx5e_get_netdev(void *vpriv
)
4717 struct mlx5e_priv
*priv
= vpriv
;
4719 return priv
->netdev
;
4722 static struct mlx5_interface mlx5e_interface
= {
4724 .remove
= mlx5e_remove
,
4725 .attach
= mlx5e_attach
,
4726 .detach
= mlx5e_detach
,
4727 .event
= mlx5e_async_event
,
4728 .protocol
= MLX5_INTERFACE_PROTOCOL_ETH
,
4729 .get_dev
= mlx5e_get_netdev
,
4732 void mlx5e_init(void)
4734 mlx5e_ipsec_build_inverse_table();
4735 mlx5e_build_ptys2ethtool_map();
4736 mlx5_register_interface(&mlx5e_interface
);
4739 void mlx5e_cleanup(void)
4741 mlx5_unregister_interface(&mlx5e_interface
);