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drm/i915: Macro to determine DPF support
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / i915 / i915_irq.c
blob440c9051aa9bc5edc09fef008da34ecacb01adc7
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include "drmP.h"
34 #include "drm.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 /* For display hotplug interrupt */
41 static void
42 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
43 {
44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
47 POSTING_READ(DEIMR);
48 }
49 }
50
51 static inline void
52 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
53 {
54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
57 POSTING_READ(DEIMR);
58 }
59 }
60
61 void
62 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63 {
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
65 u32 reg = PIPESTAT(pipe);
66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
70 POSTING_READ(reg);
71 }
72 }
73
74 void
75 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76 {
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
78 u32 reg = PIPESTAT(pipe);
79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
82 POSTING_READ(reg);
83 }
84 }
85
86 /**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
89 void intel_enable_asle(struct drm_device *dev)
90 {
91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
99
100 if (HAS_PCH_SPLIT(dev))
101 ironlake_enable_display_irq(dev_priv, DE_GSE);
102 else {
103 i915_enable_pipestat(dev_priv, 1,
104 PIPE_LEGACY_BLC_EVENT_ENABLE);
105 if (INTEL_INFO(dev)->gen >= 4)
106 i915_enable_pipestat(dev_priv, 0,
107 PIPE_LEGACY_BLC_EVENT_ENABLE);
108 }
109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
111 }
112
113 /**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122 static int
123 i915_pipe_enabled(struct drm_device *dev, int pipe)
124 {
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
127 }
128
129 /* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
132 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
133 {
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
137 u32 high1, high2, low;
138
139 if (!i915_pipe_enabled(dev, pipe)) {
140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
141 "pipe %c\n", pipe_name(pipe));
142 return 0;
143 }
144
145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
147
148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
157 } while (high1 != high2);
158
159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
162 }
163
164 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
165 {
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
167 int reg = PIPE_FRMCOUNT_GM45(pipe);
168
169 if (!i915_pipe_enabled(dev, pipe)) {
170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
171 "pipe %c\n", pipe_name(pipe));
172 return 0;
173 }
174
175 return I915_READ(reg);
176 }
177
178 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
179 int *vpos, int *hpos)
180 {
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
189 "pipe %c\n", pipe_name(pipe));
190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242 }
243
244 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248 {
249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
251
252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
268
269 /* Helper routine in DRM core does all the work: */
270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
273 }
274
275 /*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278 static void i915_hotplug_work_func(struct work_struct *work)
279 {
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
283 struct drm_mode_config *mode_config = &dev->mode_config;
284 struct intel_encoder *encoder;
285
286 mutex_lock(&mode_config->mutex);
287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
293 mutex_unlock(&mode_config->mutex);
294
295 /* Just fire off a uevent and let userspace tell us what to do */
296 drm_helper_hpd_irq_event(dev);
297 }
298
299 static void i915_handle_rps_change(struct drm_device *dev)
300 {
301 drm_i915_private_t *dev_priv = dev->dev_private;
302 u32 busy_up, busy_down, max_avg, min_avg;
303 u8 new_delay = dev_priv->cur_delay;
304
305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
310
311 /* Handle RCS change request from hw */
312 if (busy_up > max_avg) {
313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
317 } else if (busy_down < min_avg) {
318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
322 }
323
324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
326
327 return;
328 }
329
330 static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
332 {
333 struct drm_i915_private *dev_priv = dev->dev_private;
334
335 if (ring->obj == NULL)
336 return;
337
338 trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
339
340 wake_up_all(&ring->irq_queue);
341 if (i915_enable_hangcheck) {
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer,
344 jiffies +
345 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
346 }
347 }
348
349 static void gen6_pm_rps_work(struct work_struct *work)
350 {
351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
352 rps_work);
353 u32 pm_iir, pm_imr;
354 u8 new_delay;
355
356 spin_lock_irq(&dev_priv->rps_lock);
357 pm_iir = dev_priv->pm_iir;
358 dev_priv->pm_iir = 0;
359 pm_imr = I915_READ(GEN6_PMIMR);
360 I915_WRITE(GEN6_PMIMR, 0);
361 spin_unlock_irq(&dev_priv->rps_lock);
362
363 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
364 return;
365
366 mutex_lock(&dev_priv->dev->struct_mutex);
367
368 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
369 new_delay = dev_priv->cur_delay + 1;
370 else
371 new_delay = dev_priv->cur_delay - 1;
372
373 gen6_set_rps(dev_priv->dev, new_delay);
374
375 mutex_unlock(&dev_priv->dev->struct_mutex);
376 }
377
378
379 /**
380 * ivybridge_parity_work - Workqueue called when a parity error interrupt
381 * occurred.
382 * @work: workqueue struct
383 *
384 * Doesn't actually do anything except notify userspace. As a consequence of
385 * this event, userspace should try to remap the bad rows since statistically
386 * it is likely the same row is more likely to go bad again.
387 */
388 static void ivybridge_parity_work(struct work_struct *work)
389 {
390 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
391 parity_error_work);
392 u32 error_status, row, bank, subbank;
393 char *parity_event[5];
394 uint32_t misccpctl;
395 unsigned long flags;
396
397 /* We must turn off DOP level clock gating to access the L3 registers.
398 * In order to prevent a get/put style interface, acquire struct mutex
399 * any time we access those registers.
400 */
401 mutex_lock(&dev_priv->dev->struct_mutex);
402
403 misccpctl = I915_READ(GEN7_MISCCPCTL);
404 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
405 POSTING_READ(GEN7_MISCCPCTL);
406
407 error_status = I915_READ(GEN7_L3CDERRST1);
408 row = GEN7_PARITY_ERROR_ROW(error_status);
409 bank = GEN7_PARITY_ERROR_BANK(error_status);
410 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
411
412 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
413 GEN7_L3CDERRST1_ENABLE);
414 POSTING_READ(GEN7_L3CDERRST1);
415
416 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
417
418 spin_lock_irqsave(&dev_priv->irq_lock, flags);
419 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
420 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
421 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
422
423 mutex_unlock(&dev_priv->dev->struct_mutex);
424
425 parity_event[0] = "L3_PARITY_ERROR=1";
426 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
427 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
428 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
429 parity_event[4] = NULL;
430
431 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
432 KOBJ_CHANGE, parity_event);
433
434 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
435 row, bank, subbank);
436
437 kfree(parity_event[3]);
438 kfree(parity_event[2]);
439 kfree(parity_event[1]);
440 }
441
442 static void ivybridge_handle_parity_error(struct drm_device *dev)
443 {
444 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
445 unsigned long flags;
446
447 if (!HAS_L3_GPU_CACHE(dev))
448 return;
449
450 spin_lock_irqsave(&dev_priv->irq_lock, flags);
451 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
452 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
453 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
454
455 queue_work(dev_priv->wq, &dev_priv->parity_error_work);
456 }
457
458 static void snb_gt_irq_handler(struct drm_device *dev,
459 struct drm_i915_private *dev_priv,
460 u32 gt_iir)
461 {
462
463 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
464 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
465 notify_ring(dev, &dev_priv->ring[RCS]);
466 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
467 notify_ring(dev, &dev_priv->ring[VCS]);
468 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
469 notify_ring(dev, &dev_priv->ring[BCS]);
470
471 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
472 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
473 GT_RENDER_CS_ERROR_INTERRUPT)) {
474 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
475 i915_handle_error(dev, false);
476 }
477
478 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
479 ivybridge_handle_parity_error(dev);
480 }
481
482 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
483 u32 pm_iir)
484 {
485 unsigned long flags;
486
487 /*
488 * IIR bits should never already be set because IMR should
489 * prevent an interrupt from being shown in IIR. The warning
490 * displays a case where we've unsafely cleared
491 * dev_priv->pm_iir. Although missing an interrupt of the same
492 * type is not a problem, it displays a problem in the logic.
493 *
494 * The mask bit in IMR is cleared by rps_work.
495 */
496
497 spin_lock_irqsave(&dev_priv->rps_lock, flags);
498 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
499 dev_priv->pm_iir |= pm_iir;
500 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
501 POSTING_READ(GEN6_PMIMR);
502 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
503
504 queue_work(dev_priv->wq, &dev_priv->rps_work);
505 }
506
507 static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
508 {
509 struct drm_device *dev = (struct drm_device *) arg;
510 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
511 u32 iir, gt_iir, pm_iir;
512 irqreturn_t ret = IRQ_NONE;
513 unsigned long irqflags;
514 int pipe;
515 u32 pipe_stats[I915_MAX_PIPES];
516 bool blc_event;
517
518 atomic_inc(&dev_priv->irq_received);
519
520 while (true) {
521 iir = I915_READ(VLV_IIR);
522 gt_iir = I915_READ(GTIIR);
523 pm_iir = I915_READ(GEN6_PMIIR);
524
525 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
526 goto out;
527
528 ret = IRQ_HANDLED;
529
530 snb_gt_irq_handler(dev, dev_priv, gt_iir);
531
532 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
533 for_each_pipe(pipe) {
534 int reg = PIPESTAT(pipe);
535 pipe_stats[pipe] = I915_READ(reg);
536
537 /*
538 * Clear the PIPE*STAT regs before the IIR
539 */
540 if (pipe_stats[pipe] & 0x8000ffff) {
541 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
542 DRM_DEBUG_DRIVER("pipe %c underrun\n",
543 pipe_name(pipe));
544 I915_WRITE(reg, pipe_stats[pipe]);
545 }
546 }
547 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
548
549 for_each_pipe(pipe) {
550 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
551 drm_handle_vblank(dev, pipe);
552
553 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
554 intel_prepare_page_flip(dev, pipe);
555 intel_finish_page_flip(dev, pipe);
556 }
557 }
558
559 /* Consume port. Then clear IIR or we'll miss events */
560 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
561 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
562
563 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
564 hotplug_status);
565 if (hotplug_status & dev_priv->hotplug_supported_mask)
566 queue_work(dev_priv->wq,
567 &dev_priv->hotplug_work);
568
569 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
570 I915_READ(PORT_HOTPLUG_STAT);
571 }
572
573 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
574 blc_event = true;
575
576 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
577 gen6_queue_rps_work(dev_priv, pm_iir);
578
579 I915_WRITE(GTIIR, gt_iir);
580 I915_WRITE(GEN6_PMIIR, pm_iir);
581 I915_WRITE(VLV_IIR, iir);
582 }
583
584 out:
585 return ret;
586 }
587
588 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
589 {
590 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
591 int pipe;
592
593 if (pch_iir & SDE_AUDIO_POWER_MASK)
594 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
595 (pch_iir & SDE_AUDIO_POWER_MASK) >>
596 SDE_AUDIO_POWER_SHIFT);
597
598 if (pch_iir & SDE_GMBUS)
599 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
600
601 if (pch_iir & SDE_AUDIO_HDCP_MASK)
602 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
603
604 if (pch_iir & SDE_AUDIO_TRANS_MASK)
605 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
606
607 if (pch_iir & SDE_POISON)
608 DRM_ERROR("PCH poison interrupt\n");
609
610 if (pch_iir & SDE_FDI_MASK)
611 for_each_pipe(pipe)
612 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
613 pipe_name(pipe),
614 I915_READ(FDI_RX_IIR(pipe)));
615
616 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
617 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
618
619 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
620 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
621
622 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
623 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
624 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
625 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
626 }
627
628 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
629 {
630 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
631 int pipe;
632
633 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
634 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
635 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
636 SDE_AUDIO_POWER_SHIFT_CPT);
637
638 if (pch_iir & SDE_AUX_MASK_CPT)
639 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
640
641 if (pch_iir & SDE_GMBUS_CPT)
642 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
643
644 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
645 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
646
647 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
648 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
649
650 if (pch_iir & SDE_FDI_MASK_CPT)
651 for_each_pipe(pipe)
652 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
653 pipe_name(pipe),
654 I915_READ(FDI_RX_IIR(pipe)));
655 }
656
657 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
658 {
659 struct drm_device *dev = (struct drm_device *) arg;
660 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
661 u32 de_iir, gt_iir, de_ier, pm_iir;
662 irqreturn_t ret = IRQ_NONE;
663 int i;
664
665 atomic_inc(&dev_priv->irq_received);
666
667 /* disable master interrupt before clearing iir */
668 de_ier = I915_READ(DEIER);
669 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
670
671 gt_iir = I915_READ(GTIIR);
672 if (gt_iir) {
673 snb_gt_irq_handler(dev, dev_priv, gt_iir);
674 I915_WRITE(GTIIR, gt_iir);
675 ret = IRQ_HANDLED;
676 }
677
678 de_iir = I915_READ(DEIIR);
679 if (de_iir) {
680 if (de_iir & DE_GSE_IVB)
681 intel_opregion_gse_intr(dev);
682
683 for (i = 0; i < 3; i++) {
684 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
685 intel_prepare_page_flip(dev, i);
686 intel_finish_page_flip_plane(dev, i);
687 }
688 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
689 drm_handle_vblank(dev, i);
690 }
691
692 /* check event from PCH */
693 if (de_iir & DE_PCH_EVENT_IVB) {
694 u32 pch_iir = I915_READ(SDEIIR);
695
696 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
697 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
698 cpt_irq_handler(dev, pch_iir);
699
700 /* clear PCH hotplug event before clear CPU irq */
701 I915_WRITE(SDEIIR, pch_iir);
702 }
703
704 I915_WRITE(DEIIR, de_iir);
705 ret = IRQ_HANDLED;
706 }
707
708 pm_iir = I915_READ(GEN6_PMIIR);
709 if (pm_iir) {
710 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
711 gen6_queue_rps_work(dev_priv, pm_iir);
712 I915_WRITE(GEN6_PMIIR, pm_iir);
713 ret = IRQ_HANDLED;
714 }
715
716 I915_WRITE(DEIER, de_ier);
717 POSTING_READ(DEIER);
718
719 return ret;
720 }
721
722 static void ilk_gt_irq_handler(struct drm_device *dev,
723 struct drm_i915_private *dev_priv,
724 u32 gt_iir)
725 {
726 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
727 notify_ring(dev, &dev_priv->ring[RCS]);
728 if (gt_iir & GT_BSD_USER_INTERRUPT)
729 notify_ring(dev, &dev_priv->ring[VCS]);
730 }
731
732 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
733 {
734 struct drm_device *dev = (struct drm_device *) arg;
735 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
736 int ret = IRQ_NONE;
737 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
738 u32 hotplug_mask;
739
740 atomic_inc(&dev_priv->irq_received);
741
742 /* disable master interrupt before clearing iir */
743 de_ier = I915_READ(DEIER);
744 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
745 POSTING_READ(DEIER);
746
747 de_iir = I915_READ(DEIIR);
748 gt_iir = I915_READ(GTIIR);
749 pch_iir = I915_READ(SDEIIR);
750 pm_iir = I915_READ(GEN6_PMIIR);
751
752 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
753 (!IS_GEN6(dev) || pm_iir == 0))
754 goto done;
755
756 if (HAS_PCH_CPT(dev))
757 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
758 else
759 hotplug_mask = SDE_HOTPLUG_MASK;
760
761 ret = IRQ_HANDLED;
762
763 if (IS_GEN5(dev))
764 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
765 else
766 snb_gt_irq_handler(dev, dev_priv, gt_iir);
767
768 if (de_iir & DE_GSE)
769 intel_opregion_gse_intr(dev);
770
771 if (de_iir & DE_PLANEA_FLIP_DONE) {
772 intel_prepare_page_flip(dev, 0);
773 intel_finish_page_flip_plane(dev, 0);
774 }
775
776 if (de_iir & DE_PLANEB_FLIP_DONE) {
777 intel_prepare_page_flip(dev, 1);
778 intel_finish_page_flip_plane(dev, 1);
779 }
780
781 if (de_iir & DE_PIPEA_VBLANK)
782 drm_handle_vblank(dev, 0);
783
784 if (de_iir & DE_PIPEB_VBLANK)
785 drm_handle_vblank(dev, 1);
786
787 /* check event from PCH */
788 if (de_iir & DE_PCH_EVENT) {
789 if (pch_iir & hotplug_mask)
790 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
791 if (HAS_PCH_CPT(dev))
792 cpt_irq_handler(dev, pch_iir);
793 else
794 ibx_irq_handler(dev, pch_iir);
795 }
796
797 if (de_iir & DE_PCU_EVENT) {
798 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
799 i915_handle_rps_change(dev);
800 }
801
802 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
803 gen6_queue_rps_work(dev_priv, pm_iir);
804
805 /* should clear PCH hotplug event before clear CPU irq */
806 I915_WRITE(SDEIIR, pch_iir);
807 I915_WRITE(GTIIR, gt_iir);
808 I915_WRITE(DEIIR, de_iir);
809 I915_WRITE(GEN6_PMIIR, pm_iir);
810
811 done:
812 I915_WRITE(DEIER, de_ier);
813 POSTING_READ(DEIER);
814
815 return ret;
816 }
817
818 /**
819 * i915_error_work_func - do process context error handling work
820 * @work: work struct
821 *
822 * Fire an error uevent so userspace can see that a hang or error
823 * was detected.
824 */
825 static void i915_error_work_func(struct work_struct *work)
826 {
827 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
828 error_work);
829 struct drm_device *dev = dev_priv->dev;
830 char *error_event[] = { "ERROR=1", NULL };
831 char *reset_event[] = { "RESET=1", NULL };
832 char *reset_done_event[] = { "ERROR=0", NULL };
833
834 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
835
836 if (atomic_read(&dev_priv->mm.wedged)) {
837 DRM_DEBUG_DRIVER("resetting chip\n");
838 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
839 if (!i915_reset(dev)) {
840 atomic_set(&dev_priv->mm.wedged, 0);
841 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
842 }
843 complete_all(&dev_priv->error_completion);
844 }
845 }
846
847 #ifdef CONFIG_DEBUG_FS
848 static struct drm_i915_error_object *
849 i915_error_object_create(struct drm_i915_private *dev_priv,
850 struct drm_i915_gem_object *src)
851 {
852 struct drm_i915_error_object *dst;
853 int page, page_count;
854 u32 reloc_offset;
855
856 if (src == NULL || src->pages == NULL)
857 return NULL;
858
859 page_count = src->base.size / PAGE_SIZE;
860
861 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
862 if (dst == NULL)
863 return NULL;
864
865 reloc_offset = src->gtt_offset;
866 for (page = 0; page < page_count; page++) {
867 unsigned long flags;
868 void *d;
869
870 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
871 if (d == NULL)
872 goto unwind;
873
874 local_irq_save(flags);
875 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
876 src->has_global_gtt_mapping) {
877 void __iomem *s;
878
879 /* Simply ignore tiling or any overlapping fence.
880 * It's part of the error state, and this hopefully
881 * captures what the GPU read.
882 */
883
884 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
885 reloc_offset);
886 memcpy_fromio(d, s, PAGE_SIZE);
887 io_mapping_unmap_atomic(s);
888 } else {
889 void *s;
890
891 drm_clflush_pages(&src->pages[page], 1);
892
893 s = kmap_atomic(src->pages[page]);
894 memcpy(d, s, PAGE_SIZE);
895 kunmap_atomic(s);
896
897 drm_clflush_pages(&src->pages[page], 1);
898 }
899 local_irq_restore(flags);
900
901 dst->pages[page] = d;
902
903 reloc_offset += PAGE_SIZE;
904 }
905 dst->page_count = page_count;
906 dst->gtt_offset = src->gtt_offset;
907
908 return dst;
909
910 unwind:
911 while (page--)
912 kfree(dst->pages[page]);
913 kfree(dst);
914 return NULL;
915 }
916
917 static void
918 i915_error_object_free(struct drm_i915_error_object *obj)
919 {
920 int page;
921
922 if (obj == NULL)
923 return;
924
925 for (page = 0; page < obj->page_count; page++)
926 kfree(obj->pages[page]);
927
928 kfree(obj);
929 }
930
931 void
932 i915_error_state_free(struct kref *error_ref)
933 {
934 struct drm_i915_error_state *error = container_of(error_ref,
935 typeof(*error), ref);
936 int i;
937
938 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
939 i915_error_object_free(error->ring[i].batchbuffer);
940 i915_error_object_free(error->ring[i].ringbuffer);
941 kfree(error->ring[i].requests);
942 }
943
944 kfree(error->active_bo);
945 kfree(error->overlay);
946 kfree(error);
947 }
948 static void capture_bo(struct drm_i915_error_buffer *err,
949 struct drm_i915_gem_object *obj)
950 {
951 err->size = obj->base.size;
952 err->name = obj->base.name;
953 err->rseqno = obj->last_read_seqno;
954 err->wseqno = obj->last_write_seqno;
955 err->gtt_offset = obj->gtt_offset;
956 err->read_domains = obj->base.read_domains;
957 err->write_domain = obj->base.write_domain;
958 err->fence_reg = obj->fence_reg;
959 err->pinned = 0;
960 if (obj->pin_count > 0)
961 err->pinned = 1;
962 if (obj->user_pin_count > 0)
963 err->pinned = -1;
964 err->tiling = obj->tiling_mode;
965 err->dirty = obj->dirty;
966 err->purgeable = obj->madv != I915_MADV_WILLNEED;
967 err->ring = obj->ring ? obj->ring->id : -1;
968 err->cache_level = obj->cache_level;
969 }
970
971 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
972 int count, struct list_head *head)
973 {
974 struct drm_i915_gem_object *obj;
975 int i = 0;
976
977 list_for_each_entry(obj, head, mm_list) {
978 capture_bo(err++, obj);
979 if (++i == count)
980 break;
981 }
982
983 return i;
984 }
985
986 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
987 int count, struct list_head *head)
988 {
989 struct drm_i915_gem_object *obj;
990 int i = 0;
991
992 list_for_each_entry(obj, head, gtt_list) {
993 if (obj->pin_count == 0)
994 continue;
995
996 capture_bo(err++, obj);
997 if (++i == count)
998 break;
999 }
1000
1001 return i;
1002 }
1003
1004 static void i915_gem_record_fences(struct drm_device *dev,
1005 struct drm_i915_error_state *error)
1006 {
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 int i;
1009
1010 /* Fences */
1011 switch (INTEL_INFO(dev)->gen) {
1012 case 7:
1013 case 6:
1014 for (i = 0; i < 16; i++)
1015 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1016 break;
1017 case 5:
1018 case 4:
1019 for (i = 0; i < 16; i++)
1020 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1021 break;
1022 case 3:
1023 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1024 for (i = 0; i < 8; i++)
1025 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1026 case 2:
1027 for (i = 0; i < 8; i++)
1028 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1029 break;
1030
1031 }
1032 }
1033
1034 static struct drm_i915_error_object *
1035 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1036 struct intel_ring_buffer *ring)
1037 {
1038 struct drm_i915_gem_object *obj;
1039 u32 seqno;
1040
1041 if (!ring->get_seqno)
1042 return NULL;
1043
1044 seqno = ring->get_seqno(ring);
1045 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1046 if (obj->ring != ring)
1047 continue;
1048
1049 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1050 continue;
1051
1052 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1053 continue;
1054
1055 /* We need to copy these to an anonymous buffer as the simplest
1056 * method to avoid being overwritten by userspace.
1057 */
1058 return i915_error_object_create(dev_priv, obj);
1059 }
1060
1061 return NULL;
1062 }
1063
1064 static void i915_record_ring_state(struct drm_device *dev,
1065 struct drm_i915_error_state *error,
1066 struct intel_ring_buffer *ring)
1067 {
1068 struct drm_i915_private *dev_priv = dev->dev_private;
1069
1070 if (INTEL_INFO(dev)->gen >= 6) {
1071 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1072 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1073 error->semaphore_mboxes[ring->id][0]
1074 = I915_READ(RING_SYNC_0(ring->mmio_base));
1075 error->semaphore_mboxes[ring->id][1]
1076 = I915_READ(RING_SYNC_1(ring->mmio_base));
1077 }
1078
1079 if (INTEL_INFO(dev)->gen >= 4) {
1080 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1081 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1082 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1083 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1084 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1085 if (ring->id == RCS) {
1086 error->instdone1 = I915_READ(INSTDONE1);
1087 error->bbaddr = I915_READ64(BB_ADDR);
1088 }
1089 } else {
1090 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1091 error->ipeir[ring->id] = I915_READ(IPEIR);
1092 error->ipehr[ring->id] = I915_READ(IPEHR);
1093 error->instdone[ring->id] = I915_READ(INSTDONE);
1094 }
1095
1096 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1097 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1098 error->seqno[ring->id] = ring->get_seqno(ring);
1099 error->acthd[ring->id] = intel_ring_get_active_head(ring);
1100 error->head[ring->id] = I915_READ_HEAD(ring);
1101 error->tail[ring->id] = I915_READ_TAIL(ring);
1102
1103 error->cpu_ring_head[ring->id] = ring->head;
1104 error->cpu_ring_tail[ring->id] = ring->tail;
1105 }
1106
1107 static void i915_gem_record_rings(struct drm_device *dev,
1108 struct drm_i915_error_state *error)
1109 {
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1111 struct intel_ring_buffer *ring;
1112 struct drm_i915_gem_request *request;
1113 int i, count;
1114
1115 for_each_ring(ring, dev_priv, i) {
1116 i915_record_ring_state(dev, error, ring);
1117
1118 error->ring[i].batchbuffer =
1119 i915_error_first_batchbuffer(dev_priv, ring);
1120
1121 error->ring[i].ringbuffer =
1122 i915_error_object_create(dev_priv, ring->obj);
1123
1124 count = 0;
1125 list_for_each_entry(request, &ring->request_list, list)
1126 count++;
1127
1128 error->ring[i].num_requests = count;
1129 error->ring[i].requests =
1130 kmalloc(count*sizeof(struct drm_i915_error_request),
1131 GFP_ATOMIC);
1132 if (error->ring[i].requests == NULL) {
1133 error->ring[i].num_requests = 0;
1134 continue;
1135 }
1136
1137 count = 0;
1138 list_for_each_entry(request, &ring->request_list, list) {
1139 struct drm_i915_error_request *erq;
1140
1141 erq = &error->ring[i].requests[count++];
1142 erq->seqno = request->seqno;
1143 erq->jiffies = request->emitted_jiffies;
1144 erq->tail = request->tail;
1145 }
1146 }
1147 }
1148
1149 /**
1150 * i915_capture_error_state - capture an error record for later analysis
1151 * @dev: drm device
1152 *
1153 * Should be called when an error is detected (either a hang or an error
1154 * interrupt) to capture error state from the time of the error. Fills
1155 * out a structure which becomes available in debugfs for user level tools
1156 * to pick up.
1157 */
1158 static void i915_capture_error_state(struct drm_device *dev)
1159 {
1160 struct drm_i915_private *dev_priv = dev->dev_private;
1161 struct drm_i915_gem_object *obj;
1162 struct drm_i915_error_state *error;
1163 unsigned long flags;
1164 int i, pipe;
1165
1166 spin_lock_irqsave(&dev_priv->error_lock, flags);
1167 error = dev_priv->first_error;
1168 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1169 if (error)
1170 return;
1171
1172 /* Account for pipe specific data like PIPE*STAT */
1173 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1174 if (!error) {
1175 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1176 return;
1177 }
1178
1179 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1180 dev->primary->index);
1181
1182 kref_init(&error->ref);
1183 error->eir = I915_READ(EIR);
1184 error->pgtbl_er = I915_READ(PGTBL_ER);
1185 error->ccid = I915_READ(CCID);
1186
1187 if (HAS_PCH_SPLIT(dev))
1188 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1189 else if (IS_VALLEYVIEW(dev))
1190 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1191 else if (IS_GEN2(dev))
1192 error->ier = I915_READ16(IER);
1193 else
1194 error->ier = I915_READ(IER);
1195
1196 for_each_pipe(pipe)
1197 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1198
1199 if (INTEL_INFO(dev)->gen >= 6) {
1200 error->error = I915_READ(ERROR_GEN6);
1201 error->done_reg = I915_READ(DONE_REG);
1202 }
1203
1204 i915_gem_record_fences(dev, error);
1205 i915_gem_record_rings(dev, error);
1206
1207 /* Record buffers on the active and pinned lists. */
1208 error->active_bo = NULL;
1209 error->pinned_bo = NULL;
1210
1211 i = 0;
1212 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1213 i++;
1214 error->active_bo_count = i;
1215 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1216 if (obj->pin_count)
1217 i++;
1218 error->pinned_bo_count = i - error->active_bo_count;
1219
1220 error->active_bo = NULL;
1221 error->pinned_bo = NULL;
1222 if (i) {
1223 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1224 GFP_ATOMIC);
1225 if (error->active_bo)
1226 error->pinned_bo =
1227 error->active_bo + error->active_bo_count;
1228 }
1229
1230 if (error->active_bo)
1231 error->active_bo_count =
1232 capture_active_bo(error->active_bo,
1233 error->active_bo_count,
1234 &dev_priv->mm.active_list);
1235
1236 if (error->pinned_bo)
1237 error->pinned_bo_count =
1238 capture_pinned_bo(error->pinned_bo,
1239 error->pinned_bo_count,
1240 &dev_priv->mm.gtt_list);
1241
1242 do_gettimeofday(&error->time);
1243
1244 error->overlay = intel_overlay_capture_error_state(dev);
1245 error->display = intel_display_capture_error_state(dev);
1246
1247 spin_lock_irqsave(&dev_priv->error_lock, flags);
1248 if (dev_priv->first_error == NULL) {
1249 dev_priv->first_error = error;
1250 error = NULL;
1251 }
1252 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1253
1254 if (error)
1255 i915_error_state_free(&error->ref);
1256 }
1257
1258 void i915_destroy_error_state(struct drm_device *dev)
1259 {
1260 struct drm_i915_private *dev_priv = dev->dev_private;
1261 struct drm_i915_error_state *error;
1262 unsigned long flags;
1263
1264 spin_lock_irqsave(&dev_priv->error_lock, flags);
1265 error = dev_priv->first_error;
1266 dev_priv->first_error = NULL;
1267 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1268
1269 if (error)
1270 kref_put(&error->ref, i915_error_state_free);
1271 }
1272 #else
1273 #define i915_capture_error_state(x)
1274 #endif
1275
1276 static void i915_report_and_clear_eir(struct drm_device *dev)
1277 {
1278 struct drm_i915_private *dev_priv = dev->dev_private;
1279 u32 eir = I915_READ(EIR);
1280 int pipe;
1281
1282 if (!eir)
1283 return;
1284
1285 pr_err("render error detected, EIR: 0x%08x\n", eir);
1286
1287 if (IS_G4X(dev)) {
1288 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1289 u32 ipeir = I915_READ(IPEIR_I965);
1290
1291 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1292 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1293 pr_err(" INSTDONE: 0x%08x\n",
1294 I915_READ(INSTDONE_I965));
1295 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1296 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1297 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1298 I915_WRITE(IPEIR_I965, ipeir);
1299 POSTING_READ(IPEIR_I965);
1300 }
1301 if (eir & GM45_ERROR_PAGE_TABLE) {
1302 u32 pgtbl_err = I915_READ(PGTBL_ER);
1303 pr_err("page table error\n");
1304 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1305 I915_WRITE(PGTBL_ER, pgtbl_err);
1306 POSTING_READ(PGTBL_ER);
1307 }
1308 }
1309
1310 if (!IS_GEN2(dev)) {
1311 if (eir & I915_ERROR_PAGE_TABLE) {
1312 u32 pgtbl_err = I915_READ(PGTBL_ER);
1313 pr_err("page table error\n");
1314 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1315 I915_WRITE(PGTBL_ER, pgtbl_err);
1316 POSTING_READ(PGTBL_ER);
1317 }
1318 }
1319
1320 if (eir & I915_ERROR_MEMORY_REFRESH) {
1321 pr_err("memory refresh error:\n");
1322 for_each_pipe(pipe)
1323 pr_err("pipe %c stat: 0x%08x\n",
1324 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1325 /* pipestat has already been acked */
1326 }
1327 if (eir & I915_ERROR_INSTRUCTION) {
1328 pr_err("instruction error\n");
1329 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
1330 if (INTEL_INFO(dev)->gen < 4) {
1331 u32 ipeir = I915_READ(IPEIR);
1332
1333 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1334 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1335 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1336 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
1337 I915_WRITE(IPEIR, ipeir);
1338 POSTING_READ(IPEIR);
1339 } else {
1340 u32 ipeir = I915_READ(IPEIR_I965);
1341
1342 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1343 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1344 pr_err(" INSTDONE: 0x%08x\n",
1345 I915_READ(INSTDONE_I965));
1346 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1347 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1348 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1349 I915_WRITE(IPEIR_I965, ipeir);
1350 POSTING_READ(IPEIR_I965);
1351 }
1352 }
1353
1354 I915_WRITE(EIR, eir);
1355 POSTING_READ(EIR);
1356 eir = I915_READ(EIR);
1357 if (eir) {
1358 /*
1359 * some errors might have become stuck,
1360 * mask them.
1361 */
1362 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1363 I915_WRITE(EMR, I915_READ(EMR) | eir);
1364 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1365 }
1366 }
1367
1368 /**
1369 * i915_handle_error - handle an error interrupt
1370 * @dev: drm device
1371 *
1372 * Do some basic checking of regsiter state at error interrupt time and
1373 * dump it to the syslog. Also call i915_capture_error_state() to make
1374 * sure we get a record and make it available in debugfs. Fire a uevent
1375 * so userspace knows something bad happened (should trigger collection
1376 * of a ring dump etc.).
1377 */
1378 void i915_handle_error(struct drm_device *dev, bool wedged)
1379 {
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 struct intel_ring_buffer *ring;
1382 int i;
1383
1384 i915_capture_error_state(dev);
1385 i915_report_and_clear_eir(dev);
1386
1387 if (wedged) {
1388 INIT_COMPLETION(dev_priv->error_completion);
1389 atomic_set(&dev_priv->mm.wedged, 1);
1390
1391 /*
1392 * Wakeup waiting processes so they don't hang
1393 */
1394 for_each_ring(ring, dev_priv, i)
1395 wake_up_all(&ring->irq_queue);
1396 }
1397
1398 queue_work(dev_priv->wq, &dev_priv->error_work);
1399 }
1400
1401 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1402 {
1403 drm_i915_private_t *dev_priv = dev->dev_private;
1404 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1406 struct drm_i915_gem_object *obj;
1407 struct intel_unpin_work *work;
1408 unsigned long flags;
1409 bool stall_detected;
1410
1411 /* Ignore early vblank irqs */
1412 if (intel_crtc == NULL)
1413 return;
1414
1415 spin_lock_irqsave(&dev->event_lock, flags);
1416 work = intel_crtc->unpin_work;
1417
1418 if (work == NULL || work->pending || !work->enable_stall_check) {
1419 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1420 spin_unlock_irqrestore(&dev->event_lock, flags);
1421 return;
1422 }
1423
1424 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1425 obj = work->pending_flip_obj;
1426 if (INTEL_INFO(dev)->gen >= 4) {
1427 int dspsurf = DSPSURF(intel_crtc->plane);
1428 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1429 obj->gtt_offset;
1430 } else {
1431 int dspaddr = DSPADDR(intel_crtc->plane);
1432 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1433 crtc->y * crtc->fb->pitches[0] +
1434 crtc->x * crtc->fb->bits_per_pixel/8);
1435 }
1436
1437 spin_unlock_irqrestore(&dev->event_lock, flags);
1438
1439 if (stall_detected) {
1440 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1441 intel_prepare_page_flip(dev, intel_crtc->plane);
1442 }
1443 }
1444
1445 /* Called from drm generic code, passed 'crtc' which
1446 * we use as a pipe index
1447 */
1448 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1449 {
1450 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1451 unsigned long irqflags;
1452
1453 if (!i915_pipe_enabled(dev, pipe))
1454 return -EINVAL;
1455
1456 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1457 if (INTEL_INFO(dev)->gen >= 4)
1458 i915_enable_pipestat(dev_priv, pipe,
1459 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1460 else
1461 i915_enable_pipestat(dev_priv, pipe,
1462 PIPE_VBLANK_INTERRUPT_ENABLE);
1463
1464 /* maintain vblank delivery even in deep C-states */
1465 if (dev_priv->info->gen == 3)
1466 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1467 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1468
1469 return 0;
1470 }
1471
1472 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1473 {
1474 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1475 unsigned long irqflags;
1476
1477 if (!i915_pipe_enabled(dev, pipe))
1478 return -EINVAL;
1479
1480 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1481 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1482 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1483 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1484
1485 return 0;
1486 }
1487
1488 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1489 {
1490 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1491 unsigned long irqflags;
1492
1493 if (!i915_pipe_enabled(dev, pipe))
1494 return -EINVAL;
1495
1496 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1497 ironlake_enable_display_irq(dev_priv,
1498 DE_PIPEA_VBLANK_IVB << (5 * pipe));
1499 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1500
1501 return 0;
1502 }
1503
1504 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1505 {
1506 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1507 unsigned long irqflags;
1508 u32 imr;
1509
1510 if (!i915_pipe_enabled(dev, pipe))
1511 return -EINVAL;
1512
1513 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1514 imr = I915_READ(VLV_IMR);
1515 if (pipe == 0)
1516 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1517 else
1518 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1519 I915_WRITE(VLV_IMR, imr);
1520 i915_enable_pipestat(dev_priv, pipe,
1521 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1522 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1523
1524 return 0;
1525 }
1526
1527 /* Called from drm generic code, passed 'crtc' which
1528 * we use as a pipe index
1529 */
1530 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1531 {
1532 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1533 unsigned long irqflags;
1534
1535 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1536 if (dev_priv->info->gen == 3)
1537 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1538
1539 i915_disable_pipestat(dev_priv, pipe,
1540 PIPE_VBLANK_INTERRUPT_ENABLE |
1541 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1542 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1543 }
1544
1545 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1546 {
1547 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1548 unsigned long irqflags;
1549
1550 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1551 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1552 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1553 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1554 }
1555
1556 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1557 {
1558 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1559 unsigned long irqflags;
1560
1561 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1562 ironlake_disable_display_irq(dev_priv,
1563 DE_PIPEA_VBLANK_IVB << (pipe * 5));
1564 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1565 }
1566
1567 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1568 {
1569 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1570 unsigned long irqflags;
1571 u32 imr;
1572
1573 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1574 i915_disable_pipestat(dev_priv, pipe,
1575 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1576 imr = I915_READ(VLV_IMR);
1577 if (pipe == 0)
1578 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1579 else
1580 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1581 I915_WRITE(VLV_IMR, imr);
1582 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1583 }
1584
1585 static u32
1586 ring_last_seqno(struct intel_ring_buffer *ring)
1587 {
1588 return list_entry(ring->request_list.prev,
1589 struct drm_i915_gem_request, list)->seqno;
1590 }
1591
1592 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1593 {
1594 if (list_empty(&ring->request_list) ||
1595 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1596 /* Issue a wake-up to catch stuck h/w. */
1597 if (waitqueue_active(&ring->irq_queue)) {
1598 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1599 ring->name);
1600 wake_up_all(&ring->irq_queue);
1601 *err = true;
1602 }
1603 return true;
1604 }
1605 return false;
1606 }
1607
1608 static bool kick_ring(struct intel_ring_buffer *ring)
1609 {
1610 struct drm_device *dev = ring->dev;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 u32 tmp = I915_READ_CTL(ring);
1613 if (tmp & RING_WAIT) {
1614 DRM_ERROR("Kicking stuck wait on %s\n",
1615 ring->name);
1616 I915_WRITE_CTL(ring, tmp);
1617 return true;
1618 }
1619 return false;
1620 }
1621
1622 static bool i915_hangcheck_hung(struct drm_device *dev)
1623 {
1624 drm_i915_private_t *dev_priv = dev->dev_private;
1625
1626 if (dev_priv->hangcheck_count++ > 1) {
1627 bool hung = true;
1628
1629 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1630 i915_handle_error(dev, true);
1631
1632 if (!IS_GEN2(dev)) {
1633 struct intel_ring_buffer *ring;
1634 int i;
1635
1636 /* Is the chip hanging on a WAIT_FOR_EVENT?
1637 * If so we can simply poke the RB_WAIT bit
1638 * and break the hang. This should work on
1639 * all but the second generation chipsets.
1640 */
1641 for_each_ring(ring, dev_priv, i)
1642 hung &= !kick_ring(ring);
1643 }
1644
1645 return hung;
1646 }
1647
1648 return false;
1649 }
1650
1651 /**
1652 * This is called when the chip hasn't reported back with completed
1653 * batchbuffers in a long time. The first time this is called we simply record
1654 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1655 * again, we assume the chip is wedged and try to fix it.
1656 */
1657 void i915_hangcheck_elapsed(unsigned long data)
1658 {
1659 struct drm_device *dev = (struct drm_device *)data;
1660 drm_i915_private_t *dev_priv = dev->dev_private;
1661 uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1662 struct intel_ring_buffer *ring;
1663 bool err = false, idle;
1664 int i;
1665
1666 if (!i915_enable_hangcheck)
1667 return;
1668
1669 memset(acthd, 0, sizeof(acthd));
1670 idle = true;
1671 for_each_ring(ring, dev_priv, i) {
1672 idle &= i915_hangcheck_ring_idle(ring, &err);
1673 acthd[i] = intel_ring_get_active_head(ring);
1674 }
1675
1676 /* If all work is done then ACTHD clearly hasn't advanced. */
1677 if (idle) {
1678 if (err) {
1679 if (i915_hangcheck_hung(dev))
1680 return;
1681
1682 goto repeat;
1683 }
1684
1685 dev_priv->hangcheck_count = 0;
1686 return;
1687 }
1688
1689 if (INTEL_INFO(dev)->gen < 4) {
1690 instdone = I915_READ(INSTDONE);
1691 instdone1 = 0;
1692 } else {
1693 instdone = I915_READ(INSTDONE_I965);
1694 instdone1 = I915_READ(INSTDONE1);
1695 }
1696
1697 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1698 dev_priv->last_instdone == instdone &&
1699 dev_priv->last_instdone1 == instdone1) {
1700 if (i915_hangcheck_hung(dev))
1701 return;
1702 } else {
1703 dev_priv->hangcheck_count = 0;
1704
1705 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1706 dev_priv->last_instdone = instdone;
1707 dev_priv->last_instdone1 = instdone1;
1708 }
1709
1710 repeat:
1711 /* Reset timer case chip hangs without another request being added */
1712 mod_timer(&dev_priv->hangcheck_timer,
1713 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1714 }
1715
1716 /* drm_dma.h hooks
1717 */
1718 static void ironlake_irq_preinstall(struct drm_device *dev)
1719 {
1720 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1721
1722 atomic_set(&dev_priv->irq_received, 0);
1723
1724 I915_WRITE(HWSTAM, 0xeffe);
1725
1726 /* XXX hotplug from PCH */
1727
1728 I915_WRITE(DEIMR, 0xffffffff);
1729 I915_WRITE(DEIER, 0x0);
1730 POSTING_READ(DEIER);
1731
1732 /* and GT */
1733 I915_WRITE(GTIMR, 0xffffffff);
1734 I915_WRITE(GTIER, 0x0);
1735 POSTING_READ(GTIER);
1736
1737 /* south display irq */
1738 I915_WRITE(SDEIMR, 0xffffffff);
1739 I915_WRITE(SDEIER, 0x0);
1740 POSTING_READ(SDEIER);
1741 }
1742
1743 static void valleyview_irq_preinstall(struct drm_device *dev)
1744 {
1745 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1746 int pipe;
1747
1748 atomic_set(&dev_priv->irq_received, 0);
1749
1750 /* VLV magic */
1751 I915_WRITE(VLV_IMR, 0);
1752 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1753 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1754 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1755
1756 /* and GT */
1757 I915_WRITE(GTIIR, I915_READ(GTIIR));
1758 I915_WRITE(GTIIR, I915_READ(GTIIR));
1759 I915_WRITE(GTIMR, 0xffffffff);
1760 I915_WRITE(GTIER, 0x0);
1761 POSTING_READ(GTIER);
1762
1763 I915_WRITE(DPINVGTT, 0xff);
1764
1765 I915_WRITE(PORT_HOTPLUG_EN, 0);
1766 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1767 for_each_pipe(pipe)
1768 I915_WRITE(PIPESTAT(pipe), 0xffff);
1769 I915_WRITE(VLV_IIR, 0xffffffff);
1770 I915_WRITE(VLV_IMR, 0xffffffff);
1771 I915_WRITE(VLV_IER, 0x0);
1772 POSTING_READ(VLV_IER);
1773 }
1774
1775 /*
1776 * Enable digital hotplug on the PCH, and configure the DP short pulse
1777 * duration to 2ms (which is the minimum in the Display Port spec)
1778 *
1779 * This register is the same on all known PCH chips.
1780 */
1781
1782 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1783 {
1784 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1785 u32 hotplug;
1786
1787 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1788 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1789 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1790 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1791 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1792 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1793 }
1794
1795 static int ironlake_irq_postinstall(struct drm_device *dev)
1796 {
1797 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1798 /* enable kind of interrupts always enabled */
1799 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1800 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1801 u32 render_irqs;
1802 u32 hotplug_mask;
1803
1804 dev_priv->irq_mask = ~display_mask;
1805
1806 /* should always can generate irq */
1807 I915_WRITE(DEIIR, I915_READ(DEIIR));
1808 I915_WRITE(DEIMR, dev_priv->irq_mask);
1809 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1810 POSTING_READ(DEIER);
1811
1812 dev_priv->gt_irq_mask = ~0;
1813
1814 I915_WRITE(GTIIR, I915_READ(GTIIR));
1815 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1816
1817 if (IS_GEN6(dev))
1818 render_irqs =
1819 GT_USER_INTERRUPT |
1820 GEN6_BSD_USER_INTERRUPT |
1821 GEN6_BLITTER_USER_INTERRUPT;
1822 else
1823 render_irqs =
1824 GT_USER_INTERRUPT |
1825 GT_PIPE_NOTIFY |
1826 GT_BSD_USER_INTERRUPT;
1827 I915_WRITE(GTIER, render_irqs);
1828 POSTING_READ(GTIER);
1829
1830 if (HAS_PCH_CPT(dev)) {
1831 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1832 SDE_PORTB_HOTPLUG_CPT |
1833 SDE_PORTC_HOTPLUG_CPT |
1834 SDE_PORTD_HOTPLUG_CPT);
1835 } else {
1836 hotplug_mask = (SDE_CRT_HOTPLUG |
1837 SDE_PORTB_HOTPLUG |
1838 SDE_PORTC_HOTPLUG |
1839 SDE_PORTD_HOTPLUG |
1840 SDE_AUX_MASK);
1841 }
1842
1843 dev_priv->pch_irq_mask = ~hotplug_mask;
1844
1845 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1846 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1847 I915_WRITE(SDEIER, hotplug_mask);
1848 POSTING_READ(SDEIER);
1849
1850 ironlake_enable_pch_hotplug(dev);
1851
1852 if (IS_IRONLAKE_M(dev)) {
1853 /* Clear & enable PCU event interrupts */
1854 I915_WRITE(DEIIR, DE_PCU_EVENT);
1855 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1856 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1857 }
1858
1859 return 0;
1860 }
1861
1862 static int ivybridge_irq_postinstall(struct drm_device *dev)
1863 {
1864 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1865 /* enable kind of interrupts always enabled */
1866 u32 display_mask =
1867 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1868 DE_PLANEC_FLIP_DONE_IVB |
1869 DE_PLANEB_FLIP_DONE_IVB |
1870 DE_PLANEA_FLIP_DONE_IVB;
1871 u32 render_irqs;
1872 u32 hotplug_mask;
1873
1874 dev_priv->irq_mask = ~display_mask;
1875
1876 /* should always can generate irq */
1877 I915_WRITE(DEIIR, I915_READ(DEIIR));
1878 I915_WRITE(DEIMR, dev_priv->irq_mask);
1879 I915_WRITE(DEIER,
1880 display_mask |
1881 DE_PIPEC_VBLANK_IVB |
1882 DE_PIPEB_VBLANK_IVB |
1883 DE_PIPEA_VBLANK_IVB);
1884 POSTING_READ(DEIER);
1885
1886 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1887
1888 I915_WRITE(GTIIR, I915_READ(GTIIR));
1889 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1890
1891 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1892 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1893 I915_WRITE(GTIER, render_irqs);
1894 POSTING_READ(GTIER);
1895
1896 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1897 SDE_PORTB_HOTPLUG_CPT |
1898 SDE_PORTC_HOTPLUG_CPT |
1899 SDE_PORTD_HOTPLUG_CPT);
1900 dev_priv->pch_irq_mask = ~hotplug_mask;
1901
1902 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1903 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1904 I915_WRITE(SDEIER, hotplug_mask);
1905 POSTING_READ(SDEIER);
1906
1907 ironlake_enable_pch_hotplug(dev);
1908
1909 return 0;
1910 }
1911
1912 static int valleyview_irq_postinstall(struct drm_device *dev)
1913 {
1914 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1915 u32 enable_mask;
1916 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1917 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
1918 u16 msid;
1919
1920 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1921 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1922 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1923 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1924 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1925
1926 /*
1927 *Leave vblank interrupts masked initially. enable/disable will
1928 * toggle them based on usage.
1929 */
1930 dev_priv->irq_mask = (~enable_mask) |
1931 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1932 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1933
1934 dev_priv->pipestat[0] = 0;
1935 dev_priv->pipestat[1] = 0;
1936
1937 /* Hack for broken MSIs on VLV */
1938 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1939 pci_read_config_word(dev->pdev, 0x98, &msid);
1940 msid &= 0xff; /* mask out delivery bits */
1941 msid |= (1<<14);
1942 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1943
1944 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1945 I915_WRITE(VLV_IER, enable_mask);
1946 I915_WRITE(VLV_IIR, 0xffffffff);
1947 I915_WRITE(PIPESTAT(0), 0xffff);
1948 I915_WRITE(PIPESTAT(1), 0xffff);
1949 POSTING_READ(VLV_IER);
1950
1951 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1952 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1953
1954 I915_WRITE(VLV_IIR, 0xffffffff);
1955 I915_WRITE(VLV_IIR, 0xffffffff);
1956
1957 dev_priv->gt_irq_mask = ~0;
1958
1959 I915_WRITE(GTIIR, I915_READ(GTIIR));
1960 I915_WRITE(GTIIR, I915_READ(GTIIR));
1961 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1962 I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1963 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1964 GT_GEN6_BLT_USER_INTERRUPT |
1965 GT_GEN6_BSD_USER_INTERRUPT |
1966 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1967 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1968 GT_PIPE_NOTIFY |
1969 GT_RENDER_CS_ERROR_INTERRUPT |
1970 GT_SYNC_STATUS |
1971 GT_USER_INTERRUPT);
1972 POSTING_READ(GTIER);
1973
1974 /* ack & enable invalid PTE error interrupts */
1975 #if 0 /* FIXME: add support to irq handler for checking these bits */
1976 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1977 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1978 #endif
1979
1980 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1981 #if 0 /* FIXME: check register definitions; some have moved */
1982 /* Note HDMI and DP share bits */
1983 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1984 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1985 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1986 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1987 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1988 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1989 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1990 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1991 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1992 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1993 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1994 hotplug_en |= CRT_HOTPLUG_INT_EN;
1995 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1996 }
1997 #endif
1998
1999 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2000
2001 return 0;
2002 }
2003
2004 static void valleyview_irq_uninstall(struct drm_device *dev)
2005 {
2006 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2007 int pipe;
2008
2009 if (!dev_priv)
2010 return;
2011
2012 for_each_pipe(pipe)
2013 I915_WRITE(PIPESTAT(pipe), 0xffff);
2014
2015 I915_WRITE(HWSTAM, 0xffffffff);
2016 I915_WRITE(PORT_HOTPLUG_EN, 0);
2017 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2018 for_each_pipe(pipe)
2019 I915_WRITE(PIPESTAT(pipe), 0xffff);
2020 I915_WRITE(VLV_IIR, 0xffffffff);
2021 I915_WRITE(VLV_IMR, 0xffffffff);
2022 I915_WRITE(VLV_IER, 0x0);
2023 POSTING_READ(VLV_IER);
2024 }
2025
2026 static void ironlake_irq_uninstall(struct drm_device *dev)
2027 {
2028 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2029
2030 if (!dev_priv)
2031 return;
2032
2033 I915_WRITE(HWSTAM, 0xffffffff);
2034
2035 I915_WRITE(DEIMR, 0xffffffff);
2036 I915_WRITE(DEIER, 0x0);
2037 I915_WRITE(DEIIR, I915_READ(DEIIR));
2038
2039 I915_WRITE(GTIMR, 0xffffffff);
2040 I915_WRITE(GTIER, 0x0);
2041 I915_WRITE(GTIIR, I915_READ(GTIIR));
2042
2043 I915_WRITE(SDEIMR, 0xffffffff);
2044 I915_WRITE(SDEIER, 0x0);
2045 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2046 }
2047
2048 static void i8xx_irq_preinstall(struct drm_device * dev)
2049 {
2050 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2051 int pipe;
2052
2053 atomic_set(&dev_priv->irq_received, 0);
2054
2055 for_each_pipe(pipe)
2056 I915_WRITE(PIPESTAT(pipe), 0);
2057 I915_WRITE16(IMR, 0xffff);
2058 I915_WRITE16(IER, 0x0);
2059 POSTING_READ16(IER);
2060 }
2061
2062 static int i8xx_irq_postinstall(struct drm_device *dev)
2063 {
2064 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2065
2066 dev_priv->pipestat[0] = 0;
2067 dev_priv->pipestat[1] = 0;
2068
2069 I915_WRITE16(EMR,
2070 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2071
2072 /* Unmask the interrupts that we always want on. */
2073 dev_priv->irq_mask =
2074 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2075 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2076 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2077 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2078 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2079 I915_WRITE16(IMR, dev_priv->irq_mask);
2080
2081 I915_WRITE16(IER,
2082 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2083 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2084 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2085 I915_USER_INTERRUPT);
2086 POSTING_READ16(IER);
2087
2088 return 0;
2089 }
2090
2091 static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2092 {
2093 struct drm_device *dev = (struct drm_device *) arg;
2094 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2095 u16 iir, new_iir;
2096 u32 pipe_stats[2];
2097 unsigned long irqflags;
2098 int irq_received;
2099 int pipe;
2100 u16 flip_mask =
2101 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2102 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2103
2104 atomic_inc(&dev_priv->irq_received);
2105
2106 iir = I915_READ16(IIR);
2107 if (iir == 0)
2108 return IRQ_NONE;
2109
2110 while (iir & ~flip_mask) {
2111 /* Can't rely on pipestat interrupt bit in iir as it might
2112 * have been cleared after the pipestat interrupt was received.
2113 * It doesn't set the bit in iir again, but it still produces
2114 * interrupts (for non-MSI).
2115 */
2116 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2117 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2118 i915_handle_error(dev, false);
2119
2120 for_each_pipe(pipe) {
2121 int reg = PIPESTAT(pipe);
2122 pipe_stats[pipe] = I915_READ(reg);
2123
2124 /*
2125 * Clear the PIPE*STAT regs before the IIR
2126 */
2127 if (pipe_stats[pipe] & 0x8000ffff) {
2128 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2129 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2130 pipe_name(pipe));
2131 I915_WRITE(reg, pipe_stats[pipe]);
2132 irq_received = 1;
2133 }
2134 }
2135 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2136
2137 I915_WRITE16(IIR, iir & ~flip_mask);
2138 new_iir = I915_READ16(IIR); /* Flush posted writes */
2139
2140 i915_update_dri1_breadcrumb(dev);
2141
2142 if (iir & I915_USER_INTERRUPT)
2143 notify_ring(dev, &dev_priv->ring[RCS]);
2144
2145 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2146 drm_handle_vblank(dev, 0)) {
2147 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2148 intel_prepare_page_flip(dev, 0);
2149 intel_finish_page_flip(dev, 0);
2150 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2151 }
2152 }
2153
2154 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2155 drm_handle_vblank(dev, 1)) {
2156 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2157 intel_prepare_page_flip(dev, 1);
2158 intel_finish_page_flip(dev, 1);
2159 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2160 }
2161 }
2162
2163 iir = new_iir;
2164 }
2165
2166 return IRQ_HANDLED;
2167 }
2168
2169 static void i8xx_irq_uninstall(struct drm_device * dev)
2170 {
2171 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2172 int pipe;
2173
2174 for_each_pipe(pipe) {
2175 /* Clear enable bits; then clear status bits */
2176 I915_WRITE(PIPESTAT(pipe), 0);
2177 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2178 }
2179 I915_WRITE16(IMR, 0xffff);
2180 I915_WRITE16(IER, 0x0);
2181 I915_WRITE16(IIR, I915_READ16(IIR));
2182 }
2183
2184 static void i915_irq_preinstall(struct drm_device * dev)
2185 {
2186 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2187 int pipe;
2188
2189 atomic_set(&dev_priv->irq_received, 0);
2190
2191 if (I915_HAS_HOTPLUG(dev)) {
2192 I915_WRITE(PORT_HOTPLUG_EN, 0);
2193 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2194 }
2195
2196 I915_WRITE16(HWSTAM, 0xeffe);
2197 for_each_pipe(pipe)
2198 I915_WRITE(PIPESTAT(pipe), 0);
2199 I915_WRITE(IMR, 0xffffffff);
2200 I915_WRITE(IER, 0x0);
2201 POSTING_READ(IER);
2202 }
2203
2204 static int i915_irq_postinstall(struct drm_device *dev)
2205 {
2206 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2207 u32 enable_mask;
2208
2209 dev_priv->pipestat[0] = 0;
2210 dev_priv->pipestat[1] = 0;
2211
2212 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2213
2214 /* Unmask the interrupts that we always want on. */
2215 dev_priv->irq_mask =
2216 ~(I915_ASLE_INTERRUPT |
2217 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2218 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2219 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2220 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2221 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2222
2223 enable_mask =
2224 I915_ASLE_INTERRUPT |
2225 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2226 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2227 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2228 I915_USER_INTERRUPT;
2229
2230 if (I915_HAS_HOTPLUG(dev)) {
2231 /* Enable in IER... */
2232 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2233 /* and unmask in IMR */
2234 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2235 }
2236
2237 I915_WRITE(IMR, dev_priv->irq_mask);
2238 I915_WRITE(IER, enable_mask);
2239 POSTING_READ(IER);
2240
2241 if (I915_HAS_HOTPLUG(dev)) {
2242 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2243
2244 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2245 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2246 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2247 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2248 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2249 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2250 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2251 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2252 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2253 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2254 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2255 hotplug_en |= CRT_HOTPLUG_INT_EN;
2256 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2257 }
2258
2259 /* Ignore TV since it's buggy */
2260
2261 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2262 }
2263
2264 intel_opregion_enable_asle(dev);
2265
2266 return 0;
2267 }
2268
2269 static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2270 {
2271 struct drm_device *dev = (struct drm_device *) arg;
2272 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2273 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2274 unsigned long irqflags;
2275 u32 flip_mask =
2276 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2277 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2278 u32 flip[2] = {
2279 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2280 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2281 };
2282 int pipe, ret = IRQ_NONE;
2283
2284 atomic_inc(&dev_priv->irq_received);
2285
2286 iir = I915_READ(IIR);
2287 do {
2288 bool irq_received = (iir & ~flip_mask) != 0;
2289 bool blc_event = false;
2290
2291 /* Can't rely on pipestat interrupt bit in iir as it might
2292 * have been cleared after the pipestat interrupt was received.
2293 * It doesn't set the bit in iir again, but it still produces
2294 * interrupts (for non-MSI).
2295 */
2296 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2297 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2298 i915_handle_error(dev, false);
2299
2300 for_each_pipe(pipe) {
2301 int reg = PIPESTAT(pipe);
2302 pipe_stats[pipe] = I915_READ(reg);
2303
2304 /* Clear the PIPE*STAT regs before the IIR */
2305 if (pipe_stats[pipe] & 0x8000ffff) {
2306 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2307 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2308 pipe_name(pipe));
2309 I915_WRITE(reg, pipe_stats[pipe]);
2310 irq_received = true;
2311 }
2312 }
2313 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2314
2315 if (!irq_received)
2316 break;
2317
2318 /* Consume port. Then clear IIR or we'll miss events */
2319 if ((I915_HAS_HOTPLUG(dev)) &&
2320 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2321 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2322
2323 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2324 hotplug_status);
2325 if (hotplug_status & dev_priv->hotplug_supported_mask)
2326 queue_work(dev_priv->wq,
2327 &dev_priv->hotplug_work);
2328
2329 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2330 POSTING_READ(PORT_HOTPLUG_STAT);
2331 }
2332
2333 I915_WRITE(IIR, iir & ~flip_mask);
2334 new_iir = I915_READ(IIR); /* Flush posted writes */
2335
2336 if (iir & I915_USER_INTERRUPT)
2337 notify_ring(dev, &dev_priv->ring[RCS]);
2338
2339 for_each_pipe(pipe) {
2340 int plane = pipe;
2341 if (IS_MOBILE(dev))
2342 plane = !plane;
2343 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2344 drm_handle_vblank(dev, pipe)) {
2345 if (iir & flip[plane]) {
2346 intel_prepare_page_flip(dev, plane);
2347 intel_finish_page_flip(dev, pipe);
2348 flip_mask &= ~flip[plane];
2349 }
2350 }
2351
2352 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2353 blc_event = true;
2354 }
2355
2356 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2357 intel_opregion_asle_intr(dev);
2358
2359 /* With MSI, interrupts are only generated when iir
2360 * transitions from zero to nonzero. If another bit got
2361 * set while we were handling the existing iir bits, then
2362 * we would never get another interrupt.
2363 *
2364 * This is fine on non-MSI as well, as if we hit this path
2365 * we avoid exiting the interrupt handler only to generate
2366 * another one.
2367 *
2368 * Note that for MSI this could cause a stray interrupt report
2369 * if an interrupt landed in the time between writing IIR and
2370 * the posting read. This should be rare enough to never
2371 * trigger the 99% of 100,000 interrupts test for disabling
2372 * stray interrupts.
2373 */
2374 ret = IRQ_HANDLED;
2375 iir = new_iir;
2376 } while (iir & ~flip_mask);
2377
2378 i915_update_dri1_breadcrumb(dev);
2379
2380 return ret;
2381 }
2382
2383 static void i915_irq_uninstall(struct drm_device * dev)
2384 {
2385 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2386 int pipe;
2387
2388 if (I915_HAS_HOTPLUG(dev)) {
2389 I915_WRITE(PORT_HOTPLUG_EN, 0);
2390 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2391 }
2392
2393 I915_WRITE16(HWSTAM, 0xffff);
2394 for_each_pipe(pipe) {
2395 /* Clear enable bits; then clear status bits */
2396 I915_WRITE(PIPESTAT(pipe), 0);
2397 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2398 }
2399 I915_WRITE(IMR, 0xffffffff);
2400 I915_WRITE(IER, 0x0);
2401
2402 I915_WRITE(IIR, I915_READ(IIR));
2403 }
2404
2405 static void i965_irq_preinstall(struct drm_device * dev)
2406 {
2407 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2408 int pipe;
2409
2410 atomic_set(&dev_priv->irq_received, 0);
2411
2412 I915_WRITE(PORT_HOTPLUG_EN, 0);
2413 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2414
2415 I915_WRITE(HWSTAM, 0xeffe);
2416 for_each_pipe(pipe)
2417 I915_WRITE(PIPESTAT(pipe), 0);
2418 I915_WRITE(IMR, 0xffffffff);
2419 I915_WRITE(IER, 0x0);
2420 POSTING_READ(IER);
2421 }
2422
2423 static int i965_irq_postinstall(struct drm_device *dev)
2424 {
2425 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2426 u32 hotplug_en;
2427 u32 enable_mask;
2428 u32 error_mask;
2429
2430 /* Unmask the interrupts that we always want on. */
2431 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2432 I915_DISPLAY_PORT_INTERRUPT |
2433 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2434 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2435 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2436 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2437 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2438
2439 enable_mask = ~dev_priv->irq_mask;
2440 enable_mask |= I915_USER_INTERRUPT;
2441
2442 if (IS_G4X(dev))
2443 enable_mask |= I915_BSD_USER_INTERRUPT;
2444
2445 dev_priv->pipestat[0] = 0;
2446 dev_priv->pipestat[1] = 0;
2447
2448 /*
2449 * Enable some error detection, note the instruction error mask
2450 * bit is reserved, so we leave it masked.
2451 */
2452 if (IS_G4X(dev)) {
2453 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2454 GM45_ERROR_MEM_PRIV |
2455 GM45_ERROR_CP_PRIV |
2456 I915_ERROR_MEMORY_REFRESH);
2457 } else {
2458 error_mask = ~(I915_ERROR_PAGE_TABLE |
2459 I915_ERROR_MEMORY_REFRESH);
2460 }
2461 I915_WRITE(EMR, error_mask);
2462
2463 I915_WRITE(IMR, dev_priv->irq_mask);
2464 I915_WRITE(IER, enable_mask);
2465 POSTING_READ(IER);
2466
2467 /* Note HDMI and DP share hotplug bits */
2468 hotplug_en = 0;
2469 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2470 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2471 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2472 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2473 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2474 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2475 if (IS_G4X(dev)) {
2476 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2477 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2478 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2479 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2480 } else {
2481 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2482 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2483 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2484 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2485 }
2486 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2487 hotplug_en |= CRT_HOTPLUG_INT_EN;
2488
2489 /* Programming the CRT detection parameters tends
2490 to generate a spurious hotplug event about three
2491 seconds later. So just do it once.
2492 */
2493 if (IS_G4X(dev))
2494 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2495 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2496 }
2497
2498 /* Ignore TV since it's buggy */
2499
2500 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2501
2502 intel_opregion_enable_asle(dev);
2503
2504 return 0;
2505 }
2506
2507 static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2508 {
2509 struct drm_device *dev = (struct drm_device *) arg;
2510 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2511 u32 iir, new_iir;
2512 u32 pipe_stats[I915_MAX_PIPES];
2513 unsigned long irqflags;
2514 int irq_received;
2515 int ret = IRQ_NONE, pipe;
2516
2517 atomic_inc(&dev_priv->irq_received);
2518
2519 iir = I915_READ(IIR);
2520
2521 for (;;) {
2522 bool blc_event = false;
2523
2524 irq_received = iir != 0;
2525
2526 /* Can't rely on pipestat interrupt bit in iir as it might
2527 * have been cleared after the pipestat interrupt was received.
2528 * It doesn't set the bit in iir again, but it still produces
2529 * interrupts (for non-MSI).
2530 */
2531 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2532 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2533 i915_handle_error(dev, false);
2534
2535 for_each_pipe(pipe) {
2536 int reg = PIPESTAT(pipe);
2537 pipe_stats[pipe] = I915_READ(reg);
2538
2539 /*
2540 * Clear the PIPE*STAT regs before the IIR
2541 */
2542 if (pipe_stats[pipe] & 0x8000ffff) {
2543 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2544 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2545 pipe_name(pipe));
2546 I915_WRITE(reg, pipe_stats[pipe]);
2547 irq_received = 1;
2548 }
2549 }
2550 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2551
2552 if (!irq_received)
2553 break;
2554
2555 ret = IRQ_HANDLED;
2556
2557 /* Consume port. Then clear IIR or we'll miss events */
2558 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2559 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2560
2561 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2562 hotplug_status);
2563 if (hotplug_status & dev_priv->hotplug_supported_mask)
2564 queue_work(dev_priv->wq,
2565 &dev_priv->hotplug_work);
2566
2567 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2568 I915_READ(PORT_HOTPLUG_STAT);
2569 }
2570
2571 I915_WRITE(IIR, iir);
2572 new_iir = I915_READ(IIR); /* Flush posted writes */
2573
2574 if (iir & I915_USER_INTERRUPT)
2575 notify_ring(dev, &dev_priv->ring[RCS]);
2576 if (iir & I915_BSD_USER_INTERRUPT)
2577 notify_ring(dev, &dev_priv->ring[VCS]);
2578
2579 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2580 intel_prepare_page_flip(dev, 0);
2581
2582 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2583 intel_prepare_page_flip(dev, 1);
2584
2585 for_each_pipe(pipe) {
2586 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2587 drm_handle_vblank(dev, pipe)) {
2588 i915_pageflip_stall_check(dev, pipe);
2589 intel_finish_page_flip(dev, pipe);
2590 }
2591
2592 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2593 blc_event = true;
2594 }
2595
2596
2597 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2598 intel_opregion_asle_intr(dev);
2599
2600 /* With MSI, interrupts are only generated when iir
2601 * transitions from zero to nonzero. If another bit got
2602 * set while we were handling the existing iir bits, then
2603 * we would never get another interrupt.
2604 *
2605 * This is fine on non-MSI as well, as if we hit this path
2606 * we avoid exiting the interrupt handler only to generate
2607 * another one.
2608 *
2609 * Note that for MSI this could cause a stray interrupt report
2610 * if an interrupt landed in the time between writing IIR and
2611 * the posting read. This should be rare enough to never
2612 * trigger the 99% of 100,000 interrupts test for disabling
2613 * stray interrupts.
2614 */
2615 iir = new_iir;
2616 }
2617
2618 i915_update_dri1_breadcrumb(dev);
2619
2620 return ret;
2621 }
2622
2623 static void i965_irq_uninstall(struct drm_device * dev)
2624 {
2625 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2626 int pipe;
2627
2628 if (!dev_priv)
2629 return;
2630
2631 I915_WRITE(PORT_HOTPLUG_EN, 0);
2632 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2633
2634 I915_WRITE(HWSTAM, 0xffffffff);
2635 for_each_pipe(pipe)
2636 I915_WRITE(PIPESTAT(pipe), 0);
2637 I915_WRITE(IMR, 0xffffffff);
2638 I915_WRITE(IER, 0x0);
2639
2640 for_each_pipe(pipe)
2641 I915_WRITE(PIPESTAT(pipe),
2642 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2643 I915_WRITE(IIR, I915_READ(IIR));
2644 }
2645
2646 void intel_irq_init(struct drm_device *dev)
2647 {
2648 struct drm_i915_private *dev_priv = dev->dev_private;
2649
2650 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2651 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2652 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2653 INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
2654
2655 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2656 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2657 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2658 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2659 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2660 }
2661
2662 if (drm_core_check_feature(dev, DRIVER_MODESET))
2663 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2664 else
2665 dev->driver->get_vblank_timestamp = NULL;
2666 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2667
2668 if (IS_VALLEYVIEW(dev)) {
2669 dev->driver->irq_handler = valleyview_irq_handler;
2670 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2671 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2672 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2673 dev->driver->enable_vblank = valleyview_enable_vblank;
2674 dev->driver->disable_vblank = valleyview_disable_vblank;
2675 } else if (IS_IVYBRIDGE(dev)) {
2676 /* Share pre & uninstall handlers with ILK/SNB */
2677 dev->driver->irq_handler = ivybridge_irq_handler;
2678 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2679 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2680 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2681 dev->driver->enable_vblank = ivybridge_enable_vblank;
2682 dev->driver->disable_vblank = ivybridge_disable_vblank;
2683 } else if (IS_HASWELL(dev)) {
2684 /* Share interrupts handling with IVB */
2685 dev->driver->irq_handler = ivybridge_irq_handler;
2686 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2687 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2688 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2689 dev->driver->enable_vblank = ivybridge_enable_vblank;
2690 dev->driver->disable_vblank = ivybridge_disable_vblank;
2691 } else if (HAS_PCH_SPLIT(dev)) {
2692 dev->driver->irq_handler = ironlake_irq_handler;
2693 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2694 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2695 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2696 dev->driver->enable_vblank = ironlake_enable_vblank;
2697 dev->driver->disable_vblank = ironlake_disable_vblank;
2698 } else {
2699 if (INTEL_INFO(dev)->gen == 2) {
2700 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2701 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2702 dev->driver->irq_handler = i8xx_irq_handler;
2703 dev->driver->irq_uninstall = i8xx_irq_uninstall;
2704 } else if (INTEL_INFO(dev)->gen == 3) {
2705 /* IIR "flip pending" means done if this bit is set */
2706 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2707
2708 dev->driver->irq_preinstall = i915_irq_preinstall;
2709 dev->driver->irq_postinstall = i915_irq_postinstall;
2710 dev->driver->irq_uninstall = i915_irq_uninstall;
2711 dev->driver->irq_handler = i915_irq_handler;
2712 } else {
2713 dev->driver->irq_preinstall = i965_irq_preinstall;
2714 dev->driver->irq_postinstall = i965_irq_postinstall;
2715 dev->driver->irq_uninstall = i965_irq_uninstall;
2716 dev->driver->irq_handler = i965_irq_handler;
2717 }
2718 dev->driver->enable_vblank = i915_enable_vblank;
2719 dev->driver->disable_vblank = i915_disable_vblank;
2720 }
2721 }
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