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ethernet/broadcom: use core min/max MTU checking
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
bloba042da1ff4b90e9aae4f76db71c99c2c4da321d3
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10 #include <linux/module.h>
11
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
26 #include <linux/io.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
30 #include <asm/page.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
33 #include <linux/if.h>
34 #include <linux/if_vlan.h>
35 #include <linux/rtc.h>
36 #include <net/ip.h>
37 #include <net/tcp.h>
38 #include <net/udp.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <net/udp_tunnel.h>
42 #ifdef CONFIG_NET_RX_BUSY_POLL
43 #include <net/busy_poll.h>
44 #endif
45 #include <linux/workqueue.h>
46 #include <linux/prefetch.h>
47 #include <linux/cache.h>
48 #include <linux/log2.h>
49 #include <linux/aer.h>
50 #include <linux/bitmap.h>
51 #include <linux/cpu_rmap.h>
52
53 #include "bnxt_hsi.h"
54 #include "bnxt.h"
55 #include "bnxt_sriov.h"
56 #include "bnxt_ethtool.h"
57
58 #define BNXT_TX_TIMEOUT (5 * HZ)
59
60 static const char version[] =
61 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
62
63 MODULE_LICENSE("GPL");
64 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
65 MODULE_VERSION(DRV_MODULE_VERSION);
66
67 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
68 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
69 #define BNXT_RX_COPY_THRESH 256
70
71 #define BNXT_TX_PUSH_THRESH 164
72
73 enum board_idx {
74 BCM57301,
75 BCM57302,
76 BCM57304,
77 BCM57417_NPAR,
78 BCM58700,
79 BCM57311,
80 BCM57312,
81 BCM57402,
82 BCM57404,
83 BCM57406,
84 BCM57402_NPAR,
85 BCM57407,
86 BCM57412,
87 BCM57414,
88 BCM57416,
89 BCM57417,
90 BCM57412_NPAR,
91 BCM57314,
92 BCM57417_SFP,
93 BCM57416_SFP,
94 BCM57404_NPAR,
95 BCM57406_NPAR,
96 BCM57407_SFP,
97 BCM57407_NPAR,
98 BCM57414_NPAR,
99 BCM57416_NPAR,
100 NETXTREME_E_VF,
101 NETXTREME_C_VF,
102 };
103
104 /* indexed by enum above */
105 static const struct {
106 char *name;
107 } board_info[] = {
108 { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
109 { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
110 { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
111 { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
112 { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
113 { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
114 { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
115 { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
116 { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
117 { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
118 { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
119 { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
120 { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
121 { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
122 { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
123 { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
124 { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
125 { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
126 { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
127 { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
128 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
129 { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
130 { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
131 { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
132 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
133 { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
134 { "Broadcom NetXtreme-E Ethernet Virtual Function" },
135 { "Broadcom NetXtreme-C Ethernet Virtual Function" },
136 };
137
138 static const struct pci_device_id bnxt_pci_tbl[] = {
139 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
140 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
141 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
142 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
143 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
144 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
145 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
146 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
147 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
148 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
149 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
150 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
151 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
152 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
153 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
154 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
155 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
156 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
157 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
158 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
159 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
160 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
161 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
162 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
163 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
164 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
165 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
166 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
167 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
168 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
169 #ifdef CONFIG_BNXT_SRIOV
170 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
171 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
172 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
173 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
174 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
175 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
176 #endif
177 { 0 }
178 };
179
180 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
181
182 static const u16 bnxt_vf_req_snif[] = {
183 HWRM_FUNC_CFG,
184 HWRM_PORT_PHY_QCFG,
185 HWRM_CFA_L2_FILTER_ALLOC,
186 };
187
188 static const u16 bnxt_async_events_arr[] = {
189 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
190 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
191 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
192 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
193 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
194 };
195
196 static bool bnxt_vf_pciid(enum board_idx idx)
197 {
198 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
199 }
200
201 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
202 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
203 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
204
205 #define BNXT_CP_DB_REARM(db, raw_cons) \
206 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
207
208 #define BNXT_CP_DB(db, raw_cons) \
209 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
210
211 #define BNXT_CP_DB_IRQ_DIS(db) \
212 writel(DB_CP_IRQ_DIS_FLAGS, db)
213
214 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
215 {
216 /* Tell compiler to fetch tx indices from memory. */
217 barrier();
218
219 return bp->tx_ring_size -
220 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
221 }
222
223 static const u16 bnxt_lhint_arr[] = {
224 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
225 TX_BD_FLAGS_LHINT_512_TO_1023,
226 TX_BD_FLAGS_LHINT_1024_TO_2047,
227 TX_BD_FLAGS_LHINT_1024_TO_2047,
228 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
229 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
230 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
231 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
232 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
233 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
234 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
235 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
236 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
237 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
238 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
239 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
240 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
241 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
242 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
243 };
244
245 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
246 {
247 struct bnxt *bp = netdev_priv(dev);
248 struct tx_bd *txbd;
249 struct tx_bd_ext *txbd1;
250 struct netdev_queue *txq;
251 int i;
252 dma_addr_t mapping;
253 unsigned int length, pad = 0;
254 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
255 u16 prod, last_frag;
256 struct pci_dev *pdev = bp->pdev;
257 struct bnxt_tx_ring_info *txr;
258 struct bnxt_sw_tx_bd *tx_buf;
259
260 i = skb_get_queue_mapping(skb);
261 if (unlikely(i >= bp->tx_nr_rings)) {
262 dev_kfree_skb_any(skb);
263 return NETDEV_TX_OK;
264 }
265
266 txr = &bp->tx_ring[i];
267 txq = netdev_get_tx_queue(dev, i);
268 prod = txr->tx_prod;
269
270 free_size = bnxt_tx_avail(bp, txr);
271 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
272 netif_tx_stop_queue(txq);
273 return NETDEV_TX_BUSY;
274 }
275
276 length = skb->len;
277 len = skb_headlen(skb);
278 last_frag = skb_shinfo(skb)->nr_frags;
279
280 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
281
282 txbd->tx_bd_opaque = prod;
283
284 tx_buf = &txr->tx_buf_ring[prod];
285 tx_buf->skb = skb;
286 tx_buf->nr_frags = last_frag;
287
288 vlan_tag_flags = 0;
289 cfa_action = 0;
290 if (skb_vlan_tag_present(skb)) {
291 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
292 skb_vlan_tag_get(skb);
293 /* Currently supports 8021Q, 8021AD vlan offloads
294 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
295 */
296 if (skb->vlan_proto == htons(ETH_P_8021Q))
297 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
298 }
299
300 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
301 struct tx_push_buffer *tx_push_buf = txr->tx_push;
302 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
303 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
304 void *pdata = tx_push_buf->data;
305 u64 *end;
306 int j, push_len;
307
308 /* Set COAL_NOW to be ready quickly for the next push */
309 tx_push->tx_bd_len_flags_type =
310 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
311 TX_BD_TYPE_LONG_TX_BD |
312 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
313 TX_BD_FLAGS_COAL_NOW |
314 TX_BD_FLAGS_PACKET_END |
315 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
316
317 if (skb->ip_summed == CHECKSUM_PARTIAL)
318 tx_push1->tx_bd_hsize_lflags =
319 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
320 else
321 tx_push1->tx_bd_hsize_lflags = 0;
322
323 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
324 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
325
326 end = pdata + length;
327 end = PTR_ALIGN(end, 8) - 1;
328 *end = 0;
329
330 skb_copy_from_linear_data(skb, pdata, len);
331 pdata += len;
332 for (j = 0; j < last_frag; j++) {
333 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
334 void *fptr;
335
336 fptr = skb_frag_address_safe(frag);
337 if (!fptr)
338 goto normal_tx;
339
340 memcpy(pdata, fptr, skb_frag_size(frag));
341 pdata += skb_frag_size(frag);
342 }
343
344 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
345 txbd->tx_bd_haddr = txr->data_mapping;
346 prod = NEXT_TX(prod);
347 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
348 memcpy(txbd, tx_push1, sizeof(*txbd));
349 prod = NEXT_TX(prod);
350 tx_push->doorbell =
351 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
352 txr->tx_prod = prod;
353
354 tx_buf->is_push = 1;
355 netdev_tx_sent_queue(txq, skb->len);
356 wmb(); /* Sync is_push and byte queue before pushing data */
357
358 push_len = (length + sizeof(*tx_push) + 7) / 8;
359 if (push_len > 16) {
360 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
361 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
362 (push_len - 16) << 1);
363 } else {
364 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
365 push_len);
366 }
367
368 goto tx_done;
369 }
370
371 normal_tx:
372 if (length < BNXT_MIN_PKT_SIZE) {
373 pad = BNXT_MIN_PKT_SIZE - length;
374 if (skb_pad(skb, pad)) {
375 /* SKB already freed. */
376 tx_buf->skb = NULL;
377 return NETDEV_TX_OK;
378 }
379 length = BNXT_MIN_PKT_SIZE;
380 }
381
382 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
383
384 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
385 dev_kfree_skb_any(skb);
386 tx_buf->skb = NULL;
387 return NETDEV_TX_OK;
388 }
389
390 dma_unmap_addr_set(tx_buf, mapping, mapping);
391 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
392 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
393
394 txbd->tx_bd_haddr = cpu_to_le64(mapping);
395
396 prod = NEXT_TX(prod);
397 txbd1 = (struct tx_bd_ext *)
398 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
399
400 txbd1->tx_bd_hsize_lflags = 0;
401 if (skb_is_gso(skb)) {
402 u32 hdr_len;
403
404 if (skb->encapsulation)
405 hdr_len = skb_inner_network_offset(skb) +
406 skb_inner_network_header_len(skb) +
407 inner_tcp_hdrlen(skb);
408 else
409 hdr_len = skb_transport_offset(skb) +
410 tcp_hdrlen(skb);
411
412 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
413 TX_BD_FLAGS_T_IPID |
414 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
415 length = skb_shinfo(skb)->gso_size;
416 txbd1->tx_bd_mss = cpu_to_le32(length);
417 length += hdr_len;
418 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
419 txbd1->tx_bd_hsize_lflags =
420 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
421 txbd1->tx_bd_mss = 0;
422 }
423
424 length >>= 9;
425 flags |= bnxt_lhint_arr[length];
426 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
427
428 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
429 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
430 for (i = 0; i < last_frag; i++) {
431 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432
433 prod = NEXT_TX(prod);
434 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
435
436 len = skb_frag_size(frag);
437 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
438 DMA_TO_DEVICE);
439
440 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
441 goto tx_dma_error;
442
443 tx_buf = &txr->tx_buf_ring[prod];
444 dma_unmap_addr_set(tx_buf, mapping, mapping);
445
446 txbd->tx_bd_haddr = cpu_to_le64(mapping);
447
448 flags = len << TX_BD_LEN_SHIFT;
449 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
450 }
451
452 flags &= ~TX_BD_LEN;
453 txbd->tx_bd_len_flags_type =
454 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
455 TX_BD_FLAGS_PACKET_END);
456
457 netdev_tx_sent_queue(txq, skb->len);
458
459 /* Sync BD data before updating doorbell */
460 wmb();
461
462 prod = NEXT_TX(prod);
463 txr->tx_prod = prod;
464
465 writel(DB_KEY_TX | prod, txr->tx_doorbell);
466 writel(DB_KEY_TX | prod, txr->tx_doorbell);
467
468 tx_done:
469
470 mmiowb();
471
472 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
473 netif_tx_stop_queue(txq);
474
475 /* netif_tx_stop_queue() must be done before checking
476 * tx index in bnxt_tx_avail() below, because in
477 * bnxt_tx_int(), we update tx index before checking for
478 * netif_tx_queue_stopped().
479 */
480 smp_mb();
481 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
482 netif_tx_wake_queue(txq);
483 }
484 return NETDEV_TX_OK;
485
486 tx_dma_error:
487 last_frag = i;
488
489 /* start back at beginning and unmap skb */
490 prod = txr->tx_prod;
491 tx_buf = &txr->tx_buf_ring[prod];
492 tx_buf->skb = NULL;
493 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
494 skb_headlen(skb), PCI_DMA_TODEVICE);
495 prod = NEXT_TX(prod);
496
497 /* unmap remaining mapped pages */
498 for (i = 0; i < last_frag; i++) {
499 prod = NEXT_TX(prod);
500 tx_buf = &txr->tx_buf_ring[prod];
501 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
502 skb_frag_size(&skb_shinfo(skb)->frags[i]),
503 PCI_DMA_TODEVICE);
504 }
505
506 dev_kfree_skb_any(skb);
507 return NETDEV_TX_OK;
508 }
509
510 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
511 {
512 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
513 int index = txr - &bp->tx_ring[0];
514 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
515 u16 cons = txr->tx_cons;
516 struct pci_dev *pdev = bp->pdev;
517 int i;
518 unsigned int tx_bytes = 0;
519
520 for (i = 0; i < nr_pkts; i++) {
521 struct bnxt_sw_tx_bd *tx_buf;
522 struct sk_buff *skb;
523 int j, last;
524
525 tx_buf = &txr->tx_buf_ring[cons];
526 cons = NEXT_TX(cons);
527 skb = tx_buf->skb;
528 tx_buf->skb = NULL;
529
530 if (tx_buf->is_push) {
531 tx_buf->is_push = 0;
532 goto next_tx_int;
533 }
534
535 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
536 skb_headlen(skb), PCI_DMA_TODEVICE);
537 last = tx_buf->nr_frags;
538
539 for (j = 0; j < last; j++) {
540 cons = NEXT_TX(cons);
541 tx_buf = &txr->tx_buf_ring[cons];
542 dma_unmap_page(
543 &pdev->dev,
544 dma_unmap_addr(tx_buf, mapping),
545 skb_frag_size(&skb_shinfo(skb)->frags[j]),
546 PCI_DMA_TODEVICE);
547 }
548
549 next_tx_int:
550 cons = NEXT_TX(cons);
551
552 tx_bytes += skb->len;
553 dev_kfree_skb_any(skb);
554 }
555
556 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
557 txr->tx_cons = cons;
558
559 /* Need to make the tx_cons update visible to bnxt_start_xmit()
560 * before checking for netif_tx_queue_stopped(). Without the
561 * memory barrier, there is a small possibility that bnxt_start_xmit()
562 * will miss it and cause the queue to be stopped forever.
563 */
564 smp_mb();
565
566 if (unlikely(netif_tx_queue_stopped(txq)) &&
567 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
568 __netif_tx_lock(txq, smp_processor_id());
569 if (netif_tx_queue_stopped(txq) &&
570 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
571 txr->dev_state != BNXT_DEV_STATE_CLOSING)
572 netif_tx_wake_queue(txq);
573 __netif_tx_unlock(txq);
574 }
575 }
576
577 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
578 gfp_t gfp)
579 {
580 u8 *data;
581 struct pci_dev *pdev = bp->pdev;
582
583 data = kmalloc(bp->rx_buf_size, gfp);
584 if (!data)
585 return NULL;
586
587 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
588 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
589
590 if (dma_mapping_error(&pdev->dev, *mapping)) {
591 kfree(data);
592 data = NULL;
593 }
594 return data;
595 }
596
597 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
598 struct bnxt_rx_ring_info *rxr,
599 u16 prod, gfp_t gfp)
600 {
601 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
602 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
603 u8 *data;
604 dma_addr_t mapping;
605
606 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
607 if (!data)
608 return -ENOMEM;
609
610 rx_buf->data = data;
611 dma_unmap_addr_set(rx_buf, mapping, mapping);
612
613 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
614
615 return 0;
616 }
617
618 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
619 u8 *data)
620 {
621 u16 prod = rxr->rx_prod;
622 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
623 struct rx_bd *cons_bd, *prod_bd;
624
625 prod_rx_buf = &rxr->rx_buf_ring[prod];
626 cons_rx_buf = &rxr->rx_buf_ring[cons];
627
628 prod_rx_buf->data = data;
629
630 dma_unmap_addr_set(prod_rx_buf, mapping,
631 dma_unmap_addr(cons_rx_buf, mapping));
632
633 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
634 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
635
636 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
637 }
638
639 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
640 {
641 u16 next, max = rxr->rx_agg_bmap_size;
642
643 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
644 if (next >= max)
645 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
646 return next;
647 }
648
649 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
650 struct bnxt_rx_ring_info *rxr,
651 u16 prod, gfp_t gfp)
652 {
653 struct rx_bd *rxbd =
654 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
655 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
656 struct pci_dev *pdev = bp->pdev;
657 struct page *page;
658 dma_addr_t mapping;
659 u16 sw_prod = rxr->rx_sw_agg_prod;
660 unsigned int offset = 0;
661
662 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
663 page = rxr->rx_page;
664 if (!page) {
665 page = alloc_page(gfp);
666 if (!page)
667 return -ENOMEM;
668 rxr->rx_page = page;
669 rxr->rx_page_offset = 0;
670 }
671 offset = rxr->rx_page_offset;
672 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
673 if (rxr->rx_page_offset == PAGE_SIZE)
674 rxr->rx_page = NULL;
675 else
676 get_page(page);
677 } else {
678 page = alloc_page(gfp);
679 if (!page)
680 return -ENOMEM;
681 }
682
683 mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
684 PCI_DMA_FROMDEVICE);
685 if (dma_mapping_error(&pdev->dev, mapping)) {
686 __free_page(page);
687 return -EIO;
688 }
689
690 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
691 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
692
693 __set_bit(sw_prod, rxr->rx_agg_bmap);
694 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
695 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
696
697 rx_agg_buf->page = page;
698 rx_agg_buf->offset = offset;
699 rx_agg_buf->mapping = mapping;
700 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
701 rxbd->rx_bd_opaque = sw_prod;
702 return 0;
703 }
704
705 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
706 u32 agg_bufs)
707 {
708 struct bnxt *bp = bnapi->bp;
709 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
710 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
711 u16 prod = rxr->rx_agg_prod;
712 u16 sw_prod = rxr->rx_sw_agg_prod;
713 u32 i;
714
715 for (i = 0; i < agg_bufs; i++) {
716 u16 cons;
717 struct rx_agg_cmp *agg;
718 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
719 struct rx_bd *prod_bd;
720 struct page *page;
721
722 agg = (struct rx_agg_cmp *)
723 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
724 cons = agg->rx_agg_cmp_opaque;
725 __clear_bit(cons, rxr->rx_agg_bmap);
726
727 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
728 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
729
730 __set_bit(sw_prod, rxr->rx_agg_bmap);
731 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
732 cons_rx_buf = &rxr->rx_agg_ring[cons];
733
734 /* It is possible for sw_prod to be equal to cons, so
735 * set cons_rx_buf->page to NULL first.
736 */
737 page = cons_rx_buf->page;
738 cons_rx_buf->page = NULL;
739 prod_rx_buf->page = page;
740 prod_rx_buf->offset = cons_rx_buf->offset;
741
742 prod_rx_buf->mapping = cons_rx_buf->mapping;
743
744 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
745
746 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
747 prod_bd->rx_bd_opaque = sw_prod;
748
749 prod = NEXT_RX_AGG(prod);
750 sw_prod = NEXT_RX_AGG(sw_prod);
751 cp_cons = NEXT_CMP(cp_cons);
752 }
753 rxr->rx_agg_prod = prod;
754 rxr->rx_sw_agg_prod = sw_prod;
755 }
756
757 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
758 struct bnxt_rx_ring_info *rxr, u16 cons,
759 u16 prod, u8 *data, dma_addr_t dma_addr,
760 unsigned int len)
761 {
762 int err;
763 struct sk_buff *skb;
764
765 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
766 if (unlikely(err)) {
767 bnxt_reuse_rx_data(rxr, cons, data);
768 return NULL;
769 }
770
771 skb = build_skb(data, 0);
772 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
773 PCI_DMA_FROMDEVICE);
774 if (!skb) {
775 kfree(data);
776 return NULL;
777 }
778
779 skb_reserve(skb, BNXT_RX_OFFSET);
780 skb_put(skb, len);
781 return skb;
782 }
783
784 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
785 struct sk_buff *skb, u16 cp_cons,
786 u32 agg_bufs)
787 {
788 struct pci_dev *pdev = bp->pdev;
789 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
790 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
791 u16 prod = rxr->rx_agg_prod;
792 u32 i;
793
794 for (i = 0; i < agg_bufs; i++) {
795 u16 cons, frag_len;
796 struct rx_agg_cmp *agg;
797 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
798 struct page *page;
799 dma_addr_t mapping;
800
801 agg = (struct rx_agg_cmp *)
802 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
803 cons = agg->rx_agg_cmp_opaque;
804 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
805 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
806
807 cons_rx_buf = &rxr->rx_agg_ring[cons];
808 skb_fill_page_desc(skb, i, cons_rx_buf->page,
809 cons_rx_buf->offset, frag_len);
810 __clear_bit(cons, rxr->rx_agg_bmap);
811
812 /* It is possible for bnxt_alloc_rx_page() to allocate
813 * a sw_prod index that equals the cons index, so we
814 * need to clear the cons entry now.
815 */
816 mapping = dma_unmap_addr(cons_rx_buf, mapping);
817 page = cons_rx_buf->page;
818 cons_rx_buf->page = NULL;
819
820 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
821 struct skb_shared_info *shinfo;
822 unsigned int nr_frags;
823
824 shinfo = skb_shinfo(skb);
825 nr_frags = --shinfo->nr_frags;
826 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
827
828 dev_kfree_skb(skb);
829
830 cons_rx_buf->page = page;
831
832 /* Update prod since possibly some pages have been
833 * allocated already.
834 */
835 rxr->rx_agg_prod = prod;
836 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
837 return NULL;
838 }
839
840 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
841 PCI_DMA_FROMDEVICE);
842
843 skb->data_len += frag_len;
844 skb->len += frag_len;
845 skb->truesize += PAGE_SIZE;
846
847 prod = NEXT_RX_AGG(prod);
848 cp_cons = NEXT_CMP(cp_cons);
849 }
850 rxr->rx_agg_prod = prod;
851 return skb;
852 }
853
854 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
855 u8 agg_bufs, u32 *raw_cons)
856 {
857 u16 last;
858 struct rx_agg_cmp *agg;
859
860 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
861 last = RING_CMP(*raw_cons);
862 agg = (struct rx_agg_cmp *)
863 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
864 return RX_AGG_CMP_VALID(agg, *raw_cons);
865 }
866
867 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
868 unsigned int len,
869 dma_addr_t mapping)
870 {
871 struct bnxt *bp = bnapi->bp;
872 struct pci_dev *pdev = bp->pdev;
873 struct sk_buff *skb;
874
875 skb = napi_alloc_skb(&bnapi->napi, len);
876 if (!skb)
877 return NULL;
878
879 dma_sync_single_for_cpu(&pdev->dev, mapping,
880 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
881
882 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
883
884 dma_sync_single_for_device(&pdev->dev, mapping,
885 bp->rx_copy_thresh,
886 PCI_DMA_FROMDEVICE);
887
888 skb_put(skb, len);
889 return skb;
890 }
891
892 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
893 u32 *raw_cons, void *cmp)
894 {
895 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
896 struct rx_cmp *rxcmp = cmp;
897 u32 tmp_raw_cons = *raw_cons;
898 u8 cmp_type, agg_bufs = 0;
899
900 cmp_type = RX_CMP_TYPE(rxcmp);
901
902 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
903 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
904 RX_CMP_AGG_BUFS) >>
905 RX_CMP_AGG_BUFS_SHIFT;
906 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
907 struct rx_tpa_end_cmp *tpa_end = cmp;
908
909 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
910 RX_TPA_END_CMP_AGG_BUFS) >>
911 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
912 }
913
914 if (agg_bufs) {
915 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
916 return -EBUSY;
917 }
918 *raw_cons = tmp_raw_cons;
919 return 0;
920 }
921
922 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
923 {
924 if (!rxr->bnapi->in_reset) {
925 rxr->bnapi->in_reset = true;
926 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
927 schedule_work(&bp->sp_task);
928 }
929 rxr->rx_next_cons = 0xffff;
930 }
931
932 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
933 struct rx_tpa_start_cmp *tpa_start,
934 struct rx_tpa_start_cmp_ext *tpa_start1)
935 {
936 u8 agg_id = TPA_START_AGG_ID(tpa_start);
937 u16 cons, prod;
938 struct bnxt_tpa_info *tpa_info;
939 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
940 struct rx_bd *prod_bd;
941 dma_addr_t mapping;
942
943 cons = tpa_start->rx_tpa_start_cmp_opaque;
944 prod = rxr->rx_prod;
945 cons_rx_buf = &rxr->rx_buf_ring[cons];
946 prod_rx_buf = &rxr->rx_buf_ring[prod];
947 tpa_info = &rxr->rx_tpa[agg_id];
948
949 if (unlikely(cons != rxr->rx_next_cons)) {
950 bnxt_sched_reset(bp, rxr);
951 return;
952 }
953
954 prod_rx_buf->data = tpa_info->data;
955
956 mapping = tpa_info->mapping;
957 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
958
959 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
960
961 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
962
963 tpa_info->data = cons_rx_buf->data;
964 cons_rx_buf->data = NULL;
965 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
966
967 tpa_info->len =
968 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
969 RX_TPA_START_CMP_LEN_SHIFT;
970 if (likely(TPA_START_HASH_VALID(tpa_start))) {
971 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
972
973 tpa_info->hash_type = PKT_HASH_TYPE_L4;
974 tpa_info->gso_type = SKB_GSO_TCPV4;
975 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
976 if (hash_type == 3)
977 tpa_info->gso_type = SKB_GSO_TCPV6;
978 tpa_info->rss_hash =
979 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
980 } else {
981 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
982 tpa_info->gso_type = 0;
983 if (netif_msg_rx_err(bp))
984 netdev_warn(bp->dev, "TPA packet without valid hash\n");
985 }
986 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
987 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
988 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
989
990 rxr->rx_prod = NEXT_RX(prod);
991 cons = NEXT_RX(cons);
992 rxr->rx_next_cons = NEXT_RX(cons);
993 cons_rx_buf = &rxr->rx_buf_ring[cons];
994
995 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
996 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
997 cons_rx_buf->data = NULL;
998 }
999
1000 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1001 u16 cp_cons, u32 agg_bufs)
1002 {
1003 if (agg_bufs)
1004 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1005 }
1006
1007 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1008 int payload_off, int tcp_ts,
1009 struct sk_buff *skb)
1010 {
1011 #ifdef CONFIG_INET
1012 struct tcphdr *th;
1013 int len, nw_off;
1014 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1015 u32 hdr_info = tpa_info->hdr_info;
1016 bool loopback = false;
1017
1018 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1019 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1020 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1021
1022 /* If the packet is an internal loopback packet, the offsets will
1023 * have an extra 4 bytes.
1024 */
1025 if (inner_mac_off == 4) {
1026 loopback = true;
1027 } else if (inner_mac_off > 4) {
1028 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1029 ETH_HLEN - 2));
1030
1031 /* We only support inner iPv4/ipv6. If we don't see the
1032 * correct protocol ID, it must be a loopback packet where
1033 * the offsets are off by 4.
1034 */
1035 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1036 loopback = true;
1037 }
1038 if (loopback) {
1039 /* internal loopback packet, subtract all offsets by 4 */
1040 inner_ip_off -= 4;
1041 inner_mac_off -= 4;
1042 outer_ip_off -= 4;
1043 }
1044
1045 nw_off = inner_ip_off - ETH_HLEN;
1046 skb_set_network_header(skb, nw_off);
1047 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1048 struct ipv6hdr *iph = ipv6_hdr(skb);
1049
1050 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1051 len = skb->len - skb_transport_offset(skb);
1052 th = tcp_hdr(skb);
1053 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1054 } else {
1055 struct iphdr *iph = ip_hdr(skb);
1056
1057 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1058 len = skb->len - skb_transport_offset(skb);
1059 th = tcp_hdr(skb);
1060 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1061 }
1062
1063 if (inner_mac_off) { /* tunnel */
1064 struct udphdr *uh = NULL;
1065 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1066 ETH_HLEN - 2));
1067
1068 if (proto == htons(ETH_P_IP)) {
1069 struct iphdr *iph = (struct iphdr *)skb->data;
1070
1071 if (iph->protocol == IPPROTO_UDP)
1072 uh = (struct udphdr *)(iph + 1);
1073 } else {
1074 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1075
1076 if (iph->nexthdr == IPPROTO_UDP)
1077 uh = (struct udphdr *)(iph + 1);
1078 }
1079 if (uh) {
1080 if (uh->check)
1081 skb_shinfo(skb)->gso_type |=
1082 SKB_GSO_UDP_TUNNEL_CSUM;
1083 else
1084 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1085 }
1086 }
1087 #endif
1088 return skb;
1089 }
1090
1091 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1092 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1093
1094 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1095 int payload_off, int tcp_ts,
1096 struct sk_buff *skb)
1097 {
1098 #ifdef CONFIG_INET
1099 struct tcphdr *th;
1100 int len, nw_off, tcp_opt_len;
1101
1102 if (tcp_ts)
1103 tcp_opt_len = 12;
1104
1105 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1106 struct iphdr *iph;
1107
1108 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1109 ETH_HLEN;
1110 skb_set_network_header(skb, nw_off);
1111 iph = ip_hdr(skb);
1112 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1113 len = skb->len - skb_transport_offset(skb);
1114 th = tcp_hdr(skb);
1115 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1116 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1117 struct ipv6hdr *iph;
1118
1119 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1120 ETH_HLEN;
1121 skb_set_network_header(skb, nw_off);
1122 iph = ipv6_hdr(skb);
1123 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1124 len = skb->len - skb_transport_offset(skb);
1125 th = tcp_hdr(skb);
1126 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1127 } else {
1128 dev_kfree_skb_any(skb);
1129 return NULL;
1130 }
1131 tcp_gro_complete(skb);
1132
1133 if (nw_off) { /* tunnel */
1134 struct udphdr *uh = NULL;
1135
1136 if (skb->protocol == htons(ETH_P_IP)) {
1137 struct iphdr *iph = (struct iphdr *)skb->data;
1138
1139 if (iph->protocol == IPPROTO_UDP)
1140 uh = (struct udphdr *)(iph + 1);
1141 } else {
1142 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1143
1144 if (iph->nexthdr == IPPROTO_UDP)
1145 uh = (struct udphdr *)(iph + 1);
1146 }
1147 if (uh) {
1148 if (uh->check)
1149 skb_shinfo(skb)->gso_type |=
1150 SKB_GSO_UDP_TUNNEL_CSUM;
1151 else
1152 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1153 }
1154 }
1155 #endif
1156 return skb;
1157 }
1158
1159 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1160 struct bnxt_tpa_info *tpa_info,
1161 struct rx_tpa_end_cmp *tpa_end,
1162 struct rx_tpa_end_cmp_ext *tpa_end1,
1163 struct sk_buff *skb)
1164 {
1165 #ifdef CONFIG_INET
1166 int payload_off;
1167 u16 segs;
1168
1169 segs = TPA_END_TPA_SEGS(tpa_end);
1170 if (segs == 1)
1171 return skb;
1172
1173 NAPI_GRO_CB(skb)->count = segs;
1174 skb_shinfo(skb)->gso_size =
1175 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1176 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1177 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1178 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1179 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1180 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1181 #endif
1182 return skb;
1183 }
1184
1185 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1186 struct bnxt_napi *bnapi,
1187 u32 *raw_cons,
1188 struct rx_tpa_end_cmp *tpa_end,
1189 struct rx_tpa_end_cmp_ext *tpa_end1,
1190 bool *agg_event)
1191 {
1192 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1193 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1194 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1195 u8 *data, agg_bufs;
1196 u16 cp_cons = RING_CMP(*raw_cons);
1197 unsigned int len;
1198 struct bnxt_tpa_info *tpa_info;
1199 dma_addr_t mapping;
1200 struct sk_buff *skb;
1201
1202 if (unlikely(bnapi->in_reset)) {
1203 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1204
1205 if (rc < 0)
1206 return ERR_PTR(-EBUSY);
1207 return NULL;
1208 }
1209
1210 tpa_info = &rxr->rx_tpa[agg_id];
1211 data = tpa_info->data;
1212 prefetch(data);
1213 len = tpa_info->len;
1214 mapping = tpa_info->mapping;
1215
1216 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1217 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1218
1219 if (agg_bufs) {
1220 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1221 return ERR_PTR(-EBUSY);
1222
1223 *agg_event = true;
1224 cp_cons = NEXT_CMP(cp_cons);
1225 }
1226
1227 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1228 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1229 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1230 agg_bufs, (int)MAX_SKB_FRAGS);
1231 return NULL;
1232 }
1233
1234 if (len <= bp->rx_copy_thresh) {
1235 skb = bnxt_copy_skb(bnapi, data, len, mapping);
1236 if (!skb) {
1237 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1238 return NULL;
1239 }
1240 } else {
1241 u8 *new_data;
1242 dma_addr_t new_mapping;
1243
1244 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1245 if (!new_data) {
1246 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1247 return NULL;
1248 }
1249
1250 tpa_info->data = new_data;
1251 tpa_info->mapping = new_mapping;
1252
1253 skb = build_skb(data, 0);
1254 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1255 PCI_DMA_FROMDEVICE);
1256
1257 if (!skb) {
1258 kfree(data);
1259 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1260 return NULL;
1261 }
1262 skb_reserve(skb, BNXT_RX_OFFSET);
1263 skb_put(skb, len);
1264 }
1265
1266 if (agg_bufs) {
1267 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1268 if (!skb) {
1269 /* Page reuse already handled by bnxt_rx_pages(). */
1270 return NULL;
1271 }
1272 }
1273 skb->protocol = eth_type_trans(skb, bp->dev);
1274
1275 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1276 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1277
1278 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1279 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1280 u16 vlan_proto = tpa_info->metadata >>
1281 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1282 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1283
1284 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1285 }
1286
1287 skb_checksum_none_assert(skb);
1288 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1289 skb->ip_summed = CHECKSUM_UNNECESSARY;
1290 skb->csum_level =
1291 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1292 }
1293
1294 if (TPA_END_GRO(tpa_end))
1295 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1296
1297 return skb;
1298 }
1299
1300 /* returns the following:
1301 * 1 - 1 packet successfully received
1302 * 0 - successful TPA_START, packet not completed yet
1303 * -EBUSY - completion ring does not have all the agg buffers yet
1304 * -ENOMEM - packet aborted due to out of memory
1305 * -EIO - packet aborted due to hw error indicated in BD
1306 */
1307 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1308 bool *agg_event)
1309 {
1310 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1311 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1312 struct net_device *dev = bp->dev;
1313 struct rx_cmp *rxcmp;
1314 struct rx_cmp_ext *rxcmp1;
1315 u32 tmp_raw_cons = *raw_cons;
1316 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1317 struct bnxt_sw_rx_bd *rx_buf;
1318 unsigned int len;
1319 u8 *data, agg_bufs, cmp_type;
1320 dma_addr_t dma_addr;
1321 struct sk_buff *skb;
1322 int rc = 0;
1323
1324 rxcmp = (struct rx_cmp *)
1325 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1326
1327 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1328 cp_cons = RING_CMP(tmp_raw_cons);
1329 rxcmp1 = (struct rx_cmp_ext *)
1330 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1331
1332 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1333 return -EBUSY;
1334
1335 cmp_type = RX_CMP_TYPE(rxcmp);
1336
1337 prod = rxr->rx_prod;
1338
1339 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1340 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1341 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1342
1343 goto next_rx_no_prod;
1344
1345 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1346 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1347 (struct rx_tpa_end_cmp *)rxcmp,
1348 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1349 agg_event);
1350
1351 if (unlikely(IS_ERR(skb)))
1352 return -EBUSY;
1353
1354 rc = -ENOMEM;
1355 if (likely(skb)) {
1356 skb_record_rx_queue(skb, bnapi->index);
1357 skb_mark_napi_id(skb, &bnapi->napi);
1358 if (bnxt_busy_polling(bnapi))
1359 netif_receive_skb(skb);
1360 else
1361 napi_gro_receive(&bnapi->napi, skb);
1362 rc = 1;
1363 }
1364 goto next_rx_no_prod;
1365 }
1366
1367 cons = rxcmp->rx_cmp_opaque;
1368 rx_buf = &rxr->rx_buf_ring[cons];
1369 data = rx_buf->data;
1370 if (unlikely(cons != rxr->rx_next_cons)) {
1371 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1372
1373 bnxt_sched_reset(bp, rxr);
1374 return rc1;
1375 }
1376 prefetch(data);
1377
1378 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1379 RX_CMP_AGG_BUFS_SHIFT;
1380
1381 if (agg_bufs) {
1382 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1383 return -EBUSY;
1384
1385 cp_cons = NEXT_CMP(cp_cons);
1386 *agg_event = true;
1387 }
1388
1389 rx_buf->data = NULL;
1390 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1391 bnxt_reuse_rx_data(rxr, cons, data);
1392 if (agg_bufs)
1393 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1394
1395 rc = -EIO;
1396 goto next_rx;
1397 }
1398
1399 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1400 dma_addr = dma_unmap_addr(rx_buf, mapping);
1401
1402 if (len <= bp->rx_copy_thresh) {
1403 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1404 bnxt_reuse_rx_data(rxr, cons, data);
1405 if (!skb) {
1406 rc = -ENOMEM;
1407 goto next_rx;
1408 }
1409 } else {
1410 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1411 if (!skb) {
1412 rc = -ENOMEM;
1413 goto next_rx;
1414 }
1415 }
1416
1417 if (agg_bufs) {
1418 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1419 if (!skb) {
1420 rc = -ENOMEM;
1421 goto next_rx;
1422 }
1423 }
1424
1425 if (RX_CMP_HASH_VALID(rxcmp)) {
1426 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1427 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1428
1429 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1430 if (hash_type != 1 && hash_type != 3)
1431 type = PKT_HASH_TYPE_L3;
1432 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1433 }
1434
1435 skb->protocol = eth_type_trans(skb, dev);
1436
1437 if ((rxcmp1->rx_cmp_flags2 &
1438 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1439 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1440 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1441 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1442 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1443
1444 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1445 }
1446
1447 skb_checksum_none_assert(skb);
1448 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1449 if (dev->features & NETIF_F_RXCSUM) {
1450 skb->ip_summed = CHECKSUM_UNNECESSARY;
1451 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1452 }
1453 } else {
1454 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1455 if (dev->features & NETIF_F_RXCSUM)
1456 cpr->rx_l4_csum_errors++;
1457 }
1458 }
1459
1460 skb_record_rx_queue(skb, bnapi->index);
1461 skb_mark_napi_id(skb, &bnapi->napi);
1462 if (bnxt_busy_polling(bnapi))
1463 netif_receive_skb(skb);
1464 else
1465 napi_gro_receive(&bnapi->napi, skb);
1466 rc = 1;
1467
1468 next_rx:
1469 rxr->rx_prod = NEXT_RX(prod);
1470 rxr->rx_next_cons = NEXT_RX(cons);
1471
1472 next_rx_no_prod:
1473 *raw_cons = tmp_raw_cons;
1474
1475 return rc;
1476 }
1477
1478 #define BNXT_GET_EVENT_PORT(data) \
1479 ((data) & \
1480 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1481
1482 static int bnxt_async_event_process(struct bnxt *bp,
1483 struct hwrm_async_event_cmpl *cmpl)
1484 {
1485 u16 event_id = le16_to_cpu(cmpl->event_id);
1486
1487 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1488 switch (event_id) {
1489 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1490 u32 data1 = le32_to_cpu(cmpl->event_data1);
1491 struct bnxt_link_info *link_info = &bp->link_info;
1492
1493 if (BNXT_VF(bp))
1494 goto async_event_process_exit;
1495 if (data1 & 0x20000) {
1496 u16 fw_speed = link_info->force_link_speed;
1497 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1498
1499 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1500 speed);
1501 }
1502 /* fall thru */
1503 }
1504 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1505 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1506 break;
1507 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1508 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1509 break;
1510 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1511 u32 data1 = le32_to_cpu(cmpl->event_data1);
1512 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1513
1514 if (BNXT_VF(bp))
1515 break;
1516
1517 if (bp->pf.port_id != port_id)
1518 break;
1519
1520 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1521 break;
1522 }
1523 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1524 if (BNXT_PF(bp))
1525 goto async_event_process_exit;
1526 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1527 break;
1528 default:
1529 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1530 event_id);
1531 goto async_event_process_exit;
1532 }
1533 schedule_work(&bp->sp_task);
1534 async_event_process_exit:
1535 return 0;
1536 }
1537
1538 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1539 {
1540 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1541 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1542 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1543 (struct hwrm_fwd_req_cmpl *)txcmp;
1544
1545 switch (cmpl_type) {
1546 case CMPL_BASE_TYPE_HWRM_DONE:
1547 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1548 if (seq_id == bp->hwrm_intr_seq_id)
1549 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1550 else
1551 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1552 break;
1553
1554 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1555 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1556
1557 if ((vf_id < bp->pf.first_vf_id) ||
1558 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1559 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1560 vf_id);
1561 return -EINVAL;
1562 }
1563
1564 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1565 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1566 schedule_work(&bp->sp_task);
1567 break;
1568
1569 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1570 bnxt_async_event_process(bp,
1571 (struct hwrm_async_event_cmpl *)txcmp);
1572
1573 default:
1574 break;
1575 }
1576
1577 return 0;
1578 }
1579
1580 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1581 {
1582 struct bnxt_napi *bnapi = dev_instance;
1583 struct bnxt *bp = bnapi->bp;
1584 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1585 u32 cons = RING_CMP(cpr->cp_raw_cons);
1586
1587 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1588 napi_schedule(&bnapi->napi);
1589 return IRQ_HANDLED;
1590 }
1591
1592 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1593 {
1594 u32 raw_cons = cpr->cp_raw_cons;
1595 u16 cons = RING_CMP(raw_cons);
1596 struct tx_cmp *txcmp;
1597
1598 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1599
1600 return TX_CMP_VALID(txcmp, raw_cons);
1601 }
1602
1603 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1604 {
1605 struct bnxt_napi *bnapi = dev_instance;
1606 struct bnxt *bp = bnapi->bp;
1607 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1608 u32 cons = RING_CMP(cpr->cp_raw_cons);
1609 u32 int_status;
1610
1611 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1612
1613 if (!bnxt_has_work(bp, cpr)) {
1614 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1615 /* return if erroneous interrupt */
1616 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1617 return IRQ_NONE;
1618 }
1619
1620 /* disable ring IRQ */
1621 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1622
1623 /* Return here if interrupt is shared and is disabled. */
1624 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1625 return IRQ_HANDLED;
1626
1627 napi_schedule(&bnapi->napi);
1628 return IRQ_HANDLED;
1629 }
1630
1631 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1632 {
1633 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1634 u32 raw_cons = cpr->cp_raw_cons;
1635 u32 cons;
1636 int tx_pkts = 0;
1637 int rx_pkts = 0;
1638 bool rx_event = false;
1639 bool agg_event = false;
1640 struct tx_cmp *txcmp;
1641
1642 while (1) {
1643 int rc;
1644
1645 cons = RING_CMP(raw_cons);
1646 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1647
1648 if (!TX_CMP_VALID(txcmp, raw_cons))
1649 break;
1650
1651 /* The valid test of the entry must be done first before
1652 * reading any further.
1653 */
1654 dma_rmb();
1655 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1656 tx_pkts++;
1657 /* return full budget so NAPI will complete. */
1658 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1659 rx_pkts = budget;
1660 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1661 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1662 if (likely(rc >= 0))
1663 rx_pkts += rc;
1664 else if (rc == -EBUSY) /* partial completion */
1665 break;
1666 rx_event = true;
1667 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1668 CMPL_BASE_TYPE_HWRM_DONE) ||
1669 (TX_CMP_TYPE(txcmp) ==
1670 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1671 (TX_CMP_TYPE(txcmp) ==
1672 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1673 bnxt_hwrm_handler(bp, txcmp);
1674 }
1675 raw_cons = NEXT_RAW_CMP(raw_cons);
1676
1677 if (rx_pkts == budget)
1678 break;
1679 }
1680
1681 cpr->cp_raw_cons = raw_cons;
1682 /* ACK completion ring before freeing tx ring and producing new
1683 * buffers in rx/agg rings to prevent overflowing the completion
1684 * ring.
1685 */
1686 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1687
1688 if (tx_pkts)
1689 bnxt_tx_int(bp, bnapi, tx_pkts);
1690
1691 if (rx_event) {
1692 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1693
1694 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1695 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1696 if (agg_event) {
1697 writel(DB_KEY_RX | rxr->rx_agg_prod,
1698 rxr->rx_agg_doorbell);
1699 writel(DB_KEY_RX | rxr->rx_agg_prod,
1700 rxr->rx_agg_doorbell);
1701 }
1702 }
1703 return rx_pkts;
1704 }
1705
1706 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1707 {
1708 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1709 struct bnxt *bp = bnapi->bp;
1710 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1711 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1712 struct tx_cmp *txcmp;
1713 struct rx_cmp_ext *rxcmp1;
1714 u32 cp_cons, tmp_raw_cons;
1715 u32 raw_cons = cpr->cp_raw_cons;
1716 u32 rx_pkts = 0;
1717 bool agg_event = false;
1718
1719 while (1) {
1720 int rc;
1721
1722 cp_cons = RING_CMP(raw_cons);
1723 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1724
1725 if (!TX_CMP_VALID(txcmp, raw_cons))
1726 break;
1727
1728 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1729 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1730 cp_cons = RING_CMP(tmp_raw_cons);
1731 rxcmp1 = (struct rx_cmp_ext *)
1732 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1733
1734 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1735 break;
1736
1737 /* force an error to recycle the buffer */
1738 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1739 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1740
1741 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1742 if (likely(rc == -EIO))
1743 rx_pkts++;
1744 else if (rc == -EBUSY) /* partial completion */
1745 break;
1746 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1747 CMPL_BASE_TYPE_HWRM_DONE)) {
1748 bnxt_hwrm_handler(bp, txcmp);
1749 } else {
1750 netdev_err(bp->dev,
1751 "Invalid completion received on special ring\n");
1752 }
1753 raw_cons = NEXT_RAW_CMP(raw_cons);
1754
1755 if (rx_pkts == budget)
1756 break;
1757 }
1758
1759 cpr->cp_raw_cons = raw_cons;
1760 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1761 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1762 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1763
1764 if (agg_event) {
1765 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1766 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1767 }
1768
1769 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
1770 napi_complete(napi);
1771 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1772 }
1773 return rx_pkts;
1774 }
1775
1776 static int bnxt_poll(struct napi_struct *napi, int budget)
1777 {
1778 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1779 struct bnxt *bp = bnapi->bp;
1780 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1781 int work_done = 0;
1782
1783 if (!bnxt_lock_napi(bnapi))
1784 return budget;
1785
1786 while (1) {
1787 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1788
1789 if (work_done >= budget)
1790 break;
1791
1792 if (!bnxt_has_work(bp, cpr)) {
1793 napi_complete(napi);
1794 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1795 break;
1796 }
1797 }
1798 mmiowb();
1799 bnxt_unlock_napi(bnapi);
1800 return work_done;
1801 }
1802
1803 #ifdef CONFIG_NET_RX_BUSY_POLL
1804 static int bnxt_busy_poll(struct napi_struct *napi)
1805 {
1806 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1807 struct bnxt *bp = bnapi->bp;
1808 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1809 int rx_work, budget = 4;
1810
1811 if (atomic_read(&bp->intr_sem) != 0)
1812 return LL_FLUSH_FAILED;
1813
1814 if (!bnxt_lock_poll(bnapi))
1815 return LL_FLUSH_BUSY;
1816
1817 rx_work = bnxt_poll_work(bp, bnapi, budget);
1818
1819 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1820
1821 bnxt_unlock_poll(bnapi);
1822 return rx_work;
1823 }
1824 #endif
1825
1826 static void bnxt_free_tx_skbs(struct bnxt *bp)
1827 {
1828 int i, max_idx;
1829 struct pci_dev *pdev = bp->pdev;
1830
1831 if (!bp->tx_ring)
1832 return;
1833
1834 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1835 for (i = 0; i < bp->tx_nr_rings; i++) {
1836 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1837 int j;
1838
1839 for (j = 0; j < max_idx;) {
1840 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1841 struct sk_buff *skb = tx_buf->skb;
1842 int k, last;
1843
1844 if (!skb) {
1845 j++;
1846 continue;
1847 }
1848
1849 tx_buf->skb = NULL;
1850
1851 if (tx_buf->is_push) {
1852 dev_kfree_skb(skb);
1853 j += 2;
1854 continue;
1855 }
1856
1857 dma_unmap_single(&pdev->dev,
1858 dma_unmap_addr(tx_buf, mapping),
1859 skb_headlen(skb),
1860 PCI_DMA_TODEVICE);
1861
1862 last = tx_buf->nr_frags;
1863 j += 2;
1864 for (k = 0; k < last; k++, j++) {
1865 int ring_idx = j & bp->tx_ring_mask;
1866 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1867
1868 tx_buf = &txr->tx_buf_ring[ring_idx];
1869 dma_unmap_page(
1870 &pdev->dev,
1871 dma_unmap_addr(tx_buf, mapping),
1872 skb_frag_size(frag), PCI_DMA_TODEVICE);
1873 }
1874 dev_kfree_skb(skb);
1875 }
1876 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1877 }
1878 }
1879
1880 static void bnxt_free_rx_skbs(struct bnxt *bp)
1881 {
1882 int i, max_idx, max_agg_idx;
1883 struct pci_dev *pdev = bp->pdev;
1884
1885 if (!bp->rx_ring)
1886 return;
1887
1888 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1889 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1890 for (i = 0; i < bp->rx_nr_rings; i++) {
1891 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1892 int j;
1893
1894 if (rxr->rx_tpa) {
1895 for (j = 0; j < MAX_TPA; j++) {
1896 struct bnxt_tpa_info *tpa_info =
1897 &rxr->rx_tpa[j];
1898 u8 *data = tpa_info->data;
1899
1900 if (!data)
1901 continue;
1902
1903 dma_unmap_single(
1904 &pdev->dev,
1905 dma_unmap_addr(tpa_info, mapping),
1906 bp->rx_buf_use_size,
1907 PCI_DMA_FROMDEVICE);
1908
1909 tpa_info->data = NULL;
1910
1911 kfree(data);
1912 }
1913 }
1914
1915 for (j = 0; j < max_idx; j++) {
1916 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1917 u8 *data = rx_buf->data;
1918
1919 if (!data)
1920 continue;
1921
1922 dma_unmap_single(&pdev->dev,
1923 dma_unmap_addr(rx_buf, mapping),
1924 bp->rx_buf_use_size,
1925 PCI_DMA_FROMDEVICE);
1926
1927 rx_buf->data = NULL;
1928
1929 kfree(data);
1930 }
1931
1932 for (j = 0; j < max_agg_idx; j++) {
1933 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1934 &rxr->rx_agg_ring[j];
1935 struct page *page = rx_agg_buf->page;
1936
1937 if (!page)
1938 continue;
1939
1940 dma_unmap_page(&pdev->dev,
1941 dma_unmap_addr(rx_agg_buf, mapping),
1942 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
1943
1944 rx_agg_buf->page = NULL;
1945 __clear_bit(j, rxr->rx_agg_bmap);
1946
1947 __free_page(page);
1948 }
1949 if (rxr->rx_page) {
1950 __free_page(rxr->rx_page);
1951 rxr->rx_page = NULL;
1952 }
1953 }
1954 }
1955
1956 static void bnxt_free_skbs(struct bnxt *bp)
1957 {
1958 bnxt_free_tx_skbs(bp);
1959 bnxt_free_rx_skbs(bp);
1960 }
1961
1962 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1963 {
1964 struct pci_dev *pdev = bp->pdev;
1965 int i;
1966
1967 for (i = 0; i < ring->nr_pages; i++) {
1968 if (!ring->pg_arr[i])
1969 continue;
1970
1971 dma_free_coherent(&pdev->dev, ring->page_size,
1972 ring->pg_arr[i], ring->dma_arr[i]);
1973
1974 ring->pg_arr[i] = NULL;
1975 }
1976 if (ring->pg_tbl) {
1977 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1978 ring->pg_tbl, ring->pg_tbl_map);
1979 ring->pg_tbl = NULL;
1980 }
1981 if (ring->vmem_size && *ring->vmem) {
1982 vfree(*ring->vmem);
1983 *ring->vmem = NULL;
1984 }
1985 }
1986
1987 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1988 {
1989 int i;
1990 struct pci_dev *pdev = bp->pdev;
1991
1992 if (ring->nr_pages > 1) {
1993 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1994 ring->nr_pages * 8,
1995 &ring->pg_tbl_map,
1996 GFP_KERNEL);
1997 if (!ring->pg_tbl)
1998 return -ENOMEM;
1999 }
2000
2001 for (i = 0; i < ring->nr_pages; i++) {
2002 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2003 ring->page_size,
2004 &ring->dma_arr[i],
2005 GFP_KERNEL);
2006 if (!ring->pg_arr[i])
2007 return -ENOMEM;
2008
2009 if (ring->nr_pages > 1)
2010 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2011 }
2012
2013 if (ring->vmem_size) {
2014 *ring->vmem = vzalloc(ring->vmem_size);
2015 if (!(*ring->vmem))
2016 return -ENOMEM;
2017 }
2018 return 0;
2019 }
2020
2021 static void bnxt_free_rx_rings(struct bnxt *bp)
2022 {
2023 int i;
2024
2025 if (!bp->rx_ring)
2026 return;
2027
2028 for (i = 0; i < bp->rx_nr_rings; i++) {
2029 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2030 struct bnxt_ring_struct *ring;
2031
2032 kfree(rxr->rx_tpa);
2033 rxr->rx_tpa = NULL;
2034
2035 kfree(rxr->rx_agg_bmap);
2036 rxr->rx_agg_bmap = NULL;
2037
2038 ring = &rxr->rx_ring_struct;
2039 bnxt_free_ring(bp, ring);
2040
2041 ring = &rxr->rx_agg_ring_struct;
2042 bnxt_free_ring(bp, ring);
2043 }
2044 }
2045
2046 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2047 {
2048 int i, rc, agg_rings = 0, tpa_rings = 0;
2049
2050 if (!bp->rx_ring)
2051 return -ENOMEM;
2052
2053 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2054 agg_rings = 1;
2055
2056 if (bp->flags & BNXT_FLAG_TPA)
2057 tpa_rings = 1;
2058
2059 for (i = 0; i < bp->rx_nr_rings; i++) {
2060 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2061 struct bnxt_ring_struct *ring;
2062
2063 ring = &rxr->rx_ring_struct;
2064
2065 rc = bnxt_alloc_ring(bp, ring);
2066 if (rc)
2067 return rc;
2068
2069 if (agg_rings) {
2070 u16 mem_size;
2071
2072 ring = &rxr->rx_agg_ring_struct;
2073 rc = bnxt_alloc_ring(bp, ring);
2074 if (rc)
2075 return rc;
2076
2077 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2078 mem_size = rxr->rx_agg_bmap_size / 8;
2079 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2080 if (!rxr->rx_agg_bmap)
2081 return -ENOMEM;
2082
2083 if (tpa_rings) {
2084 rxr->rx_tpa = kcalloc(MAX_TPA,
2085 sizeof(struct bnxt_tpa_info),
2086 GFP_KERNEL);
2087 if (!rxr->rx_tpa)
2088 return -ENOMEM;
2089 }
2090 }
2091 }
2092 return 0;
2093 }
2094
2095 static void bnxt_free_tx_rings(struct bnxt *bp)
2096 {
2097 int i;
2098 struct pci_dev *pdev = bp->pdev;
2099
2100 if (!bp->tx_ring)
2101 return;
2102
2103 for (i = 0; i < bp->tx_nr_rings; i++) {
2104 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2105 struct bnxt_ring_struct *ring;
2106
2107 if (txr->tx_push) {
2108 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2109 txr->tx_push, txr->tx_push_mapping);
2110 txr->tx_push = NULL;
2111 }
2112
2113 ring = &txr->tx_ring_struct;
2114
2115 bnxt_free_ring(bp, ring);
2116 }
2117 }
2118
2119 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2120 {
2121 int i, j, rc;
2122 struct pci_dev *pdev = bp->pdev;
2123
2124 bp->tx_push_size = 0;
2125 if (bp->tx_push_thresh) {
2126 int push_size;
2127
2128 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2129 bp->tx_push_thresh);
2130
2131 if (push_size > 256) {
2132 push_size = 0;
2133 bp->tx_push_thresh = 0;
2134 }
2135
2136 bp->tx_push_size = push_size;
2137 }
2138
2139 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2140 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2141 struct bnxt_ring_struct *ring;
2142
2143 ring = &txr->tx_ring_struct;
2144
2145 rc = bnxt_alloc_ring(bp, ring);
2146 if (rc)
2147 return rc;
2148
2149 if (bp->tx_push_size) {
2150 dma_addr_t mapping;
2151
2152 /* One pre-allocated DMA buffer to backup
2153 * TX push operation
2154 */
2155 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2156 bp->tx_push_size,
2157 &txr->tx_push_mapping,
2158 GFP_KERNEL);
2159
2160 if (!txr->tx_push)
2161 return -ENOMEM;
2162
2163 mapping = txr->tx_push_mapping +
2164 sizeof(struct tx_push_bd);
2165 txr->data_mapping = cpu_to_le64(mapping);
2166
2167 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2168 }
2169 ring->queue_id = bp->q_info[j].queue_id;
2170 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2171 j++;
2172 }
2173 return 0;
2174 }
2175
2176 static void bnxt_free_cp_rings(struct bnxt *bp)
2177 {
2178 int i;
2179
2180 if (!bp->bnapi)
2181 return;
2182
2183 for (i = 0; i < bp->cp_nr_rings; i++) {
2184 struct bnxt_napi *bnapi = bp->bnapi[i];
2185 struct bnxt_cp_ring_info *cpr;
2186 struct bnxt_ring_struct *ring;
2187
2188 if (!bnapi)
2189 continue;
2190
2191 cpr = &bnapi->cp_ring;
2192 ring = &cpr->cp_ring_struct;
2193
2194 bnxt_free_ring(bp, ring);
2195 }
2196 }
2197
2198 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2199 {
2200 int i, rc;
2201
2202 for (i = 0; i < bp->cp_nr_rings; i++) {
2203 struct bnxt_napi *bnapi = bp->bnapi[i];
2204 struct bnxt_cp_ring_info *cpr;
2205 struct bnxt_ring_struct *ring;
2206
2207 if (!bnapi)
2208 continue;
2209
2210 cpr = &bnapi->cp_ring;
2211 ring = &cpr->cp_ring_struct;
2212
2213 rc = bnxt_alloc_ring(bp, ring);
2214 if (rc)
2215 return rc;
2216 }
2217 return 0;
2218 }
2219
2220 static void bnxt_init_ring_struct(struct bnxt *bp)
2221 {
2222 int i;
2223
2224 for (i = 0; i < bp->cp_nr_rings; i++) {
2225 struct bnxt_napi *bnapi = bp->bnapi[i];
2226 struct bnxt_cp_ring_info *cpr;
2227 struct bnxt_rx_ring_info *rxr;
2228 struct bnxt_tx_ring_info *txr;
2229 struct bnxt_ring_struct *ring;
2230
2231 if (!bnapi)
2232 continue;
2233
2234 cpr = &bnapi->cp_ring;
2235 ring = &cpr->cp_ring_struct;
2236 ring->nr_pages = bp->cp_nr_pages;
2237 ring->page_size = HW_CMPD_RING_SIZE;
2238 ring->pg_arr = (void **)cpr->cp_desc_ring;
2239 ring->dma_arr = cpr->cp_desc_mapping;
2240 ring->vmem_size = 0;
2241
2242 rxr = bnapi->rx_ring;
2243 if (!rxr)
2244 goto skip_rx;
2245
2246 ring = &rxr->rx_ring_struct;
2247 ring->nr_pages = bp->rx_nr_pages;
2248 ring->page_size = HW_RXBD_RING_SIZE;
2249 ring->pg_arr = (void **)rxr->rx_desc_ring;
2250 ring->dma_arr = rxr->rx_desc_mapping;
2251 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2252 ring->vmem = (void **)&rxr->rx_buf_ring;
2253
2254 ring = &rxr->rx_agg_ring_struct;
2255 ring->nr_pages = bp->rx_agg_nr_pages;
2256 ring->page_size = HW_RXBD_RING_SIZE;
2257 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2258 ring->dma_arr = rxr->rx_agg_desc_mapping;
2259 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2260 ring->vmem = (void **)&rxr->rx_agg_ring;
2261
2262 skip_rx:
2263 txr = bnapi->tx_ring;
2264 if (!txr)
2265 continue;
2266
2267 ring = &txr->tx_ring_struct;
2268 ring->nr_pages = bp->tx_nr_pages;
2269 ring->page_size = HW_RXBD_RING_SIZE;
2270 ring->pg_arr = (void **)txr->tx_desc_ring;
2271 ring->dma_arr = txr->tx_desc_mapping;
2272 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2273 ring->vmem = (void **)&txr->tx_buf_ring;
2274 }
2275 }
2276
2277 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2278 {
2279 int i;
2280 u32 prod;
2281 struct rx_bd **rx_buf_ring;
2282
2283 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2284 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2285 int j;
2286 struct rx_bd *rxbd;
2287
2288 rxbd = rx_buf_ring[i];
2289 if (!rxbd)
2290 continue;
2291
2292 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2293 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2294 rxbd->rx_bd_opaque = prod;
2295 }
2296 }
2297 }
2298
2299 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2300 {
2301 struct net_device *dev = bp->dev;
2302 struct bnxt_rx_ring_info *rxr;
2303 struct bnxt_ring_struct *ring;
2304 u32 prod, type;
2305 int i;
2306
2307 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2308 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2309
2310 if (NET_IP_ALIGN == 2)
2311 type |= RX_BD_FLAGS_SOP;
2312
2313 rxr = &bp->rx_ring[ring_nr];
2314 ring = &rxr->rx_ring_struct;
2315 bnxt_init_rxbd_pages(ring, type);
2316
2317 prod = rxr->rx_prod;
2318 for (i = 0; i < bp->rx_ring_size; i++) {
2319 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2320 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2321 ring_nr, i, bp->rx_ring_size);
2322 break;
2323 }
2324 prod = NEXT_RX(prod);
2325 }
2326 rxr->rx_prod = prod;
2327 ring->fw_ring_id = INVALID_HW_RING_ID;
2328
2329 ring = &rxr->rx_agg_ring_struct;
2330 ring->fw_ring_id = INVALID_HW_RING_ID;
2331
2332 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2333 return 0;
2334
2335 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2336 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2337
2338 bnxt_init_rxbd_pages(ring, type);
2339
2340 prod = rxr->rx_agg_prod;
2341 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2342 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2343 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2344 ring_nr, i, bp->rx_ring_size);
2345 break;
2346 }
2347 prod = NEXT_RX_AGG(prod);
2348 }
2349 rxr->rx_agg_prod = prod;
2350
2351 if (bp->flags & BNXT_FLAG_TPA) {
2352 if (rxr->rx_tpa) {
2353 u8 *data;
2354 dma_addr_t mapping;
2355
2356 for (i = 0; i < MAX_TPA; i++) {
2357 data = __bnxt_alloc_rx_data(bp, &mapping,
2358 GFP_KERNEL);
2359 if (!data)
2360 return -ENOMEM;
2361
2362 rxr->rx_tpa[i].data = data;
2363 rxr->rx_tpa[i].mapping = mapping;
2364 }
2365 } else {
2366 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2367 return -ENOMEM;
2368 }
2369 }
2370
2371 return 0;
2372 }
2373
2374 static int bnxt_init_rx_rings(struct bnxt *bp)
2375 {
2376 int i, rc = 0;
2377
2378 for (i = 0; i < bp->rx_nr_rings; i++) {
2379 rc = bnxt_init_one_rx_ring(bp, i);
2380 if (rc)
2381 break;
2382 }
2383
2384 return rc;
2385 }
2386
2387 static int bnxt_init_tx_rings(struct bnxt *bp)
2388 {
2389 u16 i;
2390
2391 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2392 MAX_SKB_FRAGS + 1);
2393
2394 for (i = 0; i < bp->tx_nr_rings; i++) {
2395 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2396 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2397
2398 ring->fw_ring_id = INVALID_HW_RING_ID;
2399 }
2400
2401 return 0;
2402 }
2403
2404 static void bnxt_free_ring_grps(struct bnxt *bp)
2405 {
2406 kfree(bp->grp_info);
2407 bp->grp_info = NULL;
2408 }
2409
2410 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2411 {
2412 int i;
2413
2414 if (irq_re_init) {
2415 bp->grp_info = kcalloc(bp->cp_nr_rings,
2416 sizeof(struct bnxt_ring_grp_info),
2417 GFP_KERNEL);
2418 if (!bp->grp_info)
2419 return -ENOMEM;
2420 }
2421 for (i = 0; i < bp->cp_nr_rings; i++) {
2422 if (irq_re_init)
2423 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2424 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2425 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2426 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2427 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2428 }
2429 return 0;
2430 }
2431
2432 static void bnxt_free_vnics(struct bnxt *bp)
2433 {
2434 kfree(bp->vnic_info);
2435 bp->vnic_info = NULL;
2436 bp->nr_vnics = 0;
2437 }
2438
2439 static int bnxt_alloc_vnics(struct bnxt *bp)
2440 {
2441 int num_vnics = 1;
2442
2443 #ifdef CONFIG_RFS_ACCEL
2444 if (bp->flags & BNXT_FLAG_RFS)
2445 num_vnics += bp->rx_nr_rings;
2446 #endif
2447
2448 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2449 num_vnics++;
2450
2451 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2452 GFP_KERNEL);
2453 if (!bp->vnic_info)
2454 return -ENOMEM;
2455
2456 bp->nr_vnics = num_vnics;
2457 return 0;
2458 }
2459
2460 static void bnxt_init_vnics(struct bnxt *bp)
2461 {
2462 int i;
2463
2464 for (i = 0; i < bp->nr_vnics; i++) {
2465 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2466
2467 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2468 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2469 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2470 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2471
2472 if (bp->vnic_info[i].rss_hash_key) {
2473 if (i == 0)
2474 prandom_bytes(vnic->rss_hash_key,
2475 HW_HASH_KEY_SIZE);
2476 else
2477 memcpy(vnic->rss_hash_key,
2478 bp->vnic_info[0].rss_hash_key,
2479 HW_HASH_KEY_SIZE);
2480 }
2481 }
2482 }
2483
2484 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2485 {
2486 int pages;
2487
2488 pages = ring_size / desc_per_pg;
2489
2490 if (!pages)
2491 return 1;
2492
2493 pages++;
2494
2495 while (pages & (pages - 1))
2496 pages++;
2497
2498 return pages;
2499 }
2500
2501 static void bnxt_set_tpa_flags(struct bnxt *bp)
2502 {
2503 bp->flags &= ~BNXT_FLAG_TPA;
2504 if (bp->dev->features & NETIF_F_LRO)
2505 bp->flags |= BNXT_FLAG_LRO;
2506 if (bp->dev->features & NETIF_F_GRO)
2507 bp->flags |= BNXT_FLAG_GRO;
2508 }
2509
2510 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2511 * be set on entry.
2512 */
2513 void bnxt_set_ring_params(struct bnxt *bp)
2514 {
2515 u32 ring_size, rx_size, rx_space;
2516 u32 agg_factor = 0, agg_ring_size = 0;
2517
2518 /* 8 for CRC and VLAN */
2519 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2520
2521 rx_space = rx_size + NET_SKB_PAD +
2522 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2523
2524 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2525 ring_size = bp->rx_ring_size;
2526 bp->rx_agg_ring_size = 0;
2527 bp->rx_agg_nr_pages = 0;
2528
2529 if (bp->flags & BNXT_FLAG_TPA)
2530 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2531
2532 bp->flags &= ~BNXT_FLAG_JUMBO;
2533 if (rx_space > PAGE_SIZE) {
2534 u32 jumbo_factor;
2535
2536 bp->flags |= BNXT_FLAG_JUMBO;
2537 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2538 if (jumbo_factor > agg_factor)
2539 agg_factor = jumbo_factor;
2540 }
2541 agg_ring_size = ring_size * agg_factor;
2542
2543 if (agg_ring_size) {
2544 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2545 RX_DESC_CNT);
2546 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2547 u32 tmp = agg_ring_size;
2548
2549 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2550 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2551 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2552 tmp, agg_ring_size);
2553 }
2554 bp->rx_agg_ring_size = agg_ring_size;
2555 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2556 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2557 rx_space = rx_size + NET_SKB_PAD +
2558 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2559 }
2560
2561 bp->rx_buf_use_size = rx_size;
2562 bp->rx_buf_size = rx_space;
2563
2564 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2565 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2566
2567 ring_size = bp->tx_ring_size;
2568 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2569 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2570
2571 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2572 bp->cp_ring_size = ring_size;
2573
2574 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2575 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2576 bp->cp_nr_pages = MAX_CP_PAGES;
2577 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2578 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2579 ring_size, bp->cp_ring_size);
2580 }
2581 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2582 bp->cp_ring_mask = bp->cp_bit - 1;
2583 }
2584
2585 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2586 {
2587 int i;
2588 struct bnxt_vnic_info *vnic;
2589 struct pci_dev *pdev = bp->pdev;
2590
2591 if (!bp->vnic_info)
2592 return;
2593
2594 for (i = 0; i < bp->nr_vnics; i++) {
2595 vnic = &bp->vnic_info[i];
2596
2597 kfree(vnic->fw_grp_ids);
2598 vnic->fw_grp_ids = NULL;
2599
2600 kfree(vnic->uc_list);
2601 vnic->uc_list = NULL;
2602
2603 if (vnic->mc_list) {
2604 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2605 vnic->mc_list, vnic->mc_list_mapping);
2606 vnic->mc_list = NULL;
2607 }
2608
2609 if (vnic->rss_table) {
2610 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2611 vnic->rss_table,
2612 vnic->rss_table_dma_addr);
2613 vnic->rss_table = NULL;
2614 }
2615
2616 vnic->rss_hash_key = NULL;
2617 vnic->flags = 0;
2618 }
2619 }
2620
2621 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2622 {
2623 int i, rc = 0, size;
2624 struct bnxt_vnic_info *vnic;
2625 struct pci_dev *pdev = bp->pdev;
2626 int max_rings;
2627
2628 for (i = 0; i < bp->nr_vnics; i++) {
2629 vnic = &bp->vnic_info[i];
2630
2631 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2632 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2633
2634 if (mem_size > 0) {
2635 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2636 if (!vnic->uc_list) {
2637 rc = -ENOMEM;
2638 goto out;
2639 }
2640 }
2641 }
2642
2643 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2644 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2645 vnic->mc_list =
2646 dma_alloc_coherent(&pdev->dev,
2647 vnic->mc_list_size,
2648 &vnic->mc_list_mapping,
2649 GFP_KERNEL);
2650 if (!vnic->mc_list) {
2651 rc = -ENOMEM;
2652 goto out;
2653 }
2654 }
2655
2656 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2657 max_rings = bp->rx_nr_rings;
2658 else
2659 max_rings = 1;
2660
2661 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2662 if (!vnic->fw_grp_ids) {
2663 rc = -ENOMEM;
2664 goto out;
2665 }
2666
2667 /* Allocate rss table and hash key */
2668 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2669 &vnic->rss_table_dma_addr,
2670 GFP_KERNEL);
2671 if (!vnic->rss_table) {
2672 rc = -ENOMEM;
2673 goto out;
2674 }
2675
2676 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2677
2678 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2679 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2680 }
2681 return 0;
2682
2683 out:
2684 return rc;
2685 }
2686
2687 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2688 {
2689 struct pci_dev *pdev = bp->pdev;
2690
2691 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2692 bp->hwrm_cmd_resp_dma_addr);
2693
2694 bp->hwrm_cmd_resp_addr = NULL;
2695 if (bp->hwrm_dbg_resp_addr) {
2696 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2697 bp->hwrm_dbg_resp_addr,
2698 bp->hwrm_dbg_resp_dma_addr);
2699
2700 bp->hwrm_dbg_resp_addr = NULL;
2701 }
2702 }
2703
2704 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2705 {
2706 struct pci_dev *pdev = bp->pdev;
2707
2708 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2709 &bp->hwrm_cmd_resp_dma_addr,
2710 GFP_KERNEL);
2711 if (!bp->hwrm_cmd_resp_addr)
2712 return -ENOMEM;
2713 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2714 HWRM_DBG_REG_BUF_SIZE,
2715 &bp->hwrm_dbg_resp_dma_addr,
2716 GFP_KERNEL);
2717 if (!bp->hwrm_dbg_resp_addr)
2718 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2719
2720 return 0;
2721 }
2722
2723 static void bnxt_free_stats(struct bnxt *bp)
2724 {
2725 u32 size, i;
2726 struct pci_dev *pdev = bp->pdev;
2727
2728 if (bp->hw_rx_port_stats) {
2729 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2730 bp->hw_rx_port_stats,
2731 bp->hw_rx_port_stats_map);
2732 bp->hw_rx_port_stats = NULL;
2733 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2734 }
2735
2736 if (!bp->bnapi)
2737 return;
2738
2739 size = sizeof(struct ctx_hw_stats);
2740
2741 for (i = 0; i < bp->cp_nr_rings; i++) {
2742 struct bnxt_napi *bnapi = bp->bnapi[i];
2743 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2744
2745 if (cpr->hw_stats) {
2746 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2747 cpr->hw_stats_map);
2748 cpr->hw_stats = NULL;
2749 }
2750 }
2751 }
2752
2753 static int bnxt_alloc_stats(struct bnxt *bp)
2754 {
2755 u32 size, i;
2756 struct pci_dev *pdev = bp->pdev;
2757
2758 size = sizeof(struct ctx_hw_stats);
2759
2760 for (i = 0; i < bp->cp_nr_rings; i++) {
2761 struct bnxt_napi *bnapi = bp->bnapi[i];
2762 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2763
2764 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2765 &cpr->hw_stats_map,
2766 GFP_KERNEL);
2767 if (!cpr->hw_stats)
2768 return -ENOMEM;
2769
2770 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2771 }
2772
2773 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
2774 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2775 sizeof(struct tx_port_stats) + 1024;
2776
2777 bp->hw_rx_port_stats =
2778 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2779 &bp->hw_rx_port_stats_map,
2780 GFP_KERNEL);
2781 if (!bp->hw_rx_port_stats)
2782 return -ENOMEM;
2783
2784 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2785 512;
2786 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2787 sizeof(struct rx_port_stats) + 512;
2788 bp->flags |= BNXT_FLAG_PORT_STATS;
2789 }
2790 return 0;
2791 }
2792
2793 static void bnxt_clear_ring_indices(struct bnxt *bp)
2794 {
2795 int i;
2796
2797 if (!bp->bnapi)
2798 return;
2799
2800 for (i = 0; i < bp->cp_nr_rings; i++) {
2801 struct bnxt_napi *bnapi = bp->bnapi[i];
2802 struct bnxt_cp_ring_info *cpr;
2803 struct bnxt_rx_ring_info *rxr;
2804 struct bnxt_tx_ring_info *txr;
2805
2806 if (!bnapi)
2807 continue;
2808
2809 cpr = &bnapi->cp_ring;
2810 cpr->cp_raw_cons = 0;
2811
2812 txr = bnapi->tx_ring;
2813 if (txr) {
2814 txr->tx_prod = 0;
2815 txr->tx_cons = 0;
2816 }
2817
2818 rxr = bnapi->rx_ring;
2819 if (rxr) {
2820 rxr->rx_prod = 0;
2821 rxr->rx_agg_prod = 0;
2822 rxr->rx_sw_agg_prod = 0;
2823 rxr->rx_next_cons = 0;
2824 }
2825 }
2826 }
2827
2828 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2829 {
2830 #ifdef CONFIG_RFS_ACCEL
2831 int i;
2832
2833 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2834 * safe to delete the hash table.
2835 */
2836 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2837 struct hlist_head *head;
2838 struct hlist_node *tmp;
2839 struct bnxt_ntuple_filter *fltr;
2840
2841 head = &bp->ntp_fltr_hash_tbl[i];
2842 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2843 hlist_del(&fltr->hash);
2844 kfree(fltr);
2845 }
2846 }
2847 if (irq_reinit) {
2848 kfree(bp->ntp_fltr_bmap);
2849 bp->ntp_fltr_bmap = NULL;
2850 }
2851 bp->ntp_fltr_count = 0;
2852 #endif
2853 }
2854
2855 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2856 {
2857 #ifdef CONFIG_RFS_ACCEL
2858 int i, rc = 0;
2859
2860 if (!(bp->flags & BNXT_FLAG_RFS))
2861 return 0;
2862
2863 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2864 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2865
2866 bp->ntp_fltr_count = 0;
2867 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2868 GFP_KERNEL);
2869
2870 if (!bp->ntp_fltr_bmap)
2871 rc = -ENOMEM;
2872
2873 return rc;
2874 #else
2875 return 0;
2876 #endif
2877 }
2878
2879 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2880 {
2881 bnxt_free_vnic_attributes(bp);
2882 bnxt_free_tx_rings(bp);
2883 bnxt_free_rx_rings(bp);
2884 bnxt_free_cp_rings(bp);
2885 bnxt_free_ntp_fltrs(bp, irq_re_init);
2886 if (irq_re_init) {
2887 bnxt_free_stats(bp);
2888 bnxt_free_ring_grps(bp);
2889 bnxt_free_vnics(bp);
2890 kfree(bp->tx_ring);
2891 bp->tx_ring = NULL;
2892 kfree(bp->rx_ring);
2893 bp->rx_ring = NULL;
2894 kfree(bp->bnapi);
2895 bp->bnapi = NULL;
2896 } else {
2897 bnxt_clear_ring_indices(bp);
2898 }
2899 }
2900
2901 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2902 {
2903 int i, j, rc, size, arr_size;
2904 void *bnapi;
2905
2906 if (irq_re_init) {
2907 /* Allocate bnapi mem pointer array and mem block for
2908 * all queues
2909 */
2910 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2911 bp->cp_nr_rings);
2912 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2913 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2914 if (!bnapi)
2915 return -ENOMEM;
2916
2917 bp->bnapi = bnapi;
2918 bnapi += arr_size;
2919 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2920 bp->bnapi[i] = bnapi;
2921 bp->bnapi[i]->index = i;
2922 bp->bnapi[i]->bp = bp;
2923 }
2924
2925 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2926 sizeof(struct bnxt_rx_ring_info),
2927 GFP_KERNEL);
2928 if (!bp->rx_ring)
2929 return -ENOMEM;
2930
2931 for (i = 0; i < bp->rx_nr_rings; i++) {
2932 bp->rx_ring[i].bnapi = bp->bnapi[i];
2933 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2934 }
2935
2936 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2937 sizeof(struct bnxt_tx_ring_info),
2938 GFP_KERNEL);
2939 if (!bp->tx_ring)
2940 return -ENOMEM;
2941
2942 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2943 j = 0;
2944 else
2945 j = bp->rx_nr_rings;
2946
2947 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2948 bp->tx_ring[i].bnapi = bp->bnapi[j];
2949 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
2950 }
2951
2952 rc = bnxt_alloc_stats(bp);
2953 if (rc)
2954 goto alloc_mem_err;
2955
2956 rc = bnxt_alloc_ntp_fltrs(bp);
2957 if (rc)
2958 goto alloc_mem_err;
2959
2960 rc = bnxt_alloc_vnics(bp);
2961 if (rc)
2962 goto alloc_mem_err;
2963 }
2964
2965 bnxt_init_ring_struct(bp);
2966
2967 rc = bnxt_alloc_rx_rings(bp);
2968 if (rc)
2969 goto alloc_mem_err;
2970
2971 rc = bnxt_alloc_tx_rings(bp);
2972 if (rc)
2973 goto alloc_mem_err;
2974
2975 rc = bnxt_alloc_cp_rings(bp);
2976 if (rc)
2977 goto alloc_mem_err;
2978
2979 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2980 BNXT_VNIC_UCAST_FLAG;
2981 rc = bnxt_alloc_vnic_attributes(bp);
2982 if (rc)
2983 goto alloc_mem_err;
2984 return 0;
2985
2986 alloc_mem_err:
2987 bnxt_free_mem(bp, true);
2988 return rc;
2989 }
2990
2991 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2992 u16 cmpl_ring, u16 target_id)
2993 {
2994 struct input *req = request;
2995
2996 req->req_type = cpu_to_le16(req_type);
2997 req->cmpl_ring = cpu_to_le16(cmpl_ring);
2998 req->target_id = cpu_to_le16(target_id);
2999 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3000 }
3001
3002 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3003 int timeout, bool silent)
3004 {
3005 int i, intr_process, rc, tmo_count;
3006 struct input *req = msg;
3007 u32 *data = msg;
3008 __le32 *resp_len, *valid;
3009 u16 cp_ring_id, len = 0;
3010 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3011
3012 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3013 memset(resp, 0, PAGE_SIZE);
3014 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3015 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3016
3017 /* Write request msg to hwrm channel */
3018 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3019
3020 for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
3021 writel(0, bp->bar0 + i);
3022
3023 /* currently supports only one outstanding message */
3024 if (intr_process)
3025 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3026
3027 /* Ring channel doorbell */
3028 writel(1, bp->bar0 + 0x100);
3029
3030 if (!timeout)
3031 timeout = DFLT_HWRM_CMD_TIMEOUT;
3032
3033 i = 0;
3034 tmo_count = timeout * 40;
3035 if (intr_process) {
3036 /* Wait until hwrm response cmpl interrupt is processed */
3037 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3038 i++ < tmo_count) {
3039 usleep_range(25, 40);
3040 }
3041
3042 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3043 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3044 le16_to_cpu(req->req_type));
3045 return -1;
3046 }
3047 } else {
3048 /* Check if response len is updated */
3049 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3050 for (i = 0; i < tmo_count; i++) {
3051 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3052 HWRM_RESP_LEN_SFT;
3053 if (len)
3054 break;
3055 usleep_range(25, 40);
3056 }
3057
3058 if (i >= tmo_count) {
3059 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3060 timeout, le16_to_cpu(req->req_type),
3061 le16_to_cpu(req->seq_id), len);
3062 return -1;
3063 }
3064
3065 /* Last word of resp contains valid bit */
3066 valid = bp->hwrm_cmd_resp_addr + len - 4;
3067 for (i = 0; i < 5; i++) {
3068 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3069 break;
3070 udelay(1);
3071 }
3072
3073 if (i >= 5) {
3074 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3075 timeout, le16_to_cpu(req->req_type),
3076 le16_to_cpu(req->seq_id), len, *valid);
3077 return -1;
3078 }
3079 }
3080
3081 rc = le16_to_cpu(resp->error_code);
3082 if (rc && !silent)
3083 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3084 le16_to_cpu(resp->req_type),
3085 le16_to_cpu(resp->seq_id), rc);
3086 return rc;
3087 }
3088
3089 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3090 {
3091 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3092 }
3093
3094 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3095 {
3096 int rc;
3097
3098 mutex_lock(&bp->hwrm_cmd_lock);
3099 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3100 mutex_unlock(&bp->hwrm_cmd_lock);
3101 return rc;
3102 }
3103
3104 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3105 int timeout)
3106 {
3107 int rc;
3108
3109 mutex_lock(&bp->hwrm_cmd_lock);
3110 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3111 mutex_unlock(&bp->hwrm_cmd_lock);
3112 return rc;
3113 }
3114
3115 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3116 {
3117 struct hwrm_func_drv_rgtr_input req = {0};
3118 int i;
3119 DECLARE_BITMAP(async_events_bmap, 256);
3120 u32 *events = (u32 *)async_events_bmap;
3121
3122 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3123
3124 req.enables =
3125 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3126 FUNC_DRV_RGTR_REQ_ENABLES_VER |
3127 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3128
3129 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3130 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3131 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3132
3133 for (i = 0; i < 8; i++)
3134 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3135
3136 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3137 req.ver_maj = DRV_VER_MAJ;
3138 req.ver_min = DRV_VER_MIN;
3139 req.ver_upd = DRV_VER_UPD;
3140
3141 if (BNXT_PF(bp)) {
3142 DECLARE_BITMAP(vf_req_snif_bmap, 256);
3143 u32 *data = (u32 *)vf_req_snif_bmap;
3144
3145 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
3146 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3147 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3148
3149 for (i = 0; i < 8; i++)
3150 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3151
3152 req.enables |=
3153 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3154 }
3155
3156 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3157 }
3158
3159 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3160 {
3161 struct hwrm_func_drv_unrgtr_input req = {0};
3162
3163 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3164 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3165 }
3166
3167 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3168 {
3169 u32 rc = 0;
3170 struct hwrm_tunnel_dst_port_free_input req = {0};
3171
3172 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3173 req.tunnel_type = tunnel_type;
3174
3175 switch (tunnel_type) {
3176 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3177 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3178 break;
3179 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3180 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3181 break;
3182 default:
3183 break;
3184 }
3185
3186 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3187 if (rc)
3188 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3189 rc);
3190 return rc;
3191 }
3192
3193 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3194 u8 tunnel_type)
3195 {
3196 u32 rc = 0;
3197 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3198 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3199
3200 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3201
3202 req.tunnel_type = tunnel_type;
3203 req.tunnel_dst_port_val = port;
3204
3205 mutex_lock(&bp->hwrm_cmd_lock);
3206 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3207 if (rc) {
3208 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3209 rc);
3210 goto err_out;
3211 }
3212
3213 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
3214 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3215
3216 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
3217 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3218 err_out:
3219 mutex_unlock(&bp->hwrm_cmd_lock);
3220 return rc;
3221 }
3222
3223 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3224 {
3225 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3226 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3227
3228 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3229 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3230
3231 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3232 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3233 req.mask = cpu_to_le32(vnic->rx_mask);
3234 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3235 }
3236
3237 #ifdef CONFIG_RFS_ACCEL
3238 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3239 struct bnxt_ntuple_filter *fltr)
3240 {
3241 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3242
3243 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3244 req.ntuple_filter_id = fltr->filter_id;
3245 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3246 }
3247
3248 #define BNXT_NTP_FLTR_FLAGS \
3249 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3250 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3251 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3252 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3253 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3254 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3255 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3256 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3257 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3258 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3259 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3260 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3261 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3262 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3263
3264 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3265 struct bnxt_ntuple_filter *fltr)
3266 {
3267 int rc = 0;
3268 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3269 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3270 bp->hwrm_cmd_resp_addr;
3271 struct flow_keys *keys = &fltr->fkeys;
3272 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3273
3274 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3275 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3276
3277 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3278
3279 req.ethertype = htons(ETH_P_IP);
3280 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3281 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3282 req.ip_protocol = keys->basic.ip_proto;
3283
3284 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3285 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3286 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3287 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3288
3289 req.src_port = keys->ports.src;
3290 req.src_port_mask = cpu_to_be16(0xffff);
3291 req.dst_port = keys->ports.dst;
3292 req.dst_port_mask = cpu_to_be16(0xffff);
3293
3294 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3295 mutex_lock(&bp->hwrm_cmd_lock);
3296 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3297 if (!rc)
3298 fltr->filter_id = resp->ntuple_filter_id;
3299 mutex_unlock(&bp->hwrm_cmd_lock);
3300 return rc;
3301 }
3302 #endif
3303
3304 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3305 u8 *mac_addr)
3306 {
3307 u32 rc = 0;
3308 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3309 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3310
3311 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3312 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3313 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3314 req.flags |=
3315 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3316 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3317 req.enables =
3318 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3319 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3320 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3321 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3322 req.l2_addr_mask[0] = 0xff;
3323 req.l2_addr_mask[1] = 0xff;
3324 req.l2_addr_mask[2] = 0xff;
3325 req.l2_addr_mask[3] = 0xff;
3326 req.l2_addr_mask[4] = 0xff;
3327 req.l2_addr_mask[5] = 0xff;
3328
3329 mutex_lock(&bp->hwrm_cmd_lock);
3330 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3331 if (!rc)
3332 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3333 resp->l2_filter_id;
3334 mutex_unlock(&bp->hwrm_cmd_lock);
3335 return rc;
3336 }
3337
3338 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3339 {
3340 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3341 int rc = 0;
3342
3343 /* Any associated ntuple filters will also be cleared by firmware. */
3344 mutex_lock(&bp->hwrm_cmd_lock);
3345 for (i = 0; i < num_of_vnics; i++) {
3346 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3347
3348 for (j = 0; j < vnic->uc_filter_count; j++) {
3349 struct hwrm_cfa_l2_filter_free_input req = {0};
3350
3351 bnxt_hwrm_cmd_hdr_init(bp, &req,
3352 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3353
3354 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3355
3356 rc = _hwrm_send_message(bp, &req, sizeof(req),
3357 HWRM_CMD_TIMEOUT);
3358 }
3359 vnic->uc_filter_count = 0;
3360 }
3361 mutex_unlock(&bp->hwrm_cmd_lock);
3362
3363 return rc;
3364 }
3365
3366 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3367 {
3368 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3369 struct hwrm_vnic_tpa_cfg_input req = {0};
3370
3371 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3372
3373 if (tpa_flags) {
3374 u16 mss = bp->dev->mtu - 40;
3375 u32 nsegs, n, segs = 0, flags;
3376
3377 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3378 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3379 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3380 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3381 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3382 if (tpa_flags & BNXT_FLAG_GRO)
3383 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3384
3385 req.flags = cpu_to_le32(flags);
3386
3387 req.enables =
3388 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3389 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3390 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3391
3392 /* Number of segs are log2 units, and first packet is not
3393 * included as part of this units.
3394 */
3395 if (mss <= BNXT_RX_PAGE_SIZE) {
3396 n = BNXT_RX_PAGE_SIZE / mss;
3397 nsegs = (MAX_SKB_FRAGS - 1) * n;
3398 } else {
3399 n = mss / BNXT_RX_PAGE_SIZE;
3400 if (mss & (BNXT_RX_PAGE_SIZE - 1))
3401 n++;
3402 nsegs = (MAX_SKB_FRAGS - n) / n;
3403 }
3404
3405 segs = ilog2(nsegs);
3406 req.max_agg_segs = cpu_to_le16(segs);
3407 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3408
3409 req.min_agg_len = cpu_to_le32(512);
3410 }
3411 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3412
3413 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3414 }
3415
3416 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3417 {
3418 u32 i, j, max_rings;
3419 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3420 struct hwrm_vnic_rss_cfg_input req = {0};
3421
3422 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3423 return 0;
3424
3425 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3426 if (set_rss) {
3427 vnic->hash_type = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
3428 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
3429 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
3430 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
3431
3432 req.hash_type = cpu_to_le32(vnic->hash_type);
3433
3434 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3435 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3436 max_rings = bp->rx_nr_rings - 1;
3437 else
3438 max_rings = bp->rx_nr_rings;
3439 } else {
3440 max_rings = 1;
3441 }
3442
3443 /* Fill the RSS indirection table with ring group ids */
3444 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3445 if (j == max_rings)
3446 j = 0;
3447 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3448 }
3449
3450 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3451 req.hash_key_tbl_addr =
3452 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3453 }
3454 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3455 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3456 }
3457
3458 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3459 {
3460 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3461 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3462
3463 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3464 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3465 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3466 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3467 req.enables =
3468 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3469 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3470 /* thresholds not implemented in firmware yet */
3471 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3472 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3473 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3474 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3475 }
3476
3477 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3478 u16 ctx_idx)
3479 {
3480 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3481
3482 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3483 req.rss_cos_lb_ctx_id =
3484 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
3485
3486 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3487 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
3488 }
3489
3490 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3491 {
3492 int i, j;
3493
3494 for (i = 0; i < bp->nr_vnics; i++) {
3495 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3496
3497 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3498 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3499 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3500 }
3501 }
3502 bp->rsscos_nr_ctxs = 0;
3503 }
3504
3505 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
3506 {
3507 int rc;
3508 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3509 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3510 bp->hwrm_cmd_resp_addr;
3511
3512 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3513 -1);
3514
3515 mutex_lock(&bp->hwrm_cmd_lock);
3516 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3517 if (!rc)
3518 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
3519 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3520 mutex_unlock(&bp->hwrm_cmd_lock);
3521
3522 return rc;
3523 }
3524
3525 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3526 {
3527 unsigned int ring = 0, grp_idx;
3528 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3529 struct hwrm_vnic_cfg_input req = {0};
3530 u16 def_vlan = 0;
3531
3532 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3533
3534 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
3535 /* Only RSS support for now TBD: COS & LB */
3536 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3537 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3538 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3539 VNIC_CFG_REQ_ENABLES_MRU);
3540 } else {
3541 req.rss_rule = cpu_to_le16(0xffff);
3542 }
3543
3544 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3545 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
3546 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3547 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3548 } else {
3549 req.cos_rule = cpu_to_le16(0xffff);
3550 }
3551
3552 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3553 ring = 0;
3554 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3555 ring = vnic_id - 1;
3556 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
3557 ring = bp->rx_nr_rings - 1;
3558
3559 grp_idx = bp->rx_ring[ring].bnapi->index;
3560 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3561 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3562
3563 req.lb_rule = cpu_to_le16(0xffff);
3564 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3565 VLAN_HLEN);
3566
3567 #ifdef CONFIG_BNXT_SRIOV
3568 if (BNXT_VF(bp))
3569 def_vlan = bp->vf.vlan;
3570 #endif
3571 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
3572 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3573
3574 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3575 }
3576
3577 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3578 {
3579 u32 rc = 0;
3580
3581 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3582 struct hwrm_vnic_free_input req = {0};
3583
3584 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3585 req.vnic_id =
3586 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3587
3588 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3589 if (rc)
3590 return rc;
3591 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3592 }
3593 return rc;
3594 }
3595
3596 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3597 {
3598 u16 i;
3599
3600 for (i = 0; i < bp->nr_vnics; i++)
3601 bnxt_hwrm_vnic_free_one(bp, i);
3602 }
3603
3604 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3605 unsigned int start_rx_ring_idx,
3606 unsigned int nr_rings)
3607 {
3608 int rc = 0;
3609 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3610 struct hwrm_vnic_alloc_input req = {0};
3611 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3612
3613 /* map ring groups to this vnic */
3614 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3615 grp_idx = bp->rx_ring[i].bnapi->index;
3616 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3617 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3618 j, nr_rings);
3619 break;
3620 }
3621 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3622 bp->grp_info[grp_idx].fw_grp_id;
3623 }
3624
3625 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
3626 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
3627 if (vnic_id == 0)
3628 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3629
3630 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3631
3632 mutex_lock(&bp->hwrm_cmd_lock);
3633 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3634 if (!rc)
3635 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3636 mutex_unlock(&bp->hwrm_cmd_lock);
3637 return rc;
3638 }
3639
3640 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3641 {
3642 u16 i;
3643 u32 rc = 0;
3644
3645 mutex_lock(&bp->hwrm_cmd_lock);
3646 for (i = 0; i < bp->rx_nr_rings; i++) {
3647 struct hwrm_ring_grp_alloc_input req = {0};
3648 struct hwrm_ring_grp_alloc_output *resp =
3649 bp->hwrm_cmd_resp_addr;
3650 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3651
3652 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3653
3654 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3655 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3656 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3657 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3658
3659 rc = _hwrm_send_message(bp, &req, sizeof(req),
3660 HWRM_CMD_TIMEOUT);
3661 if (rc)
3662 break;
3663
3664 bp->grp_info[grp_idx].fw_grp_id =
3665 le32_to_cpu(resp->ring_group_id);
3666 }
3667 mutex_unlock(&bp->hwrm_cmd_lock);
3668 return rc;
3669 }
3670
3671 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3672 {
3673 u16 i;
3674 u32 rc = 0;
3675 struct hwrm_ring_grp_free_input req = {0};
3676
3677 if (!bp->grp_info)
3678 return 0;
3679
3680 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3681
3682 mutex_lock(&bp->hwrm_cmd_lock);
3683 for (i = 0; i < bp->cp_nr_rings; i++) {
3684 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3685 continue;
3686 req.ring_group_id =
3687 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3688
3689 rc = _hwrm_send_message(bp, &req, sizeof(req),
3690 HWRM_CMD_TIMEOUT);
3691 if (rc)
3692 break;
3693 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3694 }
3695 mutex_unlock(&bp->hwrm_cmd_lock);
3696 return rc;
3697 }
3698
3699 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3700 struct bnxt_ring_struct *ring,
3701 u32 ring_type, u32 map_index,
3702 u32 stats_ctx_id)
3703 {
3704 int rc = 0, err = 0;
3705 struct hwrm_ring_alloc_input req = {0};
3706 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3707 u16 ring_id;
3708
3709 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3710
3711 req.enables = 0;
3712 if (ring->nr_pages > 1) {
3713 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3714 /* Page size is in log2 units */
3715 req.page_size = BNXT_PAGE_SHIFT;
3716 req.page_tbl_depth = 1;
3717 } else {
3718 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3719 }
3720 req.fbo = 0;
3721 /* Association of ring index with doorbell index and MSIX number */
3722 req.logical_id = cpu_to_le16(map_index);
3723
3724 switch (ring_type) {
3725 case HWRM_RING_ALLOC_TX:
3726 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3727 /* Association of transmit ring with completion ring */
3728 req.cmpl_ring_id =
3729 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3730 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3731 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3732 req.queue_id = cpu_to_le16(ring->queue_id);
3733 break;
3734 case HWRM_RING_ALLOC_RX:
3735 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3736 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3737 break;
3738 case HWRM_RING_ALLOC_AGG:
3739 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3740 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3741 break;
3742 case HWRM_RING_ALLOC_CMPL:
3743 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3744 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3745 if (bp->flags & BNXT_FLAG_USING_MSIX)
3746 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3747 break;
3748 default:
3749 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3750 ring_type);
3751 return -1;
3752 }
3753
3754 mutex_lock(&bp->hwrm_cmd_lock);
3755 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3756 err = le16_to_cpu(resp->error_code);
3757 ring_id = le16_to_cpu(resp->ring_id);
3758 mutex_unlock(&bp->hwrm_cmd_lock);
3759
3760 if (rc || err) {
3761 switch (ring_type) {
3762 case RING_FREE_REQ_RING_TYPE_CMPL:
3763 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3764 rc, err);
3765 return -1;
3766
3767 case RING_FREE_REQ_RING_TYPE_RX:
3768 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3769 rc, err);
3770 return -1;
3771
3772 case RING_FREE_REQ_RING_TYPE_TX:
3773 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3774 rc, err);
3775 return -1;
3776
3777 default:
3778 netdev_err(bp->dev, "Invalid ring\n");
3779 return -1;
3780 }
3781 }
3782 ring->fw_ring_id = ring_id;
3783 return rc;
3784 }
3785
3786 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3787 {
3788 int i, rc = 0;
3789
3790 for (i = 0; i < bp->cp_nr_rings; i++) {
3791 struct bnxt_napi *bnapi = bp->bnapi[i];
3792 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3793 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3794
3795 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3796 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3797 INVALID_STATS_CTX_ID);
3798 if (rc)
3799 goto err_out;
3800 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3801 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3802 }
3803
3804 for (i = 0; i < bp->tx_nr_rings; i++) {
3805 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3806 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3807 u32 map_idx = txr->bnapi->index;
3808 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
3809
3810 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3811 map_idx, fw_stats_ctx);
3812 if (rc)
3813 goto err_out;
3814 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
3815 }
3816
3817 for (i = 0; i < bp->rx_nr_rings; i++) {
3818 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3819 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3820 u32 map_idx = rxr->bnapi->index;
3821
3822 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3823 map_idx, INVALID_STATS_CTX_ID);
3824 if (rc)
3825 goto err_out;
3826 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
3827 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3828 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3829 }
3830
3831 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3832 for (i = 0; i < bp->rx_nr_rings; i++) {
3833 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3834 struct bnxt_ring_struct *ring =
3835 &rxr->rx_agg_ring_struct;
3836 u32 grp_idx = rxr->bnapi->index;
3837 u32 map_idx = grp_idx + bp->rx_nr_rings;
3838
3839 rc = hwrm_ring_alloc_send_msg(bp, ring,
3840 HWRM_RING_ALLOC_AGG,
3841 map_idx,
3842 INVALID_STATS_CTX_ID);
3843 if (rc)
3844 goto err_out;
3845
3846 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
3847 writel(DB_KEY_RX | rxr->rx_agg_prod,
3848 rxr->rx_agg_doorbell);
3849 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
3850 }
3851 }
3852 err_out:
3853 return rc;
3854 }
3855
3856 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3857 struct bnxt_ring_struct *ring,
3858 u32 ring_type, int cmpl_ring_id)
3859 {
3860 int rc;
3861 struct hwrm_ring_free_input req = {0};
3862 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3863 u16 error_code;
3864
3865 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
3866 req.ring_type = ring_type;
3867 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3868
3869 mutex_lock(&bp->hwrm_cmd_lock);
3870 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3871 error_code = le16_to_cpu(resp->error_code);
3872 mutex_unlock(&bp->hwrm_cmd_lock);
3873
3874 if (rc || error_code) {
3875 switch (ring_type) {
3876 case RING_FREE_REQ_RING_TYPE_CMPL:
3877 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3878 rc);
3879 return rc;
3880 case RING_FREE_REQ_RING_TYPE_RX:
3881 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3882 rc);
3883 return rc;
3884 case RING_FREE_REQ_RING_TYPE_TX:
3885 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3886 rc);
3887 return rc;
3888 default:
3889 netdev_err(bp->dev, "Invalid ring\n");
3890 return -1;
3891 }
3892 }
3893 return 0;
3894 }
3895
3896 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3897 {
3898 int i;
3899
3900 if (!bp->bnapi)
3901 return;
3902
3903 for (i = 0; i < bp->tx_nr_rings; i++) {
3904 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3905 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3906 u32 grp_idx = txr->bnapi->index;
3907 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3908
3909 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3910 hwrm_ring_free_send_msg(bp, ring,
3911 RING_FREE_REQ_RING_TYPE_TX,
3912 close_path ? cmpl_ring_id :
3913 INVALID_HW_RING_ID);
3914 ring->fw_ring_id = INVALID_HW_RING_ID;
3915 }
3916 }
3917
3918 for (i = 0; i < bp->rx_nr_rings; i++) {
3919 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3920 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3921 u32 grp_idx = rxr->bnapi->index;
3922 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3923
3924 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3925 hwrm_ring_free_send_msg(bp, ring,
3926 RING_FREE_REQ_RING_TYPE_RX,
3927 close_path ? cmpl_ring_id :
3928 INVALID_HW_RING_ID);
3929 ring->fw_ring_id = INVALID_HW_RING_ID;
3930 bp->grp_info[grp_idx].rx_fw_ring_id =
3931 INVALID_HW_RING_ID;
3932 }
3933 }
3934
3935 for (i = 0; i < bp->rx_nr_rings; i++) {
3936 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3937 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3938 u32 grp_idx = rxr->bnapi->index;
3939 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3940
3941 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3942 hwrm_ring_free_send_msg(bp, ring,
3943 RING_FREE_REQ_RING_TYPE_RX,
3944 close_path ? cmpl_ring_id :
3945 INVALID_HW_RING_ID);
3946 ring->fw_ring_id = INVALID_HW_RING_ID;
3947 bp->grp_info[grp_idx].agg_fw_ring_id =
3948 INVALID_HW_RING_ID;
3949 }
3950 }
3951
3952 for (i = 0; i < bp->cp_nr_rings; i++) {
3953 struct bnxt_napi *bnapi = bp->bnapi[i];
3954 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3955 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3956
3957 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3958 hwrm_ring_free_send_msg(bp, ring,
3959 RING_FREE_REQ_RING_TYPE_CMPL,
3960 INVALID_HW_RING_ID);
3961 ring->fw_ring_id = INVALID_HW_RING_ID;
3962 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3963 }
3964 }
3965 }
3966
3967 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
3968 u32 buf_tmrs, u16 flags,
3969 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3970 {
3971 req->flags = cpu_to_le16(flags);
3972 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
3973 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
3974 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
3975 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
3976 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3977 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
3978 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
3979 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
3980 }
3981
3982 int bnxt_hwrm_set_coal(struct bnxt *bp)
3983 {
3984 int i, rc = 0;
3985 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
3986 req_tx = {0}, *req;
3987 u16 max_buf, max_buf_irq;
3988 u16 buf_tmr, buf_tmr_irq;
3989 u32 flags;
3990
3991 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
3992 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3993 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
3994 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3995
3996 /* Each rx completion (2 records) should be DMAed immediately.
3997 * DMA 1/4 of the completion buffers at a time.
3998 */
3999 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
4000 /* max_buf must not be zero */
4001 max_buf = clamp_t(u16, max_buf, 1, 63);
4002 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4003 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4004 /* buf timer set to 1/4 of interrupt timer */
4005 buf_tmr = max_t(u16, buf_tmr / 4, 1);
4006 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4007 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4008
4009 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4010
4011 /* RING_IDLE generates more IRQs for lower latency. Enable it only
4012 * if coal_ticks is less than 25 us.
4013 */
4014 if (bp->rx_coal_ticks < 25)
4015 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4016
4017 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4018 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4019
4020 /* max_buf must not be zero */
4021 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4022 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4023 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4024 /* buf timer set to 1/4 of interrupt timer */
4025 buf_tmr = max_t(u16, buf_tmr / 4, 1);
4026 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4027 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4028
4029 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4030 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4031 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
4032
4033 mutex_lock(&bp->hwrm_cmd_lock);
4034 for (i = 0; i < bp->cp_nr_rings; i++) {
4035 struct bnxt_napi *bnapi = bp->bnapi[i];
4036
4037 req = &req_rx;
4038 if (!bnapi->rx_ring)
4039 req = &req_tx;
4040 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4041
4042 rc = _hwrm_send_message(bp, req, sizeof(*req),
4043 HWRM_CMD_TIMEOUT);
4044 if (rc)
4045 break;
4046 }
4047 mutex_unlock(&bp->hwrm_cmd_lock);
4048 return rc;
4049 }
4050
4051 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4052 {
4053 int rc = 0, i;
4054 struct hwrm_stat_ctx_free_input req = {0};
4055
4056 if (!bp->bnapi)
4057 return 0;
4058
4059 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4060 return 0;
4061
4062 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4063
4064 mutex_lock(&bp->hwrm_cmd_lock);
4065 for (i = 0; i < bp->cp_nr_rings; i++) {
4066 struct bnxt_napi *bnapi = bp->bnapi[i];
4067 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4068
4069 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4070 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4071
4072 rc = _hwrm_send_message(bp, &req, sizeof(req),
4073 HWRM_CMD_TIMEOUT);
4074 if (rc)
4075 break;
4076
4077 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4078 }
4079 }
4080 mutex_unlock(&bp->hwrm_cmd_lock);
4081 return rc;
4082 }
4083
4084 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4085 {
4086 int rc = 0, i;
4087 struct hwrm_stat_ctx_alloc_input req = {0};
4088 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4089
4090 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4091 return 0;
4092
4093 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4094
4095 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
4096
4097 mutex_lock(&bp->hwrm_cmd_lock);
4098 for (i = 0; i < bp->cp_nr_rings; i++) {
4099 struct bnxt_napi *bnapi = bp->bnapi[i];
4100 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4101
4102 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4103
4104 rc = _hwrm_send_message(bp, &req, sizeof(req),
4105 HWRM_CMD_TIMEOUT);
4106 if (rc)
4107 break;
4108
4109 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4110
4111 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4112 }
4113 mutex_unlock(&bp->hwrm_cmd_lock);
4114 return 0;
4115 }
4116
4117 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4118 {
4119 struct hwrm_func_qcfg_input req = {0};
4120 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4121 int rc;
4122
4123 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4124 req.fid = cpu_to_le16(0xffff);
4125 mutex_lock(&bp->hwrm_cmd_lock);
4126 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4127 if (rc)
4128 goto func_qcfg_exit;
4129
4130 #ifdef CONFIG_BNXT_SRIOV
4131 if (BNXT_VF(bp)) {
4132 struct bnxt_vf_info *vf = &bp->vf;
4133
4134 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4135 }
4136 #endif
4137 switch (resp->port_partition_type) {
4138 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4139 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4140 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4141 bp->port_partition_type = resp->port_partition_type;
4142 break;
4143 }
4144
4145 func_qcfg_exit:
4146 mutex_unlock(&bp->hwrm_cmd_lock);
4147 return rc;
4148 }
4149
4150 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4151 {
4152 int rc = 0;
4153 struct hwrm_func_qcaps_input req = {0};
4154 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4155
4156 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4157 req.fid = cpu_to_le16(0xffff);
4158
4159 mutex_lock(&bp->hwrm_cmd_lock);
4160 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4161 if (rc)
4162 goto hwrm_func_qcaps_exit;
4163
4164 bp->tx_push_thresh = 0;
4165 if (resp->flags &
4166 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4167 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4168
4169 if (BNXT_PF(bp)) {
4170 struct bnxt_pf_info *pf = &bp->pf;
4171
4172 pf->fw_fid = le16_to_cpu(resp->fid);
4173 pf->port_id = le16_to_cpu(resp->port_id);
4174 bp->dev->dev_port = pf->port_id;
4175 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4176 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
4177 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4178 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4179 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4180 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4181 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4182 if (!pf->max_hw_ring_grps)
4183 pf->max_hw_ring_grps = pf->max_tx_rings;
4184 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4185 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4186 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4187 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4188 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4189 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4190 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4191 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4192 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4193 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4194 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4195 } else {
4196 #ifdef CONFIG_BNXT_SRIOV
4197 struct bnxt_vf_info *vf = &bp->vf;
4198
4199 vf->fw_fid = le16_to_cpu(resp->fid);
4200
4201 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4202 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4203 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4204 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4205 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4206 if (!vf->max_hw_ring_grps)
4207 vf->max_hw_ring_grps = vf->max_tx_rings;
4208 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4209 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4210 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4211
4212 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4213 mutex_unlock(&bp->hwrm_cmd_lock);
4214
4215 if (is_valid_ether_addr(vf->mac_addr)) {
4216 /* overwrite netdev dev_adr with admin VF MAC */
4217 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
4218 } else {
4219 random_ether_addr(bp->dev->dev_addr);
4220 rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
4221 }
4222 return rc;
4223 #endif
4224 }
4225
4226 hwrm_func_qcaps_exit:
4227 mutex_unlock(&bp->hwrm_cmd_lock);
4228 return rc;
4229 }
4230
4231 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4232 {
4233 struct hwrm_func_reset_input req = {0};
4234
4235 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4236 req.enables = 0;
4237
4238 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4239 }
4240
4241 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4242 {
4243 int rc = 0;
4244 struct hwrm_queue_qportcfg_input req = {0};
4245 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4246 u8 i, *qptr;
4247
4248 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4249
4250 mutex_lock(&bp->hwrm_cmd_lock);
4251 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4252 if (rc)
4253 goto qportcfg_exit;
4254
4255 if (!resp->max_configurable_queues) {
4256 rc = -EINVAL;
4257 goto qportcfg_exit;
4258 }
4259 bp->max_tc = resp->max_configurable_queues;
4260 if (bp->max_tc > BNXT_MAX_QUEUE)
4261 bp->max_tc = BNXT_MAX_QUEUE;
4262
4263 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4264 bp->max_tc = 1;
4265
4266 qptr = &resp->queue_id0;
4267 for (i = 0; i < bp->max_tc; i++) {
4268 bp->q_info[i].queue_id = *qptr++;
4269 bp->q_info[i].queue_profile = *qptr++;
4270 }
4271
4272 qportcfg_exit:
4273 mutex_unlock(&bp->hwrm_cmd_lock);
4274 return rc;
4275 }
4276
4277 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4278 {
4279 int rc;
4280 struct hwrm_ver_get_input req = {0};
4281 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4282
4283 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4284 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4285 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4286 req.hwrm_intf_min = HWRM_VERSION_MINOR;
4287 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4288 mutex_lock(&bp->hwrm_cmd_lock);
4289 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4290 if (rc)
4291 goto hwrm_ver_get_exit;
4292
4293 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4294
4295 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4296 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4297 if (resp->hwrm_intf_maj < 1) {
4298 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4299 resp->hwrm_intf_maj, resp->hwrm_intf_min,
4300 resp->hwrm_intf_upd);
4301 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4302 }
4303 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
4304 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4305 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4306
4307 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4308 if (!bp->hwrm_cmd_timeout)
4309 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4310
4311 if (resp->hwrm_intf_maj >= 1)
4312 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4313
4314 bp->chip_num = le16_to_cpu(resp->chip_num);
4315 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4316 !resp->chip_metal)
4317 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
4318
4319 hwrm_ver_get_exit:
4320 mutex_unlock(&bp->hwrm_cmd_lock);
4321 return rc;
4322 }
4323
4324 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4325 {
4326 #if IS_ENABLED(CONFIG_RTC_LIB)
4327 struct hwrm_fw_set_time_input req = {0};
4328 struct rtc_time tm;
4329 struct timeval tv;
4330
4331 if (bp->hwrm_spec_code < 0x10400)
4332 return -EOPNOTSUPP;
4333
4334 do_gettimeofday(&tv);
4335 rtc_time_to_tm(tv.tv_sec, &tm);
4336 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4337 req.year = cpu_to_le16(1900 + tm.tm_year);
4338 req.month = 1 + tm.tm_mon;
4339 req.day = tm.tm_mday;
4340 req.hour = tm.tm_hour;
4341 req.minute = tm.tm_min;
4342 req.second = tm.tm_sec;
4343 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4344 #else
4345 return -EOPNOTSUPP;
4346 #endif
4347 }
4348
4349 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4350 {
4351 int rc;
4352 struct bnxt_pf_info *pf = &bp->pf;
4353 struct hwrm_port_qstats_input req = {0};
4354
4355 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4356 return 0;
4357
4358 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4359 req.port_id = cpu_to_le16(pf->port_id);
4360 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4361 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4362 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4363 return rc;
4364 }
4365
4366 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4367 {
4368 if (bp->vxlan_port_cnt) {
4369 bnxt_hwrm_tunnel_dst_port_free(
4370 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4371 }
4372 bp->vxlan_port_cnt = 0;
4373 if (bp->nge_port_cnt) {
4374 bnxt_hwrm_tunnel_dst_port_free(
4375 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4376 }
4377 bp->nge_port_cnt = 0;
4378 }
4379
4380 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4381 {
4382 int rc, i;
4383 u32 tpa_flags = 0;
4384
4385 if (set_tpa)
4386 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4387 for (i = 0; i < bp->nr_vnics; i++) {
4388 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4389 if (rc) {
4390 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4391 rc, i);
4392 return rc;
4393 }
4394 }
4395 return 0;
4396 }
4397
4398 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4399 {
4400 int i;
4401
4402 for (i = 0; i < bp->nr_vnics; i++)
4403 bnxt_hwrm_vnic_set_rss(bp, i, false);
4404 }
4405
4406 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4407 bool irq_re_init)
4408 {
4409 if (bp->vnic_info) {
4410 bnxt_hwrm_clear_vnic_filter(bp);
4411 /* clear all RSS setting before free vnic ctx */
4412 bnxt_hwrm_clear_vnic_rss(bp);
4413 bnxt_hwrm_vnic_ctx_free(bp);
4414 /* before free the vnic, undo the vnic tpa settings */
4415 if (bp->flags & BNXT_FLAG_TPA)
4416 bnxt_set_tpa(bp, false);
4417 bnxt_hwrm_vnic_free(bp);
4418 }
4419 bnxt_hwrm_ring_free(bp, close_path);
4420 bnxt_hwrm_ring_grp_free(bp);
4421 if (irq_re_init) {
4422 bnxt_hwrm_stat_ctx_free(bp);
4423 bnxt_hwrm_free_tunnel_ports(bp);
4424 }
4425 }
4426
4427 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4428 {
4429 int rc;
4430
4431 /* allocate context for vnic */
4432 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
4433 if (rc) {
4434 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4435 vnic_id, rc);
4436 goto vnic_setup_err;
4437 }
4438 bp->rsscos_nr_ctxs++;
4439
4440 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4441 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
4442 if (rc) {
4443 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4444 vnic_id, rc);
4445 goto vnic_setup_err;
4446 }
4447 bp->rsscos_nr_ctxs++;
4448 }
4449
4450 /* configure default vnic, ring grp */
4451 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4452 if (rc) {
4453 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4454 vnic_id, rc);
4455 goto vnic_setup_err;
4456 }
4457
4458 /* Enable RSS hashing on vnic */
4459 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4460 if (rc) {
4461 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4462 vnic_id, rc);
4463 goto vnic_setup_err;
4464 }
4465
4466 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4467 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4468 if (rc) {
4469 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4470 vnic_id, rc);
4471 }
4472 }
4473
4474 vnic_setup_err:
4475 return rc;
4476 }
4477
4478 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4479 {
4480 #ifdef CONFIG_RFS_ACCEL
4481 int i, rc = 0;
4482
4483 for (i = 0; i < bp->rx_nr_rings; i++) {
4484 u16 vnic_id = i + 1;
4485 u16 ring_id = i;
4486
4487 if (vnic_id >= bp->nr_vnics)
4488 break;
4489
4490 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
4491 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4492 if (rc) {
4493 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4494 vnic_id, rc);
4495 break;
4496 }
4497 rc = bnxt_setup_vnic(bp, vnic_id);
4498 if (rc)
4499 break;
4500 }
4501 return rc;
4502 #else
4503 return 0;
4504 #endif
4505 }
4506
4507 /* Allow PF and VF with default VLAN to be in promiscuous mode */
4508 static bool bnxt_promisc_ok(struct bnxt *bp)
4509 {
4510 #ifdef CONFIG_BNXT_SRIOV
4511 if (BNXT_VF(bp) && !bp->vf.vlan)
4512 return false;
4513 #endif
4514 return true;
4515 }
4516
4517 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
4518 {
4519 unsigned int rc = 0;
4520
4521 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
4522 if (rc) {
4523 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4524 rc);
4525 return rc;
4526 }
4527
4528 rc = bnxt_hwrm_vnic_cfg(bp, 1);
4529 if (rc) {
4530 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4531 rc);
4532 return rc;
4533 }
4534 return rc;
4535 }
4536
4537 static int bnxt_cfg_rx_mode(struct bnxt *);
4538 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
4539
4540 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4541 {
4542 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4543 int rc = 0;
4544 unsigned int rx_nr_rings = bp->rx_nr_rings;
4545
4546 if (irq_re_init) {
4547 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4548 if (rc) {
4549 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4550 rc);
4551 goto err_out;
4552 }
4553 }
4554
4555 rc = bnxt_hwrm_ring_alloc(bp);
4556 if (rc) {
4557 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4558 goto err_out;
4559 }
4560
4561 rc = bnxt_hwrm_ring_grp_alloc(bp);
4562 if (rc) {
4563 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4564 goto err_out;
4565 }
4566
4567 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4568 rx_nr_rings--;
4569
4570 /* default vnic 0 */
4571 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
4572 if (rc) {
4573 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4574 goto err_out;
4575 }
4576
4577 rc = bnxt_setup_vnic(bp, 0);
4578 if (rc)
4579 goto err_out;
4580
4581 if (bp->flags & BNXT_FLAG_RFS) {
4582 rc = bnxt_alloc_rfs_vnics(bp);
4583 if (rc)
4584 goto err_out;
4585 }
4586
4587 if (bp->flags & BNXT_FLAG_TPA) {
4588 rc = bnxt_set_tpa(bp, true);
4589 if (rc)
4590 goto err_out;
4591 }
4592
4593 if (BNXT_VF(bp))
4594 bnxt_update_vf_mac(bp);
4595
4596 /* Filter for default vnic 0 */
4597 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4598 if (rc) {
4599 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4600 goto err_out;
4601 }
4602 vnic->uc_filter_count = 1;
4603
4604 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
4605
4606 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
4607 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4608
4609 if (bp->dev->flags & IFF_ALLMULTI) {
4610 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4611 vnic->mc_list_count = 0;
4612 } else {
4613 u32 mask = 0;
4614
4615 bnxt_mc_list_updated(bp, &mask);
4616 vnic->rx_mask |= mask;
4617 }
4618
4619 rc = bnxt_cfg_rx_mode(bp);
4620 if (rc)
4621 goto err_out;
4622
4623 rc = bnxt_hwrm_set_coal(bp);
4624 if (rc)
4625 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4626 rc);
4627
4628 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4629 rc = bnxt_setup_nitroa0_vnic(bp);
4630 if (rc)
4631 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
4632 rc);
4633 }
4634
4635 if (BNXT_VF(bp)) {
4636 bnxt_hwrm_func_qcfg(bp);
4637 netdev_update_features(bp->dev);
4638 }
4639
4640 return 0;
4641
4642 err_out:
4643 bnxt_hwrm_resource_free(bp, 0, true);
4644
4645 return rc;
4646 }
4647
4648 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4649 {
4650 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4651 return 0;
4652 }
4653
4654 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4655 {
4656 bnxt_init_rx_rings(bp);
4657 bnxt_init_tx_rings(bp);
4658 bnxt_init_ring_grps(bp, irq_re_init);
4659 bnxt_init_vnics(bp);
4660
4661 return bnxt_init_chip(bp, irq_re_init);
4662 }
4663
4664 static void bnxt_disable_int(struct bnxt *bp)
4665 {
4666 int i;
4667
4668 if (!bp->bnapi)
4669 return;
4670
4671 for (i = 0; i < bp->cp_nr_rings; i++) {
4672 struct bnxt_napi *bnapi = bp->bnapi[i];
4673 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4674
4675 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4676 }
4677 }
4678
4679 static void bnxt_enable_int(struct bnxt *bp)
4680 {
4681 int i;
4682
4683 atomic_set(&bp->intr_sem, 0);
4684 for (i = 0; i < bp->cp_nr_rings; i++) {
4685 struct bnxt_napi *bnapi = bp->bnapi[i];
4686 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4687
4688 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4689 }
4690 }
4691
4692 static int bnxt_set_real_num_queues(struct bnxt *bp)
4693 {
4694 int rc;
4695 struct net_device *dev = bp->dev;
4696
4697 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4698 if (rc)
4699 return rc;
4700
4701 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4702 if (rc)
4703 return rc;
4704
4705 #ifdef CONFIG_RFS_ACCEL
4706 if (bp->flags & BNXT_FLAG_RFS)
4707 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4708 #endif
4709
4710 return rc;
4711 }
4712
4713 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4714 bool shared)
4715 {
4716 int _rx = *rx, _tx = *tx;
4717
4718 if (shared) {
4719 *rx = min_t(int, _rx, max);
4720 *tx = min_t(int, _tx, max);
4721 } else {
4722 if (max < 2)
4723 return -ENOMEM;
4724
4725 while (_rx + _tx > max) {
4726 if (_rx > _tx && _rx > 1)
4727 _rx--;
4728 else if (_tx > 1)
4729 _tx--;
4730 }
4731 *rx = _rx;
4732 *tx = _tx;
4733 }
4734 return 0;
4735 }
4736
4737 static int bnxt_setup_msix(struct bnxt *bp)
4738 {
4739 struct msix_entry *msix_ent;
4740 struct net_device *dev = bp->dev;
4741 int i, total_vecs, rc = 0, min = 1;
4742 const int len = sizeof(bp->irq_tbl[0].name);
4743
4744 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4745 total_vecs = bp->cp_nr_rings;
4746
4747 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4748 if (!msix_ent)
4749 return -ENOMEM;
4750
4751 for (i = 0; i < total_vecs; i++) {
4752 msix_ent[i].entry = i;
4753 msix_ent[i].vector = 0;
4754 }
4755
4756 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4757 min = 2;
4758
4759 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
4760 if (total_vecs < 0) {
4761 rc = -ENODEV;
4762 goto msix_setup_exit;
4763 }
4764
4765 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4766 if (bp->irq_tbl) {
4767 int tcs;
4768
4769 /* Trim rings based upon num of vectors allocated */
4770 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
4771 total_vecs, min == 1);
4772 if (rc)
4773 goto msix_setup_exit;
4774
4775 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4776 tcs = netdev_get_num_tc(dev);
4777 if (tcs > 1) {
4778 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4779 if (bp->tx_nr_rings_per_tc == 0) {
4780 netdev_reset_tc(dev);
4781 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4782 } else {
4783 int i, off, count;
4784
4785 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4786 for (i = 0; i < tcs; i++) {
4787 count = bp->tx_nr_rings_per_tc;
4788 off = i * count;
4789 netdev_set_tc_queue(dev, i, count, off);
4790 }
4791 }
4792 }
4793 bp->cp_nr_rings = total_vecs;
4794
4795 for (i = 0; i < bp->cp_nr_rings; i++) {
4796 char *attr;
4797
4798 bp->irq_tbl[i].vector = msix_ent[i].vector;
4799 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4800 attr = "TxRx";
4801 else if (i < bp->rx_nr_rings)
4802 attr = "rx";
4803 else
4804 attr = "tx";
4805
4806 snprintf(bp->irq_tbl[i].name, len,
4807 "%s-%s-%d", dev->name, attr, i);
4808 bp->irq_tbl[i].handler = bnxt_msix;
4809 }
4810 rc = bnxt_set_real_num_queues(bp);
4811 if (rc)
4812 goto msix_setup_exit;
4813 } else {
4814 rc = -ENOMEM;
4815 goto msix_setup_exit;
4816 }
4817 bp->flags |= BNXT_FLAG_USING_MSIX;
4818 kfree(msix_ent);
4819 return 0;
4820
4821 msix_setup_exit:
4822 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4823 pci_disable_msix(bp->pdev);
4824 kfree(msix_ent);
4825 return rc;
4826 }
4827
4828 static int bnxt_setup_inta(struct bnxt *bp)
4829 {
4830 int rc;
4831 const int len = sizeof(bp->irq_tbl[0].name);
4832
4833 if (netdev_get_num_tc(bp->dev))
4834 netdev_reset_tc(bp->dev);
4835
4836 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4837 if (!bp->irq_tbl) {
4838 rc = -ENOMEM;
4839 return rc;
4840 }
4841 bp->rx_nr_rings = 1;
4842 bp->tx_nr_rings = 1;
4843 bp->cp_nr_rings = 1;
4844 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4845 bp->flags |= BNXT_FLAG_SHARED_RINGS;
4846 bp->irq_tbl[0].vector = bp->pdev->irq;
4847 snprintf(bp->irq_tbl[0].name, len,
4848 "%s-%s-%d", bp->dev->name, "TxRx", 0);
4849 bp->irq_tbl[0].handler = bnxt_inta;
4850 rc = bnxt_set_real_num_queues(bp);
4851 return rc;
4852 }
4853
4854 static int bnxt_setup_int_mode(struct bnxt *bp)
4855 {
4856 int rc = 0;
4857
4858 if (bp->flags & BNXT_FLAG_MSIX_CAP)
4859 rc = bnxt_setup_msix(bp);
4860
4861 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
4862 /* fallback to INTA */
4863 rc = bnxt_setup_inta(bp);
4864 }
4865 return rc;
4866 }
4867
4868 static void bnxt_free_irq(struct bnxt *bp)
4869 {
4870 struct bnxt_irq *irq;
4871 int i;
4872
4873 #ifdef CONFIG_RFS_ACCEL
4874 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4875 bp->dev->rx_cpu_rmap = NULL;
4876 #endif
4877 if (!bp->irq_tbl)
4878 return;
4879
4880 for (i = 0; i < bp->cp_nr_rings; i++) {
4881 irq = &bp->irq_tbl[i];
4882 if (irq->requested)
4883 free_irq(irq->vector, bp->bnapi[i]);
4884 irq->requested = 0;
4885 }
4886 if (bp->flags & BNXT_FLAG_USING_MSIX)
4887 pci_disable_msix(bp->pdev);
4888 kfree(bp->irq_tbl);
4889 bp->irq_tbl = NULL;
4890 }
4891
4892 static int bnxt_request_irq(struct bnxt *bp)
4893 {
4894 int i, j, rc = 0;
4895 unsigned long flags = 0;
4896 #ifdef CONFIG_RFS_ACCEL
4897 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4898 #endif
4899
4900 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4901 flags = IRQF_SHARED;
4902
4903 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4904 struct bnxt_irq *irq = &bp->irq_tbl[i];
4905 #ifdef CONFIG_RFS_ACCEL
4906 if (rmap && bp->bnapi[i]->rx_ring) {
4907 rc = irq_cpu_rmap_add(rmap, irq->vector);
4908 if (rc)
4909 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4910 j);
4911 j++;
4912 }
4913 #endif
4914 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4915 bp->bnapi[i]);
4916 if (rc)
4917 break;
4918
4919 irq->requested = 1;
4920 }
4921 return rc;
4922 }
4923
4924 static void bnxt_del_napi(struct bnxt *bp)
4925 {
4926 int i;
4927
4928 if (!bp->bnapi)
4929 return;
4930
4931 for (i = 0; i < bp->cp_nr_rings; i++) {
4932 struct bnxt_napi *bnapi = bp->bnapi[i];
4933
4934 napi_hash_del(&bnapi->napi);
4935 netif_napi_del(&bnapi->napi);
4936 }
4937 }
4938
4939 static void bnxt_init_napi(struct bnxt *bp)
4940 {
4941 int i;
4942 unsigned int cp_nr_rings = bp->cp_nr_rings;
4943 struct bnxt_napi *bnapi;
4944
4945 if (bp->flags & BNXT_FLAG_USING_MSIX) {
4946 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4947 cp_nr_rings--;
4948 for (i = 0; i < cp_nr_rings; i++) {
4949 bnapi = bp->bnapi[i];
4950 netif_napi_add(bp->dev, &bnapi->napi,
4951 bnxt_poll, 64);
4952 }
4953 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4954 bnapi = bp->bnapi[cp_nr_rings];
4955 netif_napi_add(bp->dev, &bnapi->napi,
4956 bnxt_poll_nitroa0, 64);
4957 napi_hash_add(&bnapi->napi);
4958 }
4959 } else {
4960 bnapi = bp->bnapi[0];
4961 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4962 }
4963 }
4964
4965 static void bnxt_disable_napi(struct bnxt *bp)
4966 {
4967 int i;
4968
4969 if (!bp->bnapi)
4970 return;
4971
4972 for (i = 0; i < bp->cp_nr_rings; i++) {
4973 napi_disable(&bp->bnapi[i]->napi);
4974 bnxt_disable_poll(bp->bnapi[i]);
4975 }
4976 }
4977
4978 static void bnxt_enable_napi(struct bnxt *bp)
4979 {
4980 int i;
4981
4982 for (i = 0; i < bp->cp_nr_rings; i++) {
4983 bp->bnapi[i]->in_reset = false;
4984 bnxt_enable_poll(bp->bnapi[i]);
4985 napi_enable(&bp->bnapi[i]->napi);
4986 }
4987 }
4988
4989 static void bnxt_tx_disable(struct bnxt *bp)
4990 {
4991 int i;
4992 struct bnxt_tx_ring_info *txr;
4993 struct netdev_queue *txq;
4994
4995 if (bp->tx_ring) {
4996 for (i = 0; i < bp->tx_nr_rings; i++) {
4997 txr = &bp->tx_ring[i];
4998 txq = netdev_get_tx_queue(bp->dev, i);
4999 txr->dev_state = BNXT_DEV_STATE_CLOSING;
5000 }
5001 }
5002 /* Stop all TX queues */
5003 netif_tx_disable(bp->dev);
5004 netif_carrier_off(bp->dev);
5005 }
5006
5007 static void bnxt_tx_enable(struct bnxt *bp)
5008 {
5009 int i;
5010 struct bnxt_tx_ring_info *txr;
5011 struct netdev_queue *txq;
5012
5013 for (i = 0; i < bp->tx_nr_rings; i++) {
5014 txr = &bp->tx_ring[i];
5015 txq = netdev_get_tx_queue(bp->dev, i);
5016 txr->dev_state = 0;
5017 }
5018 netif_tx_wake_all_queues(bp->dev);
5019 if (bp->link_info.link_up)
5020 netif_carrier_on(bp->dev);
5021 }
5022
5023 static void bnxt_report_link(struct bnxt *bp)
5024 {
5025 if (bp->link_info.link_up) {
5026 const char *duplex;
5027 const char *flow_ctrl;
5028 u16 speed;
5029
5030 netif_carrier_on(bp->dev);
5031 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5032 duplex = "full";
5033 else
5034 duplex = "half";
5035 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5036 flow_ctrl = "ON - receive & transmit";
5037 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5038 flow_ctrl = "ON - transmit";
5039 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5040 flow_ctrl = "ON - receive";
5041 else
5042 flow_ctrl = "none";
5043 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5044 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
5045 speed, duplex, flow_ctrl);
5046 if (bp->flags & BNXT_FLAG_EEE_CAP)
5047 netdev_info(bp->dev, "EEE is %s\n",
5048 bp->eee.eee_active ? "active" :
5049 "not active");
5050 } else {
5051 netif_carrier_off(bp->dev);
5052 netdev_err(bp->dev, "NIC Link is Down\n");
5053 }
5054 }
5055
5056 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5057 {
5058 int rc = 0;
5059 struct hwrm_port_phy_qcaps_input req = {0};
5060 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5061 struct bnxt_link_info *link_info = &bp->link_info;
5062
5063 if (bp->hwrm_spec_code < 0x10201)
5064 return 0;
5065
5066 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5067
5068 mutex_lock(&bp->hwrm_cmd_lock);
5069 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5070 if (rc)
5071 goto hwrm_phy_qcaps_exit;
5072
5073 if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
5074 struct ethtool_eee *eee = &bp->eee;
5075 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5076
5077 bp->flags |= BNXT_FLAG_EEE_CAP;
5078 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5079 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5080 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5081 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5082 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5083 }
5084 link_info->support_auto_speeds =
5085 le16_to_cpu(resp->supported_speeds_auto_mode);
5086
5087 hwrm_phy_qcaps_exit:
5088 mutex_unlock(&bp->hwrm_cmd_lock);
5089 return rc;
5090 }
5091
5092 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5093 {
5094 int rc = 0;
5095 struct bnxt_link_info *link_info = &bp->link_info;
5096 struct hwrm_port_phy_qcfg_input req = {0};
5097 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5098 u8 link_up = link_info->link_up;
5099
5100 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5101
5102 mutex_lock(&bp->hwrm_cmd_lock);
5103 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5104 if (rc) {
5105 mutex_unlock(&bp->hwrm_cmd_lock);
5106 return rc;
5107 }
5108
5109 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5110 link_info->phy_link_status = resp->link;
5111 link_info->duplex = resp->duplex;
5112 link_info->pause = resp->pause;
5113 link_info->auto_mode = resp->auto_mode;
5114 link_info->auto_pause_setting = resp->auto_pause;
5115 link_info->lp_pause = resp->link_partner_adv_pause;
5116 link_info->force_pause_setting = resp->force_pause;
5117 link_info->duplex_setting = resp->duplex;
5118 if (link_info->phy_link_status == BNXT_LINK_LINK)
5119 link_info->link_speed = le16_to_cpu(resp->link_speed);
5120 else
5121 link_info->link_speed = 0;
5122 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
5123 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5124 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
5125 link_info->lp_auto_link_speeds =
5126 le16_to_cpu(resp->link_partner_adv_speeds);
5127 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5128 link_info->phy_ver[0] = resp->phy_maj;
5129 link_info->phy_ver[1] = resp->phy_min;
5130 link_info->phy_ver[2] = resp->phy_bld;
5131 link_info->media_type = resp->media_type;
5132 link_info->phy_type = resp->phy_type;
5133 link_info->transceiver = resp->xcvr_pkg_type;
5134 link_info->phy_addr = resp->eee_config_phy_addr &
5135 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
5136 link_info->module_status = resp->module_status;
5137
5138 if (bp->flags & BNXT_FLAG_EEE_CAP) {
5139 struct ethtool_eee *eee = &bp->eee;
5140 u16 fw_speeds;
5141
5142 eee->eee_active = 0;
5143 if (resp->eee_config_phy_addr &
5144 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5145 eee->eee_active = 1;
5146 fw_speeds = le16_to_cpu(
5147 resp->link_partner_adv_eee_link_speed_mask);
5148 eee->lp_advertised =
5149 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5150 }
5151
5152 /* Pull initial EEE config */
5153 if (!chng_link_state) {
5154 if (resp->eee_config_phy_addr &
5155 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5156 eee->eee_enabled = 1;
5157
5158 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5159 eee->advertised =
5160 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5161
5162 if (resp->eee_config_phy_addr &
5163 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5164 __le32 tmr;
5165
5166 eee->tx_lpi_enabled = 1;
5167 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5168 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5169 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5170 }
5171 }
5172 }
5173 /* TODO: need to add more logic to report VF link */
5174 if (chng_link_state) {
5175 if (link_info->phy_link_status == BNXT_LINK_LINK)
5176 link_info->link_up = 1;
5177 else
5178 link_info->link_up = 0;
5179 if (link_up != link_info->link_up)
5180 bnxt_report_link(bp);
5181 } else {
5182 /* alwasy link down if not require to update link state */
5183 link_info->link_up = 0;
5184 }
5185 mutex_unlock(&bp->hwrm_cmd_lock);
5186 return 0;
5187 }
5188
5189 static void bnxt_get_port_module_status(struct bnxt *bp)
5190 {
5191 struct bnxt_link_info *link_info = &bp->link_info;
5192 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5193 u8 module_status;
5194
5195 if (bnxt_update_link(bp, true))
5196 return;
5197
5198 module_status = link_info->module_status;
5199 switch (module_status) {
5200 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5201 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5202 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5203 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5204 bp->pf.port_id);
5205 if (bp->hwrm_spec_code >= 0x10201) {
5206 netdev_warn(bp->dev, "Module part number %s\n",
5207 resp->phy_vendor_partnumber);
5208 }
5209 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5210 netdev_warn(bp->dev, "TX is disabled\n");
5211 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5212 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5213 }
5214 }
5215
5216 static void
5217 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5218 {
5219 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
5220 if (bp->hwrm_spec_code >= 0x10201)
5221 req->auto_pause =
5222 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
5223 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5224 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5225 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5226 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
5227 req->enables |=
5228 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5229 } else {
5230 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5231 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5232 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5233 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5234 req->enables |=
5235 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
5236 if (bp->hwrm_spec_code >= 0x10201) {
5237 req->auto_pause = req->force_pause;
5238 req->enables |= cpu_to_le32(
5239 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5240 }
5241 }
5242 }
5243
5244 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5245 struct hwrm_port_phy_cfg_input *req)
5246 {
5247 u8 autoneg = bp->link_info.autoneg;
5248 u16 fw_link_speed = bp->link_info.req_link_speed;
5249 u32 advertising = bp->link_info.advertising;
5250
5251 if (autoneg & BNXT_AUTONEG_SPEED) {
5252 req->auto_mode |=
5253 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
5254
5255 req->enables |= cpu_to_le32(
5256 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5257 req->auto_link_speed_mask = cpu_to_le16(advertising);
5258
5259 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5260 req->flags |=
5261 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5262 } else {
5263 req->force_link_speed = cpu_to_le16(fw_link_speed);
5264 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5265 }
5266
5267 /* tell chimp that the setting takes effect immediately */
5268 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5269 }
5270
5271 int bnxt_hwrm_set_pause(struct bnxt *bp)
5272 {
5273 struct hwrm_port_phy_cfg_input req = {0};
5274 int rc;
5275
5276 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5277 bnxt_hwrm_set_pause_common(bp, &req);
5278
5279 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5280 bp->link_info.force_link_chng)
5281 bnxt_hwrm_set_link_common(bp, &req);
5282
5283 mutex_lock(&bp->hwrm_cmd_lock);
5284 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5285 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5286 /* since changing of pause setting doesn't trigger any link
5287 * change event, the driver needs to update the current pause
5288 * result upon successfully return of the phy_cfg command
5289 */
5290 bp->link_info.pause =
5291 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5292 bp->link_info.auto_pause_setting = 0;
5293 if (!bp->link_info.force_link_chng)
5294 bnxt_report_link(bp);
5295 }
5296 bp->link_info.force_link_chng = false;
5297 mutex_unlock(&bp->hwrm_cmd_lock);
5298 return rc;
5299 }
5300
5301 static void bnxt_hwrm_set_eee(struct bnxt *bp,
5302 struct hwrm_port_phy_cfg_input *req)
5303 {
5304 struct ethtool_eee *eee = &bp->eee;
5305
5306 if (eee->eee_enabled) {
5307 u16 eee_speeds;
5308 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5309
5310 if (eee->tx_lpi_enabled)
5311 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5312 else
5313 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5314
5315 req->flags |= cpu_to_le32(flags);
5316 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5317 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5318 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5319 } else {
5320 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5321 }
5322 }
5323
5324 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
5325 {
5326 struct hwrm_port_phy_cfg_input req = {0};
5327
5328 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5329 if (set_pause)
5330 bnxt_hwrm_set_pause_common(bp, &req);
5331
5332 bnxt_hwrm_set_link_common(bp, &req);
5333
5334 if (set_eee)
5335 bnxt_hwrm_set_eee(bp, &req);
5336 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5337 }
5338
5339 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5340 {
5341 struct hwrm_port_phy_cfg_input req = {0};
5342
5343 if (!BNXT_SINGLE_PF(bp))
5344 return 0;
5345
5346 if (pci_num_vf(bp->pdev))
5347 return 0;
5348
5349 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5350 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN);
5351 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5352 }
5353
5354 static bool bnxt_eee_config_ok(struct bnxt *bp)
5355 {
5356 struct ethtool_eee *eee = &bp->eee;
5357 struct bnxt_link_info *link_info = &bp->link_info;
5358
5359 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5360 return true;
5361
5362 if (eee->eee_enabled) {
5363 u32 advertising =
5364 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5365
5366 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5367 eee->eee_enabled = 0;
5368 return false;
5369 }
5370 if (eee->advertised & ~advertising) {
5371 eee->advertised = advertising & eee->supported;
5372 return false;
5373 }
5374 }
5375 return true;
5376 }
5377
5378 static int bnxt_update_phy_setting(struct bnxt *bp)
5379 {
5380 int rc;
5381 bool update_link = false;
5382 bool update_pause = false;
5383 bool update_eee = false;
5384 struct bnxt_link_info *link_info = &bp->link_info;
5385
5386 rc = bnxt_update_link(bp, true);
5387 if (rc) {
5388 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5389 rc);
5390 return rc;
5391 }
5392 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5393 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5394 link_info->req_flow_ctrl)
5395 update_pause = true;
5396 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5397 link_info->force_pause_setting != link_info->req_flow_ctrl)
5398 update_pause = true;
5399 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5400 if (BNXT_AUTO_MODE(link_info->auto_mode))
5401 update_link = true;
5402 if (link_info->req_link_speed != link_info->force_link_speed)
5403 update_link = true;
5404 if (link_info->req_duplex != link_info->duplex_setting)
5405 update_link = true;
5406 } else {
5407 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5408 update_link = true;
5409 if (link_info->advertising != link_info->auto_link_speeds)
5410 update_link = true;
5411 }
5412
5413 if (!bnxt_eee_config_ok(bp))
5414 update_eee = true;
5415
5416 if (update_link)
5417 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
5418 else if (update_pause)
5419 rc = bnxt_hwrm_set_pause(bp);
5420 if (rc) {
5421 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
5422 rc);
5423 return rc;
5424 }
5425
5426 return rc;
5427 }
5428
5429 /* Common routine to pre-map certain register block to different GRC window.
5430 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5431 * in PF and 3 windows in VF that can be customized to map in different
5432 * register blocks.
5433 */
5434 static void bnxt_preset_reg_win(struct bnxt *bp)
5435 {
5436 if (BNXT_PF(bp)) {
5437 /* CAG registers map to GRC window #4 */
5438 writel(BNXT_CAG_REG_BASE,
5439 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
5440 }
5441 }
5442
5443 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5444 {
5445 int rc = 0;
5446
5447 bnxt_preset_reg_win(bp);
5448 netif_carrier_off(bp->dev);
5449 if (irq_re_init) {
5450 rc = bnxt_setup_int_mode(bp);
5451 if (rc) {
5452 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
5453 rc);
5454 return rc;
5455 }
5456 }
5457 if ((bp->flags & BNXT_FLAG_RFS) &&
5458 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
5459 /* disable RFS if falling back to INTA */
5460 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
5461 bp->flags &= ~BNXT_FLAG_RFS;
5462 }
5463
5464 rc = bnxt_alloc_mem(bp, irq_re_init);
5465 if (rc) {
5466 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
5467 goto open_err_free_mem;
5468 }
5469
5470 if (irq_re_init) {
5471 bnxt_init_napi(bp);
5472 rc = bnxt_request_irq(bp);
5473 if (rc) {
5474 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
5475 goto open_err;
5476 }
5477 }
5478
5479 bnxt_enable_napi(bp);
5480
5481 rc = bnxt_init_nic(bp, irq_re_init);
5482 if (rc) {
5483 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
5484 goto open_err;
5485 }
5486
5487 if (link_re_init) {
5488 rc = bnxt_update_phy_setting(bp);
5489 if (rc)
5490 netdev_warn(bp->dev, "failed to update phy settings\n");
5491 }
5492
5493 if (irq_re_init)
5494 udp_tunnel_get_rx_info(bp->dev);
5495
5496 set_bit(BNXT_STATE_OPEN, &bp->state);
5497 bnxt_enable_int(bp);
5498 /* Enable TX queues */
5499 bnxt_tx_enable(bp);
5500 mod_timer(&bp->timer, jiffies + bp->current_interval);
5501 /* Poll link status and check for SFP+ module status */
5502 bnxt_get_port_module_status(bp);
5503
5504 return 0;
5505
5506 open_err:
5507 bnxt_disable_napi(bp);
5508 bnxt_del_napi(bp);
5509
5510 open_err_free_mem:
5511 bnxt_free_skbs(bp);
5512 bnxt_free_irq(bp);
5513 bnxt_free_mem(bp, true);
5514 return rc;
5515 }
5516
5517 /* rtnl_lock held */
5518 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5519 {
5520 int rc = 0;
5521
5522 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
5523 if (rc) {
5524 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
5525 dev_close(bp->dev);
5526 }
5527 return rc;
5528 }
5529
5530 static int bnxt_open(struct net_device *dev)
5531 {
5532 struct bnxt *bp = netdev_priv(dev);
5533 int rc = 0;
5534
5535 if (!test_bit(BNXT_STATE_FN_RST_DONE, &bp->state)) {
5536 rc = bnxt_hwrm_func_reset(bp);
5537 if (rc) {
5538 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
5539 rc);
5540 rc = -EBUSY;
5541 return rc;
5542 }
5543 /* Do func_reset during the 1st PF open only to prevent killing
5544 * the VFs when the PF is brought down and up.
5545 */
5546 if (BNXT_PF(bp))
5547 set_bit(BNXT_STATE_FN_RST_DONE, &bp->state);
5548 }
5549 return __bnxt_open_nic(bp, true, true);
5550 }
5551
5552 static void bnxt_disable_int_sync(struct bnxt *bp)
5553 {
5554 int i;
5555
5556 atomic_inc(&bp->intr_sem);
5557 if (!netif_running(bp->dev))
5558 return;
5559
5560 bnxt_disable_int(bp);
5561 for (i = 0; i < bp->cp_nr_rings; i++)
5562 synchronize_irq(bp->irq_tbl[i].vector);
5563 }
5564
5565 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5566 {
5567 int rc = 0;
5568
5569 #ifdef CONFIG_BNXT_SRIOV
5570 if (bp->sriov_cfg) {
5571 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
5572 !bp->sriov_cfg,
5573 BNXT_SRIOV_CFG_WAIT_TMO);
5574 if (rc)
5575 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
5576 }
5577 #endif
5578 /* Change device state to avoid TX queue wake up's */
5579 bnxt_tx_disable(bp);
5580
5581 clear_bit(BNXT_STATE_OPEN, &bp->state);
5582 smp_mb__after_atomic();
5583 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
5584 msleep(20);
5585
5586 /* Flush rings before disabling interrupts */
5587 bnxt_shutdown_nic(bp, irq_re_init);
5588
5589 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5590
5591 bnxt_disable_napi(bp);
5592 bnxt_disable_int_sync(bp);
5593 del_timer_sync(&bp->timer);
5594 bnxt_free_skbs(bp);
5595
5596 if (irq_re_init) {
5597 bnxt_free_irq(bp);
5598 bnxt_del_napi(bp);
5599 }
5600 bnxt_free_mem(bp, irq_re_init);
5601 return rc;
5602 }
5603
5604 static int bnxt_close(struct net_device *dev)
5605 {
5606 struct bnxt *bp = netdev_priv(dev);
5607
5608 bnxt_close_nic(bp, true, true);
5609 bnxt_hwrm_shutdown_link(bp);
5610 return 0;
5611 }
5612
5613 /* rtnl_lock held */
5614 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5615 {
5616 switch (cmd) {
5617 case SIOCGMIIPHY:
5618 /* fallthru */
5619 case SIOCGMIIREG: {
5620 if (!netif_running(dev))
5621 return -EAGAIN;
5622
5623 return 0;
5624 }
5625
5626 case SIOCSMIIREG:
5627 if (!netif_running(dev))
5628 return -EAGAIN;
5629
5630 return 0;
5631
5632 default:
5633 /* do nothing */
5634 break;
5635 }
5636 return -EOPNOTSUPP;
5637 }
5638
5639 static struct rtnl_link_stats64 *
5640 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5641 {
5642 u32 i;
5643 struct bnxt *bp = netdev_priv(dev);
5644
5645 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5646
5647 if (!bp->bnapi)
5648 return stats;
5649
5650 /* TODO check if we need to synchronize with bnxt_close path */
5651 for (i = 0; i < bp->cp_nr_rings; i++) {
5652 struct bnxt_napi *bnapi = bp->bnapi[i];
5653 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5654 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
5655
5656 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
5657 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
5658 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
5659
5660 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
5661 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
5662 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
5663
5664 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
5665 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
5666 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
5667
5668 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
5669 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
5670 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
5671
5672 stats->rx_missed_errors +=
5673 le64_to_cpu(hw_stats->rx_discard_pkts);
5674
5675 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
5676
5677 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
5678 }
5679
5680 if (bp->flags & BNXT_FLAG_PORT_STATS) {
5681 struct rx_port_stats *rx = bp->hw_rx_port_stats;
5682 struct tx_port_stats *tx = bp->hw_tx_port_stats;
5683
5684 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
5685 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
5686 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
5687 le64_to_cpu(rx->rx_ovrsz_frames) +
5688 le64_to_cpu(rx->rx_runt_frames);
5689 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
5690 le64_to_cpu(rx->rx_jbr_frames);
5691 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
5692 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
5693 stats->tx_errors = le64_to_cpu(tx->tx_err);
5694 }
5695
5696 return stats;
5697 }
5698
5699 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
5700 {
5701 struct net_device *dev = bp->dev;
5702 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5703 struct netdev_hw_addr *ha;
5704 u8 *haddr;
5705 int mc_count = 0;
5706 bool update = false;
5707 int off = 0;
5708
5709 netdev_for_each_mc_addr(ha, dev) {
5710 if (mc_count >= BNXT_MAX_MC_ADDRS) {
5711 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5712 vnic->mc_list_count = 0;
5713 return false;
5714 }
5715 haddr = ha->addr;
5716 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
5717 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
5718 update = true;
5719 }
5720 off += ETH_ALEN;
5721 mc_count++;
5722 }
5723 if (mc_count)
5724 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
5725
5726 if (mc_count != vnic->mc_list_count) {
5727 vnic->mc_list_count = mc_count;
5728 update = true;
5729 }
5730 return update;
5731 }
5732
5733 static bool bnxt_uc_list_updated(struct bnxt *bp)
5734 {
5735 struct net_device *dev = bp->dev;
5736 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5737 struct netdev_hw_addr *ha;
5738 int off = 0;
5739
5740 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
5741 return true;
5742
5743 netdev_for_each_uc_addr(ha, dev) {
5744 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
5745 return true;
5746
5747 off += ETH_ALEN;
5748 }
5749 return false;
5750 }
5751
5752 static void bnxt_set_rx_mode(struct net_device *dev)
5753 {
5754 struct bnxt *bp = netdev_priv(dev);
5755 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5756 u32 mask = vnic->rx_mask;
5757 bool mc_update = false;
5758 bool uc_update;
5759
5760 if (!netif_running(dev))
5761 return;
5762
5763 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
5764 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
5765 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
5766
5767 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5768 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5769
5770 uc_update = bnxt_uc_list_updated(bp);
5771
5772 if (dev->flags & IFF_ALLMULTI) {
5773 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5774 vnic->mc_list_count = 0;
5775 } else {
5776 mc_update = bnxt_mc_list_updated(bp, &mask);
5777 }
5778
5779 if (mask != vnic->rx_mask || uc_update || mc_update) {
5780 vnic->rx_mask = mask;
5781
5782 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
5783 schedule_work(&bp->sp_task);
5784 }
5785 }
5786
5787 static int bnxt_cfg_rx_mode(struct bnxt *bp)
5788 {
5789 struct net_device *dev = bp->dev;
5790 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5791 struct netdev_hw_addr *ha;
5792 int i, off = 0, rc;
5793 bool uc_update;
5794
5795 netif_addr_lock_bh(dev);
5796 uc_update = bnxt_uc_list_updated(bp);
5797 netif_addr_unlock_bh(dev);
5798
5799 if (!uc_update)
5800 goto skip_uc;
5801
5802 mutex_lock(&bp->hwrm_cmd_lock);
5803 for (i = 1; i < vnic->uc_filter_count; i++) {
5804 struct hwrm_cfa_l2_filter_free_input req = {0};
5805
5806 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
5807 -1);
5808
5809 req.l2_filter_id = vnic->fw_l2_filter_id[i];
5810
5811 rc = _hwrm_send_message(bp, &req, sizeof(req),
5812 HWRM_CMD_TIMEOUT);
5813 }
5814 mutex_unlock(&bp->hwrm_cmd_lock);
5815
5816 vnic->uc_filter_count = 1;
5817
5818 netif_addr_lock_bh(dev);
5819 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
5820 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5821 } else {
5822 netdev_for_each_uc_addr(ha, dev) {
5823 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
5824 off += ETH_ALEN;
5825 vnic->uc_filter_count++;
5826 }
5827 }
5828 netif_addr_unlock_bh(dev);
5829
5830 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
5831 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
5832 if (rc) {
5833 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
5834 rc);
5835 vnic->uc_filter_count = i;
5836 return rc;
5837 }
5838 }
5839
5840 skip_uc:
5841 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
5842 if (rc)
5843 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
5844 rc);
5845
5846 return rc;
5847 }
5848
5849 static bool bnxt_rfs_capable(struct bnxt *bp)
5850 {
5851 #ifdef CONFIG_RFS_ACCEL
5852 struct bnxt_pf_info *pf = &bp->pf;
5853 int vnics;
5854
5855 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
5856 return false;
5857
5858 vnics = 1 + bp->rx_nr_rings;
5859 if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics) {
5860 netdev_warn(bp->dev,
5861 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
5862 min(pf->max_rsscos_ctxs - 1, pf->max_vnics - 1));
5863 return false;
5864 }
5865
5866 return true;
5867 #else
5868 return false;
5869 #endif
5870 }
5871
5872 static netdev_features_t bnxt_fix_features(struct net_device *dev,
5873 netdev_features_t features)
5874 {
5875 struct bnxt *bp = netdev_priv(dev);
5876
5877 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
5878 features &= ~NETIF_F_NTUPLE;
5879
5880 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
5881 * turned on or off together.
5882 */
5883 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
5884 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
5885 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
5886 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5887 NETIF_F_HW_VLAN_STAG_RX);
5888 else
5889 features |= NETIF_F_HW_VLAN_CTAG_RX |
5890 NETIF_F_HW_VLAN_STAG_RX;
5891 }
5892 #ifdef CONFIG_BNXT_SRIOV
5893 if (BNXT_VF(bp)) {
5894 if (bp->vf.vlan) {
5895 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5896 NETIF_F_HW_VLAN_STAG_RX);
5897 }
5898 }
5899 #endif
5900 return features;
5901 }
5902
5903 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5904 {
5905 struct bnxt *bp = netdev_priv(dev);
5906 u32 flags = bp->flags;
5907 u32 changes;
5908 int rc = 0;
5909 bool re_init = false;
5910 bool update_tpa = false;
5911
5912 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5913 if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
5914 flags |= BNXT_FLAG_GRO;
5915 if (features & NETIF_F_LRO)
5916 flags |= BNXT_FLAG_LRO;
5917
5918 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5919 flags |= BNXT_FLAG_STRIP_VLAN;
5920
5921 if (features & NETIF_F_NTUPLE)
5922 flags |= BNXT_FLAG_RFS;
5923
5924 changes = flags ^ bp->flags;
5925 if (changes & BNXT_FLAG_TPA) {
5926 update_tpa = true;
5927 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5928 (flags & BNXT_FLAG_TPA) == 0)
5929 re_init = true;
5930 }
5931
5932 if (changes & ~BNXT_FLAG_TPA)
5933 re_init = true;
5934
5935 if (flags != bp->flags) {
5936 u32 old_flags = bp->flags;
5937
5938 bp->flags = flags;
5939
5940 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5941 if (update_tpa)
5942 bnxt_set_ring_params(bp);
5943 return rc;
5944 }
5945
5946 if (re_init) {
5947 bnxt_close_nic(bp, false, false);
5948 if (update_tpa)
5949 bnxt_set_ring_params(bp);
5950
5951 return bnxt_open_nic(bp, false, false);
5952 }
5953 if (update_tpa) {
5954 rc = bnxt_set_tpa(bp,
5955 (flags & BNXT_FLAG_TPA) ?
5956 true : false);
5957 if (rc)
5958 bp->flags = old_flags;
5959 }
5960 }
5961 return rc;
5962 }
5963
5964 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5965 {
5966 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
5967 int i = bnapi->index;
5968
5969 if (!txr)
5970 return;
5971
5972 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5973 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5974 txr->tx_cons);
5975 }
5976
5977 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5978 {
5979 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
5980 int i = bnapi->index;
5981
5982 if (!rxr)
5983 return;
5984
5985 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5986 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5987 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5988 rxr->rx_sw_agg_prod);
5989 }
5990
5991 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5992 {
5993 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5994 int i = bnapi->index;
5995
5996 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5997 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5998 }
5999
6000 static void bnxt_dbg_dump_states(struct bnxt *bp)
6001 {
6002 int i;
6003 struct bnxt_napi *bnapi;
6004
6005 for (i = 0; i < bp->cp_nr_rings; i++) {
6006 bnapi = bp->bnapi[i];
6007 if (netif_msg_drv(bp)) {
6008 bnxt_dump_tx_sw_state(bnapi);
6009 bnxt_dump_rx_sw_state(bnapi);
6010 bnxt_dump_cp_sw_state(bnapi);
6011 }
6012 }
6013 }
6014
6015 static void bnxt_reset_task(struct bnxt *bp, bool silent)
6016 {
6017 if (!silent)
6018 bnxt_dbg_dump_states(bp);
6019 if (netif_running(bp->dev)) {
6020 bnxt_close_nic(bp, false, false);
6021 bnxt_open_nic(bp, false, false);
6022 }
6023 }
6024
6025 static void bnxt_tx_timeout(struct net_device *dev)
6026 {
6027 struct bnxt *bp = netdev_priv(dev);
6028
6029 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
6030 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6031 schedule_work(&bp->sp_task);
6032 }
6033
6034 #ifdef CONFIG_NET_POLL_CONTROLLER
6035 static void bnxt_poll_controller(struct net_device *dev)
6036 {
6037 struct bnxt *bp = netdev_priv(dev);
6038 int i;
6039
6040 for (i = 0; i < bp->cp_nr_rings; i++) {
6041 struct bnxt_irq *irq = &bp->irq_tbl[i];
6042
6043 disable_irq(irq->vector);
6044 irq->handler(irq->vector, bp->bnapi[i]);
6045 enable_irq(irq->vector);
6046 }
6047 }
6048 #endif
6049
6050 static void bnxt_timer(unsigned long data)
6051 {
6052 struct bnxt *bp = (struct bnxt *)data;
6053 struct net_device *dev = bp->dev;
6054
6055 if (!netif_running(dev))
6056 return;
6057
6058 if (atomic_read(&bp->intr_sem) != 0)
6059 goto bnxt_restart_timer;
6060
6061 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
6062 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6063 schedule_work(&bp->sp_task);
6064 }
6065 bnxt_restart_timer:
6066 mod_timer(&bp->timer, jiffies + bp->current_interval);
6067 }
6068
6069 /* Only called from bnxt_sp_task() */
6070 static void bnxt_reset(struct bnxt *bp, bool silent)
6071 {
6072 /* bnxt_reset_task() calls bnxt_close_nic() which waits
6073 * for BNXT_STATE_IN_SP_TASK to clear.
6074 * If there is a parallel dev_close(), bnxt_close() may be holding
6075 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
6076 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6077 */
6078 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6079 rtnl_lock();
6080 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6081 bnxt_reset_task(bp, silent);
6082 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6083 rtnl_unlock();
6084 }
6085
6086 static void bnxt_cfg_ntp_filters(struct bnxt *);
6087
6088 static void bnxt_sp_task(struct work_struct *work)
6089 {
6090 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
6091 int rc;
6092
6093 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6094 smp_mb__after_atomic();
6095 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6096 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6097 return;
6098 }
6099
6100 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
6101 bnxt_cfg_rx_mode(bp);
6102
6103 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
6104 bnxt_cfg_ntp_filters(bp);
6105 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
6106 rc = bnxt_update_link(bp, true);
6107 if (rc)
6108 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
6109 rc);
6110 }
6111 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
6112 bnxt_hwrm_exec_fwd_req(bp);
6113 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6114 bnxt_hwrm_tunnel_dst_port_alloc(
6115 bp, bp->vxlan_port,
6116 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6117 }
6118 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6119 bnxt_hwrm_tunnel_dst_port_free(
6120 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6121 }
6122 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6123 bnxt_hwrm_tunnel_dst_port_alloc(
6124 bp, bp->nge_port,
6125 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6126 }
6127 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6128 bnxt_hwrm_tunnel_dst_port_free(
6129 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6130 }
6131 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
6132 bnxt_reset(bp, false);
6133
6134 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
6135 bnxt_reset(bp, true);
6136
6137 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event))
6138 bnxt_get_port_module_status(bp);
6139
6140 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
6141 bnxt_hwrm_port_qstats(bp);
6142
6143 smp_mb__before_atomic();
6144 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6145 }
6146
6147 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
6148 {
6149 int rc;
6150 struct bnxt *bp = netdev_priv(dev);
6151
6152 SET_NETDEV_DEV(dev, &pdev->dev);
6153
6154 /* enable device (incl. PCI PM wakeup), and bus-mastering */
6155 rc = pci_enable_device(pdev);
6156 if (rc) {
6157 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
6158 goto init_err;
6159 }
6160
6161 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6162 dev_err(&pdev->dev,
6163 "Cannot find PCI device base address, aborting\n");
6164 rc = -ENODEV;
6165 goto init_err_disable;
6166 }
6167
6168 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6169 if (rc) {
6170 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
6171 goto init_err_disable;
6172 }
6173
6174 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
6175 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
6176 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
6177 goto init_err_disable;
6178 }
6179
6180 pci_set_master(pdev);
6181
6182 bp->dev = dev;
6183 bp->pdev = pdev;
6184
6185 bp->bar0 = pci_ioremap_bar(pdev, 0);
6186 if (!bp->bar0) {
6187 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
6188 rc = -ENOMEM;
6189 goto init_err_release;
6190 }
6191
6192 bp->bar1 = pci_ioremap_bar(pdev, 2);
6193 if (!bp->bar1) {
6194 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
6195 rc = -ENOMEM;
6196 goto init_err_release;
6197 }
6198
6199 bp->bar2 = pci_ioremap_bar(pdev, 4);
6200 if (!bp->bar2) {
6201 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
6202 rc = -ENOMEM;
6203 goto init_err_release;
6204 }
6205
6206 pci_enable_pcie_error_reporting(pdev);
6207
6208 INIT_WORK(&bp->sp_task, bnxt_sp_task);
6209
6210 spin_lock_init(&bp->ntp_fltr_lock);
6211
6212 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
6213 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
6214
6215 /* tick values in micro seconds */
6216 bp->rx_coal_ticks = 12;
6217 bp->rx_coal_bufs = 30;
6218 bp->rx_coal_ticks_irq = 1;
6219 bp->rx_coal_bufs_irq = 2;
6220
6221 bp->tx_coal_ticks = 25;
6222 bp->tx_coal_bufs = 30;
6223 bp->tx_coal_ticks_irq = 2;
6224 bp->tx_coal_bufs_irq = 2;
6225
6226 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
6227
6228 init_timer(&bp->timer);
6229 bp->timer.data = (unsigned long)bp;
6230 bp->timer.function = bnxt_timer;
6231 bp->current_interval = BNXT_TIMER_INTERVAL;
6232
6233 clear_bit(BNXT_STATE_OPEN, &bp->state);
6234
6235 return 0;
6236
6237 init_err_release:
6238 if (bp->bar2) {
6239 pci_iounmap(pdev, bp->bar2);
6240 bp->bar2 = NULL;
6241 }
6242
6243 if (bp->bar1) {
6244 pci_iounmap(pdev, bp->bar1);
6245 bp->bar1 = NULL;
6246 }
6247
6248 if (bp->bar0) {
6249 pci_iounmap(pdev, bp->bar0);
6250 bp->bar0 = NULL;
6251 }
6252
6253 pci_release_regions(pdev);
6254
6255 init_err_disable:
6256 pci_disable_device(pdev);
6257
6258 init_err:
6259 return rc;
6260 }
6261
6262 /* rtnl_lock held */
6263 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6264 {
6265 struct sockaddr *addr = p;
6266 struct bnxt *bp = netdev_priv(dev);
6267 int rc = 0;
6268
6269 if (!is_valid_ether_addr(addr->sa_data))
6270 return -EADDRNOTAVAIL;
6271
6272 rc = bnxt_approve_mac(bp, addr->sa_data);
6273 if (rc)
6274 return rc;
6275
6276 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6277 return 0;
6278
6279 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6280 if (netif_running(dev)) {
6281 bnxt_close_nic(bp, false, false);
6282 rc = bnxt_open_nic(bp, false, false);
6283 }
6284
6285 return rc;
6286 }
6287
6288 /* rtnl_lock held */
6289 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6290 {
6291 struct bnxt *bp = netdev_priv(dev);
6292
6293 if (netif_running(dev))
6294 bnxt_close_nic(bp, false, false);
6295
6296 dev->mtu = new_mtu;
6297 bnxt_set_ring_params(bp);
6298
6299 if (netif_running(dev))
6300 return bnxt_open_nic(bp, false, false);
6301
6302 return 0;
6303 }
6304
6305 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
6306 struct tc_to_netdev *ntc)
6307 {
6308 struct bnxt *bp = netdev_priv(dev);
6309 u8 tc;
6310
6311 if (ntc->type != TC_SETUP_MQPRIO)
6312 return -EINVAL;
6313
6314 tc = ntc->tc;
6315
6316 if (tc > bp->max_tc) {
6317 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
6318 tc, bp->max_tc);
6319 return -EINVAL;
6320 }
6321
6322 if (netdev_get_num_tc(dev) == tc)
6323 return 0;
6324
6325 if (tc) {
6326 int max_rx_rings, max_tx_rings, rc;
6327 bool sh = false;
6328
6329 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6330 sh = true;
6331
6332 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6333 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
6334 return -ENOMEM;
6335 }
6336
6337 /* Needs to close the device and do hw resource re-allocations */
6338 if (netif_running(bp->dev))
6339 bnxt_close_nic(bp, true, false);
6340
6341 if (tc) {
6342 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
6343 netdev_set_num_tc(dev, tc);
6344 } else {
6345 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6346 netdev_reset_tc(dev);
6347 }
6348 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
6349 bp->num_stat_ctxs = bp->cp_nr_rings;
6350
6351 if (netif_running(bp->dev))
6352 return bnxt_open_nic(bp, true, false);
6353
6354 return 0;
6355 }
6356
6357 #ifdef CONFIG_RFS_ACCEL
6358 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
6359 struct bnxt_ntuple_filter *f2)
6360 {
6361 struct flow_keys *keys1 = &f1->fkeys;
6362 struct flow_keys *keys2 = &f2->fkeys;
6363
6364 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
6365 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
6366 keys1->ports.ports == keys2->ports.ports &&
6367 keys1->basic.ip_proto == keys2->basic.ip_proto &&
6368 keys1->basic.n_proto == keys2->basic.n_proto &&
6369 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
6370 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
6371 return true;
6372
6373 return false;
6374 }
6375
6376 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
6377 u16 rxq_index, u32 flow_id)
6378 {
6379 struct bnxt *bp = netdev_priv(dev);
6380 struct bnxt_ntuple_filter *fltr, *new_fltr;
6381 struct flow_keys *fkeys;
6382 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
6383 int rc = 0, idx, bit_id, l2_idx = 0;
6384 struct hlist_head *head;
6385
6386 if (skb->encapsulation)
6387 return -EPROTONOSUPPORT;
6388
6389 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
6390 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6391 int off = 0, j;
6392
6393 netif_addr_lock_bh(dev);
6394 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
6395 if (ether_addr_equal(eth->h_dest,
6396 vnic->uc_list + off)) {
6397 l2_idx = j + 1;
6398 break;
6399 }
6400 }
6401 netif_addr_unlock_bh(dev);
6402 if (!l2_idx)
6403 return -EINVAL;
6404 }
6405 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
6406 if (!new_fltr)
6407 return -ENOMEM;
6408
6409 fkeys = &new_fltr->fkeys;
6410 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
6411 rc = -EPROTONOSUPPORT;
6412 goto err_free;
6413 }
6414
6415 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
6416 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
6417 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
6418 rc = -EPROTONOSUPPORT;
6419 goto err_free;
6420 }
6421
6422 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
6423 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
6424
6425 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
6426 head = &bp->ntp_fltr_hash_tbl[idx];
6427 rcu_read_lock();
6428 hlist_for_each_entry_rcu(fltr, head, hash) {
6429 if (bnxt_fltr_match(fltr, new_fltr)) {
6430 rcu_read_unlock();
6431 rc = 0;
6432 goto err_free;
6433 }
6434 }
6435 rcu_read_unlock();
6436
6437 spin_lock_bh(&bp->ntp_fltr_lock);
6438 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6439 BNXT_NTP_FLTR_MAX_FLTR, 0);
6440 if (bit_id < 0) {
6441 spin_unlock_bh(&bp->ntp_fltr_lock);
6442 rc = -ENOMEM;
6443 goto err_free;
6444 }
6445
6446 new_fltr->sw_id = (u16)bit_id;
6447 new_fltr->flow_id = flow_id;
6448 new_fltr->l2_fltr_idx = l2_idx;
6449 new_fltr->rxq = rxq_index;
6450 hlist_add_head_rcu(&new_fltr->hash, head);
6451 bp->ntp_fltr_count++;
6452 spin_unlock_bh(&bp->ntp_fltr_lock);
6453
6454 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
6455 schedule_work(&bp->sp_task);
6456
6457 return new_fltr->sw_id;
6458
6459 err_free:
6460 kfree(new_fltr);
6461 return rc;
6462 }
6463
6464 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6465 {
6466 int i;
6467
6468 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
6469 struct hlist_head *head;
6470 struct hlist_node *tmp;
6471 struct bnxt_ntuple_filter *fltr;
6472 int rc;
6473
6474 head = &bp->ntp_fltr_hash_tbl[i];
6475 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
6476 bool del = false;
6477
6478 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
6479 if (rps_may_expire_flow(bp->dev, fltr->rxq,
6480 fltr->flow_id,
6481 fltr->sw_id)) {
6482 bnxt_hwrm_cfa_ntuple_filter_free(bp,
6483 fltr);
6484 del = true;
6485 }
6486 } else {
6487 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
6488 fltr);
6489 if (rc)
6490 del = true;
6491 else
6492 set_bit(BNXT_FLTR_VALID, &fltr->state);
6493 }
6494
6495 if (del) {
6496 spin_lock_bh(&bp->ntp_fltr_lock);
6497 hlist_del_rcu(&fltr->hash);
6498 bp->ntp_fltr_count--;
6499 spin_unlock_bh(&bp->ntp_fltr_lock);
6500 synchronize_rcu();
6501 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
6502 kfree(fltr);
6503 }
6504 }
6505 }
6506 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
6507 netdev_info(bp->dev, "Receive PF driver unload event!");
6508 }
6509
6510 #else
6511
6512 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6513 {
6514 }
6515
6516 #endif /* CONFIG_RFS_ACCEL */
6517
6518 static void bnxt_udp_tunnel_add(struct net_device *dev,
6519 struct udp_tunnel_info *ti)
6520 {
6521 struct bnxt *bp = netdev_priv(dev);
6522
6523 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
6524 return;
6525
6526 if (!netif_running(dev))
6527 return;
6528
6529 switch (ti->type) {
6530 case UDP_TUNNEL_TYPE_VXLAN:
6531 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
6532 return;
6533
6534 bp->vxlan_port_cnt++;
6535 if (bp->vxlan_port_cnt == 1) {
6536 bp->vxlan_port = ti->port;
6537 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
6538 schedule_work(&bp->sp_task);
6539 }
6540 break;
6541 case UDP_TUNNEL_TYPE_GENEVE:
6542 if (bp->nge_port_cnt && bp->nge_port != ti->port)
6543 return;
6544
6545 bp->nge_port_cnt++;
6546 if (bp->nge_port_cnt == 1) {
6547 bp->nge_port = ti->port;
6548 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
6549 }
6550 break;
6551 default:
6552 return;
6553 }
6554
6555 schedule_work(&bp->sp_task);
6556 }
6557
6558 static void bnxt_udp_tunnel_del(struct net_device *dev,
6559 struct udp_tunnel_info *ti)
6560 {
6561 struct bnxt *bp = netdev_priv(dev);
6562
6563 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
6564 return;
6565
6566 if (!netif_running(dev))
6567 return;
6568
6569 switch (ti->type) {
6570 case UDP_TUNNEL_TYPE_VXLAN:
6571 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
6572 return;
6573 bp->vxlan_port_cnt--;
6574
6575 if (bp->vxlan_port_cnt != 0)
6576 return;
6577
6578 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
6579 break;
6580 case UDP_TUNNEL_TYPE_GENEVE:
6581 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
6582 return;
6583 bp->nge_port_cnt--;
6584
6585 if (bp->nge_port_cnt != 0)
6586 return;
6587
6588 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
6589 break;
6590 default:
6591 return;
6592 }
6593
6594 schedule_work(&bp->sp_task);
6595 }
6596
6597 static const struct net_device_ops bnxt_netdev_ops = {
6598 .ndo_open = bnxt_open,
6599 .ndo_start_xmit = bnxt_start_xmit,
6600 .ndo_stop = bnxt_close,
6601 .ndo_get_stats64 = bnxt_get_stats64,
6602 .ndo_set_rx_mode = bnxt_set_rx_mode,
6603 .ndo_do_ioctl = bnxt_ioctl,
6604 .ndo_validate_addr = eth_validate_addr,
6605 .ndo_set_mac_address = bnxt_change_mac_addr,
6606 .ndo_change_mtu = bnxt_change_mtu,
6607 .ndo_fix_features = bnxt_fix_features,
6608 .ndo_set_features = bnxt_set_features,
6609 .ndo_tx_timeout = bnxt_tx_timeout,
6610 #ifdef CONFIG_BNXT_SRIOV
6611 .ndo_get_vf_config = bnxt_get_vf_config,
6612 .ndo_set_vf_mac = bnxt_set_vf_mac,
6613 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
6614 .ndo_set_vf_rate = bnxt_set_vf_bw,
6615 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
6616 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
6617 #endif
6618 #ifdef CONFIG_NET_POLL_CONTROLLER
6619 .ndo_poll_controller = bnxt_poll_controller,
6620 #endif
6621 .ndo_setup_tc = bnxt_setup_tc,
6622 #ifdef CONFIG_RFS_ACCEL
6623 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
6624 #endif
6625 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
6626 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
6627 #ifdef CONFIG_NET_RX_BUSY_POLL
6628 .ndo_busy_poll = bnxt_busy_poll,
6629 #endif
6630 };
6631
6632 static void bnxt_remove_one(struct pci_dev *pdev)
6633 {
6634 struct net_device *dev = pci_get_drvdata(pdev);
6635 struct bnxt *bp = netdev_priv(dev);
6636
6637 if (BNXT_PF(bp))
6638 bnxt_sriov_disable(bp);
6639
6640 pci_disable_pcie_error_reporting(pdev);
6641 unregister_netdev(dev);
6642 cancel_work_sync(&bp->sp_task);
6643 bp->sp_event = 0;
6644
6645 bnxt_hwrm_func_drv_unrgtr(bp);
6646 bnxt_free_hwrm_resources(bp);
6647 pci_iounmap(pdev, bp->bar2);
6648 pci_iounmap(pdev, bp->bar1);
6649 pci_iounmap(pdev, bp->bar0);
6650 free_netdev(dev);
6651
6652 pci_release_regions(pdev);
6653 pci_disable_device(pdev);
6654 }
6655
6656 static int bnxt_probe_phy(struct bnxt *bp)
6657 {
6658 int rc = 0;
6659 struct bnxt_link_info *link_info = &bp->link_info;
6660
6661 rc = bnxt_hwrm_phy_qcaps(bp);
6662 if (rc) {
6663 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
6664 rc);
6665 return rc;
6666 }
6667
6668 rc = bnxt_update_link(bp, false);
6669 if (rc) {
6670 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
6671 rc);
6672 return rc;
6673 }
6674
6675 /* Older firmware does not have supported_auto_speeds, so assume
6676 * that all supported speeds can be autonegotiated.
6677 */
6678 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
6679 link_info->support_auto_speeds = link_info->support_speeds;
6680
6681 /*initialize the ethool setting copy with NVM settings */
6682 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
6683 link_info->autoneg = BNXT_AUTONEG_SPEED;
6684 if (bp->hwrm_spec_code >= 0x10201) {
6685 if (link_info->auto_pause_setting &
6686 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
6687 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6688 } else {
6689 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6690 }
6691 link_info->advertising = link_info->auto_link_speeds;
6692 } else {
6693 link_info->req_link_speed = link_info->force_link_speed;
6694 link_info->req_duplex = link_info->duplex_setting;
6695 }
6696 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
6697 link_info->req_flow_ctrl =
6698 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
6699 else
6700 link_info->req_flow_ctrl = link_info->force_pause_setting;
6701 return rc;
6702 }
6703
6704 static int bnxt_get_max_irq(struct pci_dev *pdev)
6705 {
6706 u16 ctrl;
6707
6708 if (!pdev->msix_cap)
6709 return 1;
6710
6711 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
6712 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
6713 }
6714
6715 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
6716 int *max_cp)
6717 {
6718 int max_ring_grps = 0;
6719
6720 #ifdef CONFIG_BNXT_SRIOV
6721 if (!BNXT_PF(bp)) {
6722 *max_tx = bp->vf.max_tx_rings;
6723 *max_rx = bp->vf.max_rx_rings;
6724 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
6725 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
6726 max_ring_grps = bp->vf.max_hw_ring_grps;
6727 } else
6728 #endif
6729 {
6730 *max_tx = bp->pf.max_tx_rings;
6731 *max_rx = bp->pf.max_rx_rings;
6732 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
6733 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
6734 max_ring_grps = bp->pf.max_hw_ring_grps;
6735 }
6736 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
6737 *max_cp -= 1;
6738 *max_rx -= 2;
6739 }
6740 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6741 *max_rx >>= 1;
6742 *max_rx = min_t(int, *max_rx, max_ring_grps);
6743 }
6744
6745 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
6746 {
6747 int rx, tx, cp;
6748
6749 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
6750 if (!rx || !tx || !cp)
6751 return -ENOMEM;
6752
6753 *max_rx = rx;
6754 *max_tx = tx;
6755 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
6756 }
6757
6758 static int bnxt_set_dflt_rings(struct bnxt *bp)
6759 {
6760 int dflt_rings, max_rx_rings, max_tx_rings, rc;
6761 bool sh = true;
6762
6763 if (sh)
6764 bp->flags |= BNXT_FLAG_SHARED_RINGS;
6765 dflt_rings = netif_get_num_default_rss_queues();
6766 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6767 if (rc)
6768 return rc;
6769 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
6770 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
6771 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6772 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6773 bp->tx_nr_rings + bp->rx_nr_rings;
6774 bp->num_stat_ctxs = bp->cp_nr_rings;
6775 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6776 bp->rx_nr_rings++;
6777 bp->cp_nr_rings++;
6778 }
6779 return rc;
6780 }
6781
6782 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
6783 {
6784 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
6785 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
6786
6787 if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
6788 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
6789 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
6790 else
6791 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
6792 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
6793 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
6794 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
6795 "Unknown", width);
6796 }
6797
6798 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6799 {
6800 static int version_printed;
6801 struct net_device *dev;
6802 struct bnxt *bp;
6803 int rc, max_irqs;
6804
6805 if (pdev->device == 0x16cd && pci_is_bridge(pdev))
6806 return -ENODEV;
6807
6808 if (version_printed++ == 0)
6809 pr_info("%s", version);
6810
6811 max_irqs = bnxt_get_max_irq(pdev);
6812 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
6813 if (!dev)
6814 return -ENOMEM;
6815
6816 bp = netdev_priv(dev);
6817
6818 if (bnxt_vf_pciid(ent->driver_data))
6819 bp->flags |= BNXT_FLAG_VF;
6820
6821 if (pdev->msix_cap)
6822 bp->flags |= BNXT_FLAG_MSIX_CAP;
6823
6824 rc = bnxt_init_board(pdev, dev);
6825 if (rc < 0)
6826 goto init_err_free;
6827
6828 dev->netdev_ops = &bnxt_netdev_ops;
6829 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
6830 dev->ethtool_ops = &bnxt_ethtool_ops;
6831
6832 pci_set_drvdata(pdev, dev);
6833
6834 rc = bnxt_alloc_hwrm_resources(bp);
6835 if (rc)
6836 goto init_err;
6837
6838 mutex_init(&bp->hwrm_cmd_lock);
6839 rc = bnxt_hwrm_ver_get(bp);
6840 if (rc)
6841 goto init_err;
6842
6843 bnxt_hwrm_fw_set_time(bp);
6844
6845 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6846 NETIF_F_TSO | NETIF_F_TSO6 |
6847 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6848 NETIF_F_GSO_IPXIP4 |
6849 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6850 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
6851 NETIF_F_RXCSUM | NETIF_F_GRO;
6852
6853 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
6854 dev->hw_features |= NETIF_F_LRO;
6855
6856 dev->hw_enc_features =
6857 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6858 NETIF_F_TSO | NETIF_F_TSO6 |
6859 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6860 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6861 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
6862 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
6863 NETIF_F_GSO_GRE_CSUM;
6864 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
6865 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6866 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
6867 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
6868 dev->priv_flags |= IFF_UNICAST_FLT;
6869
6870 /* MTU range: 60 - 9500 */
6871 dev->min_mtu = ETH_ZLEN;
6872 dev->max_mtu = 9500;
6873
6874 #ifdef CONFIG_BNXT_SRIOV
6875 init_waitqueue_head(&bp->sriov_cfg_wait);
6876 #endif
6877 bp->gro_func = bnxt_gro_func_5730x;
6878 if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
6879 bp->gro_func = bnxt_gro_func_5731x;
6880
6881 rc = bnxt_hwrm_func_drv_rgtr(bp);
6882 if (rc)
6883 goto init_err;
6884
6885 /* Get the MAX capabilities for this function */
6886 rc = bnxt_hwrm_func_qcaps(bp);
6887 if (rc) {
6888 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
6889 rc);
6890 rc = -1;
6891 goto init_err;
6892 }
6893
6894 rc = bnxt_hwrm_queue_qportcfg(bp);
6895 if (rc) {
6896 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
6897 rc);
6898 rc = -1;
6899 goto init_err;
6900 }
6901
6902 bnxt_hwrm_func_qcfg(bp);
6903
6904 bnxt_set_tpa_flags(bp);
6905 bnxt_set_ring_params(bp);
6906 if (BNXT_PF(bp))
6907 bp->pf.max_irqs = max_irqs;
6908 #if defined(CONFIG_BNXT_SRIOV)
6909 else
6910 bp->vf.max_irqs = max_irqs;
6911 #endif
6912 bnxt_set_dflt_rings(bp);
6913
6914 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6915 dev->hw_features |= NETIF_F_NTUPLE;
6916 if (bnxt_rfs_capable(bp)) {
6917 bp->flags |= BNXT_FLAG_RFS;
6918 dev->features |= NETIF_F_NTUPLE;
6919 }
6920 }
6921
6922 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
6923 bp->flags |= BNXT_FLAG_STRIP_VLAN;
6924
6925 rc = bnxt_probe_phy(bp);
6926 if (rc)
6927 goto init_err;
6928
6929 rc = register_netdev(dev);
6930 if (rc)
6931 goto init_err;
6932
6933 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
6934 board_info[ent->driver_data].name,
6935 (long)pci_resource_start(pdev, 0), dev->dev_addr);
6936
6937 bnxt_parse_log_pcie_link(bp);
6938
6939 return 0;
6940
6941 init_err:
6942 pci_iounmap(pdev, bp->bar0);
6943 pci_release_regions(pdev);
6944 pci_disable_device(pdev);
6945
6946 init_err_free:
6947 free_netdev(dev);
6948 return rc;
6949 }
6950
6951 /**
6952 * bnxt_io_error_detected - called when PCI error is detected
6953 * @pdev: Pointer to PCI device
6954 * @state: The current pci connection state
6955 *
6956 * This function is called after a PCI bus error affecting
6957 * this device has been detected.
6958 */
6959 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
6960 pci_channel_state_t state)
6961 {
6962 struct net_device *netdev = pci_get_drvdata(pdev);
6963 struct bnxt *bp = netdev_priv(netdev);
6964
6965 netdev_info(netdev, "PCI I/O error detected\n");
6966
6967 rtnl_lock();
6968 netif_device_detach(netdev);
6969
6970 if (state == pci_channel_io_perm_failure) {
6971 rtnl_unlock();
6972 return PCI_ERS_RESULT_DISCONNECT;
6973 }
6974
6975 if (netif_running(netdev))
6976 bnxt_close(netdev);
6977
6978 /* So that func_reset will be done during slot_reset */
6979 clear_bit(BNXT_STATE_FN_RST_DONE, &bp->state);
6980 pci_disable_device(pdev);
6981 rtnl_unlock();
6982
6983 /* Request a slot slot reset. */
6984 return PCI_ERS_RESULT_NEED_RESET;
6985 }
6986
6987 /**
6988 * bnxt_io_slot_reset - called after the pci bus has been reset.
6989 * @pdev: Pointer to PCI device
6990 *
6991 * Restart the card from scratch, as if from a cold-boot.
6992 * At this point, the card has exprienced a hard reset,
6993 * followed by fixups by BIOS, and has its config space
6994 * set up identically to what it was at cold boot.
6995 */
6996 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
6997 {
6998 struct net_device *netdev = pci_get_drvdata(pdev);
6999 struct bnxt *bp = netdev_priv(netdev);
7000 int err = 0;
7001 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
7002
7003 netdev_info(bp->dev, "PCI Slot Reset\n");
7004
7005 rtnl_lock();
7006
7007 if (pci_enable_device(pdev)) {
7008 dev_err(&pdev->dev,
7009 "Cannot re-enable PCI device after reset.\n");
7010 } else {
7011 pci_set_master(pdev);
7012
7013 if (netif_running(netdev))
7014 err = bnxt_open(netdev);
7015
7016 if (!err)
7017 result = PCI_ERS_RESULT_RECOVERED;
7018 }
7019
7020 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
7021 dev_close(netdev);
7022
7023 rtnl_unlock();
7024
7025 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7026 if (err) {
7027 dev_err(&pdev->dev,
7028 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7029 err); /* non-fatal, continue */
7030 }
7031
7032 return PCI_ERS_RESULT_RECOVERED;
7033 }
7034
7035 /**
7036 * bnxt_io_resume - called when traffic can start flowing again.
7037 * @pdev: Pointer to PCI device
7038 *
7039 * This callback is called when the error recovery driver tells
7040 * us that its OK to resume normal operation.
7041 */
7042 static void bnxt_io_resume(struct pci_dev *pdev)
7043 {
7044 struct net_device *netdev = pci_get_drvdata(pdev);
7045
7046 rtnl_lock();
7047
7048 netif_device_attach(netdev);
7049
7050 rtnl_unlock();
7051 }
7052
7053 static const struct pci_error_handlers bnxt_err_handler = {
7054 .error_detected = bnxt_io_error_detected,
7055 .slot_reset = bnxt_io_slot_reset,
7056 .resume = bnxt_io_resume
7057 };
7058
7059 static struct pci_driver bnxt_pci_driver = {
7060 .name = DRV_MODULE_NAME,
7061 .id_table = bnxt_pci_tbl,
7062 .probe = bnxt_init_one,
7063 .remove = bnxt_remove_one,
7064 .err_handler = &bnxt_err_handler,
7065 #if defined(CONFIG_BNXT_SRIOV)
7066 .sriov_configure = bnxt_sriov_configure,
7067 #endif
7068 };
7069
7070 module_pci_driver(bnxt_pci_driver);
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