drivers/staging/imx-drm/ipu-v3/ipu-dc.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15
  16 #include <linux/export.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/errno.h>
  20 #include <linux/delay.h>
  21 #include <linux/io.h>
  22
  23 #include "../imx-drm.h"
  24 #include "imx-ipu-v3.h"
  25 #include "ipu-prv.h"
  26
  27 #define DC_MAP_CONF_PTR(n)      (0x108 + ((n) & ~0x1) * 2)
  28 #define DC_MAP_CONF_VAL(n)      (0x144 + ((n) & ~0x1) * 2)
  29
  30 #define DC_EVT_NF               0
  31 #define DC_EVT_NL               1
  32 #define DC_EVT_EOF              2
  33 #define DC_EVT_NFIELD           3
  34 #define DC_EVT_EOL              4
  35 #define DC_EVT_EOFIELD          5
  36 #define DC_EVT_NEW_ADDR         6
  37 #define DC_EVT_NEW_CHAN         7
  38 #define DC_EVT_NEW_DATA         8
  39
  40 #define DC_EVT_NEW_ADDR_W_0     0
  41 #define DC_EVT_NEW_ADDR_W_1     1
  42 #define DC_EVT_NEW_CHAN_W_0     2
  43 #define DC_EVT_NEW_CHAN_W_1     3
  44 #define DC_EVT_NEW_DATA_W_0     4
  45 #define DC_EVT_NEW_DATA_W_1     5
  46 #define DC_EVT_NEW_ADDR_R_0     6
  47 #define DC_EVT_NEW_ADDR_R_1     7
  48 #define DC_EVT_NEW_CHAN_R_0     8
  49 #define DC_EVT_NEW_CHAN_R_1     9
  50 #define DC_EVT_NEW_DATA_R_0     10
  51 #define DC_EVT_NEW_DATA_R_1     11
  52
  53 #define DC_WR_CH_CONF           0x0
  54 #define DC_WR_CH_ADDR           0x4
  55 #define DC_RL_CH(evt)           (8 + ((evt) & ~0x1) * 2)
  56
  57 #define DC_GEN                  0xd4
  58 #define DC_DISP_CONF1(disp)     (0xd8 + (disp) * 4)
  59 #define DC_DISP_CONF2(disp)     (0xe8 + (disp) * 4)
  60 #define DC_STAT                 0x1c8
  61
  62 #define WROD(lf)                (0x18 | ((lf) << 1))
  63 #define WRG                     0x01
  64 #define WCLK                    0xc9
  65
  66 #define SYNC_WAVE 0
  67 #define NULL_WAVE (-1)
  68
  69 #define DC_GEN_SYNC_1_6_SYNC    (2 << 1)
  70 #define DC_GEN_SYNC_PRIORITY_1  (1 << 7)
  71
  72 #define DC_WR_CH_CONF_WORD_SIZE_8               (0 << 0)
  73 #define DC_WR_CH_CONF_WORD_SIZE_16              (1 << 0)
  74 #define DC_WR_CH_CONF_WORD_SIZE_24              (2 << 0)
  75 #define DC_WR_CH_CONF_WORD_SIZE_32              (3 << 0)
  76 #define DC_WR_CH_CONF_DISP_ID_PARALLEL(i)       (((i) & 0x1) << 3)
  77 #define DC_WR_CH_CONF_DISP_ID_SERIAL            (2 << 3)
  78 #define DC_WR_CH_CONF_DISP_ID_ASYNC             (3 << 4)
  79 #define DC_WR_CH_CONF_FIELD_MODE                (1 << 9)
  80 #define DC_WR_CH_CONF_PROG_TYPE_NORMAL          (4 << 5)
  81 #define DC_WR_CH_CONF_PROG_TYPE_MASK            (7 << 5)
  82 #define DC_WR_CH_CONF_PROG_DI_ID                (1 << 2)
  83 #define DC_WR_CH_CONF_PROG_DISP_ID(i)           (((i) & 0x1) << 3)
  84
  85 #define IPU_DC_NUM_CHANNELS     10
  86
  87 struct ipu_dc_priv;
  88
  89 enum ipu_dc_map {
  90         IPU_DC_MAP_RGB24,
  91         IPU_DC_MAP_RGB565,
  92         IPU_DC_MAP_GBR24, /* TVEv2 */
  93         IPU_DC_MAP_BGR666,
  94 };
  95
  96 struct ipu_dc {
  97         /* The display interface number assigned to this dc channel */
  98         unsigned int            di;
  99         void __iomem            *base;
 100         struct ipu_dc_priv      *priv;
 101         int                     chno;
 102         bool                    in_use;
 103 };
 104
 105 struct ipu_dc_priv {
 106         void __iomem            *dc_reg;
 107         void __iomem            *dc_tmpl_reg;
 108         struct ipu_soc          *ipu;
 109         struct device           *dev;
 110         struct ipu_dc           channels[IPU_DC_NUM_CHANNELS];
 111         struct mutex            mutex;
 112 };
 113
 114 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
 115 {
 116         u32 reg;
 117
 118         reg = readl(dc->base + DC_RL_CH(event));
 119         reg &= ~(0xffff << (16 * (event & 0x1)));
 120         reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
 121         writel(reg, dc->base + DC_RL_CH(event));
 122 }
 123
 124 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
 125                 int map, int wave, int glue, int sync, int stop)
 126 {
 127         struct ipu_dc_priv *priv = dc->priv;
 128         u32 reg1, reg2;
 129
 130         if (opcode == WCLK) {
 131                 reg1 = (operand << 20) & 0xfff00000;
 132                 reg2 = operand >> 12 | opcode << 1 | stop << 9;
 133         } else if (opcode == WRG) {
 134                 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
 135                 reg2 = operand >> 17 | opcode << 7 | stop << 9;
 136         } else {
 137                 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
 138                 reg2 = operand >> 12 | opcode << 4 | stop << 9;
 139         }
 140         writel(reg1, priv->dc_tmpl_reg + word * 8);
 141         writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
 142 }
 143
 144 static int ipu_pixfmt_to_map(u32 fmt)
 145 {
 146         switch (fmt) {
 147         case V4L2_PIX_FMT_RGB24:
 148                 return IPU_DC_MAP_RGB24;
 149         case V4L2_PIX_FMT_RGB565:
 150                 return IPU_DC_MAP_RGB565;
 151         case IPU_PIX_FMT_GBR24:
 152                 return IPU_DC_MAP_GBR24;
 153         case V4L2_PIX_FMT_BGR666:
 154                 return IPU_DC_MAP_BGR666;
 155         default:
 156                 return -EINVAL;
 157         }
 158 }
 159
 160 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
 161                 u32 pixel_fmt, u32 width)
 162 {
 163         struct ipu_dc_priv *priv = dc->priv;
 164         u32 reg = 0;
 165         int map;
 166
 167         dc->di = ipu_di_get_num(di);
 168
 169         map = ipu_pixfmt_to_map(pixel_fmt);
 170         if (map < 0) {
 171                 dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
 172                 return map;
 173         }
 174
 175         if (interlaced) {
 176                 dc_link_event(dc, DC_EVT_NL, 0, 3);
 177                 dc_link_event(dc, DC_EVT_EOL, 0, 2);
 178                 dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);
 179
 180                 /* Init template microcode */
 181                 dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
 182         } else {
 183                 if (dc->di) {
 184                         dc_link_event(dc, DC_EVT_NL, 2, 3);
 185                         dc_link_event(dc, DC_EVT_EOL, 3, 2);
 186                         dc_link_event(dc, DC_EVT_NEW_DATA, 1, 1);
 187                         /* Init template microcode */
 188                         dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
 189                         dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
 190                         dc_write_tmpl(dc, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
 191                         dc_write_tmpl(dc, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
 192                 } else {
 193                         dc_link_event(dc, DC_EVT_NL, 5, 3);
 194                         dc_link_event(dc, DC_EVT_EOL, 6, 2);
 195                         dc_link_event(dc, DC_EVT_NEW_DATA, 8, 1);
 196                         /* Init template microcode */
 197                         dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
 198                         dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
 199                         dc_write_tmpl(dc, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
 200                         dc_write_tmpl(dc, 8, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
 201                 }
 202         }
 203         dc_link_event(dc, DC_EVT_NF, 0, 0);
 204         dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
 205         dc_link_event(dc, DC_EVT_EOF, 0, 0);
 206         dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
 207         dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
 208         dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
 209
 210         reg = readl(dc->base + DC_WR_CH_CONF);
 211         if (interlaced)
 212                 reg |= DC_WR_CH_CONF_FIELD_MODE;
 213         else
 214                 reg &= ~DC_WR_CH_CONF_FIELD_MODE;
 215         writel(reg, dc->base + DC_WR_CH_CONF);
 216
 217         writel(0x0, dc->base + DC_WR_CH_ADDR);
 218         writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
 219
 220         ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
 221
 222         return 0;
 223 }
 224 EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
 225
 226 void ipu_dc_enable_channel(struct ipu_dc *dc)
 227 {
 228         int di;
 229         u32 reg;
 230
 231         di = dc->di;
 232
 233         reg = readl(dc->base + DC_WR_CH_CONF);
 234         reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
 235         writel(reg, dc->base + DC_WR_CH_CONF);
 236 }
 237 EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
 238
 239 void ipu_dc_disable_channel(struct ipu_dc *dc)
 240 {
 241         struct ipu_dc_priv *priv = dc->priv;
 242         u32 val;
 243         int irq = 0, timeout = 50;
 244
 245         if (dc->chno == 1)
 246                 irq = IPU_IRQ_DC_FC_1;
 247         else if (dc->chno == 5)
 248                 irq = IPU_IRQ_DP_SF_END;
 249         else
 250                 return;
 251
 252         /* should wait for the interrupt here */
 253         mdelay(50);
 254
 255         if (dc->di == 0)
 256                 val = 0x00000002;
 257         else
 258                 val = 0x00000020;
 259
 260         /* Wait for DC triple buffer to empty */
 261         while ((readl(priv->dc_reg + DC_STAT) & val) != val) {
 262                 msleep(2);
 263                 timeout -= 2;
 264                 if (timeout <= 0)
 265                         break;
 266         }
 267
 268         val = readl(dc->base + DC_WR_CH_CONF);
 269         val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 270         writel(val, dc->base + DC_WR_CH_CONF);
 271 }
 272 EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
 273
 274 static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
 275                 int byte_num, int offset, int mask)
 276 {
 277         int ptr = map * 3 + byte_num;
 278         u32 reg;
 279
 280         reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
 281         reg &= ~(0xffff << (16 * (ptr & 0x1)));
 282         reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
 283         writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
 284
 285         reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
 286         reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
 287         reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
 288         writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
 289 }
 290
 291 static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
 292 {
 293         u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
 294
 295         writel(reg & ~(0xffff << (16 * (map & 0x1))),
 296                      priv->dc_reg + DC_MAP_CONF_PTR(map));
 297 }
 298
 299 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
 300 {
 301         struct ipu_dc_priv *priv = ipu->dc_priv;
 302         struct ipu_dc *dc;
 303
 304         if (channel >= IPU_DC_NUM_CHANNELS)
 305                 return ERR_PTR(-ENODEV);
 306
 307         dc = &priv->channels[channel];
 308
 309         mutex_lock(&priv->mutex);
 310
 311         if (dc->in_use) {
 312                 mutex_unlock(&priv->mutex);
 313                 return ERR_PTR(-EBUSY);
 314         }
 315
 316         dc->in_use = 1;
 317
 318         mutex_unlock(&priv->mutex);
 319
 320         return dc;
 321 }
 322 EXPORT_SYMBOL_GPL(ipu_dc_get);
 323
 324 void ipu_dc_put(struct ipu_dc *dc)
 325 {
 326         struct ipu_dc_priv *priv = dc->priv;
 327
 328         mutex_lock(&priv->mutex);
 329         dc->in_use = 0;
 330         mutex_unlock(&priv->mutex);
 331 }
 332 EXPORT_SYMBOL_GPL(ipu_dc_put);
 333
 334 int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
 335                 unsigned long base, unsigned long template_base)
 336 {
 337         struct ipu_dc_priv *priv;
 338         static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
 339                 0x78, 0, 0x94, 0xb4};
 340         int i;
 341
 342         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 343         if (!priv)
 344                 return -ENOMEM;
 345
 346         mutex_init(&priv->mutex);
 347
 348         priv->dev = dev;
 349         priv->ipu = ipu;
 350         priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
 351         priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
 352         if (!priv->dc_reg || !priv->dc_tmpl_reg)
 353                 return -ENOMEM;
 354
 355         for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
 356                 priv->channels[i].chno = i;
 357                 priv->channels[i].priv = priv;
 358                 priv->channels[i].base = priv->dc_reg + channel_offsets[i];
 359         }
 360
 361         writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
 362                         DC_WR_CH_CONF_PROG_DI_ID,
 363                         priv->channels[1].base + DC_WR_CH_CONF);
 364         writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
 365                         priv->channels[5].base + DC_WR_CH_CONF);
 366
 367         writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1, priv->dc_reg + DC_GEN);
 368
 369         ipu->dc_priv = priv;
 370
 371         dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
 372                         base, template_base);
 373
 374         /* rgb24 */
 375         ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
 376         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
 377         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
 378         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
 379
 380         /* rgb565 */
 381         ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
 382         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
 383         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
 384         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
 385
 386         /* gbr24 */
 387         ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
 388         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
 389         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
 390         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
 391
 392         /* bgr666 */
 393         ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
 394         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
 395         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
 396         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
 397
 398         return 0;
 399 }
 400
 401 void ipu_dc_exit(struct ipu_soc *ipu)
 402 {
 403 }