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mmc: omap_hsmmc: remove unused get_context_loss_count callback
[linux-2.6/btrfs-unstable.git] / drivers / gpio / gpio-davinci.c
blob9f0682534e2f46376a7086bc306cf195cc6e8e6f
1 /*
2 * TI DaVinci GPIO Support
3 *
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12 #include <linux/gpio.h>
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/platform_data/gpio-davinci.h>
25 #include <linux/irqchip/chained_irq.h>
26
27 struct davinci_gpio_regs {
28 u32 dir;
29 u32 out_data;
30 u32 set_data;
31 u32 clr_data;
32 u32 in_data;
33 u32 set_rising;
34 u32 clr_rising;
35 u32 set_falling;
36 u32 clr_falling;
37 u32 intstat;
38 };
39
40 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
41
42 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
43
44 #define chip2controller(chip) \
45 container_of(chip, struct davinci_gpio_controller, chip)
46
47 static void __iomem *gpio_base;
48
49 static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
50 {
51 void __iomem *ptr;
52
53 if (gpio < 32 * 1)
54 ptr = gpio_base + 0x10;
55 else if (gpio < 32 * 2)
56 ptr = gpio_base + 0x38;
57 else if (gpio < 32 * 3)
58 ptr = gpio_base + 0x60;
59 else if (gpio < 32 * 4)
60 ptr = gpio_base + 0x88;
61 else if (gpio < 32 * 5)
62 ptr = gpio_base + 0xb0;
63 else
64 ptr = NULL;
65 return ptr;
66 }
67
68 static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
69 {
70 struct davinci_gpio_regs __iomem *g;
71
72 g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
73
74 return g;
75 }
76
77 static int davinci_gpio_irq_setup(struct platform_device *pdev);
78
79 /*--------------------------------------------------------------------------*/
80
81 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
82 static inline int __davinci_direction(struct gpio_chip *chip,
83 unsigned offset, bool out, int value)
84 {
85 struct davinci_gpio_controller *d = chip2controller(chip);
86 struct davinci_gpio_regs __iomem *g = d->regs;
87 unsigned long flags;
88 u32 temp;
89 u32 mask = 1 << offset;
90
91 spin_lock_irqsave(&d->lock, flags);
92 temp = readl_relaxed(&g->dir);
93 if (out) {
94 temp &= ~mask;
95 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
96 } else {
97 temp |= mask;
98 }
99 writel_relaxed(temp, &g->dir);
100 spin_unlock_irqrestore(&d->lock, flags);
101
102 return 0;
103 }
104
105 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
106 {
107 return __davinci_direction(chip, offset, false, 0);
108 }
109
110 static int
111 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
112 {
113 return __davinci_direction(chip, offset, true, value);
114 }
115
116 /*
117 * Read the pin's value (works even if it's set up as output);
118 * returns zero/nonzero.
119 *
120 * Note that changes are synched to the GPIO clock, so reading values back
121 * right after you've set them may give old values.
122 */
123 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
124 {
125 struct davinci_gpio_controller *d = chip2controller(chip);
126 struct davinci_gpio_regs __iomem *g = d->regs;
127
128 return (1 << offset) & readl_relaxed(&g->in_data);
129 }
130
131 /*
132 * Assuming the pin is muxed as a gpio output, set its output value.
133 */
134 static void
135 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
136 {
137 struct davinci_gpio_controller *d = chip2controller(chip);
138 struct davinci_gpio_regs __iomem *g = d->regs;
139
140 writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
141 }
142
143 static struct davinci_gpio_platform_data *
144 davinci_gpio_get_pdata(struct platform_device *pdev)
145 {
146 struct device_node *dn = pdev->dev.of_node;
147 struct davinci_gpio_platform_data *pdata;
148 int ret;
149 u32 val;
150
151 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
152 return pdev->dev.platform_data;
153
154 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
155 if (!pdata)
156 return NULL;
157
158 ret = of_property_read_u32(dn, "ti,ngpio", &val);
159 if (ret)
160 goto of_err;
161
162 pdata->ngpio = val;
163
164 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
165 if (ret)
166 goto of_err;
167
168 pdata->gpio_unbanked = val;
169
170 return pdata;
171
172 of_err:
173 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
174 return NULL;
175 }
176
177 #ifdef CONFIG_OF_GPIO
178 static int davinci_gpio_of_xlate(struct gpio_chip *gc,
179 const struct of_phandle_args *gpiospec,
180 u32 *flags)
181 {
182 struct davinci_gpio_controller *chips = dev_get_drvdata(gc->dev);
183 struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->dev);
184
185 if (gpiospec->args[0] > pdata->ngpio)
186 return -EINVAL;
187
188 if (gc != &chips[gpiospec->args[0] / 32].chip)
189 return -EINVAL;
190
191 if (flags)
192 *flags = gpiospec->args[1];
193
194 return gpiospec->args[0] % 32;
195 }
196 #endif
197
198 static int davinci_gpio_probe(struct platform_device *pdev)
199 {
200 int i, base;
201 unsigned ngpio;
202 struct davinci_gpio_controller *chips;
203 struct davinci_gpio_platform_data *pdata;
204 struct davinci_gpio_regs __iomem *regs;
205 struct device *dev = &pdev->dev;
206 struct resource *res;
207
208 pdata = davinci_gpio_get_pdata(pdev);
209 if (!pdata) {
210 dev_err(dev, "No platform data found\n");
211 return -EINVAL;
212 }
213
214 dev->platform_data = pdata;
215
216 /*
217 * The gpio banks conceptually expose a segmented bitmap,
218 * and "ngpio" is one more than the largest zero-based
219 * bit index that's valid.
220 */
221 ngpio = pdata->ngpio;
222 if (ngpio == 0) {
223 dev_err(dev, "How many GPIOs?\n");
224 return -EINVAL;
225 }
226
227 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
228 ngpio = ARCH_NR_GPIOS;
229
230 chips = devm_kzalloc(dev,
231 ngpio * sizeof(struct davinci_gpio_controller),
232 GFP_KERNEL);
233 if (!chips)
234 return -ENOMEM;
235
236 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
237 if (!res) {
238 dev_err(dev, "Invalid memory resource\n");
239 return -EBUSY;
240 }
241
242 gpio_base = devm_ioremap_resource(dev, res);
243 if (IS_ERR(gpio_base))
244 return PTR_ERR(gpio_base);
245
246 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
247 chips[i].chip.label = "DaVinci";
248
249 chips[i].chip.direction_input = davinci_direction_in;
250 chips[i].chip.get = davinci_gpio_get;
251 chips[i].chip.direction_output = davinci_direction_out;
252 chips[i].chip.set = davinci_gpio_set;
253
254 chips[i].chip.base = base;
255 chips[i].chip.ngpio = ngpio - base;
256 if (chips[i].chip.ngpio > 32)
257 chips[i].chip.ngpio = 32;
258
259 #ifdef CONFIG_OF_GPIO
260 chips[i].chip.of_gpio_n_cells = 2;
261 chips[i].chip.of_xlate = davinci_gpio_of_xlate;
262 chips[i].chip.dev = dev;
263 chips[i].chip.of_node = dev->of_node;
264 #endif
265 spin_lock_init(&chips[i].lock);
266
267 regs = gpio2regs(base);
268 chips[i].regs = regs;
269 chips[i].set_data = &regs->set_data;
270 chips[i].clr_data = &regs->clr_data;
271 chips[i].in_data = &regs->in_data;
272
273 gpiochip_add(&chips[i].chip);
274 }
275
276 platform_set_drvdata(pdev, chips);
277 davinci_gpio_irq_setup(pdev);
278 return 0;
279 }
280
281 /*--------------------------------------------------------------------------*/
282 /*
283 * We expect irqs will normally be set up as input pins, but they can also be
284 * used as output pins ... which is convenient for testing.
285 *
286 * NOTE: The first few GPIOs also have direct INTC hookups in addition
287 * to their GPIOBNK0 irq, with a bit less overhead.
288 *
289 * All those INTC hookups (direct, plus several IRQ banks) can also
290 * serve as EDMA event triggers.
291 */
292
293 static void gpio_irq_disable(struct irq_data *d)
294 {
295 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
296 u32 mask = (u32) irq_data_get_irq_handler_data(d);
297
298 writel_relaxed(mask, &g->clr_falling);
299 writel_relaxed(mask, &g->clr_rising);
300 }
301
302 static void gpio_irq_enable(struct irq_data *d)
303 {
304 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
305 u32 mask = (u32) irq_data_get_irq_handler_data(d);
306 unsigned status = irqd_get_trigger_type(d);
307
308 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
309 if (!status)
310 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
311
312 if (status & IRQ_TYPE_EDGE_FALLING)
313 writel_relaxed(mask, &g->set_falling);
314 if (status & IRQ_TYPE_EDGE_RISING)
315 writel_relaxed(mask, &g->set_rising);
316 }
317
318 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
319 {
320 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
321 return -EINVAL;
322
323 return 0;
324 }
325
326 static struct irq_chip gpio_irqchip = {
327 .name = "GPIO",
328 .irq_enable = gpio_irq_enable,
329 .irq_disable = gpio_irq_disable,
330 .irq_set_type = gpio_irq_type,
331 .flags = IRQCHIP_SET_TYPE_MASKED,
332 };
333
334 static void
335 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
336 {
337 struct davinci_gpio_regs __iomem *g;
338 u32 mask = 0xffff;
339 struct davinci_gpio_controller *d;
340
341 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
342 g = (struct davinci_gpio_regs __iomem *)d->regs;
343
344 /* we only care about one bank */
345 if (irq & 1)
346 mask <<= 16;
347
348 /* temporarily mask (level sensitive) parent IRQ */
349 chained_irq_enter(irq_desc_get_chip(desc), desc);
350 while (1) {
351 u32 status;
352 int bit;
353
354 /* ack any irqs */
355 status = readl_relaxed(&g->intstat) & mask;
356 if (!status)
357 break;
358 writel_relaxed(status, &g->intstat);
359
360 /* now demux them to the right lowlevel handler */
361
362 while (status) {
363 bit = __ffs(status);
364 status &= ~BIT(bit);
365 generic_handle_irq(
366 irq_find_mapping(d->irq_domain,
367 d->chip.base + bit));
368 }
369 }
370 chained_irq_exit(irq_desc_get_chip(desc), desc);
371 /* now it may re-trigger */
372 }
373
374 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
375 {
376 struct davinci_gpio_controller *d = chip2controller(chip);
377
378 if (d->irq_domain)
379 return irq_create_mapping(d->irq_domain, d->chip.base + offset);
380 else
381 return -ENXIO;
382 }
383
384 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
385 {
386 struct davinci_gpio_controller *d = chip2controller(chip);
387
388 /*
389 * NOTE: we assume for now that only irqs in the first gpio_chip
390 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
391 */
392 if (offset < d->gpio_unbanked)
393 return d->gpio_irq + offset;
394 else
395 return -ENODEV;
396 }
397
398 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
399 {
400 struct davinci_gpio_controller *d;
401 struct davinci_gpio_regs __iomem *g;
402 u32 mask;
403
404 d = (struct davinci_gpio_controller *)data->handler_data;
405 g = (struct davinci_gpio_regs __iomem *)d->regs;
406 mask = __gpio_mask(data->irq - d->gpio_irq);
407
408 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
409 return -EINVAL;
410
411 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
412 ? &g->set_falling : &g->clr_falling);
413 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
414 ? &g->set_rising : &g->clr_rising);
415
416 return 0;
417 }
418
419 static int
420 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
421 irq_hw_number_t hw)
422 {
423 struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
424
425 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
426 "davinci_gpio");
427 irq_set_irq_type(irq, IRQ_TYPE_NONE);
428 irq_set_chip_data(irq, (__force void *)g);
429 irq_set_handler_data(irq, (void *)__gpio_mask(hw));
430 set_irq_flags(irq, IRQF_VALID);
431
432 return 0;
433 }
434
435 static const struct irq_domain_ops davinci_gpio_irq_ops = {
436 .map = davinci_gpio_irq_map,
437 .xlate = irq_domain_xlate_onetwocell,
438 };
439
440 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
441 {
442 static struct irq_chip_type gpio_unbanked;
443
444 gpio_unbanked = *container_of(irq_get_chip(irq),
445 struct irq_chip_type, chip);
446
447 return &gpio_unbanked.chip;
448 };
449
450 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
451 {
452 static struct irq_chip gpio_unbanked;
453
454 gpio_unbanked = *irq_get_chip(irq);
455 return &gpio_unbanked;
456 };
457
458 static const struct of_device_id davinci_gpio_ids[];
459
460 /*
461 * NOTE: for suspend/resume, probably best to make a platform_device with
462 * suspend_late/resume_resume calls hooking into results of the set_wake()
463 * calls ... so if no gpios are wakeup events the clock can be disabled,
464 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
465 * (dm6446) can be set appropriately for GPIOV33 pins.
466 */
467
468 static int davinci_gpio_irq_setup(struct platform_device *pdev)
469 {
470 unsigned gpio, bank;
471 int irq;
472 struct clk *clk;
473 u32 binten = 0;
474 unsigned ngpio, bank_irq;
475 struct device *dev = &pdev->dev;
476 struct resource *res;
477 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
478 struct davinci_gpio_platform_data *pdata = dev->platform_data;
479 struct davinci_gpio_regs __iomem *g;
480 struct irq_domain *irq_domain = NULL;
481 const struct of_device_id *match;
482 struct irq_chip *irq_chip;
483 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
484
485 /*
486 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
487 */
488 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
489 match = of_match_device(of_match_ptr(davinci_gpio_ids),
490 dev);
491 if (match)
492 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
493
494 ngpio = pdata->ngpio;
495 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
496 if (!res) {
497 dev_err(dev, "Invalid IRQ resource\n");
498 return -EBUSY;
499 }
500
501 bank_irq = res->start;
502
503 if (!bank_irq) {
504 dev_err(dev, "Invalid IRQ resource\n");
505 return -ENODEV;
506 }
507
508 clk = devm_clk_get(dev, "gpio");
509 if (IS_ERR(clk)) {
510 printk(KERN_ERR "Error %ld getting gpio clock?\n",
511 PTR_ERR(clk));
512 return PTR_ERR(clk);
513 }
514 clk_prepare_enable(clk);
515
516 if (!pdata->gpio_unbanked) {
517 irq = irq_alloc_descs(-1, 0, ngpio, 0);
518 if (irq < 0) {
519 dev_err(dev, "Couldn't allocate IRQ numbers\n");
520 return irq;
521 }
522
523 irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0,
524 &davinci_gpio_irq_ops,
525 chips);
526 if (!irq_domain) {
527 dev_err(dev, "Couldn't register an IRQ domain\n");
528 return -ENODEV;
529 }
530 }
531
532 /*
533 * Arrange gpio_to_irq() support, handling either direct IRQs or
534 * banked IRQs. Having GPIOs in the first GPIO bank use direct
535 * IRQs, while the others use banked IRQs, would need some setup
536 * tweaks to recognize hardware which can do that.
537 */
538 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
539 chips[bank].chip.to_irq = gpio_to_irq_banked;
540 chips[bank].irq_domain = irq_domain;
541 }
542
543 /*
544 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
545 * controller only handling trigger modes. We currently assume no
546 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
547 */
548 if (pdata->gpio_unbanked) {
549 /* pass "bank 0" GPIO IRQs to AINTC */
550 chips[0].chip.to_irq = gpio_to_irq_unbanked;
551 chips[0].gpio_irq = bank_irq;
552 chips[0].gpio_unbanked = pdata->gpio_unbanked;
553 binten = BIT(0);
554
555 /* AINTC handles mask/unmask; GPIO handles triggering */
556 irq = bank_irq;
557 irq_chip = gpio_get_irq_chip(irq);
558 irq_chip->name = "GPIO-AINTC";
559 irq_chip->irq_set_type = gpio_irq_type_unbanked;
560
561 /* default trigger: both edges */
562 g = gpio2regs(0);
563 writel_relaxed(~0, &g->set_falling);
564 writel_relaxed(~0, &g->set_rising);
565
566 /* set the direct IRQs up to use that irqchip */
567 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
568 irq_set_chip(irq, irq_chip);
569 irq_set_handler_data(irq, &chips[gpio / 32]);
570 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
571 }
572
573 goto done;
574 }
575
576 /*
577 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
578 * then chain through our own handler.
579 */
580 for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
581 /* disabled by default, enabled only as needed */
582 g = gpio2regs(gpio);
583 writel_relaxed(~0, &g->clr_falling);
584 writel_relaxed(~0, &g->clr_rising);
585
586 /* set up all irqs in this bank */
587 irq_set_chained_handler(bank_irq, gpio_irq_handler);
588
589 /*
590 * Each chip handles 32 gpios, and each irq bank consists of 16
591 * gpio irqs. Pass the irq bank's corresponding controller to
592 * the chained irq handler.
593 */
594 irq_set_handler_data(bank_irq, &chips[gpio / 32]);
595
596 binten |= BIT(bank);
597 }
598
599 done:
600 /*
601 * BINTEN -- per-bank interrupt enable. genirq would also let these
602 * bits be set/cleared dynamically.
603 */
604 writel_relaxed(binten, gpio_base + BINTEN);
605
606 return 0;
607 }
608
609 #if IS_ENABLED(CONFIG_OF)
610 static const struct of_device_id davinci_gpio_ids[] = {
611 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
612 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
613 { /* sentinel */ },
614 };
615 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
616 #endif
617
618 static struct platform_driver davinci_gpio_driver = {
619 .probe = davinci_gpio_probe,
620 .driver = {
621 .name = "davinci_gpio",
622 .owner = THIS_MODULE,
623 .of_match_table = of_match_ptr(davinci_gpio_ids),
624 },
625 };
626
627 /**
628 * GPIO driver registration needs to be done before machine_init functions
629 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
630 */
631 static int __init davinci_gpio_drv_reg(void)
632 {
633 return platform_driver_register(&davinci_gpio_driver);
634 }
635 postcore_initcall(davinci_gpio_drv_reg);
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