2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/slab.h>
28 #include <linux/of_device.h>
29 #include <linux/of_address.h>
30 #include <linux/pinctrl/machine.h>
31 #include <linux/pinctrl/pinctrl.h>
32 #include <linux/pinctrl/pinmux.h>
33 #include <linux/pinctrl/pinconf.h>
34 /* Since we request GPIOs from ourself */
35 #include <linux/pinctrl/consumer.h>
36 #include <linux/platform_data/pinctrl-nomadik.h>
37 #include "pinctrl-nomadik.h"
41 * The GPIO module in the Nomadik family of Systems-on-Chip is an
42 * AMBA device, managing 32 pins and alternate functions. The logic block
43 * is currently used in the Nomadik and ux500.
45 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
48 struct nmk_gpio_chip
{
49 struct gpio_chip chip
;
50 struct irq_domain
*domain
;
54 unsigned int parent_irq
;
55 int secondary_parent_irq
;
56 u32 (*get_secondary_status
)(unsigned int bank
);
57 void (*set_ioforce
)(bool enable
);
60 /* Keep track of configured edges */
73 * struct nmk_pinctrl - state container for the Nomadik pin controller
74 * @dev: containing device pointer
75 * @pctl: corresponding pin controller device
76 * @soc: SoC data for this specific chip
77 * @prcm_base: PRCM register range virtual base
81 struct pinctrl_dev
*pctl
;
82 const struct nmk_pinctrl_soc_data
*soc
;
83 void __iomem
*prcm_base
;
86 static struct nmk_gpio_chip
*
87 nmk_gpio_chips
[DIV_ROUND_UP(ARCH_NR_GPIOS
, NMK_GPIO_PER_CHIP
)];
89 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock
);
91 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
93 static void __nmk_gpio_set_mode(struct nmk_gpio_chip
*nmk_chip
,
94 unsigned offset
, int gpio_mode
)
96 u32 bit
= 1 << offset
;
99 afunc
= readl(nmk_chip
->addr
+ NMK_GPIO_AFSLA
) & ~bit
;
100 bfunc
= readl(nmk_chip
->addr
+ NMK_GPIO_AFSLB
) & ~bit
;
101 if (gpio_mode
& NMK_GPIO_ALT_A
)
103 if (gpio_mode
& NMK_GPIO_ALT_B
)
105 writel(afunc
, nmk_chip
->addr
+ NMK_GPIO_AFSLA
);
106 writel(bfunc
, nmk_chip
->addr
+ NMK_GPIO_AFSLB
);
109 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip
*nmk_chip
,
110 unsigned offset
, enum nmk_gpio_slpm mode
)
112 u32 bit
= 1 << offset
;
115 slpm
= readl(nmk_chip
->addr
+ NMK_GPIO_SLPC
);
116 if (mode
== NMK_GPIO_SLPM_NOCHANGE
)
120 writel(slpm
, nmk_chip
->addr
+ NMK_GPIO_SLPC
);
123 static void __nmk_gpio_set_pull(struct nmk_gpio_chip
*nmk_chip
,
124 unsigned offset
, enum nmk_gpio_pull pull
)
126 u32 bit
= 1 << offset
;
129 pdis
= readl(nmk_chip
->addr
+ NMK_GPIO_PDIS
);
130 if (pull
== NMK_GPIO_PULL_NONE
) {
132 nmk_chip
->pull_up
&= ~bit
;
137 writel(pdis
, nmk_chip
->addr
+ NMK_GPIO_PDIS
);
139 if (pull
== NMK_GPIO_PULL_UP
) {
140 nmk_chip
->pull_up
|= bit
;
141 writel(bit
, nmk_chip
->addr
+ NMK_GPIO_DATS
);
142 } else if (pull
== NMK_GPIO_PULL_DOWN
) {
143 nmk_chip
->pull_up
&= ~bit
;
144 writel(bit
, nmk_chip
->addr
+ NMK_GPIO_DATC
);
148 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip
*nmk_chip
,
149 unsigned offset
, bool lowemi
)
151 u32 bit
= BIT(offset
);
152 bool enabled
= nmk_chip
->lowemi
& bit
;
154 if (lowemi
== enabled
)
158 nmk_chip
->lowemi
|= bit
;
160 nmk_chip
->lowemi
&= ~bit
;
162 writel_relaxed(nmk_chip
->lowemi
,
163 nmk_chip
->addr
+ NMK_GPIO_LOWEMI
);
166 static void __nmk_gpio_make_input(struct nmk_gpio_chip
*nmk_chip
,
169 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DIRC
);
172 static void __nmk_gpio_set_output(struct nmk_gpio_chip
*nmk_chip
,
173 unsigned offset
, int val
)
176 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DATS
);
178 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DATC
);
181 static void __nmk_gpio_make_output(struct nmk_gpio_chip
*nmk_chip
,
182 unsigned offset
, int val
)
184 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DIRS
);
185 __nmk_gpio_set_output(nmk_chip
, offset
, val
);
188 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip
*nmk_chip
,
189 unsigned offset
, int gpio_mode
,
192 u32 rwimsc
= nmk_chip
->rwimsc
;
193 u32 fwimsc
= nmk_chip
->fwimsc
;
195 if (glitch
&& nmk_chip
->set_ioforce
) {
196 u32 bit
= BIT(offset
);
198 /* Prevent spurious wakeups */
199 writel(rwimsc
& ~bit
, nmk_chip
->addr
+ NMK_GPIO_RWIMSC
);
200 writel(fwimsc
& ~bit
, nmk_chip
->addr
+ NMK_GPIO_FWIMSC
);
202 nmk_chip
->set_ioforce(true);
205 __nmk_gpio_set_mode(nmk_chip
, offset
, gpio_mode
);
207 if (glitch
&& nmk_chip
->set_ioforce
) {
208 nmk_chip
->set_ioforce(false);
210 writel(rwimsc
, nmk_chip
->addr
+ NMK_GPIO_RWIMSC
);
211 writel(fwimsc
, nmk_chip
->addr
+ NMK_GPIO_FWIMSC
);
216 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip
*nmk_chip
, unsigned offset
)
218 u32 falling
= nmk_chip
->fimsc
& BIT(offset
);
219 u32 rising
= nmk_chip
->rimsc
& BIT(offset
);
220 int gpio
= nmk_chip
->chip
.base
+ offset
;
221 int irq
= irq_find_mapping(nmk_chip
->domain
, offset
);
222 struct irq_data
*d
= irq_get_irq_data(irq
);
224 if (!rising
&& !falling
)
227 if (!d
|| !irqd_irq_disabled(d
))
231 nmk_chip
->rimsc
&= ~BIT(offset
);
232 writel_relaxed(nmk_chip
->rimsc
,
233 nmk_chip
->addr
+ NMK_GPIO_RIMSC
);
237 nmk_chip
->fimsc
&= ~BIT(offset
);
238 writel_relaxed(nmk_chip
->fimsc
,
239 nmk_chip
->addr
+ NMK_GPIO_FIMSC
);
242 dev_dbg(nmk_chip
->chip
.dev
, "%d: clearing interrupt mask\n", gpio
);
245 static void nmk_write_masked(void __iomem
*reg
, u32 mask
, u32 value
)
250 val
= ((val
& ~mask
) | (value
& mask
));
254 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl
*npct
,
255 unsigned offset
, unsigned alt_num
)
261 const struct prcm_gpiocr_altcx_pin_desc
*pin_desc
;
262 const u16
*gpiocr_regs
;
264 if (!npct
->prcm_base
)
267 if (alt_num
> PRCM_IDX_GPIOCR_ALTC_MAX
) {
268 dev_err(npct
->dev
, "PRCM GPIOCR: alternate-C%i is invalid\n",
273 for (i
= 0 ; i
< npct
->soc
->npins_altcx
; i
++) {
274 if (npct
->soc
->altcx_pins
[i
].pin
== offset
)
277 if (i
== npct
->soc
->npins_altcx
) {
278 dev_dbg(npct
->dev
, "PRCM GPIOCR: pin %i is not found\n",
283 pin_desc
= npct
->soc
->altcx_pins
+ i
;
284 gpiocr_regs
= npct
->soc
->prcm_gpiocr_registers
;
287 * If alt_num is NULL, just clear current ALTCx selection
288 * to make sure we come back to a pure ALTC selection
291 for (i
= 0 ; i
< PRCM_IDX_GPIOCR_ALTC_MAX
; i
++) {
292 if (pin_desc
->altcx
[i
].used
== true) {
293 reg
= gpiocr_regs
[pin_desc
->altcx
[i
].reg_index
];
294 bit
= pin_desc
->altcx
[i
].control_bit
;
295 if (readl(npct
->prcm_base
+ reg
) & BIT(bit
)) {
296 nmk_write_masked(npct
->prcm_base
+ reg
, BIT(bit
), 0);
298 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
306 alt_index
= alt_num
- 1;
307 if (pin_desc
->altcx
[alt_index
].used
== false) {
309 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
315 * Check if any other ALTCx functions are activated on this pin
316 * and disable it first.
318 for (i
= 0 ; i
< PRCM_IDX_GPIOCR_ALTC_MAX
; i
++) {
321 if (pin_desc
->altcx
[i
].used
== true) {
322 reg
= gpiocr_regs
[pin_desc
->altcx
[i
].reg_index
];
323 bit
= pin_desc
->altcx
[i
].control_bit
;
324 if (readl(npct
->prcm_base
+ reg
) & BIT(bit
)) {
325 nmk_write_masked(npct
->prcm_base
+ reg
, BIT(bit
), 0);
327 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
333 reg
= gpiocr_regs
[pin_desc
->altcx
[alt_index
].reg_index
];
334 bit
= pin_desc
->altcx
[alt_index
].control_bit
;
335 dev_dbg(npct
->dev
, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
336 offset
, alt_index
+1);
337 nmk_write_masked(npct
->prcm_base
+ reg
, BIT(bit
), BIT(bit
));
341 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
342 * - Save SLPM registers
343 * - Set SLPM=0 for the IOs you want to switch and others to 1
344 * - Configure the GPIO registers for the IOs that are being switched
346 * - Modify the AFLSA/B registers for the IOs that are being switched
348 * - Restore SLPM registers
349 * - Any spurious wake up event during switch sequence to be ignored and
352 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm
)
356 for (i
= 0; i
< NUM_BANKS
; i
++) {
357 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
358 unsigned int temp
= slpm
[i
];
363 clk_enable(chip
->clk
);
365 slpm
[i
] = readl(chip
->addr
+ NMK_GPIO_SLPC
);
366 writel(temp
, chip
->addr
+ NMK_GPIO_SLPC
);
370 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm
)
374 for (i
= 0; i
< NUM_BANKS
; i
++) {
375 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
380 writel(slpm
[i
], chip
->addr
+ NMK_GPIO_SLPC
);
382 clk_disable(chip
->clk
);
386 static int __maybe_unused
nmk_prcm_gpiocr_get_mode(struct pinctrl_dev
*pctldev
, int gpio
)
391 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
392 const struct prcm_gpiocr_altcx_pin_desc
*pin_desc
;
393 const u16
*gpiocr_regs
;
395 if (!npct
->prcm_base
)
396 return NMK_GPIO_ALT_C
;
398 for (i
= 0; i
< npct
->soc
->npins_altcx
; i
++) {
399 if (npct
->soc
->altcx_pins
[i
].pin
== gpio
)
402 if (i
== npct
->soc
->npins_altcx
)
403 return NMK_GPIO_ALT_C
;
405 pin_desc
= npct
->soc
->altcx_pins
+ i
;
406 gpiocr_regs
= npct
->soc
->prcm_gpiocr_registers
;
407 for (i
= 0; i
< PRCM_IDX_GPIOCR_ALTC_MAX
; i
++) {
408 if (pin_desc
->altcx
[i
].used
== true) {
409 reg
= gpiocr_regs
[pin_desc
->altcx
[i
].reg_index
];
410 bit
= pin_desc
->altcx
[i
].control_bit
;
411 if (readl(npct
->prcm_base
+ reg
) & BIT(bit
))
412 return NMK_GPIO_ALT_C
+i
+1;
415 return NMK_GPIO_ALT_C
;
418 int nmk_gpio_get_mode(int gpio
)
420 struct nmk_gpio_chip
*nmk_chip
;
421 u32 afunc
, bfunc
, bit
;
423 nmk_chip
= nmk_gpio_chips
[gpio
/ NMK_GPIO_PER_CHIP
];
427 bit
= 1 << (gpio
% NMK_GPIO_PER_CHIP
);
429 clk_enable(nmk_chip
->clk
);
431 afunc
= readl(nmk_chip
->addr
+ NMK_GPIO_AFSLA
) & bit
;
432 bfunc
= readl(nmk_chip
->addr
+ NMK_GPIO_AFSLB
) & bit
;
434 clk_disable(nmk_chip
->clk
);
436 return (afunc
? NMK_GPIO_ALT_A
: 0) | (bfunc
? NMK_GPIO_ALT_B
: 0);
438 EXPORT_SYMBOL(nmk_gpio_get_mode
);
442 static inline int nmk_gpio_get_bitmask(int gpio
)
444 return 1 << (gpio
% NMK_GPIO_PER_CHIP
);
447 static void nmk_gpio_irq_ack(struct irq_data
*d
)
449 struct nmk_gpio_chip
*nmk_chip
;
451 nmk_chip
= irq_data_get_irq_chip_data(d
);
455 clk_enable(nmk_chip
->clk
);
456 writel(nmk_gpio_get_bitmask(d
->hwirq
), nmk_chip
->addr
+ NMK_GPIO_IC
);
457 clk_disable(nmk_chip
->clk
);
460 enum nmk_gpio_irq_type
{
465 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip
*nmk_chip
,
466 int gpio
, enum nmk_gpio_irq_type which
,
469 u32 bitmask
= nmk_gpio_get_bitmask(gpio
);
475 if (which
== NORMAL
) {
476 rimscreg
= NMK_GPIO_RIMSC
;
477 fimscreg
= NMK_GPIO_FIMSC
;
478 rimscval
= &nmk_chip
->rimsc
;
479 fimscval
= &nmk_chip
->fimsc
;
481 rimscreg
= NMK_GPIO_RWIMSC
;
482 fimscreg
= NMK_GPIO_FWIMSC
;
483 rimscval
= &nmk_chip
->rwimsc
;
484 fimscval
= &nmk_chip
->fwimsc
;
487 /* we must individually set/clear the two edges */
488 if (nmk_chip
->edge_rising
& bitmask
) {
490 *rimscval
|= bitmask
;
492 *rimscval
&= ~bitmask
;
493 writel(*rimscval
, nmk_chip
->addr
+ rimscreg
);
495 if (nmk_chip
->edge_falling
& bitmask
) {
497 *fimscval
|= bitmask
;
499 *fimscval
&= ~bitmask
;
500 writel(*fimscval
, nmk_chip
->addr
+ fimscreg
);
504 static void __nmk_gpio_set_wake(struct nmk_gpio_chip
*nmk_chip
,
508 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
509 * disabled, since setting SLPM to 1 increases power consumption, and
510 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
512 if (nmk_chip
->sleepmode
&& on
) {
513 __nmk_gpio_set_slpm(nmk_chip
, gpio
% NMK_GPIO_PER_CHIP
,
514 NMK_GPIO_SLPM_WAKEUP_ENABLE
);
517 __nmk_gpio_irq_modify(nmk_chip
, gpio
, WAKE
, on
);
520 static int nmk_gpio_irq_maskunmask(struct irq_data
*d
, bool enable
)
522 struct nmk_gpio_chip
*nmk_chip
;
526 nmk_chip
= irq_data_get_irq_chip_data(d
);
527 bitmask
= nmk_gpio_get_bitmask(d
->hwirq
);
531 clk_enable(nmk_chip
->clk
);
532 spin_lock_irqsave(&nmk_gpio_slpm_lock
, flags
);
533 spin_lock(&nmk_chip
->lock
);
535 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, NORMAL
, enable
);
537 if (!(nmk_chip
->real_wake
& bitmask
))
538 __nmk_gpio_set_wake(nmk_chip
, d
->hwirq
, enable
);
540 spin_unlock(&nmk_chip
->lock
);
541 spin_unlock_irqrestore(&nmk_gpio_slpm_lock
, flags
);
542 clk_disable(nmk_chip
->clk
);
547 static void nmk_gpio_irq_mask(struct irq_data
*d
)
549 nmk_gpio_irq_maskunmask(d
, false);
552 static void nmk_gpio_irq_unmask(struct irq_data
*d
)
554 nmk_gpio_irq_maskunmask(d
, true);
557 static int nmk_gpio_irq_set_wake(struct irq_data
*d
, unsigned int on
)
559 struct nmk_gpio_chip
*nmk_chip
;
563 nmk_chip
= irq_data_get_irq_chip_data(d
);
566 bitmask
= nmk_gpio_get_bitmask(d
->hwirq
);
568 clk_enable(nmk_chip
->clk
);
569 spin_lock_irqsave(&nmk_gpio_slpm_lock
, flags
);
570 spin_lock(&nmk_chip
->lock
);
572 if (irqd_irq_disabled(d
))
573 __nmk_gpio_set_wake(nmk_chip
, d
->hwirq
, on
);
576 nmk_chip
->real_wake
|= bitmask
;
578 nmk_chip
->real_wake
&= ~bitmask
;
580 spin_unlock(&nmk_chip
->lock
);
581 spin_unlock_irqrestore(&nmk_gpio_slpm_lock
, flags
);
582 clk_disable(nmk_chip
->clk
);
587 static int nmk_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
589 bool enabled
= !irqd_irq_disabled(d
);
590 bool wake
= irqd_is_wakeup_set(d
);
591 struct nmk_gpio_chip
*nmk_chip
;
595 nmk_chip
= irq_data_get_irq_chip_data(d
);
596 bitmask
= nmk_gpio_get_bitmask(d
->hwirq
);
599 if (type
& IRQ_TYPE_LEVEL_HIGH
)
601 if (type
& IRQ_TYPE_LEVEL_LOW
)
604 clk_enable(nmk_chip
->clk
);
605 spin_lock_irqsave(&nmk_chip
->lock
, flags
);
608 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, NORMAL
, false);
611 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, WAKE
, false);
613 nmk_chip
->edge_rising
&= ~bitmask
;
614 if (type
& IRQ_TYPE_EDGE_RISING
)
615 nmk_chip
->edge_rising
|= bitmask
;
617 nmk_chip
->edge_falling
&= ~bitmask
;
618 if (type
& IRQ_TYPE_EDGE_FALLING
)
619 nmk_chip
->edge_falling
|= bitmask
;
622 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, NORMAL
, true);
625 __nmk_gpio_irq_modify(nmk_chip
, d
->hwirq
, WAKE
, true);
627 spin_unlock_irqrestore(&nmk_chip
->lock
, flags
);
628 clk_disable(nmk_chip
->clk
);
633 static unsigned int nmk_gpio_irq_startup(struct irq_data
*d
)
635 struct nmk_gpio_chip
*nmk_chip
= irq_data_get_irq_chip_data(d
);
637 if (gpio_lock_as_irq(&nmk_chip
->chip
, d
->hwirq
))
638 dev_err(nmk_chip
->chip
.dev
,
639 "unable to lock HW IRQ %lu for IRQ\n",
641 clk_enable(nmk_chip
->clk
);
642 nmk_gpio_irq_unmask(d
);
646 static void nmk_gpio_irq_shutdown(struct irq_data
*d
)
648 struct nmk_gpio_chip
*nmk_chip
= irq_data_get_irq_chip_data(d
);
650 nmk_gpio_irq_mask(d
);
651 clk_disable(nmk_chip
->clk
);
652 gpio_unlock_as_irq(&nmk_chip
->chip
, d
->hwirq
);
655 static struct irq_chip nmk_gpio_irq_chip
= {
656 .name
= "Nomadik-GPIO",
657 .irq_ack
= nmk_gpio_irq_ack
,
658 .irq_mask
= nmk_gpio_irq_mask
,
659 .irq_unmask
= nmk_gpio_irq_unmask
,
660 .irq_set_type
= nmk_gpio_irq_set_type
,
661 .irq_set_wake
= nmk_gpio_irq_set_wake
,
662 .irq_startup
= nmk_gpio_irq_startup
,
663 .irq_shutdown
= nmk_gpio_irq_shutdown
,
664 .flags
= IRQCHIP_MASK_ON_SUSPEND
,
667 static void __nmk_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
,
670 struct nmk_gpio_chip
*nmk_chip
;
671 struct irq_chip
*host_chip
= irq_get_chip(irq
);
673 chained_irq_enter(host_chip
, desc
);
675 nmk_chip
= irq_get_handler_data(irq
);
677 int bit
= __ffs(status
);
679 generic_handle_irq(irq_find_mapping(nmk_chip
->domain
, bit
));
683 chained_irq_exit(host_chip
, desc
);
686 static void nmk_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
688 struct nmk_gpio_chip
*nmk_chip
= irq_get_handler_data(irq
);
691 clk_enable(nmk_chip
->clk
);
692 status
= readl(nmk_chip
->addr
+ NMK_GPIO_IS
);
693 clk_disable(nmk_chip
->clk
);
695 __nmk_gpio_irq_handler(irq
, desc
, status
);
698 static void nmk_gpio_secondary_irq_handler(unsigned int irq
,
699 struct irq_desc
*desc
)
701 struct nmk_gpio_chip
*nmk_chip
= irq_get_handler_data(irq
);
702 u32 status
= nmk_chip
->get_secondary_status(nmk_chip
->bank
);
704 __nmk_gpio_irq_handler(irq
, desc
, status
);
707 static int nmk_gpio_init_irq(struct nmk_gpio_chip
*nmk_chip
)
709 irq_set_chained_handler(nmk_chip
->parent_irq
, nmk_gpio_irq_handler
);
710 irq_set_handler_data(nmk_chip
->parent_irq
, nmk_chip
);
712 if (nmk_chip
->secondary_parent_irq
>= 0) {
713 irq_set_chained_handler(nmk_chip
->secondary_parent_irq
,
714 nmk_gpio_secondary_irq_handler
);
715 irq_set_handler_data(nmk_chip
->secondary_parent_irq
, nmk_chip
);
723 static int nmk_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
726 * Map back to global GPIO space and request muxing, the direction
727 * parameter does not matter for this controller.
729 int gpio
= chip
->base
+ offset
;
731 return pinctrl_request_gpio(gpio
);
734 static void nmk_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
736 int gpio
= chip
->base
+ offset
;
738 pinctrl_free_gpio(gpio
);
741 static int nmk_gpio_make_input(struct gpio_chip
*chip
, unsigned offset
)
743 struct nmk_gpio_chip
*nmk_chip
=
744 container_of(chip
, struct nmk_gpio_chip
, chip
);
746 clk_enable(nmk_chip
->clk
);
748 writel(1 << offset
, nmk_chip
->addr
+ NMK_GPIO_DIRC
);
750 clk_disable(nmk_chip
->clk
);
755 static int nmk_gpio_get_input(struct gpio_chip
*chip
, unsigned offset
)
757 struct nmk_gpio_chip
*nmk_chip
=
758 container_of(chip
, struct nmk_gpio_chip
, chip
);
759 u32 bit
= 1 << offset
;
762 clk_enable(nmk_chip
->clk
);
764 value
= (readl(nmk_chip
->addr
+ NMK_GPIO_DAT
) & bit
) != 0;
766 clk_disable(nmk_chip
->clk
);
771 static void nmk_gpio_set_output(struct gpio_chip
*chip
, unsigned offset
,
774 struct nmk_gpio_chip
*nmk_chip
=
775 container_of(chip
, struct nmk_gpio_chip
, chip
);
777 clk_enable(nmk_chip
->clk
);
779 __nmk_gpio_set_output(nmk_chip
, offset
, val
);
781 clk_disable(nmk_chip
->clk
);
784 static int nmk_gpio_make_output(struct gpio_chip
*chip
, unsigned offset
,
787 struct nmk_gpio_chip
*nmk_chip
=
788 container_of(chip
, struct nmk_gpio_chip
, chip
);
790 clk_enable(nmk_chip
->clk
);
792 __nmk_gpio_make_output(nmk_chip
, offset
, val
);
794 clk_disable(nmk_chip
->clk
);
799 static int nmk_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
801 struct nmk_gpio_chip
*nmk_chip
=
802 container_of(chip
, struct nmk_gpio_chip
, chip
);
804 return irq_create_mapping(nmk_chip
->domain
, offset
);
807 #ifdef CONFIG_DEBUG_FS
809 #include <linux/seq_file.h>
811 static void nmk_gpio_dbg_show_one(struct seq_file
*s
,
812 struct pinctrl_dev
*pctldev
, struct gpio_chip
*chip
,
813 unsigned offset
, unsigned gpio
)
815 const char *label
= gpiochip_is_requested(chip
, offset
);
816 struct nmk_gpio_chip
*nmk_chip
=
817 container_of(chip
, struct nmk_gpio_chip
, chip
);
821 u32 bit
= 1 << offset
;
822 const char *modes
[] = {
823 [NMK_GPIO_ALT_GPIO
] = "gpio",
824 [NMK_GPIO_ALT_A
] = "altA",
825 [NMK_GPIO_ALT_B
] = "altB",
826 [NMK_GPIO_ALT_C
] = "altC",
827 [NMK_GPIO_ALT_C
+1] = "altC1",
828 [NMK_GPIO_ALT_C
+2] = "altC2",
829 [NMK_GPIO_ALT_C
+3] = "altC3",
830 [NMK_GPIO_ALT_C
+4] = "altC4",
833 clk_enable(nmk_chip
->clk
);
834 is_out
= !!(readl(nmk_chip
->addr
+ NMK_GPIO_DIR
) & bit
);
835 pull
= !(readl(nmk_chip
->addr
+ NMK_GPIO_PDIS
) & bit
);
836 mode
= nmk_gpio_get_mode(gpio
);
837 if ((mode
== NMK_GPIO_ALT_C
) && pctldev
)
838 mode
= nmk_prcm_gpiocr_get_mode(pctldev
, gpio
);
840 seq_printf(s
, " gpio-%-3d (%-20.20s) %s %s %s %s",
841 gpio
, label
?: "(none)",
842 is_out
? "out" : "in ",
844 ? (chip
->get(chip
, offset
) ? "hi" : "lo")
846 (mode
< 0) ? "unknown" : modes
[mode
],
847 pull
? "pull" : "none");
849 if (label
&& !is_out
) {
850 int irq
= gpio_to_irq(gpio
);
851 struct irq_desc
*desc
= irq_to_desc(irq
);
853 /* This races with request_irq(), set_irq_type(),
854 * and set_irq_wake() ... but those are "rare".
856 if (irq
>= 0 && desc
->action
) {
858 u32 bitmask
= nmk_gpio_get_bitmask(gpio
);
860 if (nmk_chip
->edge_rising
& bitmask
)
861 trigger
= "edge-rising";
862 else if (nmk_chip
->edge_falling
& bitmask
)
863 trigger
= "edge-falling";
865 trigger
= "edge-undefined";
867 seq_printf(s
, " irq-%d %s%s",
869 irqd_is_wakeup_set(&desc
->irq_data
)
873 clk_disable(nmk_chip
->clk
);
876 static void nmk_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
879 unsigned gpio
= chip
->base
;
881 for (i
= 0; i
< chip
->ngpio
; i
++, gpio
++) {
882 nmk_gpio_dbg_show_one(s
, NULL
, chip
, i
, gpio
);
888 static inline void nmk_gpio_dbg_show_one(struct seq_file
*s
,
889 struct pinctrl_dev
*pctldev
,
890 struct gpio_chip
*chip
,
891 unsigned offset
, unsigned gpio
)
894 #define nmk_gpio_dbg_show NULL
897 /* This structure is replicated for each GPIO block allocated at probe time */
898 static struct gpio_chip nmk_gpio_template
= {
899 .request
= nmk_gpio_request
,
900 .free
= nmk_gpio_free
,
901 .direction_input
= nmk_gpio_make_input
,
902 .get
= nmk_gpio_get_input
,
903 .direction_output
= nmk_gpio_make_output
,
904 .set
= nmk_gpio_set_output
,
905 .to_irq
= nmk_gpio_to_irq
,
906 .dbg_show
= nmk_gpio_dbg_show
,
910 void nmk_gpio_clocks_enable(void)
914 for (i
= 0; i
< NUM_BANKS
; i
++) {
915 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
920 clk_enable(chip
->clk
);
924 void nmk_gpio_clocks_disable(void)
928 for (i
= 0; i
< NUM_BANKS
; i
++) {
929 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
934 clk_disable(chip
->clk
);
939 * Called from the suspend/resume path to only keep the real wakeup interrupts
940 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
941 * and not the rest of the interrupts which we needed to have as wakeups for
944 * PM ops are not used since this needs to be done at the end, after all the
945 * other drivers are done with their suspend callbacks.
947 void nmk_gpio_wakeups_suspend(void)
951 for (i
= 0; i
< NUM_BANKS
; i
++) {
952 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
957 clk_enable(chip
->clk
);
959 writel(chip
->rwimsc
& chip
->real_wake
,
960 chip
->addr
+ NMK_GPIO_RWIMSC
);
961 writel(chip
->fwimsc
& chip
->real_wake
,
962 chip
->addr
+ NMK_GPIO_FWIMSC
);
964 clk_disable(chip
->clk
);
968 void nmk_gpio_wakeups_resume(void)
972 for (i
= 0; i
< NUM_BANKS
; i
++) {
973 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[i
];
978 clk_enable(chip
->clk
);
980 writel(chip
->rwimsc
, chip
->addr
+ NMK_GPIO_RWIMSC
);
981 writel(chip
->fwimsc
, chip
->addr
+ NMK_GPIO_FWIMSC
);
983 clk_disable(chip
->clk
);
988 * Read the pull up/pull down status.
989 * A bit set in 'pull_up' means that pull up
990 * is selected if pull is enabled in PDIS register.
991 * Note: only pull up/down set via this driver can
992 * be detected due to HW limitations.
994 void nmk_gpio_read_pull(int gpio_bank
, u32
*pull_up
)
996 if (gpio_bank
< NUM_BANKS
) {
997 struct nmk_gpio_chip
*chip
= nmk_gpio_chips
[gpio_bank
];
1002 *pull_up
= chip
->pull_up
;
1006 static int nmk_gpio_irq_map(struct irq_domain
*d
, unsigned int irq
,
1007 irq_hw_number_t hwirq
)
1009 struct nmk_gpio_chip
*nmk_chip
= d
->host_data
;
1014 irq_set_chip_and_handler(irq
, &nmk_gpio_irq_chip
, handle_edge_irq
);
1015 set_irq_flags(irq
, IRQF_VALID
);
1016 irq_set_chip_data(irq
, nmk_chip
);
1017 irq_set_irq_type(irq
, IRQ_TYPE_EDGE_FALLING
);
1022 static const struct irq_domain_ops nmk_gpio_irq_simple_ops
= {
1023 .map
= nmk_gpio_irq_map
,
1024 .xlate
= irq_domain_xlate_twocell
,
1027 static int nmk_gpio_probe(struct platform_device
*dev
)
1029 struct nmk_gpio_platform_data
*pdata
= dev
->dev
.platform_data
;
1030 struct device_node
*np
= dev
->dev
.of_node
;
1031 struct nmk_gpio_chip
*nmk_chip
;
1032 struct gpio_chip
*chip
;
1033 struct resource
*res
;
1041 if (!pdata
&& !np
) {
1042 dev_err(&dev
->dev
, "No platform data or device tree found\n");
1047 pdata
= devm_kzalloc(&dev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1051 if (of_get_property(np
, "st,supports-sleepmode", NULL
))
1052 pdata
->supports_sleepmode
= true;
1054 if (of_property_read_u32(np
, "gpio-bank", &dev
->id
)) {
1055 dev_err(&dev
->dev
, "gpio-bank property not found\n");
1059 pdata
->first_gpio
= dev
->id
* NMK_GPIO_PER_CHIP
;
1060 pdata
->num_gpio
= NMK_GPIO_PER_CHIP
;
1063 irq
= platform_get_irq(dev
, 0);
1067 secondary_irq
= platform_get_irq(dev
, 1);
1068 if (secondary_irq
>= 0 && !pdata
->get_secondary_status
)
1071 res
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
1072 base
= devm_ioremap_resource(&dev
->dev
, res
);
1074 return PTR_ERR(base
);
1076 clk
= devm_clk_get(&dev
->dev
, NULL
);
1078 return PTR_ERR(clk
);
1081 nmk_chip
= devm_kzalloc(&dev
->dev
, sizeof(*nmk_chip
), GFP_KERNEL
);
1086 * The virt address in nmk_chip->addr is in the nomadik register space,
1087 * so we can simply convert the resource address, without remapping
1089 nmk_chip
->bank
= dev
->id
;
1090 nmk_chip
->clk
= clk
;
1091 nmk_chip
->addr
= base
;
1092 nmk_chip
->chip
= nmk_gpio_template
;
1093 nmk_chip
->parent_irq
= irq
;
1094 nmk_chip
->secondary_parent_irq
= secondary_irq
;
1095 nmk_chip
->get_secondary_status
= pdata
->get_secondary_status
;
1096 nmk_chip
->set_ioforce
= pdata
->set_ioforce
;
1097 nmk_chip
->sleepmode
= pdata
->supports_sleepmode
;
1098 spin_lock_init(&nmk_chip
->lock
);
1100 chip
= &nmk_chip
->chip
;
1101 chip
->base
= pdata
->first_gpio
;
1102 chip
->ngpio
= pdata
->num_gpio
;
1103 chip
->label
= pdata
->name
?: dev_name(&dev
->dev
);
1104 chip
->dev
= &dev
->dev
;
1105 chip
->owner
= THIS_MODULE
;
1107 clk_enable(nmk_chip
->clk
);
1108 nmk_chip
->lowemi
= readl_relaxed(nmk_chip
->addr
+ NMK_GPIO_LOWEMI
);
1109 clk_disable(nmk_chip
->clk
);
1111 #ifdef CONFIG_OF_GPIO
1115 ret
= gpiochip_add(&nmk_chip
->chip
);
1119 BUG_ON(nmk_chip
->bank
>= ARRAY_SIZE(nmk_gpio_chips
));
1121 nmk_gpio_chips
[nmk_chip
->bank
] = nmk_chip
;
1123 platform_set_drvdata(dev
, nmk_chip
);
1126 irq_start
= pdata
->first_irq
;
1127 nmk_chip
->domain
= irq_domain_add_simple(np
,
1128 NMK_GPIO_PER_CHIP
, irq_start
,
1129 &nmk_gpio_irq_simple_ops
, nmk_chip
);
1130 if (!nmk_chip
->domain
) {
1131 dev_err(&dev
->dev
, "failed to create irqdomain\n");
1132 /* Just do this, no matter if it fails */
1133 ret
= gpiochip_remove(&nmk_chip
->chip
);
1137 nmk_gpio_init_irq(nmk_chip
);
1139 dev_info(&dev
->dev
, "at address %p\n", nmk_chip
->addr
);
1144 static int nmk_get_groups_cnt(struct pinctrl_dev
*pctldev
)
1146 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1148 return npct
->soc
->ngroups
;
1151 static const char *nmk_get_group_name(struct pinctrl_dev
*pctldev
,
1154 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1156 return npct
->soc
->groups
[selector
].name
;
1159 static int nmk_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
1160 const unsigned **pins
,
1163 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1165 *pins
= npct
->soc
->groups
[selector
].pins
;
1166 *num_pins
= npct
->soc
->groups
[selector
].npins
;
1170 static struct pinctrl_gpio_range
*
1171 nmk_match_gpio_range(struct pinctrl_dev
*pctldev
, unsigned offset
)
1173 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1176 for (i
= 0; i
< npct
->soc
->gpio_num_ranges
; i
++) {
1177 struct pinctrl_gpio_range
*range
;
1179 range
= &npct
->soc
->gpio_ranges
[i
];
1180 if (offset
>= range
->pin_base
&&
1181 offset
<= (range
->pin_base
+ range
->npins
- 1))
1187 static void nmk_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
1190 struct pinctrl_gpio_range
*range
;
1191 struct gpio_chip
*chip
;
1193 range
= nmk_match_gpio_range(pctldev
, offset
);
1194 if (!range
|| !range
->gc
) {
1195 seq_printf(s
, "invalid pin offset");
1199 nmk_gpio_dbg_show_one(s
, pctldev
, chip
, offset
- chip
->base
, offset
);
1202 static void nmk_pinctrl_dt_free_map(struct pinctrl_dev
*pctldev
,
1203 struct pinctrl_map
*map
, unsigned num_maps
)
1207 for (i
= 0; i
< num_maps
; i
++)
1208 if (map
[i
].type
== PIN_MAP_TYPE_CONFIGS_PIN
)
1209 kfree(map
[i
].data
.configs
.configs
);
1213 static int nmk_dt_reserve_map(struct pinctrl_map
**map
, unsigned *reserved_maps
,
1214 unsigned *num_maps
, unsigned reserve
)
1216 unsigned old_num
= *reserved_maps
;
1217 unsigned new_num
= *num_maps
+ reserve
;
1218 struct pinctrl_map
*new_map
;
1220 if (old_num
>= new_num
)
1223 new_map
= krealloc(*map
, sizeof(*new_map
) * new_num
, GFP_KERNEL
);
1227 memset(new_map
+ old_num
, 0, (new_num
- old_num
) * sizeof(*new_map
));
1230 *reserved_maps
= new_num
;
1235 static int nmk_dt_add_map_mux(struct pinctrl_map
**map
, unsigned *reserved_maps
,
1236 unsigned *num_maps
, const char *group
,
1237 const char *function
)
1239 if (*num_maps
== *reserved_maps
)
1242 (*map
)[*num_maps
].type
= PIN_MAP_TYPE_MUX_GROUP
;
1243 (*map
)[*num_maps
].data
.mux
.group
= group
;
1244 (*map
)[*num_maps
].data
.mux
.function
= function
;
1250 static int nmk_dt_add_map_configs(struct pinctrl_map
**map
,
1251 unsigned *reserved_maps
,
1252 unsigned *num_maps
, const char *group
,
1253 unsigned long *configs
, unsigned num_configs
)
1255 unsigned long *dup_configs
;
1257 if (*num_maps
== *reserved_maps
)
1260 dup_configs
= kmemdup(configs
, num_configs
* sizeof(*dup_configs
),
1265 (*map
)[*num_maps
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
1267 (*map
)[*num_maps
].data
.configs
.group_or_pin
= group
;
1268 (*map
)[*num_maps
].data
.configs
.configs
= dup_configs
;
1269 (*map
)[*num_maps
].data
.configs
.num_configs
= num_configs
;
1275 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1276 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1277 .size = ARRAY_SIZE(y), }
1279 static const unsigned long nmk_pin_input_modes
[] = {
1285 static const unsigned long nmk_pin_output_modes
[] = {
1291 static const unsigned long nmk_pin_sleep_modes
[] = {
1292 PIN_SLEEPMODE_DISABLED
,
1293 PIN_SLEEPMODE_ENABLED
,
1296 static const unsigned long nmk_pin_sleep_input_modes
[] = {
1297 PIN_SLPM_INPUT_NOPULL
,
1298 PIN_SLPM_INPUT_PULLUP
,
1299 PIN_SLPM_INPUT_PULLDOWN
,
1303 static const unsigned long nmk_pin_sleep_output_modes
[] = {
1304 PIN_SLPM_OUTPUT_LOW
,
1305 PIN_SLPM_OUTPUT_HIGH
,
1306 PIN_SLPM_DIR_OUTPUT
,
1309 static const unsigned long nmk_pin_sleep_wakeup_modes
[] = {
1310 PIN_SLPM_WAKEUP_DISABLE
,
1311 PIN_SLPM_WAKEUP_ENABLE
,
1314 static const unsigned long nmk_pin_gpio_modes
[] = {
1315 PIN_GPIOMODE_DISABLED
,
1316 PIN_GPIOMODE_ENABLED
,
1319 static const unsigned long nmk_pin_sleep_pdis_modes
[] = {
1320 PIN_SLPM_PDIS_DISABLED
,
1321 PIN_SLPM_PDIS_ENABLED
,
1324 struct nmk_cfg_param
{
1325 const char *property
;
1326 unsigned long config
;
1327 const unsigned long *choice
;
1331 static const struct nmk_cfg_param nmk_cfg_params
[] = {
1332 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes
),
1333 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes
),
1334 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes
),
1335 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes
),
1336 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes
),
1337 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes
),
1338 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes
),
1339 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes
),
1342 static int nmk_dt_pin_config(int index
, int val
, unsigned long *config
)
1346 if (nmk_cfg_params
[index
].choice
== NULL
)
1347 *config
= nmk_cfg_params
[index
].config
;
1349 /* test if out of range */
1350 if (val
< nmk_cfg_params
[index
].size
) {
1351 *config
= nmk_cfg_params
[index
].config
|
1352 nmk_cfg_params
[index
].choice
[val
];
1358 static const char *nmk_find_pin_name(struct pinctrl_dev
*pctldev
, const char *pin_name
)
1361 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1363 if (sscanf((char *)pin_name
, "GPIO%d", &pin_number
) == 1)
1364 for (i
= 0; i
< npct
->soc
->npins
; i
++)
1365 if (npct
->soc
->pins
[i
].number
== pin_number
)
1366 return npct
->soc
->pins
[i
].name
;
1370 static bool nmk_pinctrl_dt_get_config(struct device_node
*np
,
1371 unsigned long *configs
)
1373 bool has_config
= 0;
1374 unsigned long cfg
= 0;
1377 for (i
= 0; i
< ARRAY_SIZE(nmk_cfg_params
); i
++) {
1378 ret
= of_property_read_u32(np
,
1379 nmk_cfg_params
[i
].property
, &val
);
1380 if (ret
!= -EINVAL
) {
1381 if (nmk_dt_pin_config(i
, val
, &cfg
) == 0) {
1391 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev
*pctldev
,
1392 struct device_node
*np
,
1393 struct pinctrl_map
**map
,
1394 unsigned *reserved_maps
,
1398 const char *function
= NULL
;
1399 unsigned long configs
= 0;
1400 bool has_config
= 0;
1401 unsigned reserve
= 0;
1402 struct property
*prop
;
1403 const char *group
, *gpio_name
;
1404 struct device_node
*np_config
;
1406 ret
= of_property_read_string(np
, "ste,function", &function
);
1410 has_config
= nmk_pinctrl_dt_get_config(np
, &configs
);
1412 np_config
= of_parse_phandle(np
, "ste,config", 0);
1414 has_config
|= nmk_pinctrl_dt_get_config(np_config
, &configs
);
1416 ret
= of_property_count_strings(np
, "ste,pins");
1425 ret
= nmk_dt_reserve_map(map
, reserved_maps
, num_maps
, reserve
);
1429 of_property_for_each_string(np
, "ste,pins", prop
, group
) {
1431 ret
= nmk_dt_add_map_mux(map
, reserved_maps
, num_maps
,
1437 gpio_name
= nmk_find_pin_name(pctldev
, group
);
1439 ret
= nmk_dt_add_map_configs(map
, reserved_maps
, num_maps
,
1440 gpio_name
, &configs
, 1);
1450 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev
*pctldev
,
1451 struct device_node
*np_config
,
1452 struct pinctrl_map
**map
, unsigned *num_maps
)
1454 unsigned reserved_maps
;
1455 struct device_node
*np
;
1462 for_each_child_of_node(np_config
, np
) {
1463 ret
= nmk_pinctrl_dt_subnode_to_map(pctldev
, np
, map
,
1464 &reserved_maps
, num_maps
);
1466 nmk_pinctrl_dt_free_map(pctldev
, *map
, *num_maps
);
1474 static const struct pinctrl_ops nmk_pinctrl_ops
= {
1475 .get_groups_count
= nmk_get_groups_cnt
,
1476 .get_group_name
= nmk_get_group_name
,
1477 .get_group_pins
= nmk_get_group_pins
,
1478 .pin_dbg_show
= nmk_pin_dbg_show
,
1479 .dt_node_to_map
= nmk_pinctrl_dt_node_to_map
,
1480 .dt_free_map
= nmk_pinctrl_dt_free_map
,
1483 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev
*pctldev
)
1485 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1487 return npct
->soc
->nfunctions
;
1490 static const char *nmk_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
1493 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1495 return npct
->soc
->functions
[function
].name
;
1498 static int nmk_pmx_get_func_groups(struct pinctrl_dev
*pctldev
,
1500 const char * const **groups
,
1501 unsigned * const num_groups
)
1503 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1505 *groups
= npct
->soc
->functions
[function
].groups
;
1506 *num_groups
= npct
->soc
->functions
[function
].ngroups
;
1511 static int nmk_pmx_enable(struct pinctrl_dev
*pctldev
, unsigned function
,
1514 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1515 const struct nmk_pingroup
*g
;
1516 static unsigned int slpm
[NUM_BANKS
];
1517 unsigned long flags
= 0;
1522 g
= &npct
->soc
->groups
[group
];
1524 if (g
->altsetting
< 0)
1527 dev_dbg(npct
->dev
, "enable group %s, %u pins\n", g
->name
, g
->npins
);
1530 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1531 * we may pass through an undesired state. In this case we take
1534 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1535 * - Save SLPM registers (since we have a shadow register in the
1536 * nmk_chip we're using that as backup)
1537 * - Set SLPM=0 for the IOs you want to switch and others to 1
1538 * - Configure the GPIO registers for the IOs that are being switched
1540 * - Modify the AFLSA/B registers for the IOs that are being switched
1542 * - Restore SLPM registers
1543 * - Any spurious wake up event during switch sequence to be ignored
1546 * We REALLY need to save ALL slpm registers, because the external
1547 * IOFORCE will switch *all* ports to their sleepmode setting to as
1548 * to avoid glitches. (Not just one port!)
1550 glitch
= ((g
->altsetting
& NMK_GPIO_ALT_C
) == NMK_GPIO_ALT_C
);
1553 spin_lock_irqsave(&nmk_gpio_slpm_lock
, flags
);
1555 /* Initially don't put any pins to sleep when switching */
1556 memset(slpm
, 0xff, sizeof(slpm
));
1559 * Then mask the pins that need to be sleeping now when we're
1560 * switching to the ALT C function.
1562 for (i
= 0; i
< g
->npins
; i
++)
1563 slpm
[g
->pins
[i
] / NMK_GPIO_PER_CHIP
] &= ~BIT(g
->pins
[i
]);
1564 nmk_gpio_glitch_slpm_init(slpm
);
1567 for (i
= 0; i
< g
->npins
; i
++) {
1568 struct pinctrl_gpio_range
*range
;
1569 struct nmk_gpio_chip
*nmk_chip
;
1570 struct gpio_chip
*chip
;
1573 range
= nmk_match_gpio_range(pctldev
, g
->pins
[i
]);
1576 "invalid pin offset %d in group %s at index %d\n",
1577 g
->pins
[i
], g
->name
, i
);
1581 dev_err(npct
->dev
, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1582 g
->pins
[i
], g
->name
, i
);
1586 nmk_chip
= container_of(chip
, struct nmk_gpio_chip
, chip
);
1587 dev_dbg(npct
->dev
, "setting pin %d to altsetting %d\n", g
->pins
[i
], g
->altsetting
);
1589 clk_enable(nmk_chip
->clk
);
1590 bit
= g
->pins
[i
] % NMK_GPIO_PER_CHIP
;
1592 * If the pin is switching to altfunc, and there was an
1593 * interrupt installed on it which has been lazy disabled,
1594 * actually mask the interrupt to prevent spurious interrupts
1595 * that would occur while the pin is under control of the
1596 * peripheral. Only SKE does this.
1598 nmk_gpio_disable_lazy_irq(nmk_chip
, bit
);
1600 __nmk_gpio_set_mode_safe(nmk_chip
, bit
,
1601 (g
->altsetting
& NMK_GPIO_ALT_C
), glitch
);
1602 clk_disable(nmk_chip
->clk
);
1605 * Call PRCM GPIOCR config function in case ALTC
1606 * has been selected:
1607 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1609 * - If selection is pure ALTC and previous selection was ALTCx,
1610 * then some bits in PRCM GPIOCR registers must be cleared.
1612 if ((g
->altsetting
& NMK_GPIO_ALT_C
) == NMK_GPIO_ALT_C
)
1613 nmk_prcm_altcx_set_mode(npct
, g
->pins
[i
],
1614 g
->altsetting
>> NMK_GPIO_ALT_CX_SHIFT
);
1617 /* When all pins are successfully reconfigured we get here */
1622 nmk_gpio_glitch_slpm_restore(slpm
);
1623 spin_unlock_irqrestore(&nmk_gpio_slpm_lock
, flags
);
1629 static void nmk_pmx_disable(struct pinctrl_dev
*pctldev
,
1630 unsigned function
, unsigned group
)
1632 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1633 const struct nmk_pingroup
*g
;
1635 g
= &npct
->soc
->groups
[group
];
1637 if (g
->altsetting
< 0)
1640 /* Poke out the mux, set the pin to some default state? */
1641 dev_dbg(npct
->dev
, "disable group %s, %u pins\n", g
->name
, g
->npins
);
1644 static int nmk_gpio_request_enable(struct pinctrl_dev
*pctldev
,
1645 struct pinctrl_gpio_range
*range
,
1648 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1649 struct nmk_gpio_chip
*nmk_chip
;
1650 struct gpio_chip
*chip
;
1654 dev_err(npct
->dev
, "invalid range\n");
1658 dev_err(npct
->dev
, "missing GPIO chip in range\n");
1662 nmk_chip
= container_of(chip
, struct nmk_gpio_chip
, chip
);
1664 dev_dbg(npct
->dev
, "enable pin %u as GPIO\n", offset
);
1666 clk_enable(nmk_chip
->clk
);
1667 bit
= offset
% NMK_GPIO_PER_CHIP
;
1668 /* There is no glitch when converting any pin to GPIO */
1669 __nmk_gpio_set_mode(nmk_chip
, bit
, NMK_GPIO_ALT_GPIO
);
1670 clk_disable(nmk_chip
->clk
);
1675 static void nmk_gpio_disable_free(struct pinctrl_dev
*pctldev
,
1676 struct pinctrl_gpio_range
*range
,
1679 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1681 dev_dbg(npct
->dev
, "disable pin %u as GPIO\n", offset
);
1682 /* Set the pin to some default state, GPIO is usually default */
1685 static const struct pinmux_ops nmk_pinmux_ops
= {
1686 .get_functions_count
= nmk_pmx_get_funcs_cnt
,
1687 .get_function_name
= nmk_pmx_get_func_name
,
1688 .get_function_groups
= nmk_pmx_get_func_groups
,
1689 .enable
= nmk_pmx_enable
,
1690 .disable
= nmk_pmx_disable
,
1691 .gpio_request_enable
= nmk_gpio_request_enable
,
1692 .gpio_disable_free
= nmk_gpio_disable_free
,
1695 static int nmk_pin_config_get(struct pinctrl_dev
*pctldev
, unsigned pin
,
1696 unsigned long *config
)
1698 /* Not implemented */
1702 static int nmk_pin_config_set(struct pinctrl_dev
*pctldev
, unsigned pin
,
1703 unsigned long *configs
, unsigned num_configs
)
1705 static const char *pullnames
[] = {
1706 [NMK_GPIO_PULL_NONE
] = "none",
1707 [NMK_GPIO_PULL_UP
] = "up",
1708 [NMK_GPIO_PULL_DOWN
] = "down",
1709 [3] /* illegal */ = "??"
1711 static const char *slpmnames
[] = {
1712 [NMK_GPIO_SLPM_INPUT
] = "input/wakeup",
1713 [NMK_GPIO_SLPM_NOCHANGE
] = "no-change/no-wakeup",
1715 struct nmk_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
1716 struct nmk_gpio_chip
*nmk_chip
;
1717 struct pinctrl_gpio_range
*range
;
1718 struct gpio_chip
*chip
;
1721 int pull
, slpm
, output
, val
, i
;
1722 bool lowemi
, gpiomode
, sleep
;
1724 range
= nmk_match_gpio_range(pctldev
, pin
);
1726 dev_err(npct
->dev
, "invalid pin offset %d\n", pin
);
1730 dev_err(npct
->dev
, "GPIO chip missing in range for pin %d\n",
1735 nmk_chip
= container_of(chip
, struct nmk_gpio_chip
, chip
);
1737 for (i
= 0; i
< num_configs
; i
++) {
1739 * The pin config contains pin number and altfunction fields,
1740 * here we just ignore that part. It's being handled by the
1741 * framework and pinmux callback respectively.
1743 cfg
= (pin_cfg_t
) configs
[i
];
1744 pull
= PIN_PULL(cfg
);
1745 slpm
= PIN_SLPM(cfg
);
1746 output
= PIN_DIR(cfg
);
1748 lowemi
= PIN_LOWEMI(cfg
);
1749 gpiomode
= PIN_GPIOMODE(cfg
);
1750 sleep
= PIN_SLEEPMODE(cfg
);
1753 int slpm_pull
= PIN_SLPM_PULL(cfg
);
1754 int slpm_output
= PIN_SLPM_DIR(cfg
);
1755 int slpm_val
= PIN_SLPM_VAL(cfg
);
1757 /* All pins go into GPIO mode at sleep */
1761 * The SLPM_* values are normal values + 1 to allow zero
1762 * to mean "same as normal".
1765 pull
= slpm_pull
- 1;
1767 output
= slpm_output
- 1;
1771 dev_dbg(nmk_chip
->chip
.dev
,
1772 "pin %d: sleep pull %s, dir %s, val %s\n",
1774 slpm_pull
? pullnames
[pull
] : "same",
1775 slpm_output
? (output
? "output" : "input")
1777 slpm_val
? (val
? "high" : "low") : "same");
1780 dev_dbg(nmk_chip
->chip
.dev
,
1781 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1782 pin
, cfg
, pullnames
[pull
], slpmnames
[slpm
],
1783 output
? "output " : "input",
1784 output
? (val
? "high" : "low") : "",
1785 lowemi
? "on" : "off");
1787 clk_enable(nmk_chip
->clk
);
1788 bit
= pin
% NMK_GPIO_PER_CHIP
;
1790 /* No glitch when going to GPIO mode */
1791 __nmk_gpio_set_mode(nmk_chip
, bit
, NMK_GPIO_ALT_GPIO
);
1793 __nmk_gpio_make_output(nmk_chip
, bit
, val
);
1795 __nmk_gpio_make_input(nmk_chip
, bit
);
1796 __nmk_gpio_set_pull(nmk_chip
, bit
, pull
);
1798 /* TODO: isn't this only applicable on output pins? */
1799 __nmk_gpio_set_lowemi(nmk_chip
, bit
, lowemi
);
1801 __nmk_gpio_set_slpm(nmk_chip
, bit
, slpm
);
1802 clk_disable(nmk_chip
->clk
);
1803 } /* for each config */
1808 static const struct pinconf_ops nmk_pinconf_ops
= {
1809 .pin_config_get
= nmk_pin_config_get
,
1810 .pin_config_set
= nmk_pin_config_set
,
1813 static struct pinctrl_desc nmk_pinctrl_desc
= {
1814 .name
= "pinctrl-nomadik",
1815 .pctlops
= &nmk_pinctrl_ops
,
1816 .pmxops
= &nmk_pinmux_ops
,
1817 .confops
= &nmk_pinconf_ops
,
1818 .owner
= THIS_MODULE
,
1821 static const struct of_device_id nmk_pinctrl_match
[] = {
1823 .compatible
= "stericsson,stn8815-pinctrl",
1824 .data
= (void *)PINCTRL_NMK_STN8815
,
1827 .compatible
= "stericsson,db8500-pinctrl",
1828 .data
= (void *)PINCTRL_NMK_DB8500
,
1831 .compatible
= "stericsson,db8540-pinctrl",
1832 .data
= (void *)PINCTRL_NMK_DB8540
,
1837 static int nmk_pinctrl_suspend(struct platform_device
*pdev
, pm_message_t state
)
1839 struct nmk_pinctrl
*npct
;
1841 npct
= platform_get_drvdata(pdev
);
1845 return pinctrl_force_sleep(npct
->pctl
);
1848 static int nmk_pinctrl_resume(struct platform_device
*pdev
)
1850 struct nmk_pinctrl
*npct
;
1852 npct
= platform_get_drvdata(pdev
);
1856 return pinctrl_force_default(npct
->pctl
);
1859 static int nmk_pinctrl_probe(struct platform_device
*pdev
)
1861 const struct platform_device_id
*platid
= platform_get_device_id(pdev
);
1862 struct device_node
*np
= pdev
->dev
.of_node
;
1863 struct device_node
*prcm_np
;
1864 struct nmk_pinctrl
*npct
;
1865 struct resource
*res
;
1866 unsigned int version
= 0;
1869 npct
= devm_kzalloc(&pdev
->dev
, sizeof(*npct
), GFP_KERNEL
);
1874 version
= platid
->driver_data
;
1876 const struct of_device_id
*match
;
1878 match
= of_match_device(nmk_pinctrl_match
, &pdev
->dev
);
1881 version
= (unsigned int) match
->data
;
1884 /* Poke in other ASIC variants here */
1885 if (version
== PINCTRL_NMK_STN8815
)
1886 nmk_pinctrl_stn8815_init(&npct
->soc
);
1887 if (version
== PINCTRL_NMK_DB8500
)
1888 nmk_pinctrl_db8500_init(&npct
->soc
);
1889 if (version
== PINCTRL_NMK_DB8540
)
1890 nmk_pinctrl_db8540_init(&npct
->soc
);
1893 prcm_np
= of_parse_phandle(np
, "prcm", 0);
1895 npct
->prcm_base
= of_iomap(prcm_np
, 0);
1898 /* Allow platform passed information to over-write DT. */
1899 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1901 npct
->prcm_base
= devm_ioremap(&pdev
->dev
, res
->start
,
1902 resource_size(res
));
1903 if (!npct
->prcm_base
) {
1904 if (version
== PINCTRL_NMK_STN8815
) {
1905 dev_info(&pdev
->dev
,
1907 "assuming no ALT-Cx control is available\n");
1909 dev_err(&pdev
->dev
, "missing PRCM base address\n");
1915 * We need all the GPIO drivers to probe FIRST, or we will not be able
1916 * to obtain references to the struct gpio_chip * for them, and we
1917 * need this to proceed.
1919 for (i
= 0; i
< npct
->soc
->gpio_num_ranges
; i
++) {
1920 if (!nmk_gpio_chips
[npct
->soc
->gpio_ranges
[i
].id
]) {
1921 dev_warn(&pdev
->dev
, "GPIO chip %d not registered yet\n", i
);
1922 return -EPROBE_DEFER
;
1924 npct
->soc
->gpio_ranges
[i
].gc
= &nmk_gpio_chips
[npct
->soc
->gpio_ranges
[i
].id
]->chip
;
1927 nmk_pinctrl_desc
.pins
= npct
->soc
->pins
;
1928 nmk_pinctrl_desc
.npins
= npct
->soc
->npins
;
1929 npct
->dev
= &pdev
->dev
;
1931 npct
->pctl
= pinctrl_register(&nmk_pinctrl_desc
, &pdev
->dev
, npct
);
1933 dev_err(&pdev
->dev
, "could not register Nomadik pinctrl driver\n");
1937 /* We will handle a range of GPIO pins */
1938 for (i
= 0; i
< npct
->soc
->gpio_num_ranges
; i
++)
1939 pinctrl_add_gpio_range(npct
->pctl
, &npct
->soc
->gpio_ranges
[i
]);
1941 platform_set_drvdata(pdev
, npct
);
1942 dev_info(&pdev
->dev
, "initialized Nomadik pin control driver\n");
1947 static const struct of_device_id nmk_gpio_match
[] = {
1948 { .compatible
= "st,nomadik-gpio", },
1952 static struct platform_driver nmk_gpio_driver
= {
1954 .owner
= THIS_MODULE
,
1956 .of_match_table
= nmk_gpio_match
,
1958 .probe
= nmk_gpio_probe
,
1961 static const struct platform_device_id nmk_pinctrl_id
[] = {
1962 { "pinctrl-stn8815", PINCTRL_NMK_STN8815
},
1963 { "pinctrl-db8500", PINCTRL_NMK_DB8500
},
1964 { "pinctrl-db8540", PINCTRL_NMK_DB8540
},
1968 static struct platform_driver nmk_pinctrl_driver
= {
1970 .owner
= THIS_MODULE
,
1971 .name
= "pinctrl-nomadik",
1972 .of_match_table
= nmk_pinctrl_match
,
1974 .probe
= nmk_pinctrl_probe
,
1975 .id_table
= nmk_pinctrl_id
,
1977 .suspend
= nmk_pinctrl_suspend
,
1978 .resume
= nmk_pinctrl_resume
,
1982 static int __init
nmk_gpio_init(void)
1986 ret
= platform_driver_register(&nmk_gpio_driver
);
1989 return platform_driver_register(&nmk_pinctrl_driver
);
1992 core_initcall(nmk_gpio_init
);
1994 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1995 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1996 MODULE_LICENSE("GPL");