2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/iommu-helper.h>
26 #ifdef CONFIG_IOMMU_API
27 #include <linux/iommu.h>
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list
);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock
);
45 #ifdef CONFIG_IOMMU_API
46 static struct iommu_ops amd_iommu_ops
;
50 * general struct to manage commands send to an IOMMU
56 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
57 struct unity_map_entry
*e
);
58 static struct dma_ops_domain
*find_protection_domain(u16 devid
);
61 #ifdef CONFIG_AMD_IOMMU_STATS
64 * Initialization code for statistics collection
67 DECLARE_STATS_COUNTER(compl_wait
);
68 DECLARE_STATS_COUNTER(cnt_map_single
);
69 DECLARE_STATS_COUNTER(cnt_unmap_single
);
70 DECLARE_STATS_COUNTER(cnt_map_sg
);
71 DECLARE_STATS_COUNTER(cnt_unmap_sg
);
72 DECLARE_STATS_COUNTER(cnt_alloc_coherent
);
73 DECLARE_STATS_COUNTER(cnt_free_coherent
);
74 DECLARE_STATS_COUNTER(cross_page
);
75 DECLARE_STATS_COUNTER(domain_flush_single
);
76 DECLARE_STATS_COUNTER(domain_flush_all
);
77 DECLARE_STATS_COUNTER(alloced_io_mem
);
78 DECLARE_STATS_COUNTER(total_map_requests
);
80 static struct dentry
*stats_dir
;
81 static struct dentry
*de_isolate
;
82 static struct dentry
*de_fflush
;
84 static void amd_iommu_stats_add(struct __iommu_counter
*cnt
)
86 if (stats_dir
== NULL
)
89 cnt
->dent
= debugfs_create_u64(cnt
->name
, 0444, stats_dir
,
93 static void amd_iommu_stats_init(void)
95 stats_dir
= debugfs_create_dir("amd-iommu", NULL
);
96 if (stats_dir
== NULL
)
99 de_isolate
= debugfs_create_bool("isolation", 0444, stats_dir
,
100 (u32
*)&amd_iommu_isolate
);
102 de_fflush
= debugfs_create_bool("fullflush", 0444, stats_dir
,
103 (u32
*)&amd_iommu_unmap_flush
);
105 amd_iommu_stats_add(&compl_wait
);
106 amd_iommu_stats_add(&cnt_map_single
);
107 amd_iommu_stats_add(&cnt_unmap_single
);
108 amd_iommu_stats_add(&cnt_map_sg
);
109 amd_iommu_stats_add(&cnt_unmap_sg
);
110 amd_iommu_stats_add(&cnt_alloc_coherent
);
111 amd_iommu_stats_add(&cnt_free_coherent
);
112 amd_iommu_stats_add(&cross_page
);
113 amd_iommu_stats_add(&domain_flush_single
);
114 amd_iommu_stats_add(&domain_flush_all
);
115 amd_iommu_stats_add(&alloced_io_mem
);
116 amd_iommu_stats_add(&total_map_requests
);
121 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
122 static int iommu_has_npcache(struct amd_iommu
*iommu
)
124 return iommu
->cap
& (1UL << IOMMU_CAP_NPCACHE
);
127 /****************************************************************************
129 * Interrupt handling functions
131 ****************************************************************************/
133 static void iommu_print_event(void *__evt
)
136 int type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
137 int devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
138 int domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
139 int flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
140 u64 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
142 printk(KERN_ERR
"AMD IOMMU: Event logged [");
145 case EVENT_TYPE_ILL_DEV
:
146 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
147 "address=0x%016llx flags=0x%04x]\n",
148 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
151 case EVENT_TYPE_IO_FAULT
:
152 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
153 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
154 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
155 domid
, address
, flags
);
157 case EVENT_TYPE_DEV_TAB_ERR
:
158 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
159 "address=0x%016llx flags=0x%04x]\n",
160 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
163 case EVENT_TYPE_PAGE_TAB_ERR
:
164 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
165 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
166 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
167 domid
, address
, flags
);
169 case EVENT_TYPE_ILL_CMD
:
170 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
172 case EVENT_TYPE_CMD_HARD_ERR
:
173 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
174 "flags=0x%04x]\n", address
, flags
);
176 case EVENT_TYPE_IOTLB_INV_TO
:
177 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
178 "address=0x%016llx]\n",
179 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
182 case EVENT_TYPE_INV_DEV_REQ
:
183 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
184 "address=0x%016llx flags=0x%04x]\n",
185 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
189 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
193 static void iommu_poll_events(struct amd_iommu
*iommu
)
198 spin_lock_irqsave(&iommu
->lock
, flags
);
200 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
201 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
203 while (head
!= tail
) {
204 iommu_print_event(iommu
->evt_buf
+ head
);
205 head
= (head
+ EVENT_ENTRY_SIZE
) % iommu
->evt_buf_size
;
208 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
210 spin_unlock_irqrestore(&iommu
->lock
, flags
);
213 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
215 struct amd_iommu
*iommu
;
217 list_for_each_entry(iommu
, &amd_iommu_list
, list
)
218 iommu_poll_events(iommu
);
223 /****************************************************************************
225 * IOMMU command queuing functions
227 ****************************************************************************/
230 * Writes the command to the IOMMUs command buffer and informs the
231 * hardware about the new command. Must be called with iommu->lock held.
233 static int __iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
238 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
239 target
= iommu
->cmd_buf
+ tail
;
240 memcpy_toio(target
, cmd
, sizeof(*cmd
));
241 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
242 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
245 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
251 * General queuing function for commands. Takes iommu->lock and calls
252 * __iommu_queue_command().
254 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
259 spin_lock_irqsave(&iommu
->lock
, flags
);
260 ret
= __iommu_queue_command(iommu
, cmd
);
262 iommu
->need_sync
= true;
263 spin_unlock_irqrestore(&iommu
->lock
, flags
);
269 * This function waits until an IOMMU has completed a completion
272 static void __iommu_wait_for_completion(struct amd_iommu
*iommu
)
278 INC_STATS_COUNTER(compl_wait
);
280 while (!ready
&& (i
< EXIT_LOOP_COUNT
)) {
282 /* wait for the bit to become one */
283 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
284 ready
= status
& MMIO_STATUS_COM_WAIT_INT_MASK
;
287 /* set bit back to zero */
288 status
&= ~MMIO_STATUS_COM_WAIT_INT_MASK
;
289 writel(status
, iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
291 if (unlikely(i
== EXIT_LOOP_COUNT
))
292 panic("AMD IOMMU: Completion wait loop failed\n");
296 * This function queues a completion wait command into the command
299 static int __iommu_completion_wait(struct amd_iommu
*iommu
)
301 struct iommu_cmd cmd
;
303 memset(&cmd
, 0, sizeof(cmd
));
304 cmd
.data
[0] = CMD_COMPL_WAIT_INT_MASK
;
305 CMD_SET_TYPE(&cmd
, CMD_COMPL_WAIT
);
307 return __iommu_queue_command(iommu
, &cmd
);
311 * This function is called whenever we need to ensure that the IOMMU has
312 * completed execution of all commands we sent. It sends a
313 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
314 * us about that by writing a value to a physical address we pass with
317 static int iommu_completion_wait(struct amd_iommu
*iommu
)
322 spin_lock_irqsave(&iommu
->lock
, flags
);
324 if (!iommu
->need_sync
)
327 ret
= __iommu_completion_wait(iommu
);
329 iommu
->need_sync
= false;
334 __iommu_wait_for_completion(iommu
);
337 spin_unlock_irqrestore(&iommu
->lock
, flags
);
343 * Command send function for invalidating a device table entry
345 static int iommu_queue_inv_dev_entry(struct amd_iommu
*iommu
, u16 devid
)
347 struct iommu_cmd cmd
;
350 BUG_ON(iommu
== NULL
);
352 memset(&cmd
, 0, sizeof(cmd
));
353 CMD_SET_TYPE(&cmd
, CMD_INV_DEV_ENTRY
);
356 ret
= iommu_queue_command(iommu
, &cmd
);
361 static void __iommu_build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
362 u16 domid
, int pde
, int s
)
364 memset(cmd
, 0, sizeof(*cmd
));
365 address
&= PAGE_MASK
;
366 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
367 cmd
->data
[1] |= domid
;
368 cmd
->data
[2] = lower_32_bits(address
);
369 cmd
->data
[3] = upper_32_bits(address
);
370 if (s
) /* size bit - we flush more than one 4kb page */
371 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
372 if (pde
) /* PDE bit - we wan't flush everything not only the PTEs */
373 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
377 * Generic command send function for invalidaing TLB entries
379 static int iommu_queue_inv_iommu_pages(struct amd_iommu
*iommu
,
380 u64 address
, u16 domid
, int pde
, int s
)
382 struct iommu_cmd cmd
;
385 __iommu_build_inv_iommu_pages(&cmd
, address
, domid
, pde
, s
);
387 ret
= iommu_queue_command(iommu
, &cmd
);
393 * TLB invalidation function which is called from the mapping functions.
394 * It invalidates a single PTE if the range to flush is within a single
395 * page. Otherwise it flushes the whole TLB of the IOMMU.
397 static int iommu_flush_pages(struct amd_iommu
*iommu
, u16 domid
,
398 u64 address
, size_t size
)
401 unsigned pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
403 address
&= PAGE_MASK
;
407 * If we have to flush more than one page, flush all
408 * TLB entries for this domain
410 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
414 iommu_queue_inv_iommu_pages(iommu
, address
, domid
, 0, s
);
419 /* Flush the whole IO/TLB for a given protection domain */
420 static void iommu_flush_tlb(struct amd_iommu
*iommu
, u16 domid
)
422 u64 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
424 INC_STATS_COUNTER(domain_flush_single
);
426 iommu_queue_inv_iommu_pages(iommu
, address
, domid
, 0, 1);
430 * This function is used to flush the IO/TLB for a given protection domain
431 * on every IOMMU in the system
433 static void iommu_flush_domain(u16 domid
)
436 struct amd_iommu
*iommu
;
437 struct iommu_cmd cmd
;
439 INC_STATS_COUNTER(domain_flush_all
);
441 __iommu_build_inv_iommu_pages(&cmd
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
444 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
445 spin_lock_irqsave(&iommu
->lock
, flags
);
446 __iommu_queue_command(iommu
, &cmd
);
447 __iommu_completion_wait(iommu
);
448 __iommu_wait_for_completion(iommu
);
449 spin_unlock_irqrestore(&iommu
->lock
, flags
);
453 /****************************************************************************
455 * The functions below are used the create the page table mappings for
456 * unity mapped regions.
458 ****************************************************************************/
461 * Generic mapping functions. It maps a physical address into a DMA
462 * address space. It allocates the page table pages if necessary.
463 * In the future it can be extended to a generic mapping function
464 * supporting all features of AMD IOMMU page tables like level skipping
465 * and full 64 bit address spaces.
467 static int iommu_map_page(struct protection_domain
*dom
,
468 unsigned long bus_addr
,
469 unsigned long phys_addr
,
472 u64 __pte
, *pte
, *page
;
474 bus_addr
= PAGE_ALIGN(bus_addr
);
475 phys_addr
= PAGE_ALIGN(phys_addr
);
477 /* only support 512GB address spaces for now */
478 if (bus_addr
> IOMMU_MAP_SIZE_L3
|| !(prot
& IOMMU_PROT_MASK
))
481 pte
= &dom
->pt_root
[IOMMU_PTE_L2_INDEX(bus_addr
)];
483 if (!IOMMU_PTE_PRESENT(*pte
)) {
484 page
= (u64
*)get_zeroed_page(GFP_KERNEL
);
487 *pte
= IOMMU_L2_PDE(virt_to_phys(page
));
490 pte
= IOMMU_PTE_PAGE(*pte
);
491 pte
= &pte
[IOMMU_PTE_L1_INDEX(bus_addr
)];
493 if (!IOMMU_PTE_PRESENT(*pte
)) {
494 page
= (u64
*)get_zeroed_page(GFP_KERNEL
);
497 *pte
= IOMMU_L1_PDE(virt_to_phys(page
));
500 pte
= IOMMU_PTE_PAGE(*pte
);
501 pte
= &pte
[IOMMU_PTE_L0_INDEX(bus_addr
)];
503 if (IOMMU_PTE_PRESENT(*pte
))
506 __pte
= phys_addr
| IOMMU_PTE_P
;
507 if (prot
& IOMMU_PROT_IR
)
508 __pte
|= IOMMU_PTE_IR
;
509 if (prot
& IOMMU_PROT_IW
)
510 __pte
|= IOMMU_PTE_IW
;
517 static void iommu_unmap_page(struct protection_domain
*dom
,
518 unsigned long bus_addr
)
522 pte
= &dom
->pt_root
[IOMMU_PTE_L2_INDEX(bus_addr
)];
524 if (!IOMMU_PTE_PRESENT(*pte
))
527 pte
= IOMMU_PTE_PAGE(*pte
);
528 pte
= &pte
[IOMMU_PTE_L1_INDEX(bus_addr
)];
530 if (!IOMMU_PTE_PRESENT(*pte
))
533 pte
= IOMMU_PTE_PAGE(*pte
);
534 pte
= &pte
[IOMMU_PTE_L1_INDEX(bus_addr
)];
540 * This function checks if a specific unity mapping entry is needed for
541 * this specific IOMMU.
543 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
544 struct unity_map_entry
*entry
)
548 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
549 bdf
= amd_iommu_alias_table
[i
];
550 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
558 * Init the unity mappings for a specific IOMMU in the system
560 * Basically iterates over all unity mapping entries and applies them to
561 * the default domain DMA of that IOMMU if necessary.
563 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
565 struct unity_map_entry
*entry
;
568 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
569 if (!iommu_for_unity_map(iommu
, entry
))
571 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
580 * This function actually applies the mapping to the page table of the
583 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
584 struct unity_map_entry
*e
)
589 for (addr
= e
->address_start
; addr
< e
->address_end
;
591 ret
= iommu_map_page(&dma_dom
->domain
, addr
, addr
, e
->prot
);
595 * if unity mapping is in aperture range mark the page
596 * as allocated in the aperture
598 if (addr
< dma_dom
->aperture_size
)
599 __set_bit(addr
>> PAGE_SHIFT
, dma_dom
->bitmap
);
606 * Inits the unity mappings required for a specific device
608 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
611 struct unity_map_entry
*e
;
614 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
615 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
617 ret
= dma_ops_unity_map(dma_dom
, e
);
625 /****************************************************************************
627 * The next functions belong to the address allocator for the dma_ops
628 * interface functions. They work like the allocators in the other IOMMU
629 * drivers. Its basically a bitmap which marks the allocated pages in
630 * the aperture. Maybe it could be enhanced in the future to a more
631 * efficient allocator.
633 ****************************************************************************/
636 * The address allocator core function.
638 * called with domain->lock held
640 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
641 struct dma_ops_domain
*dom
,
643 unsigned long align_mask
,
647 unsigned long address
;
648 unsigned long boundary_size
;
650 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
651 PAGE_SIZE
) >> PAGE_SHIFT
;
652 limit
= iommu_device_max_index(dom
->aperture_size
>> PAGE_SHIFT
, 0,
653 dma_mask
>> PAGE_SHIFT
);
655 if (dom
->next_bit
>= limit
) {
657 dom
->need_flush
= true;
660 address
= iommu_area_alloc(dom
->bitmap
, limit
, dom
->next_bit
, pages
,
661 0 , boundary_size
, align_mask
);
663 address
= iommu_area_alloc(dom
->bitmap
, limit
, 0, pages
,
664 0, boundary_size
, align_mask
);
665 dom
->need_flush
= true;
668 if (likely(address
!= -1)) {
669 dom
->next_bit
= address
+ pages
;
670 address
<<= PAGE_SHIFT
;
672 address
= bad_dma_address
;
674 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
680 * The address free function.
682 * called with domain->lock held
684 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
685 unsigned long address
,
688 address
>>= PAGE_SHIFT
;
689 iommu_area_free(dom
->bitmap
, address
, pages
);
691 if (address
>= dom
->next_bit
)
692 dom
->need_flush
= true;
695 /****************************************************************************
697 * The next functions belong to the domain allocation. A domain is
698 * allocated for every IOMMU as the default domain. If device isolation
699 * is enabled, every device get its own domain. The most important thing
700 * about domains is the page table mapping the DMA address space they
703 ****************************************************************************/
705 static u16
domain_id_alloc(void)
710 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
711 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
713 if (id
> 0 && id
< MAX_DOMAIN_ID
)
714 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
717 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
722 static void domain_id_free(int id
)
726 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
727 if (id
> 0 && id
< MAX_DOMAIN_ID
)
728 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
729 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
733 * Used to reserve address ranges in the aperture (e.g. for exclusion
736 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
737 unsigned long start_page
,
740 unsigned int last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
742 if (start_page
+ pages
> last_page
)
743 pages
= last_page
- start_page
;
745 iommu_area_reserve(dom
->bitmap
, start_page
, pages
);
748 static void free_pagetable(struct protection_domain
*domain
)
753 p1
= domain
->pt_root
;
758 for (i
= 0; i
< 512; ++i
) {
759 if (!IOMMU_PTE_PRESENT(p1
[i
]))
762 p2
= IOMMU_PTE_PAGE(p1
[i
]);
763 for (j
= 0; j
< 512; ++j
) {
764 if (!IOMMU_PTE_PRESENT(p2
[j
]))
766 p3
= IOMMU_PTE_PAGE(p2
[j
]);
767 free_page((unsigned long)p3
);
770 free_page((unsigned long)p2
);
773 free_page((unsigned long)p1
);
775 domain
->pt_root
= NULL
;
779 * Free a domain, only used if something went wrong in the
780 * allocation path and we need to free an already allocated page table
782 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
787 free_pagetable(&dom
->domain
);
789 kfree(dom
->pte_pages
);
797 * Allocates a new protection domain usable for the dma_ops functions.
798 * It also intializes the page table and the address allocator data
799 * structures required for the dma_ops interface
801 static struct dma_ops_domain
*dma_ops_domain_alloc(struct amd_iommu
*iommu
,
804 struct dma_ops_domain
*dma_dom
;
805 unsigned i
, num_pte_pages
;
810 * Currently the DMA aperture must be between 32 MB and 1GB in size
812 if ((order
< 25) || (order
> 30))
815 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
819 spin_lock_init(&dma_dom
->domain
.lock
);
821 dma_dom
->domain
.id
= domain_id_alloc();
822 if (dma_dom
->domain
.id
== 0)
824 dma_dom
->domain
.mode
= PAGE_MODE_3_LEVEL
;
825 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
826 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
827 dma_dom
->domain
.priv
= dma_dom
;
828 if (!dma_dom
->domain
.pt_root
)
830 dma_dom
->aperture_size
= (1ULL << order
);
831 dma_dom
->bitmap
= kzalloc(dma_dom
->aperture_size
/ (PAGE_SIZE
* 8),
833 if (!dma_dom
->bitmap
)
836 * mark the first page as allocated so we never return 0 as
837 * a valid dma-address. So we can use 0 as error value
839 dma_dom
->bitmap
[0] = 1;
840 dma_dom
->next_bit
= 0;
842 dma_dom
->need_flush
= false;
843 dma_dom
->target_dev
= 0xffff;
845 /* Intialize the exclusion range if necessary */
846 if (iommu
->exclusion_start
&&
847 iommu
->exclusion_start
< dma_dom
->aperture_size
) {
848 unsigned long startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
849 int pages
= iommu_num_pages(iommu
->exclusion_start
,
850 iommu
->exclusion_length
,
852 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
856 * At the last step, build the page tables so we don't need to
857 * allocate page table pages in the dma_ops mapping/unmapping
860 num_pte_pages
= dma_dom
->aperture_size
/ (PAGE_SIZE
* 512);
861 dma_dom
->pte_pages
= kzalloc(num_pte_pages
* sizeof(void *),
863 if (!dma_dom
->pte_pages
)
866 l2_pde
= (u64
*)get_zeroed_page(GFP_KERNEL
);
870 dma_dom
->domain
.pt_root
[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde
));
872 for (i
= 0; i
< num_pte_pages
; ++i
) {
873 dma_dom
->pte_pages
[i
] = (u64
*)get_zeroed_page(GFP_KERNEL
);
874 if (!dma_dom
->pte_pages
[i
])
876 address
= virt_to_phys(dma_dom
->pte_pages
[i
]);
877 l2_pde
[i
] = IOMMU_L1_PDE(address
);
883 dma_ops_domain_free(dma_dom
);
889 * little helper function to check whether a given protection domain is a
892 static bool dma_ops_domain(struct protection_domain
*domain
)
894 return domain
->flags
& PD_DMA_OPS_MASK
;
898 * Find out the protection domain structure for a given PCI device. This
899 * will give us the pointer to the page table root for example.
901 static struct protection_domain
*domain_for_device(u16 devid
)
903 struct protection_domain
*dom
;
906 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
907 dom
= amd_iommu_pd_table
[devid
];
908 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
914 * If a device is not yet associated with a domain, this function does
915 * assigns it visible for the hardware
917 static void attach_device(struct amd_iommu
*iommu
,
918 struct protection_domain
*domain
,
922 u64 pte_root
= virt_to_phys(domain
->pt_root
);
924 domain
->dev_cnt
+= 1;
926 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
927 << DEV_ENTRY_MODE_SHIFT
;
928 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
930 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
931 amd_iommu_dev_table
[devid
].data
[0] = lower_32_bits(pte_root
);
932 amd_iommu_dev_table
[devid
].data
[1] = upper_32_bits(pte_root
);
933 amd_iommu_dev_table
[devid
].data
[2] = domain
->id
;
935 amd_iommu_pd_table
[devid
] = domain
;
936 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
938 iommu_queue_inv_dev_entry(iommu
, devid
);
942 * Removes a device from a protection domain (unlocked)
944 static void __detach_device(struct protection_domain
*domain
, u16 devid
)
948 spin_lock(&domain
->lock
);
950 /* remove domain from the lookup table */
951 amd_iommu_pd_table
[devid
] = NULL
;
953 /* remove entry from the device table seen by the hardware */
954 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
955 amd_iommu_dev_table
[devid
].data
[1] = 0;
956 amd_iommu_dev_table
[devid
].data
[2] = 0;
958 /* decrease reference counter */
959 domain
->dev_cnt
-= 1;
962 spin_unlock(&domain
->lock
);
966 * Removes a device from a protection domain (with devtable_lock held)
968 static void detach_device(struct protection_domain
*domain
, u16 devid
)
972 /* lock device table */
973 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
974 __detach_device(domain
, devid
);
975 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
978 static int device_change_notifier(struct notifier_block
*nb
,
979 unsigned long action
, void *data
)
981 struct device
*dev
= data
;
982 struct pci_dev
*pdev
= to_pci_dev(dev
);
983 u16 devid
= calc_devid(pdev
->bus
->number
, pdev
->devfn
);
984 struct protection_domain
*domain
;
985 struct dma_ops_domain
*dma_domain
;
986 struct amd_iommu
*iommu
;
987 int order
= amd_iommu_aperture_order
;
990 if (devid
> amd_iommu_last_bdf
)
993 devid
= amd_iommu_alias_table
[devid
];
995 iommu
= amd_iommu_rlookup_table
[devid
];
999 domain
= domain_for_device(devid
);
1001 if (domain
&& !dma_ops_domain(domain
))
1002 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1003 "to a non-dma-ops domain\n", dev_name(dev
));
1006 case BUS_NOTIFY_BOUND_DRIVER
:
1009 dma_domain
= find_protection_domain(devid
);
1011 dma_domain
= iommu
->default_dom
;
1012 attach_device(iommu
, &dma_domain
->domain
, devid
);
1013 printk(KERN_INFO
"AMD IOMMU: Using protection domain %d for "
1014 "device %s\n", dma_domain
->domain
.id
, dev_name(dev
));
1016 case BUS_NOTIFY_UNBIND_DRIVER
:
1019 detach_device(domain
, devid
);
1021 case BUS_NOTIFY_ADD_DEVICE
:
1022 /* allocate a protection domain if a device is added */
1023 dma_domain
= find_protection_domain(devid
);
1026 dma_domain
= dma_ops_domain_alloc(iommu
, order
);
1029 dma_domain
->target_dev
= devid
;
1031 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
1032 list_add_tail(&dma_domain
->list
, &iommu_pd_list
);
1033 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
1040 iommu_queue_inv_dev_entry(iommu
, devid
);
1041 iommu_completion_wait(iommu
);
1047 struct notifier_block device_nb
= {
1048 .notifier_call
= device_change_notifier
,
1051 /*****************************************************************************
1053 * The next functions belong to the dma_ops mapping/unmapping code.
1055 *****************************************************************************/
1058 * This function checks if the driver got a valid device from the caller to
1059 * avoid dereferencing invalid pointers.
1061 static bool check_device(struct device
*dev
)
1063 if (!dev
|| !dev
->dma_mask
)
1070 * In this function the list of preallocated protection domains is traversed to
1071 * find the domain for a specific device
1073 static struct dma_ops_domain
*find_protection_domain(u16 devid
)
1075 struct dma_ops_domain
*entry
, *ret
= NULL
;
1076 unsigned long flags
;
1078 if (list_empty(&iommu_pd_list
))
1081 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
1083 list_for_each_entry(entry
, &iommu_pd_list
, list
) {
1084 if (entry
->target_dev
== devid
) {
1090 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
1096 * In the dma_ops path we only have the struct device. This function
1097 * finds the corresponding IOMMU, the protection domain and the
1098 * requestor id for a given device.
1099 * If the device is not yet associated with a domain this is also done
1102 static int get_device_resources(struct device
*dev
,
1103 struct amd_iommu
**iommu
,
1104 struct protection_domain
**domain
,
1107 struct dma_ops_domain
*dma_dom
;
1108 struct pci_dev
*pcidev
;
1115 if (dev
->bus
!= &pci_bus_type
)
1118 pcidev
= to_pci_dev(dev
);
1119 _bdf
= calc_devid(pcidev
->bus
->number
, pcidev
->devfn
);
1121 /* device not translated by any IOMMU in the system? */
1122 if (_bdf
> amd_iommu_last_bdf
)
1125 *bdf
= amd_iommu_alias_table
[_bdf
];
1127 *iommu
= amd_iommu_rlookup_table
[*bdf
];
1130 *domain
= domain_for_device(*bdf
);
1131 if (*domain
== NULL
) {
1132 dma_dom
= find_protection_domain(*bdf
);
1134 dma_dom
= (*iommu
)->default_dom
;
1135 *domain
= &dma_dom
->domain
;
1136 attach_device(*iommu
, *domain
, *bdf
);
1137 printk(KERN_INFO
"AMD IOMMU: Using protection domain %d for "
1138 "device %s\n", (*domain
)->id
, dev_name(dev
));
1141 if (domain_for_device(_bdf
) == NULL
)
1142 attach_device(*iommu
, *domain
, _bdf
);
1148 * This is the generic map function. It maps one 4kb page at paddr to
1149 * the given address in the DMA address space for the domain.
1151 static dma_addr_t
dma_ops_domain_map(struct amd_iommu
*iommu
,
1152 struct dma_ops_domain
*dom
,
1153 unsigned long address
,
1159 WARN_ON(address
> dom
->aperture_size
);
1163 pte
= dom
->pte_pages
[IOMMU_PTE_L1_INDEX(address
)];
1164 pte
+= IOMMU_PTE_L0_INDEX(address
);
1166 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1168 if (direction
== DMA_TO_DEVICE
)
1169 __pte
|= IOMMU_PTE_IR
;
1170 else if (direction
== DMA_FROM_DEVICE
)
1171 __pte
|= IOMMU_PTE_IW
;
1172 else if (direction
== DMA_BIDIRECTIONAL
)
1173 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
1179 return (dma_addr_t
)address
;
1183 * The generic unmapping function for on page in the DMA address space.
1185 static void dma_ops_domain_unmap(struct amd_iommu
*iommu
,
1186 struct dma_ops_domain
*dom
,
1187 unsigned long address
)
1191 if (address
>= dom
->aperture_size
)
1194 WARN_ON(address
& ~PAGE_MASK
|| address
>= dom
->aperture_size
);
1196 pte
= dom
->pte_pages
[IOMMU_PTE_L1_INDEX(address
)];
1197 pte
+= IOMMU_PTE_L0_INDEX(address
);
1205 * This function contains common code for mapping of a physically
1206 * contiguous memory region into DMA address space. It is used by all
1207 * mapping functions provided with this IOMMU driver.
1208 * Must be called with the domain lock held.
1210 static dma_addr_t
__map_single(struct device
*dev
,
1211 struct amd_iommu
*iommu
,
1212 struct dma_ops_domain
*dma_dom
,
1219 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
1220 dma_addr_t address
, start
;
1222 unsigned long align_mask
= 0;
1225 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
1228 INC_STATS_COUNTER(total_map_requests
);
1231 INC_STATS_COUNTER(cross_page
);
1234 align_mask
= (1UL << get_order(size
)) - 1;
1236 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
1238 if (unlikely(address
== bad_dma_address
))
1242 for (i
= 0; i
< pages
; ++i
) {
1243 dma_ops_domain_map(iommu
, dma_dom
, start
, paddr
, dir
);
1249 ADD_STATS_COUNTER(alloced_io_mem
, size
);
1251 if (unlikely(dma_dom
->need_flush
&& !amd_iommu_unmap_flush
)) {
1252 iommu_flush_tlb(iommu
, dma_dom
->domain
.id
);
1253 dma_dom
->need_flush
= false;
1254 } else if (unlikely(iommu_has_npcache(iommu
)))
1255 iommu_flush_pages(iommu
, dma_dom
->domain
.id
, address
, size
);
1262 * Does the reverse of the __map_single function. Must be called with
1263 * the domain lock held too
1265 static void __unmap_single(struct amd_iommu
*iommu
,
1266 struct dma_ops_domain
*dma_dom
,
1267 dma_addr_t dma_addr
,
1271 dma_addr_t i
, start
;
1274 if ((dma_addr
== bad_dma_address
) ||
1275 (dma_addr
+ size
> dma_dom
->aperture_size
))
1278 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
1279 dma_addr
&= PAGE_MASK
;
1282 for (i
= 0; i
< pages
; ++i
) {
1283 dma_ops_domain_unmap(iommu
, dma_dom
, start
);
1287 SUB_STATS_COUNTER(alloced_io_mem
, size
);
1289 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
1291 if (amd_iommu_unmap_flush
|| dma_dom
->need_flush
) {
1292 iommu_flush_pages(iommu
, dma_dom
->domain
.id
, dma_addr
, size
);
1293 dma_dom
->need_flush
= false;
1298 * The exported map_single function for dma_ops.
1300 static dma_addr_t
map_single(struct device
*dev
, phys_addr_t paddr
,
1301 size_t size
, int dir
)
1303 unsigned long flags
;
1304 struct amd_iommu
*iommu
;
1305 struct protection_domain
*domain
;
1310 INC_STATS_COUNTER(cnt_map_single
);
1312 if (!check_device(dev
))
1313 return bad_dma_address
;
1315 dma_mask
= *dev
->dma_mask
;
1317 get_device_resources(dev
, &iommu
, &domain
, &devid
);
1319 if (iommu
== NULL
|| domain
== NULL
)
1320 /* device not handled by any AMD IOMMU */
1321 return (dma_addr_t
)paddr
;
1323 if (!dma_ops_domain(domain
))
1324 return bad_dma_address
;
1326 spin_lock_irqsave(&domain
->lock
, flags
);
1327 addr
= __map_single(dev
, iommu
, domain
->priv
, paddr
, size
, dir
, false,
1329 if (addr
== bad_dma_address
)
1332 iommu_completion_wait(iommu
);
1335 spin_unlock_irqrestore(&domain
->lock
, flags
);
1341 * The exported unmap_single function for dma_ops.
1343 static void unmap_single(struct device
*dev
, dma_addr_t dma_addr
,
1344 size_t size
, int dir
)
1346 unsigned long flags
;
1347 struct amd_iommu
*iommu
;
1348 struct protection_domain
*domain
;
1351 INC_STATS_COUNTER(cnt_unmap_single
);
1353 if (!check_device(dev
) ||
1354 !get_device_resources(dev
, &iommu
, &domain
, &devid
))
1355 /* device not handled by any AMD IOMMU */
1358 if (!dma_ops_domain(domain
))
1361 spin_lock_irqsave(&domain
->lock
, flags
);
1363 __unmap_single(iommu
, domain
->priv
, dma_addr
, size
, dir
);
1365 iommu_completion_wait(iommu
);
1367 spin_unlock_irqrestore(&domain
->lock
, flags
);
1371 * This is a special map_sg function which is used if we should map a
1372 * device which is not handled by an AMD IOMMU in the system.
1374 static int map_sg_no_iommu(struct device
*dev
, struct scatterlist
*sglist
,
1375 int nelems
, int dir
)
1377 struct scatterlist
*s
;
1380 for_each_sg(sglist
, s
, nelems
, i
) {
1381 s
->dma_address
= (dma_addr_t
)sg_phys(s
);
1382 s
->dma_length
= s
->length
;
1389 * The exported map_sg function for dma_ops (handles scatter-gather
1392 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
1393 int nelems
, int dir
)
1395 unsigned long flags
;
1396 struct amd_iommu
*iommu
;
1397 struct protection_domain
*domain
;
1400 struct scatterlist
*s
;
1402 int mapped_elems
= 0;
1405 INC_STATS_COUNTER(cnt_map_sg
);
1407 if (!check_device(dev
))
1410 dma_mask
= *dev
->dma_mask
;
1412 get_device_resources(dev
, &iommu
, &domain
, &devid
);
1414 if (!iommu
|| !domain
)
1415 return map_sg_no_iommu(dev
, sglist
, nelems
, dir
);
1417 if (!dma_ops_domain(domain
))
1420 spin_lock_irqsave(&domain
->lock
, flags
);
1422 for_each_sg(sglist
, s
, nelems
, i
) {
1425 s
->dma_address
= __map_single(dev
, iommu
, domain
->priv
,
1426 paddr
, s
->length
, dir
, false,
1429 if (s
->dma_address
) {
1430 s
->dma_length
= s
->length
;
1436 iommu_completion_wait(iommu
);
1439 spin_unlock_irqrestore(&domain
->lock
, flags
);
1441 return mapped_elems
;
1443 for_each_sg(sglist
, s
, mapped_elems
, i
) {
1445 __unmap_single(iommu
, domain
->priv
, s
->dma_address
,
1446 s
->dma_length
, dir
);
1447 s
->dma_address
= s
->dma_length
= 0;
1456 * The exported map_sg function for dma_ops (handles scatter-gather
1459 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
1460 int nelems
, int dir
)
1462 unsigned long flags
;
1463 struct amd_iommu
*iommu
;
1464 struct protection_domain
*domain
;
1465 struct scatterlist
*s
;
1469 INC_STATS_COUNTER(cnt_unmap_sg
);
1471 if (!check_device(dev
) ||
1472 !get_device_resources(dev
, &iommu
, &domain
, &devid
))
1475 if (!dma_ops_domain(domain
))
1478 spin_lock_irqsave(&domain
->lock
, flags
);
1480 for_each_sg(sglist
, s
, nelems
, i
) {
1481 __unmap_single(iommu
, domain
->priv
, s
->dma_address
,
1482 s
->dma_length
, dir
);
1483 s
->dma_address
= s
->dma_length
= 0;
1486 iommu_completion_wait(iommu
);
1488 spin_unlock_irqrestore(&domain
->lock
, flags
);
1492 * The exported alloc_coherent function for dma_ops.
1494 static void *alloc_coherent(struct device
*dev
, size_t size
,
1495 dma_addr_t
*dma_addr
, gfp_t flag
)
1497 unsigned long flags
;
1499 struct amd_iommu
*iommu
;
1500 struct protection_domain
*domain
;
1503 u64 dma_mask
= dev
->coherent_dma_mask
;
1505 INC_STATS_COUNTER(cnt_alloc_coherent
);
1507 if (!check_device(dev
))
1510 if (!get_device_resources(dev
, &iommu
, &domain
, &devid
))
1511 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
1514 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
1518 paddr
= virt_to_phys(virt_addr
);
1520 if (!iommu
|| !domain
) {
1521 *dma_addr
= (dma_addr_t
)paddr
;
1525 if (!dma_ops_domain(domain
))
1529 dma_mask
= *dev
->dma_mask
;
1531 spin_lock_irqsave(&domain
->lock
, flags
);
1533 *dma_addr
= __map_single(dev
, iommu
, domain
->priv
, paddr
,
1534 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
1536 if (*dma_addr
== bad_dma_address
)
1539 iommu_completion_wait(iommu
);
1541 spin_unlock_irqrestore(&domain
->lock
, flags
);
1547 free_pages((unsigned long)virt_addr
, get_order(size
));
1553 * The exported free_coherent function for dma_ops.
1555 static void free_coherent(struct device
*dev
, size_t size
,
1556 void *virt_addr
, dma_addr_t dma_addr
)
1558 unsigned long flags
;
1559 struct amd_iommu
*iommu
;
1560 struct protection_domain
*domain
;
1563 INC_STATS_COUNTER(cnt_free_coherent
);
1565 if (!check_device(dev
))
1568 get_device_resources(dev
, &iommu
, &domain
, &devid
);
1570 if (!iommu
|| !domain
)
1573 if (!dma_ops_domain(domain
))
1576 spin_lock_irqsave(&domain
->lock
, flags
);
1578 __unmap_single(iommu
, domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
1580 iommu_completion_wait(iommu
);
1582 spin_unlock_irqrestore(&domain
->lock
, flags
);
1585 free_pages((unsigned long)virt_addr
, get_order(size
));
1589 * This function is called by the DMA layer to find out if we can handle a
1590 * particular device. It is part of the dma_ops.
1592 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
1595 struct pci_dev
*pcidev
;
1597 /* No device or no PCI device */
1598 if (!dev
|| dev
->bus
!= &pci_bus_type
)
1601 pcidev
= to_pci_dev(dev
);
1603 bdf
= calc_devid(pcidev
->bus
->number
, pcidev
->devfn
);
1605 /* Out of our scope? */
1606 if (bdf
> amd_iommu_last_bdf
)
1613 * The function for pre-allocating protection domains.
1615 * If the driver core informs the DMA layer if a driver grabs a device
1616 * we don't need to preallocate the protection domains anymore.
1617 * For now we have to.
1619 static void prealloc_protection_domains(void)
1621 struct pci_dev
*dev
= NULL
;
1622 struct dma_ops_domain
*dma_dom
;
1623 struct amd_iommu
*iommu
;
1624 int order
= amd_iommu_aperture_order
;
1627 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
1628 devid
= calc_devid(dev
->bus
->number
, dev
->devfn
);
1629 if (devid
> amd_iommu_last_bdf
)
1631 devid
= amd_iommu_alias_table
[devid
];
1632 if (domain_for_device(devid
))
1634 iommu
= amd_iommu_rlookup_table
[devid
];
1637 dma_dom
= dma_ops_domain_alloc(iommu
, order
);
1640 init_unity_mappings_for_device(dma_dom
, devid
);
1641 dma_dom
->target_dev
= devid
;
1643 list_add_tail(&dma_dom
->list
, &iommu_pd_list
);
1647 static struct dma_mapping_ops amd_iommu_dma_ops
= {
1648 .alloc_coherent
= alloc_coherent
,
1649 .free_coherent
= free_coherent
,
1650 .map_single
= map_single
,
1651 .unmap_single
= unmap_single
,
1653 .unmap_sg
= unmap_sg
,
1654 .dma_supported
= amd_iommu_dma_supported
,
1658 * The function which clues the AMD IOMMU driver into dma_ops.
1660 int __init
amd_iommu_init_dma_ops(void)
1662 struct amd_iommu
*iommu
;
1663 int order
= amd_iommu_aperture_order
;
1667 * first allocate a default protection domain for every IOMMU we
1668 * found in the system. Devices not assigned to any other
1669 * protection domain will be assigned to the default one.
1671 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
1672 iommu
->default_dom
= dma_ops_domain_alloc(iommu
, order
);
1673 if (iommu
->default_dom
== NULL
)
1675 iommu
->default_dom
->domain
.flags
|= PD_DEFAULT_MASK
;
1676 ret
= iommu_init_unity_mappings(iommu
);
1682 * If device isolation is enabled, pre-allocate the protection
1683 * domains for each device.
1685 if (amd_iommu_isolate
)
1686 prealloc_protection_domains();
1690 bad_dma_address
= 0;
1691 #ifdef CONFIG_GART_IOMMU
1692 gart_iommu_aperture_disabled
= 1;
1693 gart_iommu_aperture
= 0;
1696 /* Make the driver finally visible to the drivers */
1697 dma_ops
= &amd_iommu_dma_ops
;
1699 register_iommu(&amd_iommu_ops
);
1701 bus_register_notifier(&pci_bus_type
, &device_nb
);
1703 amd_iommu_stats_init();
1709 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
1710 if (iommu
->default_dom
)
1711 dma_ops_domain_free(iommu
->default_dom
);
1717 /*****************************************************************************
1719 * The following functions belong to the exported interface of AMD IOMMU
1721 * This interface allows access to lower level functions of the IOMMU
1722 * like protection domain handling and assignement of devices to domains
1723 * which is not possible with the dma_ops interface.
1725 *****************************************************************************/
1727 static void cleanup_domain(struct protection_domain
*domain
)
1729 unsigned long flags
;
1732 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1734 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
)
1735 if (amd_iommu_pd_table
[devid
] == domain
)
1736 __detach_device(domain
, devid
);
1738 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1741 static int amd_iommu_domain_init(struct iommu_domain
*dom
)
1743 struct protection_domain
*domain
;
1745 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
1749 spin_lock_init(&domain
->lock
);
1750 domain
->mode
= PAGE_MODE_3_LEVEL
;
1751 domain
->id
= domain_id_alloc();
1754 domain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1755 if (!domain
->pt_root
)
1768 static void amd_iommu_domain_destroy(struct iommu_domain
*dom
)
1770 struct protection_domain
*domain
= dom
->priv
;
1775 if (domain
->dev_cnt
> 0)
1776 cleanup_domain(domain
);
1778 BUG_ON(domain
->dev_cnt
!= 0);
1780 free_pagetable(domain
);
1782 domain_id_free(domain
->id
);
1789 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
1792 struct protection_domain
*domain
= dom
->priv
;
1793 struct amd_iommu
*iommu
;
1794 struct pci_dev
*pdev
;
1797 if (dev
->bus
!= &pci_bus_type
)
1800 pdev
= to_pci_dev(dev
);
1802 devid
= calc_devid(pdev
->bus
->number
, pdev
->devfn
);
1805 detach_device(domain
, devid
);
1807 iommu
= amd_iommu_rlookup_table
[devid
];
1811 iommu_queue_inv_dev_entry(iommu
, devid
);
1812 iommu_completion_wait(iommu
);
1815 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
1818 struct protection_domain
*domain
= dom
->priv
;
1819 struct protection_domain
*old_domain
;
1820 struct amd_iommu
*iommu
;
1821 struct pci_dev
*pdev
;
1824 if (dev
->bus
!= &pci_bus_type
)
1827 pdev
= to_pci_dev(dev
);
1829 devid
= calc_devid(pdev
->bus
->number
, pdev
->devfn
);
1831 if (devid
>= amd_iommu_last_bdf
||
1832 devid
!= amd_iommu_alias_table
[devid
])
1835 iommu
= amd_iommu_rlookup_table
[devid
];
1839 old_domain
= domain_for_device(devid
);
1843 attach_device(iommu
, domain
, devid
);
1845 iommu_completion_wait(iommu
);
1850 static int amd_iommu_map_range(struct iommu_domain
*dom
,
1851 unsigned long iova
, phys_addr_t paddr
,
1852 size_t size
, int iommu_prot
)
1854 struct protection_domain
*domain
= dom
->priv
;
1855 unsigned long i
, npages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
1859 if (iommu_prot
& IOMMU_READ
)
1860 prot
|= IOMMU_PROT_IR
;
1861 if (iommu_prot
& IOMMU_WRITE
)
1862 prot
|= IOMMU_PROT_IW
;
1867 for (i
= 0; i
< npages
; ++i
) {
1868 ret
= iommu_map_page(domain
, iova
, paddr
, prot
);
1879 static void amd_iommu_unmap_range(struct iommu_domain
*dom
,
1880 unsigned long iova
, size_t size
)
1883 struct protection_domain
*domain
= dom
->priv
;
1884 unsigned long i
, npages
= iommu_num_pages(iova
, size
, PAGE_SIZE
);
1888 for (i
= 0; i
< npages
; ++i
) {
1889 iommu_unmap_page(domain
, iova
);
1893 iommu_flush_domain(domain
->id
);
1896 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
1899 struct protection_domain
*domain
= dom
->priv
;
1900 unsigned long offset
= iova
& ~PAGE_MASK
;
1904 pte
= &domain
->pt_root
[IOMMU_PTE_L2_INDEX(iova
)];
1906 if (!IOMMU_PTE_PRESENT(*pte
))
1909 pte
= IOMMU_PTE_PAGE(*pte
);
1910 pte
= &pte
[IOMMU_PTE_L1_INDEX(iova
)];
1912 if (!IOMMU_PTE_PRESENT(*pte
))
1915 pte
= IOMMU_PTE_PAGE(*pte
);
1916 pte
= &pte
[IOMMU_PTE_L0_INDEX(iova
)];
1918 if (!IOMMU_PTE_PRESENT(*pte
))
1921 paddr
= *pte
& IOMMU_PAGE_MASK
;
1927 static int amd_iommu_domain_has_cap(struct iommu_domain
*domain
,
1933 static struct iommu_ops amd_iommu_ops
= {
1934 .domain_init
= amd_iommu_domain_init
,
1935 .domain_destroy
= amd_iommu_domain_destroy
,
1936 .attach_dev
= amd_iommu_attach_device
,
1937 .detach_dev
= amd_iommu_detach_device
,
1938 .map
= amd_iommu_map_range
,
1939 .unmap
= amd_iommu_unmap_range
,
1940 .iova_to_phys
= amd_iommu_iova_to_phys
,
1941 .domain_has_cap
= amd_iommu_domain_has_cap
,