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hwmon: Kconfig dependency cleanups
[linux-2.6/btrfs-unstable.git] / drivers / net / skge.c
blobe3d8520209b85e1bc5e3bccd60e58c1b1d03b0aa
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/in.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
35 #include <linux/ip.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/mii.h>
40 #include <asm/irq.h>
41
42 #include "skge.h"
43
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.11"
46 #define PFX DRV_NAME " "
47
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
52 #define MAX_RX_RING_SIZE 4096
53 #define RX_COPY_THRESHOLD 128
54 #define RX_BUF_SIZE 1536
55 #define PHY_RETRIES 1000
56 #define ETH_JUMBO_MTU 9000
57 #define TX_WATCHDOG (5 * HZ)
58 #define NAPI_WEIGHT 64
59 #define BLINK_MS 250
60 #define LINK_HZ (HZ/2)
61
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
66
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
87 { 0 }
88 };
89 MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91 static int skge_up(struct net_device *dev);
92 static int skge_down(struct net_device *dev);
93 static void skge_phy_reset(struct skge_port *skge);
94 static void skge_tx_clean(struct net_device *dev);
95 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static void genesis_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_init(struct skge_hw *hw, int port);
100 static void genesis_mac_init(struct skge_hw *hw, int port);
101 static void genesis_link_up(struct skge_port *skge);
102
103 /* Avoid conditionals by using array */
104 static const int txqaddr[] = { Q_XA1, Q_XA2 };
105 static const int rxqaddr[] = { Q_R1, Q_R2 };
106 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
108 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
109 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
110
111 static int skge_get_regs_len(struct net_device *dev)
112 {
113 return 0x4000;
114 }
115
116 /*
117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
119 * cause bus hangs!
120 */
121 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
122 void *p)
123 {
124 const struct skge_port *skge = netdev_priv(dev);
125 const void __iomem *io = skge->hw->regs;
126
127 regs->version = 1;
128 memset(p, 0, regs->len);
129 memcpy_fromio(p, io, B3_RAM_ADDR);
130
131 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
132 regs->len - B3_RI_WTO_R1);
133 }
134
135 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
136 static u32 wol_supported(const struct skge_hw *hw)
137 {
138 if (hw->chip_id == CHIP_ID_GENESIS)
139 return 0;
140
141 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
142 return 0;
143
144 return WAKE_MAGIC | WAKE_PHY;
145 }
146
147 static u32 pci_wake_enabled(struct pci_dev *dev)
148 {
149 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
150 u16 value;
151
152 /* If device doesn't support PM Capabilities, but request is to disable
153 * wake events, it's a nop; otherwise fail */
154 if (!pm)
155 return 0;
156
157 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
158
159 value &= PCI_PM_CAP_PME_MASK;
160 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
161
162 return value != 0;
163 }
164
165 static void skge_wol_init(struct skge_port *skge)
166 {
167 struct skge_hw *hw = skge->hw;
168 int port = skge->port;
169 u16 ctrl;
170
171 skge_write16(hw, B0_CTST, CS_RST_CLR);
172 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
173
174 /* Turn on Vaux */
175 skge_write8(hw, B0_POWER_CTRL,
176 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
177
178 /* WA code for COMA mode -- clear PHY reset */
179 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
180 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
181 u32 reg = skge_read32(hw, B2_GP_IO);
182 reg |= GP_DIR_9;
183 reg &= ~GP_IO_9;
184 skge_write32(hw, B2_GP_IO, reg);
185 }
186
187 skge_write32(hw, SK_REG(port, GPHY_CTRL),
188 GPC_DIS_SLEEP |
189 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
190 GPC_ANEG_1 | GPC_RST_SET);
191
192 skge_write32(hw, SK_REG(port, GPHY_CTRL),
193 GPC_DIS_SLEEP |
194 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
195 GPC_ANEG_1 | GPC_RST_CLR);
196
197 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
198
199 /* Force to 10/100 skge_reset will re-enable on resume */
200 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
201 PHY_AN_100FULL | PHY_AN_100HALF |
202 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
203 /* no 1000 HD/FD */
204 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
205 gm_phy_write(hw, port, PHY_MARV_CTRL,
206 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
207 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
208
209
210 /* Set GMAC to no flow control and auto update for speed/duplex */
211 gma_write16(hw, port, GM_GP_CTRL,
212 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
213 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
214
215 /* Set WOL address */
216 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
217 skge->netdev->dev_addr, ETH_ALEN);
218
219 /* Turn on appropriate WOL control bits */
220 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
221 ctrl = 0;
222 if (skge->wol & WAKE_PHY)
223 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
224 else
225 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
226
227 if (skge->wol & WAKE_MAGIC)
228 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
229 else
230 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
231
232 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
233 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
234
235 /* block receiver */
236 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
237 }
238
239 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
240 {
241 struct skge_port *skge = netdev_priv(dev);
242
243 wol->supported = wol_supported(skge->hw);
244 wol->wolopts = skge->wol;
245 }
246
247 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
248 {
249 struct skge_port *skge = netdev_priv(dev);
250 struct skge_hw *hw = skge->hw;
251
252 if (wol->wolopts & ~wol_supported(hw))
253 return -EOPNOTSUPP;
254
255 skge->wol = wol->wolopts;
256 return 0;
257 }
258
259 /* Determine supported/advertised modes based on hardware.
260 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
261 */
262 static u32 skge_supported_modes(const struct skge_hw *hw)
263 {
264 u32 supported;
265
266 if (hw->copper) {
267 supported = SUPPORTED_10baseT_Half
268 | SUPPORTED_10baseT_Full
269 | SUPPORTED_100baseT_Half
270 | SUPPORTED_100baseT_Full
271 | SUPPORTED_1000baseT_Half
272 | SUPPORTED_1000baseT_Full
273 | SUPPORTED_Autoneg| SUPPORTED_TP;
274
275 if (hw->chip_id == CHIP_ID_GENESIS)
276 supported &= ~(SUPPORTED_10baseT_Half
277 | SUPPORTED_10baseT_Full
278 | SUPPORTED_100baseT_Half
279 | SUPPORTED_100baseT_Full);
280
281 else if (hw->chip_id == CHIP_ID_YUKON)
282 supported &= ~SUPPORTED_1000baseT_Half;
283 } else
284 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
285 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
286
287 return supported;
288 }
289
290 static int skge_get_settings(struct net_device *dev,
291 struct ethtool_cmd *ecmd)
292 {
293 struct skge_port *skge = netdev_priv(dev);
294 struct skge_hw *hw = skge->hw;
295
296 ecmd->transceiver = XCVR_INTERNAL;
297 ecmd->supported = skge_supported_modes(hw);
298
299 if (hw->copper) {
300 ecmd->port = PORT_TP;
301 ecmd->phy_address = hw->phy_addr;
302 } else
303 ecmd->port = PORT_FIBRE;
304
305 ecmd->advertising = skge->advertising;
306 ecmd->autoneg = skge->autoneg;
307 ecmd->speed = skge->speed;
308 ecmd->duplex = skge->duplex;
309 return 0;
310 }
311
312 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
313 {
314 struct skge_port *skge = netdev_priv(dev);
315 const struct skge_hw *hw = skge->hw;
316 u32 supported = skge_supported_modes(hw);
317
318 if (ecmd->autoneg == AUTONEG_ENABLE) {
319 ecmd->advertising = supported;
320 skge->duplex = -1;
321 skge->speed = -1;
322 } else {
323 u32 setting;
324
325 switch (ecmd->speed) {
326 case SPEED_1000:
327 if (ecmd->duplex == DUPLEX_FULL)
328 setting = SUPPORTED_1000baseT_Full;
329 else if (ecmd->duplex == DUPLEX_HALF)
330 setting = SUPPORTED_1000baseT_Half;
331 else
332 return -EINVAL;
333 break;
334 case SPEED_100:
335 if (ecmd->duplex == DUPLEX_FULL)
336 setting = SUPPORTED_100baseT_Full;
337 else if (ecmd->duplex == DUPLEX_HALF)
338 setting = SUPPORTED_100baseT_Half;
339 else
340 return -EINVAL;
341 break;
342
343 case SPEED_10:
344 if (ecmd->duplex == DUPLEX_FULL)
345 setting = SUPPORTED_10baseT_Full;
346 else if (ecmd->duplex == DUPLEX_HALF)
347 setting = SUPPORTED_10baseT_Half;
348 else
349 return -EINVAL;
350 break;
351 default:
352 return -EINVAL;
353 }
354
355 if ((setting & supported) == 0)
356 return -EINVAL;
357
358 skge->speed = ecmd->speed;
359 skge->duplex = ecmd->duplex;
360 }
361
362 skge->autoneg = ecmd->autoneg;
363 skge->advertising = ecmd->advertising;
364
365 if (netif_running(dev))
366 skge_phy_reset(skge);
367
368 return (0);
369 }
370
371 static void skge_get_drvinfo(struct net_device *dev,
372 struct ethtool_drvinfo *info)
373 {
374 struct skge_port *skge = netdev_priv(dev);
375
376 strcpy(info->driver, DRV_NAME);
377 strcpy(info->version, DRV_VERSION);
378 strcpy(info->fw_version, "N/A");
379 strcpy(info->bus_info, pci_name(skge->hw->pdev));
380 }
381
382 static const struct skge_stat {
383 char name[ETH_GSTRING_LEN];
384 u16 xmac_offset;
385 u16 gma_offset;
386 } skge_stats[] = {
387 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
388 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
389
390 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
391 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
392 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
393 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
394 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
395 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
396 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
397 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
398
399 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
400 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
401 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
402 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
403 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
404 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
405
406 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
407 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
408 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
409 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
410 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
411 };
412
413 static int skge_get_stats_count(struct net_device *dev)
414 {
415 return ARRAY_SIZE(skge_stats);
416 }
417
418 static void skge_get_ethtool_stats(struct net_device *dev,
419 struct ethtool_stats *stats, u64 *data)
420 {
421 struct skge_port *skge = netdev_priv(dev);
422
423 if (skge->hw->chip_id == CHIP_ID_GENESIS)
424 genesis_get_stats(skge, data);
425 else
426 yukon_get_stats(skge, data);
427 }
428
429 /* Use hardware MIB variables for critical path statistics and
430 * transmit feedback not reported at interrupt.
431 * Other errors are accounted for in interrupt handler.
432 */
433 static struct net_device_stats *skge_get_stats(struct net_device *dev)
434 {
435 struct skge_port *skge = netdev_priv(dev);
436 u64 data[ARRAY_SIZE(skge_stats)];
437
438 if (skge->hw->chip_id == CHIP_ID_GENESIS)
439 genesis_get_stats(skge, data);
440 else
441 yukon_get_stats(skge, data);
442
443 skge->net_stats.tx_bytes = data[0];
444 skge->net_stats.rx_bytes = data[1];
445 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
446 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
447 skge->net_stats.multicast = data[3] + data[5];
448 skge->net_stats.collisions = data[10];
449 skge->net_stats.tx_aborted_errors = data[12];
450
451 return &skge->net_stats;
452 }
453
454 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
455 {
456 int i;
457
458 switch (stringset) {
459 case ETH_SS_STATS:
460 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
461 memcpy(data + i * ETH_GSTRING_LEN,
462 skge_stats[i].name, ETH_GSTRING_LEN);
463 break;
464 }
465 }
466
467 static void skge_get_ring_param(struct net_device *dev,
468 struct ethtool_ringparam *p)
469 {
470 struct skge_port *skge = netdev_priv(dev);
471
472 p->rx_max_pending = MAX_RX_RING_SIZE;
473 p->tx_max_pending = MAX_TX_RING_SIZE;
474 p->rx_mini_max_pending = 0;
475 p->rx_jumbo_max_pending = 0;
476
477 p->rx_pending = skge->rx_ring.count;
478 p->tx_pending = skge->tx_ring.count;
479 p->rx_mini_pending = 0;
480 p->rx_jumbo_pending = 0;
481 }
482
483 static int skge_set_ring_param(struct net_device *dev,
484 struct ethtool_ringparam *p)
485 {
486 struct skge_port *skge = netdev_priv(dev);
487 int err;
488
489 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
490 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
491 return -EINVAL;
492
493 skge->rx_ring.count = p->rx_pending;
494 skge->tx_ring.count = p->tx_pending;
495
496 if (netif_running(dev)) {
497 skge_down(dev);
498 err = skge_up(dev);
499 if (err)
500 dev_close(dev);
501 }
502
503 return 0;
504 }
505
506 static u32 skge_get_msglevel(struct net_device *netdev)
507 {
508 struct skge_port *skge = netdev_priv(netdev);
509 return skge->msg_enable;
510 }
511
512 static void skge_set_msglevel(struct net_device *netdev, u32 value)
513 {
514 struct skge_port *skge = netdev_priv(netdev);
515 skge->msg_enable = value;
516 }
517
518 static int skge_nway_reset(struct net_device *dev)
519 {
520 struct skge_port *skge = netdev_priv(dev);
521
522 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
523 return -EINVAL;
524
525 skge_phy_reset(skge);
526 return 0;
527 }
528
529 static int skge_set_sg(struct net_device *dev, u32 data)
530 {
531 struct skge_port *skge = netdev_priv(dev);
532 struct skge_hw *hw = skge->hw;
533
534 if (hw->chip_id == CHIP_ID_GENESIS && data)
535 return -EOPNOTSUPP;
536 return ethtool_op_set_sg(dev, data);
537 }
538
539 static int skge_set_tx_csum(struct net_device *dev, u32 data)
540 {
541 struct skge_port *skge = netdev_priv(dev);
542 struct skge_hw *hw = skge->hw;
543
544 if (hw->chip_id == CHIP_ID_GENESIS && data)
545 return -EOPNOTSUPP;
546
547 return ethtool_op_set_tx_csum(dev, data);
548 }
549
550 static u32 skge_get_rx_csum(struct net_device *dev)
551 {
552 struct skge_port *skge = netdev_priv(dev);
553
554 return skge->rx_csum;
555 }
556
557 /* Only Yukon supports checksum offload. */
558 static int skge_set_rx_csum(struct net_device *dev, u32 data)
559 {
560 struct skge_port *skge = netdev_priv(dev);
561
562 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
563 return -EOPNOTSUPP;
564
565 skge->rx_csum = data;
566 return 0;
567 }
568
569 static void skge_get_pauseparam(struct net_device *dev,
570 struct ethtool_pauseparam *ecmd)
571 {
572 struct skge_port *skge = netdev_priv(dev);
573
574 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
575 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
576 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
577
578 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
579 }
580
581 static int skge_set_pauseparam(struct net_device *dev,
582 struct ethtool_pauseparam *ecmd)
583 {
584 struct skge_port *skge = netdev_priv(dev);
585 struct ethtool_pauseparam old;
586
587 skge_get_pauseparam(dev, &old);
588
589 if (ecmd->autoneg != old.autoneg)
590 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
591 else {
592 if (ecmd->rx_pause && ecmd->tx_pause)
593 skge->flow_control = FLOW_MODE_SYMMETRIC;
594 else if (ecmd->rx_pause && !ecmd->tx_pause)
595 skge->flow_control = FLOW_MODE_SYM_OR_REM;
596 else if (!ecmd->rx_pause && ecmd->tx_pause)
597 skge->flow_control = FLOW_MODE_LOC_SEND;
598 else
599 skge->flow_control = FLOW_MODE_NONE;
600 }
601
602 if (netif_running(dev))
603 skge_phy_reset(skge);
604
605 return 0;
606 }
607
608 /* Chip internal frequency for clock calculations */
609 static inline u32 hwkhz(const struct skge_hw *hw)
610 {
611 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
612 }
613
614 /* Chip HZ to microseconds */
615 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
616 {
617 return (ticks * 1000) / hwkhz(hw);
618 }
619
620 /* Microseconds to chip HZ */
621 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
622 {
623 return hwkhz(hw) * usec / 1000;
624 }
625
626 static int skge_get_coalesce(struct net_device *dev,
627 struct ethtool_coalesce *ecmd)
628 {
629 struct skge_port *skge = netdev_priv(dev);
630 struct skge_hw *hw = skge->hw;
631 int port = skge->port;
632
633 ecmd->rx_coalesce_usecs = 0;
634 ecmd->tx_coalesce_usecs = 0;
635
636 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
637 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
638 u32 msk = skge_read32(hw, B2_IRQM_MSK);
639
640 if (msk & rxirqmask[port])
641 ecmd->rx_coalesce_usecs = delay;
642 if (msk & txirqmask[port])
643 ecmd->tx_coalesce_usecs = delay;
644 }
645
646 return 0;
647 }
648
649 /* Note: interrupt timer is per board, but can turn on/off per port */
650 static int skge_set_coalesce(struct net_device *dev,
651 struct ethtool_coalesce *ecmd)
652 {
653 struct skge_port *skge = netdev_priv(dev);
654 struct skge_hw *hw = skge->hw;
655 int port = skge->port;
656 u32 msk = skge_read32(hw, B2_IRQM_MSK);
657 u32 delay = 25;
658
659 if (ecmd->rx_coalesce_usecs == 0)
660 msk &= ~rxirqmask[port];
661 else if (ecmd->rx_coalesce_usecs < 25 ||
662 ecmd->rx_coalesce_usecs > 33333)
663 return -EINVAL;
664 else {
665 msk |= rxirqmask[port];
666 delay = ecmd->rx_coalesce_usecs;
667 }
668
669 if (ecmd->tx_coalesce_usecs == 0)
670 msk &= ~txirqmask[port];
671 else if (ecmd->tx_coalesce_usecs < 25 ||
672 ecmd->tx_coalesce_usecs > 33333)
673 return -EINVAL;
674 else {
675 msk |= txirqmask[port];
676 delay = min(delay, ecmd->rx_coalesce_usecs);
677 }
678
679 skge_write32(hw, B2_IRQM_MSK, msk);
680 if (msk == 0)
681 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
682 else {
683 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
684 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
685 }
686 return 0;
687 }
688
689 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
690 static void skge_led(struct skge_port *skge, enum led_mode mode)
691 {
692 struct skge_hw *hw = skge->hw;
693 int port = skge->port;
694
695 spin_lock_bh(&hw->phy_lock);
696 if (hw->chip_id == CHIP_ID_GENESIS) {
697 switch (mode) {
698 case LED_MODE_OFF:
699 if (hw->phy_type == SK_PHY_BCOM)
700 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
701 else {
702 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
703 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
704 }
705 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
706 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
707 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
708 break;
709
710 case LED_MODE_ON:
711 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
712 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
713
714 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
715 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
716
717 break;
718
719 case LED_MODE_TST:
720 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
721 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
722 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
723
724 if (hw->phy_type == SK_PHY_BCOM)
725 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
726 else {
727 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
728 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
729 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
730 }
731
732 }
733 } else {
734 switch (mode) {
735 case LED_MODE_OFF:
736 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
737 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
738 PHY_M_LED_MO_DUP(MO_LED_OFF) |
739 PHY_M_LED_MO_10(MO_LED_OFF) |
740 PHY_M_LED_MO_100(MO_LED_OFF) |
741 PHY_M_LED_MO_1000(MO_LED_OFF) |
742 PHY_M_LED_MO_RX(MO_LED_OFF));
743 break;
744 case LED_MODE_ON:
745 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
746 PHY_M_LED_PULS_DUR(PULS_170MS) |
747 PHY_M_LED_BLINK_RT(BLINK_84MS) |
748 PHY_M_LEDC_TX_CTRL |
749 PHY_M_LEDC_DP_CTRL);
750
751 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
752 PHY_M_LED_MO_RX(MO_LED_OFF) |
753 (skge->speed == SPEED_100 ?
754 PHY_M_LED_MO_100(MO_LED_ON) : 0));
755 break;
756 case LED_MODE_TST:
757 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
758 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
759 PHY_M_LED_MO_DUP(MO_LED_ON) |
760 PHY_M_LED_MO_10(MO_LED_ON) |
761 PHY_M_LED_MO_100(MO_LED_ON) |
762 PHY_M_LED_MO_1000(MO_LED_ON) |
763 PHY_M_LED_MO_RX(MO_LED_ON));
764 }
765 }
766 spin_unlock_bh(&hw->phy_lock);
767 }
768
769 /* blink LED's for finding board */
770 static int skge_phys_id(struct net_device *dev, u32 data)
771 {
772 struct skge_port *skge = netdev_priv(dev);
773 unsigned long ms;
774 enum led_mode mode = LED_MODE_TST;
775
776 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
777 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
778 else
779 ms = data * 1000;
780
781 while (ms > 0) {
782 skge_led(skge, mode);
783 mode ^= LED_MODE_TST;
784
785 if (msleep_interruptible(BLINK_MS))
786 break;
787 ms -= BLINK_MS;
788 }
789
790 /* back to regular LED state */
791 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
792
793 return 0;
794 }
795
796 static const struct ethtool_ops skge_ethtool_ops = {
797 .get_settings = skge_get_settings,
798 .set_settings = skge_set_settings,
799 .get_drvinfo = skge_get_drvinfo,
800 .get_regs_len = skge_get_regs_len,
801 .get_regs = skge_get_regs,
802 .get_wol = skge_get_wol,
803 .set_wol = skge_set_wol,
804 .get_msglevel = skge_get_msglevel,
805 .set_msglevel = skge_set_msglevel,
806 .nway_reset = skge_nway_reset,
807 .get_link = ethtool_op_get_link,
808 .get_ringparam = skge_get_ring_param,
809 .set_ringparam = skge_set_ring_param,
810 .get_pauseparam = skge_get_pauseparam,
811 .set_pauseparam = skge_set_pauseparam,
812 .get_coalesce = skge_get_coalesce,
813 .set_coalesce = skge_set_coalesce,
814 .get_sg = ethtool_op_get_sg,
815 .set_sg = skge_set_sg,
816 .get_tx_csum = ethtool_op_get_tx_csum,
817 .set_tx_csum = skge_set_tx_csum,
818 .get_rx_csum = skge_get_rx_csum,
819 .set_rx_csum = skge_set_rx_csum,
820 .get_strings = skge_get_strings,
821 .phys_id = skge_phys_id,
822 .get_stats_count = skge_get_stats_count,
823 .get_ethtool_stats = skge_get_ethtool_stats,
824 };
825
826 /*
827 * Allocate ring elements and chain them together
828 * One-to-one association of board descriptors with ring elements
829 */
830 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
831 {
832 struct skge_tx_desc *d;
833 struct skge_element *e;
834 int i;
835
836 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
837 if (!ring->start)
838 return -ENOMEM;
839
840 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
841 e->desc = d;
842 if (i == ring->count - 1) {
843 e->next = ring->start;
844 d->next_offset = base;
845 } else {
846 e->next = e + 1;
847 d->next_offset = base + (i+1) * sizeof(*d);
848 }
849 }
850 ring->to_use = ring->to_clean = ring->start;
851
852 return 0;
853 }
854
855 /* Allocate and setup a new buffer for receiving */
856 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
857 struct sk_buff *skb, unsigned int bufsize)
858 {
859 struct skge_rx_desc *rd = e->desc;
860 u64 map;
861
862 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
863 PCI_DMA_FROMDEVICE);
864
865 rd->dma_lo = map;
866 rd->dma_hi = map >> 32;
867 e->skb = skb;
868 rd->csum1_start = ETH_HLEN;
869 rd->csum2_start = ETH_HLEN;
870 rd->csum1 = 0;
871 rd->csum2 = 0;
872
873 wmb();
874
875 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
876 pci_unmap_addr_set(e, mapaddr, map);
877 pci_unmap_len_set(e, maplen, bufsize);
878 }
879
880 /* Resume receiving using existing skb,
881 * Note: DMA address is not changed by chip.
882 * MTU not changed while receiver active.
883 */
884 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
885 {
886 struct skge_rx_desc *rd = e->desc;
887
888 rd->csum2 = 0;
889 rd->csum2_start = ETH_HLEN;
890
891 wmb();
892
893 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
894 }
895
896
897 /* Free all buffers in receive ring, assumes receiver stopped */
898 static void skge_rx_clean(struct skge_port *skge)
899 {
900 struct skge_hw *hw = skge->hw;
901 struct skge_ring *ring = &skge->rx_ring;
902 struct skge_element *e;
903
904 e = ring->start;
905 do {
906 struct skge_rx_desc *rd = e->desc;
907 rd->control = 0;
908 if (e->skb) {
909 pci_unmap_single(hw->pdev,
910 pci_unmap_addr(e, mapaddr),
911 pci_unmap_len(e, maplen),
912 PCI_DMA_FROMDEVICE);
913 dev_kfree_skb(e->skb);
914 e->skb = NULL;
915 }
916 } while ((e = e->next) != ring->start);
917 }
918
919
920 /* Allocate buffers for receive ring
921 * For receive: to_clean is next received frame.
922 */
923 static int skge_rx_fill(struct net_device *dev)
924 {
925 struct skge_port *skge = netdev_priv(dev);
926 struct skge_ring *ring = &skge->rx_ring;
927 struct skge_element *e;
928
929 e = ring->start;
930 do {
931 struct sk_buff *skb;
932
933 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
934 GFP_KERNEL);
935 if (!skb)
936 return -ENOMEM;
937
938 skb_reserve(skb, NET_IP_ALIGN);
939 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
940 } while ( (e = e->next) != ring->start);
941
942 ring->to_clean = ring->start;
943 return 0;
944 }
945
946 static const char *skge_pause(enum pause_status status)
947 {
948 switch(status) {
949 case FLOW_STAT_NONE:
950 return "none";
951 case FLOW_STAT_REM_SEND:
952 return "rx only";
953 case FLOW_STAT_LOC_SEND:
954 return "tx_only";
955 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
956 return "both";
957 default:
958 return "indeterminated";
959 }
960 }
961
962
963 static void skge_link_up(struct skge_port *skge)
964 {
965 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
966 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
967
968 netif_carrier_on(skge->netdev);
969 netif_wake_queue(skge->netdev);
970
971 if (netif_msg_link(skge)) {
972 printk(KERN_INFO PFX
973 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
974 skge->netdev->name, skge->speed,
975 skge->duplex == DUPLEX_FULL ? "full" : "half",
976 skge_pause(skge->flow_status));
977 }
978 }
979
980 static void skge_link_down(struct skge_port *skge)
981 {
982 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
983 netif_carrier_off(skge->netdev);
984 netif_stop_queue(skge->netdev);
985
986 if (netif_msg_link(skge))
987 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
988 }
989
990
991 static void xm_link_down(struct skge_hw *hw, int port)
992 {
993 struct net_device *dev = hw->dev[port];
994 struct skge_port *skge = netdev_priv(dev);
995 u16 cmd, msk;
996
997 if (hw->phy_type == SK_PHY_XMAC) {
998 msk = xm_read16(hw, port, XM_IMSK);
999 msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
1000 xm_write16(hw, port, XM_IMSK, msk);
1001 }
1002
1003 cmd = xm_read16(hw, port, XM_MMU_CMD);
1004 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1005 xm_write16(hw, port, XM_MMU_CMD, cmd);
1006 /* dummy read to ensure writing */
1007 (void) xm_read16(hw, port, XM_MMU_CMD);
1008
1009 if (netif_carrier_ok(dev))
1010 skge_link_down(skge);
1011 }
1012
1013 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1014 {
1015 int i;
1016
1017 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1018 *val = xm_read16(hw, port, XM_PHY_DATA);
1019
1020 if (hw->phy_type == SK_PHY_XMAC)
1021 goto ready;
1022
1023 for (i = 0; i < PHY_RETRIES; i++) {
1024 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1025 goto ready;
1026 udelay(1);
1027 }
1028
1029 return -ETIMEDOUT;
1030 ready:
1031 *val = xm_read16(hw, port, XM_PHY_DATA);
1032
1033 return 0;
1034 }
1035
1036 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1037 {
1038 u16 v = 0;
1039 if (__xm_phy_read(hw, port, reg, &v))
1040 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1041 hw->dev[port]->name);
1042 return v;
1043 }
1044
1045 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1046 {
1047 int i;
1048
1049 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1050 for (i = 0; i < PHY_RETRIES; i++) {
1051 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1052 goto ready;
1053 udelay(1);
1054 }
1055 return -EIO;
1056
1057 ready:
1058 xm_write16(hw, port, XM_PHY_DATA, val);
1059 for (i = 0; i < PHY_RETRIES; i++) {
1060 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1061 return 0;
1062 udelay(1);
1063 }
1064 return -ETIMEDOUT;
1065 }
1066
1067 static void genesis_init(struct skge_hw *hw)
1068 {
1069 /* set blink source counter */
1070 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1071 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1072
1073 /* configure mac arbiter */
1074 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1075
1076 /* configure mac arbiter timeout values */
1077 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1078 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1079 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1080 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1081
1082 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1083 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1084 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1085 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1086
1087 /* configure packet arbiter timeout */
1088 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1089 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1090 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1091 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1092 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1093 }
1094
1095 static void genesis_reset(struct skge_hw *hw, int port)
1096 {
1097 const u8 zero[8] = { 0 };
1098
1099 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1100
1101 /* reset the statistics module */
1102 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1103 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1104 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1105 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1106 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1107
1108 /* disable Broadcom PHY IRQ */
1109 if (hw->phy_type == SK_PHY_BCOM)
1110 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1111
1112 xm_outhash(hw, port, XM_HSM, zero);
1113 }
1114
1115
1116 /* Convert mode to MII values */
1117 static const u16 phy_pause_map[] = {
1118 [FLOW_MODE_NONE] = 0,
1119 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1120 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1121 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1122 };
1123
1124 /* special defines for FIBER (88E1011S only) */
1125 static const u16 fiber_pause_map[] = {
1126 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1127 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1128 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1129 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1130 };
1131
1132
1133 /* Check status of Broadcom phy link */
1134 static void bcom_check_link(struct skge_hw *hw, int port)
1135 {
1136 struct net_device *dev = hw->dev[port];
1137 struct skge_port *skge = netdev_priv(dev);
1138 u16 status;
1139
1140 /* read twice because of latch */
1141 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1142 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1143
1144 if ((status & PHY_ST_LSYNC) == 0) {
1145 xm_link_down(hw, port);
1146 return;
1147 }
1148
1149 if (skge->autoneg == AUTONEG_ENABLE) {
1150 u16 lpa, aux;
1151
1152 if (!(status & PHY_ST_AN_OVER))
1153 return;
1154
1155 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1156 if (lpa & PHY_B_AN_RF) {
1157 printk(KERN_NOTICE PFX "%s: remote fault\n",
1158 dev->name);
1159 return;
1160 }
1161
1162 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1163
1164 /* Check Duplex mismatch */
1165 switch (aux & PHY_B_AS_AN_RES_MSK) {
1166 case PHY_B_RES_1000FD:
1167 skge->duplex = DUPLEX_FULL;
1168 break;
1169 case PHY_B_RES_1000HD:
1170 skge->duplex = DUPLEX_HALF;
1171 break;
1172 default:
1173 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1174 dev->name);
1175 return;
1176 }
1177
1178 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1179 switch (aux & PHY_B_AS_PAUSE_MSK) {
1180 case PHY_B_AS_PAUSE_MSK:
1181 skge->flow_status = FLOW_STAT_SYMMETRIC;
1182 break;
1183 case PHY_B_AS_PRR:
1184 skge->flow_status = FLOW_STAT_REM_SEND;
1185 break;
1186 case PHY_B_AS_PRT:
1187 skge->flow_status = FLOW_STAT_LOC_SEND;
1188 break;
1189 default:
1190 skge->flow_status = FLOW_STAT_NONE;
1191 }
1192 skge->speed = SPEED_1000;
1193 }
1194
1195 if (!netif_carrier_ok(dev))
1196 genesis_link_up(skge);
1197 }
1198
1199 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1200 * Phy on for 100 or 10Mbit operation
1201 */
1202 static void bcom_phy_init(struct skge_port *skge)
1203 {
1204 struct skge_hw *hw = skge->hw;
1205 int port = skge->port;
1206 int i;
1207 u16 id1, r, ext, ctl;
1208
1209 /* magic workaround patterns for Broadcom */
1210 static const struct {
1211 u16 reg;
1212 u16 val;
1213 } A1hack[] = {
1214 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1215 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1216 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1217 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1218 }, C0hack[] = {
1219 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1220 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1221 };
1222
1223 /* read Id from external PHY (all have the same address) */
1224 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1225
1226 /* Optimize MDIO transfer by suppressing preamble. */
1227 r = xm_read16(hw, port, XM_MMU_CMD);
1228 r |= XM_MMU_NO_PRE;
1229 xm_write16(hw, port, XM_MMU_CMD,r);
1230
1231 switch (id1) {
1232 case PHY_BCOM_ID1_C0:
1233 /*
1234 * Workaround BCOM Errata for the C0 type.
1235 * Write magic patterns to reserved registers.
1236 */
1237 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1238 xm_phy_write(hw, port,
1239 C0hack[i].reg, C0hack[i].val);
1240
1241 break;
1242 case PHY_BCOM_ID1_A1:
1243 /*
1244 * Workaround BCOM Errata for the A1 type.
1245 * Write magic patterns to reserved registers.
1246 */
1247 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1248 xm_phy_write(hw, port,
1249 A1hack[i].reg, A1hack[i].val);
1250 break;
1251 }
1252
1253 /*
1254 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1255 * Disable Power Management after reset.
1256 */
1257 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1258 r |= PHY_B_AC_DIS_PM;
1259 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1260
1261 /* Dummy read */
1262 xm_read16(hw, port, XM_ISRC);
1263
1264 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1265 ctl = PHY_CT_SP1000; /* always 1000mbit */
1266
1267 if (skge->autoneg == AUTONEG_ENABLE) {
1268 /*
1269 * Workaround BCOM Errata #1 for the C5 type.
1270 * 1000Base-T Link Acquisition Failure in Slave Mode
1271 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1272 */
1273 u16 adv = PHY_B_1000C_RD;
1274 if (skge->advertising & ADVERTISED_1000baseT_Half)
1275 adv |= PHY_B_1000C_AHD;
1276 if (skge->advertising & ADVERTISED_1000baseT_Full)
1277 adv |= PHY_B_1000C_AFD;
1278 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1279
1280 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1281 } else {
1282 if (skge->duplex == DUPLEX_FULL)
1283 ctl |= PHY_CT_DUP_MD;
1284 /* Force to slave */
1285 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1286 }
1287
1288 /* Set autonegotiation pause parameters */
1289 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1290 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1291
1292 /* Handle Jumbo frames */
1293 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1294 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1295 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1296
1297 ext |= PHY_B_PEC_HIGH_LA;
1298
1299 }
1300
1301 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1302 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1303
1304 /* Use link status change interrupt */
1305 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1306 }
1307
1308 static void xm_phy_init(struct skge_port *skge)
1309 {
1310 struct skge_hw *hw = skge->hw;
1311 int port = skge->port;
1312 u16 ctrl = 0;
1313
1314 if (skge->autoneg == AUTONEG_ENABLE) {
1315 if (skge->advertising & ADVERTISED_1000baseT_Half)
1316 ctrl |= PHY_X_AN_HD;
1317 if (skge->advertising & ADVERTISED_1000baseT_Full)
1318 ctrl |= PHY_X_AN_FD;
1319
1320 ctrl |= fiber_pause_map[skge->flow_control];
1321
1322 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1323
1324 /* Restart Auto-negotiation */
1325 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1326 } else {
1327 /* Set DuplexMode in Config register */
1328 if (skge->duplex == DUPLEX_FULL)
1329 ctrl |= PHY_CT_DUP_MD;
1330 /*
1331 * Do NOT enable Auto-negotiation here. This would hold
1332 * the link down because no IDLEs are transmitted
1333 */
1334 }
1335
1336 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1337
1338 /* Poll PHY for status changes */
1339 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1340 }
1341
1342 static void xm_check_link(struct net_device *dev)
1343 {
1344 struct skge_port *skge = netdev_priv(dev);
1345 struct skge_hw *hw = skge->hw;
1346 int port = skge->port;
1347 u16 status;
1348
1349 /* read twice because of latch */
1350 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1351 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1352
1353 if ((status & PHY_ST_LSYNC) == 0) {
1354 xm_link_down(hw, port);
1355 return;
1356 }
1357
1358 if (skge->autoneg == AUTONEG_ENABLE) {
1359 u16 lpa, res;
1360
1361 if (!(status & PHY_ST_AN_OVER))
1362 return;
1363
1364 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1365 if (lpa & PHY_B_AN_RF) {
1366 printk(KERN_NOTICE PFX "%s: remote fault\n",
1367 dev->name);
1368 return;
1369 }
1370
1371 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1372
1373 /* Check Duplex mismatch */
1374 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1375 case PHY_X_RS_FD:
1376 skge->duplex = DUPLEX_FULL;
1377 break;
1378 case PHY_X_RS_HD:
1379 skge->duplex = DUPLEX_HALF;
1380 break;
1381 default:
1382 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1383 dev->name);
1384 return;
1385 }
1386
1387 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1388 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1389 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1390 (lpa & PHY_X_P_SYM_MD))
1391 skge->flow_status = FLOW_STAT_SYMMETRIC;
1392 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1393 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1394 /* Enable PAUSE receive, disable PAUSE transmit */
1395 skge->flow_status = FLOW_STAT_REM_SEND;
1396 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1397 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1398 /* Disable PAUSE receive, enable PAUSE transmit */
1399 skge->flow_status = FLOW_STAT_LOC_SEND;
1400 else
1401 skge->flow_status = FLOW_STAT_NONE;
1402
1403 skge->speed = SPEED_1000;
1404 }
1405
1406 if (!netif_carrier_ok(dev))
1407 genesis_link_up(skge);
1408 }
1409
1410 /* Poll to check for link coming up.
1411 * Since internal PHY is wired to a level triggered pin, can't
1412 * get an interrupt when carrier is detected.
1413 */
1414 static void xm_link_timer(unsigned long arg)
1415 {
1416 struct skge_port *skge = (struct skge_port *) arg;
1417 struct net_device *dev = skge->netdev;
1418 struct skge_hw *hw = skge->hw;
1419 int port = skge->port;
1420
1421 if (!netif_running(dev))
1422 return;
1423
1424 if (netif_carrier_ok(dev)) {
1425 xm_read16(hw, port, XM_ISRC);
1426 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1427 goto nochange;
1428 } else {
1429 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1430 goto nochange;
1431 xm_read16(hw, port, XM_ISRC);
1432 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1433 goto nochange;
1434 }
1435
1436 spin_lock(&hw->phy_lock);
1437 xm_check_link(dev);
1438 spin_unlock(&hw->phy_lock);
1439
1440 nochange:
1441 if (netif_running(dev))
1442 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1443 }
1444
1445 static void genesis_mac_init(struct skge_hw *hw, int port)
1446 {
1447 struct net_device *dev = hw->dev[port];
1448 struct skge_port *skge = netdev_priv(dev);
1449 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1450 int i;
1451 u32 r;
1452 const u8 zero[6] = { 0 };
1453
1454 for (i = 0; i < 10; i++) {
1455 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1456 MFF_SET_MAC_RST);
1457 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1458 goto reset_ok;
1459 udelay(1);
1460 }
1461
1462 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1463
1464 reset_ok:
1465 /* Unreset the XMAC. */
1466 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1467
1468 /*
1469 * Perform additional initialization for external PHYs,
1470 * namely for the 1000baseTX cards that use the XMAC's
1471 * GMII mode.
1472 */
1473 if (hw->phy_type != SK_PHY_XMAC) {
1474 /* Take external Phy out of reset */
1475 r = skge_read32(hw, B2_GP_IO);
1476 if (port == 0)
1477 r |= GP_DIR_0|GP_IO_0;
1478 else
1479 r |= GP_DIR_2|GP_IO_2;
1480
1481 skge_write32(hw, B2_GP_IO, r);
1482
1483 /* Enable GMII interface */
1484 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1485 }
1486
1487
1488 switch(hw->phy_type) {
1489 case SK_PHY_XMAC:
1490 xm_phy_init(skge);
1491 break;
1492 case SK_PHY_BCOM:
1493 bcom_phy_init(skge);
1494 bcom_check_link(hw, port);
1495 }
1496
1497 /* Set Station Address */
1498 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1499
1500 /* We don't use match addresses so clear */
1501 for (i = 1; i < 16; i++)
1502 xm_outaddr(hw, port, XM_EXM(i), zero);
1503
1504 /* Clear MIB counters */
1505 xm_write16(hw, port, XM_STAT_CMD,
1506 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1507 /* Clear two times according to Errata #3 */
1508 xm_write16(hw, port, XM_STAT_CMD,
1509 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1510
1511 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1512 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1513
1514 /* We don't need the FCS appended to the packet. */
1515 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1516 if (jumbo)
1517 r |= XM_RX_BIG_PK_OK;
1518
1519 if (skge->duplex == DUPLEX_HALF) {
1520 /*
1521 * If in manual half duplex mode the other side might be in
1522 * full duplex mode, so ignore if a carrier extension is not seen
1523 * on frames received
1524 */
1525 r |= XM_RX_DIS_CEXT;
1526 }
1527 xm_write16(hw, port, XM_RX_CMD, r);
1528
1529
1530 /* We want short frames padded to 60 bytes. */
1531 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1532
1533 /*
1534 * Bump up the transmit threshold. This helps hold off transmit
1535 * underruns when we're blasting traffic from both ports at once.
1536 */
1537 xm_write16(hw, port, XM_TX_THR, 512);
1538
1539 /*
1540 * Enable the reception of all error frames. This is is
1541 * a necessary evil due to the design of the XMAC. The
1542 * XMAC's receive FIFO is only 8K in size, however jumbo
1543 * frames can be up to 9000 bytes in length. When bad
1544 * frame filtering is enabled, the XMAC's RX FIFO operates
1545 * in 'store and forward' mode. For this to work, the
1546 * entire frame has to fit into the FIFO, but that means
1547 * that jumbo frames larger than 8192 bytes will be
1548 * truncated. Disabling all bad frame filtering causes
1549 * the RX FIFO to operate in streaming mode, in which
1550 * case the XMAC will start transferring frames out of the
1551 * RX FIFO as soon as the FIFO threshold is reached.
1552 */
1553 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1554
1555
1556 /*
1557 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1558 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1559 * and 'Octets Rx OK Hi Cnt Ov'.
1560 */
1561 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1562
1563 /*
1564 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1565 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1566 * and 'Octets Tx OK Hi Cnt Ov'.
1567 */
1568 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1569
1570 /* Configure MAC arbiter */
1571 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1572
1573 /* configure timeout values */
1574 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1575 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1576 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1577 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1578
1579 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1580 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1581 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1582 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1583
1584 /* Configure Rx MAC FIFO */
1585 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1586 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1587 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1588
1589 /* Configure Tx MAC FIFO */
1590 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1591 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1592 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1593
1594 if (jumbo) {
1595 /* Enable frame flushing if jumbo frames used */
1596 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1597 } else {
1598 /* enable timeout timers if normal frames */
1599 skge_write16(hw, B3_PA_CTRL,
1600 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1601 }
1602 }
1603
1604 static void genesis_stop(struct skge_port *skge)
1605 {
1606 struct skge_hw *hw = skge->hw;
1607 int port = skge->port;
1608 u32 reg;
1609
1610 genesis_reset(hw, port);
1611
1612 /* Clear Tx packet arbiter timeout IRQ */
1613 skge_write16(hw, B3_PA_CTRL,
1614 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1615
1616 /*
1617 * If the transfer sticks at the MAC the STOP command will not
1618 * terminate if we don't flush the XMAC's transmit FIFO !
1619 */
1620 xm_write32(hw, port, XM_MODE,
1621 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1622
1623
1624 /* Reset the MAC */
1625 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1626
1627 /* For external PHYs there must be special handling */
1628 if (hw->phy_type != SK_PHY_XMAC) {
1629 reg = skge_read32(hw, B2_GP_IO);
1630 if (port == 0) {
1631 reg |= GP_DIR_0;
1632 reg &= ~GP_IO_0;
1633 } else {
1634 reg |= GP_DIR_2;
1635 reg &= ~GP_IO_2;
1636 }
1637 skge_write32(hw, B2_GP_IO, reg);
1638 skge_read32(hw, B2_GP_IO);
1639 }
1640
1641 xm_write16(hw, port, XM_MMU_CMD,
1642 xm_read16(hw, port, XM_MMU_CMD)
1643 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1644
1645 xm_read16(hw, port, XM_MMU_CMD);
1646 }
1647
1648
1649 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1650 {
1651 struct skge_hw *hw = skge->hw;
1652 int port = skge->port;
1653 int i;
1654 unsigned long timeout = jiffies + HZ;
1655
1656 xm_write16(hw, port,
1657 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1658
1659 /* wait for update to complete */
1660 while (xm_read16(hw, port, XM_STAT_CMD)
1661 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1662 if (time_after(jiffies, timeout))
1663 break;
1664 udelay(10);
1665 }
1666
1667 /* special case for 64 bit octet counter */
1668 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1669 | xm_read32(hw, port, XM_TXO_OK_LO);
1670 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1671 | xm_read32(hw, port, XM_RXO_OK_LO);
1672
1673 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1674 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1675 }
1676
1677 static void genesis_mac_intr(struct skge_hw *hw, int port)
1678 {
1679 struct skge_port *skge = netdev_priv(hw->dev[port]);
1680 u16 status = xm_read16(hw, port, XM_ISRC);
1681
1682 if (netif_msg_intr(skge))
1683 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1684 skge->netdev->name, status);
1685
1686 if (hw->phy_type == SK_PHY_XMAC &&
1687 (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
1688 xm_link_down(hw, port);
1689
1690 if (status & XM_IS_TXF_UR) {
1691 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1692 ++skge->net_stats.tx_fifo_errors;
1693 }
1694 if (status & XM_IS_RXF_OV) {
1695 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1696 ++skge->net_stats.rx_fifo_errors;
1697 }
1698 }
1699
1700 static void genesis_link_up(struct skge_port *skge)
1701 {
1702 struct skge_hw *hw = skge->hw;
1703 int port = skge->port;
1704 u16 cmd, msk;
1705 u32 mode;
1706
1707 cmd = xm_read16(hw, port, XM_MMU_CMD);
1708
1709 /*
1710 * enabling pause frame reception is required for 1000BT
1711 * because the XMAC is not reset if the link is going down
1712 */
1713 if (skge->flow_status == FLOW_STAT_NONE ||
1714 skge->flow_status == FLOW_STAT_LOC_SEND)
1715 /* Disable Pause Frame Reception */
1716 cmd |= XM_MMU_IGN_PF;
1717 else
1718 /* Enable Pause Frame Reception */
1719 cmd &= ~XM_MMU_IGN_PF;
1720
1721 xm_write16(hw, port, XM_MMU_CMD, cmd);
1722
1723 mode = xm_read32(hw, port, XM_MODE);
1724 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1725 skge->flow_status == FLOW_STAT_LOC_SEND) {
1726 /*
1727 * Configure Pause Frame Generation
1728 * Use internal and external Pause Frame Generation.
1729 * Sending pause frames is edge triggered.
1730 * Send a Pause frame with the maximum pause time if
1731 * internal oder external FIFO full condition occurs.
1732 * Send a zero pause time frame to re-start transmission.
1733 */
1734 /* XM_PAUSE_DA = '010000C28001' (default) */
1735 /* XM_MAC_PTIME = 0xffff (maximum) */
1736 /* remember this value is defined in big endian (!) */
1737 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1738
1739 mode |= XM_PAUSE_MODE;
1740 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1741 } else {
1742 /*
1743 * disable pause frame generation is required for 1000BT
1744 * because the XMAC is not reset if the link is going down
1745 */
1746 /* Disable Pause Mode in Mode Register */
1747 mode &= ~XM_PAUSE_MODE;
1748
1749 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1750 }
1751
1752 xm_write32(hw, port, XM_MODE, mode);
1753 msk = XM_DEF_MSK;
1754 if (hw->phy_type != SK_PHY_XMAC)
1755 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1756
1757 xm_write16(hw, port, XM_IMSK, msk);
1758 xm_read16(hw, port, XM_ISRC);
1759
1760 /* get MMU Command Reg. */
1761 cmd = xm_read16(hw, port, XM_MMU_CMD);
1762 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1763 cmd |= XM_MMU_GMII_FD;
1764
1765 /*
1766 * Workaround BCOM Errata (#10523) for all BCom Phys
1767 * Enable Power Management after link up
1768 */
1769 if (hw->phy_type == SK_PHY_BCOM) {
1770 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1771 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1772 & ~PHY_B_AC_DIS_PM);
1773 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1774 }
1775
1776 /* enable Rx/Tx */
1777 xm_write16(hw, port, XM_MMU_CMD,
1778 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1779 skge_link_up(skge);
1780 }
1781
1782
1783 static inline void bcom_phy_intr(struct skge_port *skge)
1784 {
1785 struct skge_hw *hw = skge->hw;
1786 int port = skge->port;
1787 u16 isrc;
1788
1789 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1790 if (netif_msg_intr(skge))
1791 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1792 skge->netdev->name, isrc);
1793
1794 if (isrc & PHY_B_IS_PSE)
1795 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1796 hw->dev[port]->name);
1797
1798 /* Workaround BCom Errata:
1799 * enable and disable loopback mode if "NO HCD" occurs.
1800 */
1801 if (isrc & PHY_B_IS_NO_HDCL) {
1802 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1803 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1804 ctrl | PHY_CT_LOOP);
1805 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1806 ctrl & ~PHY_CT_LOOP);
1807 }
1808
1809 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1810 bcom_check_link(hw, port);
1811
1812 }
1813
1814 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1815 {
1816 int i;
1817
1818 gma_write16(hw, port, GM_SMI_DATA, val);
1819 gma_write16(hw, port, GM_SMI_CTRL,
1820 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1821 for (i = 0; i < PHY_RETRIES; i++) {
1822 udelay(1);
1823
1824 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1825 return 0;
1826 }
1827
1828 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1829 hw->dev[port]->name);
1830 return -EIO;
1831 }
1832
1833 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1834 {
1835 int i;
1836
1837 gma_write16(hw, port, GM_SMI_CTRL,
1838 GM_SMI_CT_PHY_AD(hw->phy_addr)
1839 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1840
1841 for (i = 0; i < PHY_RETRIES; i++) {
1842 udelay(1);
1843 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1844 goto ready;
1845 }
1846
1847 return -ETIMEDOUT;
1848 ready:
1849 *val = gma_read16(hw, port, GM_SMI_DATA);
1850 return 0;
1851 }
1852
1853 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1854 {
1855 u16 v = 0;
1856 if (__gm_phy_read(hw, port, reg, &v))
1857 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1858 hw->dev[port]->name);
1859 return v;
1860 }
1861
1862 /* Marvell Phy Initialization */
1863 static void yukon_init(struct skge_hw *hw, int port)
1864 {
1865 struct skge_port *skge = netdev_priv(hw->dev[port]);
1866 u16 ctrl, ct1000, adv;
1867
1868 if (skge->autoneg == AUTONEG_ENABLE) {
1869 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1870
1871 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1872 PHY_M_EC_MAC_S_MSK);
1873 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1874
1875 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1876
1877 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1878 }
1879
1880 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1881 if (skge->autoneg == AUTONEG_DISABLE)
1882 ctrl &= ~PHY_CT_ANE;
1883
1884 ctrl |= PHY_CT_RESET;
1885 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1886
1887 ctrl = 0;
1888 ct1000 = 0;
1889 adv = PHY_AN_CSMA;
1890
1891 if (skge->autoneg == AUTONEG_ENABLE) {
1892 if (hw->copper) {
1893 if (skge->advertising & ADVERTISED_1000baseT_Full)
1894 ct1000 |= PHY_M_1000C_AFD;
1895 if (skge->advertising & ADVERTISED_1000baseT_Half)
1896 ct1000 |= PHY_M_1000C_AHD;
1897 if (skge->advertising & ADVERTISED_100baseT_Full)
1898 adv |= PHY_M_AN_100_FD;
1899 if (skge->advertising & ADVERTISED_100baseT_Half)
1900 adv |= PHY_M_AN_100_HD;
1901 if (skge->advertising & ADVERTISED_10baseT_Full)
1902 adv |= PHY_M_AN_10_FD;
1903 if (skge->advertising & ADVERTISED_10baseT_Half)
1904 adv |= PHY_M_AN_10_HD;
1905
1906 /* Set Flow-control capabilities */
1907 adv |= phy_pause_map[skge->flow_control];
1908 } else {
1909 if (skge->advertising & ADVERTISED_1000baseT_Full)
1910 adv |= PHY_M_AN_1000X_AFD;
1911 if (skge->advertising & ADVERTISED_1000baseT_Half)
1912 adv |= PHY_M_AN_1000X_AHD;
1913
1914 adv |= fiber_pause_map[skge->flow_control];
1915 }
1916
1917 /* Restart Auto-negotiation */
1918 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1919 } else {
1920 /* forced speed/duplex settings */
1921 ct1000 = PHY_M_1000C_MSE;
1922
1923 if (skge->duplex == DUPLEX_FULL)
1924 ctrl |= PHY_CT_DUP_MD;
1925
1926 switch (skge->speed) {
1927 case SPEED_1000:
1928 ctrl |= PHY_CT_SP1000;
1929 break;
1930 case SPEED_100:
1931 ctrl |= PHY_CT_SP100;
1932 break;
1933 }
1934
1935 ctrl |= PHY_CT_RESET;
1936 }
1937
1938 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1939
1940 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1941 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1942
1943 /* Enable phy interrupt on autonegotiation complete (or link up) */
1944 if (skge->autoneg == AUTONEG_ENABLE)
1945 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1946 else
1947 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1948 }
1949
1950 static void yukon_reset(struct skge_hw *hw, int port)
1951 {
1952 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1953 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1954 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1955 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1956 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1957
1958 gma_write16(hw, port, GM_RX_CTRL,
1959 gma_read16(hw, port, GM_RX_CTRL)
1960 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1961 }
1962
1963 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1964 static int is_yukon_lite_a0(struct skge_hw *hw)
1965 {
1966 u32 reg;
1967 int ret;
1968
1969 if (hw->chip_id != CHIP_ID_YUKON)
1970 return 0;
1971
1972 reg = skge_read32(hw, B2_FAR);
1973 skge_write8(hw, B2_FAR + 3, 0xff);
1974 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1975 skge_write32(hw, B2_FAR, reg);
1976 return ret;
1977 }
1978
1979 static void yukon_mac_init(struct skge_hw *hw, int port)
1980 {
1981 struct skge_port *skge = netdev_priv(hw->dev[port]);
1982 int i;
1983 u32 reg;
1984 const u8 *addr = hw->dev[port]->dev_addr;
1985
1986 /* WA code for COMA mode -- set PHY reset */
1987 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1988 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1989 reg = skge_read32(hw, B2_GP_IO);
1990 reg |= GP_DIR_9 | GP_IO_9;
1991 skge_write32(hw, B2_GP_IO, reg);
1992 }
1993
1994 /* hard reset */
1995 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1996 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1997
1998 /* WA code for COMA mode -- clear PHY reset */
1999 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2000 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2001 reg = skge_read32(hw, B2_GP_IO);
2002 reg |= GP_DIR_9;
2003 reg &= ~GP_IO_9;
2004 skge_write32(hw, B2_GP_IO, reg);
2005 }
2006
2007 /* Set hardware config mode */
2008 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2009 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2010 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2011
2012 /* Clear GMC reset */
2013 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2014 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2015 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2016
2017 if (skge->autoneg == AUTONEG_DISABLE) {
2018 reg = GM_GPCR_AU_ALL_DIS;
2019 gma_write16(hw, port, GM_GP_CTRL,
2020 gma_read16(hw, port, GM_GP_CTRL) | reg);
2021
2022 switch (skge->speed) {
2023 case SPEED_1000:
2024 reg &= ~GM_GPCR_SPEED_100;
2025 reg |= GM_GPCR_SPEED_1000;
2026 break;
2027 case SPEED_100:
2028 reg &= ~GM_GPCR_SPEED_1000;
2029 reg |= GM_GPCR_SPEED_100;
2030 break;
2031 case SPEED_10:
2032 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2033 break;
2034 }
2035
2036 if (skge->duplex == DUPLEX_FULL)
2037 reg |= GM_GPCR_DUP_FULL;
2038 } else
2039 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2040
2041 switch (skge->flow_control) {
2042 case FLOW_MODE_NONE:
2043 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2044 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2045 break;
2046 case FLOW_MODE_LOC_SEND:
2047 /* disable Rx flow-control */
2048 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2049 break;
2050 case FLOW_MODE_SYMMETRIC:
2051 case FLOW_MODE_SYM_OR_REM:
2052 /* enable Tx & Rx flow-control */
2053 break;
2054 }
2055
2056 gma_write16(hw, port, GM_GP_CTRL, reg);
2057 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2058
2059 yukon_init(hw, port);
2060
2061 /* MIB clear */
2062 reg = gma_read16(hw, port, GM_PHY_ADDR);
2063 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2064
2065 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2066 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2067 gma_write16(hw, port, GM_PHY_ADDR, reg);
2068
2069 /* transmit control */
2070 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2071
2072 /* receive control reg: unicast + multicast + no FCS */
2073 gma_write16(hw, port, GM_RX_CTRL,
2074 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2075
2076 /* transmit flow control */
2077 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2078
2079 /* transmit parameter */
2080 gma_write16(hw, port, GM_TX_PARAM,
2081 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2082 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2083 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2084
2085 /* serial mode register */
2086 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2087 if (hw->dev[port]->mtu > 1500)
2088 reg |= GM_SMOD_JUMBO_ENA;
2089
2090 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2091
2092 /* physical address: used for pause frames */
2093 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2094 /* virtual address for data */
2095 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2096
2097 /* enable interrupt mask for counter overflows */
2098 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2099 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2100 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2101
2102 /* Initialize Mac Fifo */
2103
2104 /* Configure Rx MAC FIFO */
2105 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2106 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2107
2108 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2109 if (is_yukon_lite_a0(hw))
2110 reg &= ~GMF_RX_F_FL_ON;
2111
2112 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2113 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2114 /*
2115 * because Pause Packet Truncation in GMAC is not working
2116 * we have to increase the Flush Threshold to 64 bytes
2117 * in order to flush pause packets in Rx FIFO on Yukon-1
2118 */
2119 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2120
2121 /* Configure Tx MAC FIFO */
2122 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2123 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2124 }
2125
2126 /* Go into power down mode */
2127 static void yukon_suspend(struct skge_hw *hw, int port)
2128 {
2129 u16 ctrl;
2130
2131 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2132 ctrl |= PHY_M_PC_POL_R_DIS;
2133 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2134
2135 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2136 ctrl |= PHY_CT_RESET;
2137 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2138
2139 /* switch IEEE compatible power down mode on */
2140 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2141 ctrl |= PHY_CT_PDOWN;
2142 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2143 }
2144
2145 static void yukon_stop(struct skge_port *skge)
2146 {
2147 struct skge_hw *hw = skge->hw;
2148 int port = skge->port;
2149
2150 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2151 yukon_reset(hw, port);
2152
2153 gma_write16(hw, port, GM_GP_CTRL,
2154 gma_read16(hw, port, GM_GP_CTRL)
2155 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2156 gma_read16(hw, port, GM_GP_CTRL);
2157
2158 yukon_suspend(hw, port);
2159
2160 /* set GPHY Control reset */
2161 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2162 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2163 }
2164
2165 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2166 {
2167 struct skge_hw *hw = skge->hw;
2168 int port = skge->port;
2169 int i;
2170
2171 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2172 | gma_read32(hw, port, GM_TXO_OK_LO);
2173 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2174 | gma_read32(hw, port, GM_RXO_OK_LO);
2175
2176 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2177 data[i] = gma_read32(hw, port,
2178 skge_stats[i].gma_offset);
2179 }
2180
2181 static void yukon_mac_intr(struct skge_hw *hw, int port)
2182 {
2183 struct net_device *dev = hw->dev[port];
2184 struct skge_port *skge = netdev_priv(dev);
2185 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2186
2187 if (netif_msg_intr(skge))
2188 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2189 dev->name, status);
2190
2191 if (status & GM_IS_RX_FF_OR) {
2192 ++skge->net_stats.rx_fifo_errors;
2193 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2194 }
2195
2196 if (status & GM_IS_TX_FF_UR) {
2197 ++skge->net_stats.tx_fifo_errors;
2198 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2199 }
2200
2201 }
2202
2203 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2204 {
2205 switch (aux & PHY_M_PS_SPEED_MSK) {
2206 case PHY_M_PS_SPEED_1000:
2207 return SPEED_1000;
2208 case PHY_M_PS_SPEED_100:
2209 return SPEED_100;
2210 default:
2211 return SPEED_10;
2212 }
2213 }
2214
2215 static void yukon_link_up(struct skge_port *skge)
2216 {
2217 struct skge_hw *hw = skge->hw;
2218 int port = skge->port;
2219 u16 reg;
2220
2221 /* Enable Transmit FIFO Underrun */
2222 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2223
2224 reg = gma_read16(hw, port, GM_GP_CTRL);
2225 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2226 reg |= GM_GPCR_DUP_FULL;
2227
2228 /* enable Rx/Tx */
2229 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2230 gma_write16(hw, port, GM_GP_CTRL, reg);
2231
2232 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2233 skge_link_up(skge);
2234 }
2235
2236 static void yukon_link_down(struct skge_port *skge)
2237 {
2238 struct skge_hw *hw = skge->hw;
2239 int port = skge->port;
2240 u16 ctrl;
2241
2242 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2243 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2244 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2245
2246 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2247 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2248 ctrl |= PHY_M_AN_ASP;
2249 /* restore Asymmetric Pause bit */
2250 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2251 }
2252
2253 skge_link_down(skge);
2254
2255 yukon_init(hw, port);
2256 }
2257
2258 static void yukon_phy_intr(struct skge_port *skge)
2259 {
2260 struct skge_hw *hw = skge->hw;
2261 int port = skge->port;
2262 const char *reason = NULL;
2263 u16 istatus, phystat;
2264
2265 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2266 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2267
2268 if (netif_msg_intr(skge))
2269 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2270 skge->netdev->name, istatus, phystat);
2271
2272 if (istatus & PHY_M_IS_AN_COMPL) {
2273 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2274 & PHY_M_AN_RF) {
2275 reason = "remote fault";
2276 goto failed;
2277 }
2278
2279 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2280 reason = "master/slave fault";
2281 goto failed;
2282 }
2283
2284 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2285 reason = "speed/duplex";
2286 goto failed;
2287 }
2288
2289 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2290 ? DUPLEX_FULL : DUPLEX_HALF;
2291 skge->speed = yukon_speed(hw, phystat);
2292
2293 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2294 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2295 case PHY_M_PS_PAUSE_MSK:
2296 skge->flow_status = FLOW_STAT_SYMMETRIC;
2297 break;
2298 case PHY_M_PS_RX_P_EN:
2299 skge->flow_status = FLOW_STAT_REM_SEND;
2300 break;
2301 case PHY_M_PS_TX_P_EN:
2302 skge->flow_status = FLOW_STAT_LOC_SEND;
2303 break;
2304 default:
2305 skge->flow_status = FLOW_STAT_NONE;
2306 }
2307
2308 if (skge->flow_status == FLOW_STAT_NONE ||
2309 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2310 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2311 else
2312 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2313 yukon_link_up(skge);
2314 return;
2315 }
2316
2317 if (istatus & PHY_M_IS_LSP_CHANGE)
2318 skge->speed = yukon_speed(hw, phystat);
2319
2320 if (istatus & PHY_M_IS_DUP_CHANGE)
2321 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2322 if (istatus & PHY_M_IS_LST_CHANGE) {
2323 if (phystat & PHY_M_PS_LINK_UP)
2324 yukon_link_up(skge);
2325 else
2326 yukon_link_down(skge);
2327 }
2328 return;
2329 failed:
2330 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2331 skge->netdev->name, reason);
2332
2333 /* XXX restart autonegotiation? */
2334 }
2335
2336 static void skge_phy_reset(struct skge_port *skge)
2337 {
2338 struct skge_hw *hw = skge->hw;
2339 int port = skge->port;
2340 struct net_device *dev = hw->dev[port];
2341
2342 netif_stop_queue(skge->netdev);
2343 netif_carrier_off(skge->netdev);
2344
2345 spin_lock_bh(&hw->phy_lock);
2346 if (hw->chip_id == CHIP_ID_GENESIS) {
2347 genesis_reset(hw, port);
2348 genesis_mac_init(hw, port);
2349 } else {
2350 yukon_reset(hw, port);
2351 yukon_init(hw, port);
2352 }
2353 spin_unlock_bh(&hw->phy_lock);
2354
2355 dev->set_multicast_list(dev);
2356 }
2357
2358 /* Basic MII support */
2359 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2360 {
2361 struct mii_ioctl_data *data = if_mii(ifr);
2362 struct skge_port *skge = netdev_priv(dev);
2363 struct skge_hw *hw = skge->hw;
2364 int err = -EOPNOTSUPP;
2365
2366 if (!netif_running(dev))
2367 return -ENODEV; /* Phy still in reset */
2368
2369 switch(cmd) {
2370 case SIOCGMIIPHY:
2371 data->phy_id = hw->phy_addr;
2372
2373 /* fallthru */
2374 case SIOCGMIIREG: {
2375 u16 val = 0;
2376 spin_lock_bh(&hw->phy_lock);
2377 if (hw->chip_id == CHIP_ID_GENESIS)
2378 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2379 else
2380 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2381 spin_unlock_bh(&hw->phy_lock);
2382 data->val_out = val;
2383 break;
2384 }
2385
2386 case SIOCSMIIREG:
2387 if (!capable(CAP_NET_ADMIN))
2388 return -EPERM;
2389
2390 spin_lock_bh(&hw->phy_lock);
2391 if (hw->chip_id == CHIP_ID_GENESIS)
2392 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2393 data->val_in);
2394 else
2395 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2396 data->val_in);
2397 spin_unlock_bh(&hw->phy_lock);
2398 break;
2399 }
2400 return err;
2401 }
2402
2403 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2404 {
2405 u32 end;
2406
2407 start /= 8;
2408 len /= 8;
2409 end = start + len - 1;
2410
2411 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2412 skge_write32(hw, RB_ADDR(q, RB_START), start);
2413 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2414 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2415 skge_write32(hw, RB_ADDR(q, RB_END), end);
2416
2417 if (q == Q_R1 || q == Q_R2) {
2418 /* Set thresholds on receive queue's */
2419 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2420 start + (2*len)/3);
2421 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2422 start + (len/3));
2423 } else {
2424 /* Enable store & forward on Tx queue's because
2425 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2426 */
2427 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2428 }
2429
2430 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2431 }
2432
2433 /* Setup Bus Memory Interface */
2434 static void skge_qset(struct skge_port *skge, u16 q,
2435 const struct skge_element *e)
2436 {
2437 struct skge_hw *hw = skge->hw;
2438 u32 watermark = 0x600;
2439 u64 base = skge->dma + (e->desc - skge->mem);
2440
2441 /* optimization to reduce window on 32bit/33mhz */
2442 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2443 watermark /= 2;
2444
2445 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2446 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2447 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2448 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2449 }
2450
2451 static int skge_up(struct net_device *dev)
2452 {
2453 struct skge_port *skge = netdev_priv(dev);
2454 struct skge_hw *hw = skge->hw;
2455 int port = skge->port;
2456 u32 chunk, ram_addr;
2457 size_t rx_size, tx_size;
2458 int err;
2459
2460 if (!is_valid_ether_addr(dev->dev_addr))
2461 return -EINVAL;
2462
2463 if (netif_msg_ifup(skge))
2464 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2465
2466 if (dev->mtu > RX_BUF_SIZE)
2467 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2468 else
2469 skge->rx_buf_size = RX_BUF_SIZE;
2470
2471
2472 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2473 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2474 skge->mem_size = tx_size + rx_size;
2475 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2476 if (!skge->mem)
2477 return -ENOMEM;
2478
2479 BUG_ON(skge->dma & 7);
2480
2481 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2482 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2483 err = -EINVAL;
2484 goto free_pci_mem;
2485 }
2486
2487 memset(skge->mem, 0, skge->mem_size);
2488
2489 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2490 if (err)
2491 goto free_pci_mem;
2492
2493 err = skge_rx_fill(dev);
2494 if (err)
2495 goto free_rx_ring;
2496
2497 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2498 skge->dma + rx_size);
2499 if (err)
2500 goto free_rx_ring;
2501
2502 /* Initialize MAC */
2503 spin_lock_bh(&hw->phy_lock);
2504 if (hw->chip_id == CHIP_ID_GENESIS)
2505 genesis_mac_init(hw, port);
2506 else
2507 yukon_mac_init(hw, port);
2508 spin_unlock_bh(&hw->phy_lock);
2509
2510 /* Configure RAMbuffers */
2511 chunk = hw->ram_size / ((hw->ports + 1)*2);
2512 ram_addr = hw->ram_offset + 2 * chunk * port;
2513
2514 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2515 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2516
2517 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2518 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2519 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2520
2521 /* Start receiver BMU */
2522 wmb();
2523 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2524 skge_led(skge, LED_MODE_ON);
2525
2526 spin_lock_irq(&hw->hw_lock);
2527 hw->intr_mask |= portmask[port];
2528 skge_write32(hw, B0_IMSK, hw->intr_mask);
2529 spin_unlock_irq(&hw->hw_lock);
2530
2531 netif_poll_enable(dev);
2532 return 0;
2533
2534 free_rx_ring:
2535 skge_rx_clean(skge);
2536 kfree(skge->rx_ring.start);
2537 free_pci_mem:
2538 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2539 skge->mem = NULL;
2540
2541 return err;
2542 }
2543
2544 static int skge_down(struct net_device *dev)
2545 {
2546 struct skge_port *skge = netdev_priv(dev);
2547 struct skge_hw *hw = skge->hw;
2548 int port = skge->port;
2549
2550 if (skge->mem == NULL)
2551 return 0;
2552
2553 if (netif_msg_ifdown(skge))
2554 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2555
2556 netif_stop_queue(dev);
2557
2558 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2559 del_timer_sync(&skge->link_timer);
2560
2561 netif_poll_disable(dev);
2562 netif_carrier_off(dev);
2563
2564 spin_lock_irq(&hw->hw_lock);
2565 hw->intr_mask &= ~portmask[port];
2566 skge_write32(hw, B0_IMSK, hw->intr_mask);
2567 spin_unlock_irq(&hw->hw_lock);
2568
2569 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2570 if (hw->chip_id == CHIP_ID_GENESIS)
2571 genesis_stop(skge);
2572 else
2573 yukon_stop(skge);
2574
2575 /* Stop transmitter */
2576 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2577 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2578 RB_RST_SET|RB_DIS_OP_MD);
2579
2580
2581 /* Disable Force Sync bit and Enable Alloc bit */
2582 skge_write8(hw, SK_REG(port, TXA_CTRL),
2583 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2584
2585 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2586 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2587 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2588
2589 /* Reset PCI FIFO */
2590 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2591 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2592
2593 /* Reset the RAM Buffer async Tx queue */
2594 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2595 /* stop receiver */
2596 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2597 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2598 RB_RST_SET|RB_DIS_OP_MD);
2599 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2600
2601 if (hw->chip_id == CHIP_ID_GENESIS) {
2602 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2603 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2604 } else {
2605 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2606 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2607 }
2608
2609 skge_led(skge, LED_MODE_OFF);
2610
2611 netif_tx_lock_bh(dev);
2612 skge_tx_clean(dev);
2613 netif_tx_unlock_bh(dev);
2614
2615 skge_rx_clean(skge);
2616
2617 kfree(skge->rx_ring.start);
2618 kfree(skge->tx_ring.start);
2619 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2620 skge->mem = NULL;
2621 return 0;
2622 }
2623
2624 static inline int skge_avail(const struct skge_ring *ring)
2625 {
2626 smp_mb();
2627 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2628 + (ring->to_clean - ring->to_use) - 1;
2629 }
2630
2631 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2632 {
2633 struct skge_port *skge = netdev_priv(dev);
2634 struct skge_hw *hw = skge->hw;
2635 struct skge_element *e;
2636 struct skge_tx_desc *td;
2637 int i;
2638 u32 control, len;
2639 u64 map;
2640
2641 if (skb_padto(skb, ETH_ZLEN))
2642 return NETDEV_TX_OK;
2643
2644 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2645 return NETDEV_TX_BUSY;
2646
2647 e = skge->tx_ring.to_use;
2648 td = e->desc;
2649 BUG_ON(td->control & BMU_OWN);
2650 e->skb = skb;
2651 len = skb_headlen(skb);
2652 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2653 pci_unmap_addr_set(e, mapaddr, map);
2654 pci_unmap_len_set(e, maplen, len);
2655
2656 td->dma_lo = map;
2657 td->dma_hi = map >> 32;
2658
2659 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2660 const int offset = skb_transport_offset(skb);
2661
2662 /* This seems backwards, but it is what the sk98lin
2663 * does. Looks like hardware is wrong?
2664 */
2665 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
2666 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2667 control = BMU_TCP_CHECK;
2668 else
2669 control = BMU_UDP_CHECK;
2670
2671 td->csum_offs = 0;
2672 td->csum_start = offset;
2673 td->csum_write = offset + skb->csum_offset;
2674 } else
2675 control = BMU_CHECK;
2676
2677 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2678 control |= BMU_EOF| BMU_IRQ_EOF;
2679 else {
2680 struct skge_tx_desc *tf = td;
2681
2682 control |= BMU_STFWD;
2683 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2684 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2685
2686 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2687 frag->size, PCI_DMA_TODEVICE);
2688
2689 e = e->next;
2690 e->skb = skb;
2691 tf = e->desc;
2692 BUG_ON(tf->control & BMU_OWN);
2693
2694 tf->dma_lo = map;
2695 tf->dma_hi = (u64) map >> 32;
2696 pci_unmap_addr_set(e, mapaddr, map);
2697 pci_unmap_len_set(e, maplen, frag->size);
2698
2699 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2700 }
2701 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2702 }
2703 /* Make sure all the descriptors written */
2704 wmb();
2705 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2706 wmb();
2707
2708 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2709
2710 if (unlikely(netif_msg_tx_queued(skge)))
2711 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2712 dev->name, e - skge->tx_ring.start, skb->len);
2713
2714 skge->tx_ring.to_use = e->next;
2715 smp_wmb();
2716
2717 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2718 pr_debug("%s: transmit queue full\n", dev->name);
2719 netif_stop_queue(dev);
2720 }
2721
2722 dev->trans_start = jiffies;
2723
2724 return NETDEV_TX_OK;
2725 }
2726
2727
2728 /* Free resources associated with this reing element */
2729 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2730 u32 control)
2731 {
2732 struct pci_dev *pdev = skge->hw->pdev;
2733
2734 /* skb header vs. fragment */
2735 if (control & BMU_STF)
2736 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2737 pci_unmap_len(e, maplen),
2738 PCI_DMA_TODEVICE);
2739 else
2740 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2741 pci_unmap_len(e, maplen),
2742 PCI_DMA_TODEVICE);
2743
2744 if (control & BMU_EOF) {
2745 if (unlikely(netif_msg_tx_done(skge)))
2746 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2747 skge->netdev->name, e - skge->tx_ring.start);
2748
2749 dev_kfree_skb(e->skb);
2750 }
2751 }
2752
2753 /* Free all buffers in transmit ring */
2754 static void skge_tx_clean(struct net_device *dev)
2755 {
2756 struct skge_port *skge = netdev_priv(dev);
2757 struct skge_element *e;
2758
2759 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2760 struct skge_tx_desc *td = e->desc;
2761 skge_tx_free(skge, e, td->control);
2762 td->control = 0;
2763 }
2764
2765 skge->tx_ring.to_clean = e;
2766 netif_wake_queue(dev);
2767 }
2768
2769 static void skge_tx_timeout(struct net_device *dev)
2770 {
2771 struct skge_port *skge = netdev_priv(dev);
2772
2773 if (netif_msg_timer(skge))
2774 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2775
2776 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2777 skge_tx_clean(dev);
2778 }
2779
2780 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2781 {
2782 int err;
2783
2784 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2785 return -EINVAL;
2786
2787 if (!netif_running(dev)) {
2788 dev->mtu = new_mtu;
2789 return 0;
2790 }
2791
2792 skge_down(dev);
2793
2794 dev->mtu = new_mtu;
2795
2796 err = skge_up(dev);
2797 if (err)
2798 dev_close(dev);
2799
2800 return err;
2801 }
2802
2803 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2804
2805 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2806 {
2807 u32 crc, bit;
2808
2809 crc = ether_crc_le(ETH_ALEN, addr);
2810 bit = ~crc & 0x3f;
2811 filter[bit/8] |= 1 << (bit%8);
2812 }
2813
2814 static void genesis_set_multicast(struct net_device *dev)
2815 {
2816 struct skge_port *skge = netdev_priv(dev);
2817 struct skge_hw *hw = skge->hw;
2818 int port = skge->port;
2819 int i, count = dev->mc_count;
2820 struct dev_mc_list *list = dev->mc_list;
2821 u32 mode;
2822 u8 filter[8];
2823
2824 mode = xm_read32(hw, port, XM_MODE);
2825 mode |= XM_MD_ENA_HASH;
2826 if (dev->flags & IFF_PROMISC)
2827 mode |= XM_MD_ENA_PROM;
2828 else
2829 mode &= ~XM_MD_ENA_PROM;
2830
2831 if (dev->flags & IFF_ALLMULTI)
2832 memset(filter, 0xff, sizeof(filter));
2833 else {
2834 memset(filter, 0, sizeof(filter));
2835
2836 if (skge->flow_status == FLOW_STAT_REM_SEND
2837 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2838 genesis_add_filter(filter, pause_mc_addr);
2839
2840 for (i = 0; list && i < count; i++, list = list->next)
2841 genesis_add_filter(filter, list->dmi_addr);
2842 }
2843
2844 xm_write32(hw, port, XM_MODE, mode);
2845 xm_outhash(hw, port, XM_HSM, filter);
2846 }
2847
2848 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2849 {
2850 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2851 filter[bit/8] |= 1 << (bit%8);
2852 }
2853
2854 static void yukon_set_multicast(struct net_device *dev)
2855 {
2856 struct skge_port *skge = netdev_priv(dev);
2857 struct skge_hw *hw = skge->hw;
2858 int port = skge->port;
2859 struct dev_mc_list *list = dev->mc_list;
2860 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
2861 || skge->flow_status == FLOW_STAT_SYMMETRIC);
2862 u16 reg;
2863 u8 filter[8];
2864
2865 memset(filter, 0, sizeof(filter));
2866
2867 reg = gma_read16(hw, port, GM_RX_CTRL);
2868 reg |= GM_RXCR_UCF_ENA;
2869
2870 if (dev->flags & IFF_PROMISC) /* promiscuous */
2871 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2872 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2873 memset(filter, 0xff, sizeof(filter));
2874 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
2875 reg &= ~GM_RXCR_MCF_ENA;
2876 else {
2877 int i;
2878 reg |= GM_RXCR_MCF_ENA;
2879
2880 if (rx_pause)
2881 yukon_add_filter(filter, pause_mc_addr);
2882
2883 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2884 yukon_add_filter(filter, list->dmi_addr);
2885 }
2886
2887
2888 gma_write16(hw, port, GM_MC_ADDR_H1,
2889 (u16)filter[0] | ((u16)filter[1] << 8));
2890 gma_write16(hw, port, GM_MC_ADDR_H2,
2891 (u16)filter[2] | ((u16)filter[3] << 8));
2892 gma_write16(hw, port, GM_MC_ADDR_H3,
2893 (u16)filter[4] | ((u16)filter[5] << 8));
2894 gma_write16(hw, port, GM_MC_ADDR_H4,
2895 (u16)filter[6] | ((u16)filter[7] << 8));
2896
2897 gma_write16(hw, port, GM_RX_CTRL, reg);
2898 }
2899
2900 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2901 {
2902 if (hw->chip_id == CHIP_ID_GENESIS)
2903 return status >> XMR_FS_LEN_SHIFT;
2904 else
2905 return status >> GMR_FS_LEN_SHIFT;
2906 }
2907
2908 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2909 {
2910 if (hw->chip_id == CHIP_ID_GENESIS)
2911 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2912 else
2913 return (status & GMR_FS_ANY_ERR) ||
2914 (status & GMR_FS_RX_OK) == 0;
2915 }
2916
2917
2918 /* Get receive buffer from descriptor.
2919 * Handles copy of small buffers and reallocation failures
2920 */
2921 static struct sk_buff *skge_rx_get(struct net_device *dev,
2922 struct skge_element *e,
2923 u32 control, u32 status, u16 csum)
2924 {
2925 struct skge_port *skge = netdev_priv(dev);
2926 struct sk_buff *skb;
2927 u16 len = control & BMU_BBC;
2928
2929 if (unlikely(netif_msg_rx_status(skge)))
2930 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2931 dev->name, e - skge->rx_ring.start,
2932 status, len);
2933
2934 if (len > skge->rx_buf_size)
2935 goto error;
2936
2937 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2938 goto error;
2939
2940 if (bad_phy_status(skge->hw, status))
2941 goto error;
2942
2943 if (phy_length(skge->hw, status) != len)
2944 goto error;
2945
2946 if (len < RX_COPY_THRESHOLD) {
2947 skb = netdev_alloc_skb(dev, len + 2);
2948 if (!skb)
2949 goto resubmit;
2950
2951 skb_reserve(skb, 2);
2952 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2953 pci_unmap_addr(e, mapaddr),
2954 len, PCI_DMA_FROMDEVICE);
2955 skb_copy_from_linear_data(e->skb, skb->data, len);
2956 pci_dma_sync_single_for_device(skge->hw->pdev,
2957 pci_unmap_addr(e, mapaddr),
2958 len, PCI_DMA_FROMDEVICE);
2959 skge_rx_reuse(e, skge->rx_buf_size);
2960 } else {
2961 struct sk_buff *nskb;
2962 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
2963 if (!nskb)
2964 goto resubmit;
2965
2966 skb_reserve(nskb, NET_IP_ALIGN);
2967 pci_unmap_single(skge->hw->pdev,
2968 pci_unmap_addr(e, mapaddr),
2969 pci_unmap_len(e, maplen),
2970 PCI_DMA_FROMDEVICE);
2971 skb = e->skb;
2972 prefetch(skb->data);
2973 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2974 }
2975
2976 skb_put(skb, len);
2977 if (skge->rx_csum) {
2978 skb->csum = csum;
2979 skb->ip_summed = CHECKSUM_COMPLETE;
2980 }
2981
2982 skb->protocol = eth_type_trans(skb, dev);
2983
2984 return skb;
2985 error:
2986
2987 if (netif_msg_rx_err(skge))
2988 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2989 dev->name, e - skge->rx_ring.start,
2990 control, status);
2991
2992 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2993 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2994 skge->net_stats.rx_length_errors++;
2995 if (status & XMR_FS_FRA_ERR)
2996 skge->net_stats.rx_frame_errors++;
2997 if (status & XMR_FS_FCS_ERR)
2998 skge->net_stats.rx_crc_errors++;
2999 } else {
3000 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3001 skge->net_stats.rx_length_errors++;
3002 if (status & GMR_FS_FRAGMENT)
3003 skge->net_stats.rx_frame_errors++;
3004 if (status & GMR_FS_CRC_ERR)
3005 skge->net_stats.rx_crc_errors++;
3006 }
3007
3008 resubmit:
3009 skge_rx_reuse(e, skge->rx_buf_size);
3010 return NULL;
3011 }
3012
3013 /* Free all buffers in Tx ring which are no longer owned by device */
3014 static void skge_tx_done(struct net_device *dev)
3015 {
3016 struct skge_port *skge = netdev_priv(dev);
3017 struct skge_ring *ring = &skge->tx_ring;
3018 struct skge_element *e;
3019
3020 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3021
3022 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3023 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3024
3025 if (control & BMU_OWN)
3026 break;
3027
3028 skge_tx_free(skge, e, control);
3029 }
3030 skge->tx_ring.to_clean = e;
3031
3032 /* Can run lockless until we need to synchronize to restart queue. */
3033 smp_mb();
3034
3035 if (unlikely(netif_queue_stopped(dev) &&
3036 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3037 netif_tx_lock(dev);
3038 if (unlikely(netif_queue_stopped(dev) &&
3039 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3040 netif_wake_queue(dev);
3041
3042 }
3043 netif_tx_unlock(dev);
3044 }
3045 }
3046
3047 static int skge_poll(struct net_device *dev, int *budget)
3048 {
3049 struct skge_port *skge = netdev_priv(dev);
3050 struct skge_hw *hw = skge->hw;
3051 struct skge_ring *ring = &skge->rx_ring;
3052 struct skge_element *e;
3053 unsigned long flags;
3054 int to_do = min(dev->quota, *budget);
3055 int work_done = 0;
3056
3057 skge_tx_done(dev);
3058
3059 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3060
3061 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3062 struct skge_rx_desc *rd = e->desc;
3063 struct sk_buff *skb;
3064 u32 control;
3065
3066 rmb();
3067 control = rd->control;
3068 if (control & BMU_OWN)
3069 break;
3070
3071 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3072 if (likely(skb)) {
3073 dev->last_rx = jiffies;
3074 netif_receive_skb(skb);
3075
3076 ++work_done;
3077 }
3078 }
3079 ring->to_clean = e;
3080
3081 /* restart receiver */
3082 wmb();
3083 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3084
3085 *budget -= work_done;
3086 dev->quota -= work_done;
3087
3088 if (work_done >= to_do)
3089 return 1; /* not done */
3090
3091 spin_lock_irqsave(&hw->hw_lock, flags);
3092 __netif_rx_complete(dev);
3093 hw->intr_mask |= napimask[skge->port];
3094 skge_write32(hw, B0_IMSK, hw->intr_mask);
3095 skge_read32(hw, B0_IMSK);
3096 spin_unlock_irqrestore(&hw->hw_lock, flags);
3097
3098 return 0;
3099 }
3100
3101 /* Parity errors seem to happen when Genesis is connected to a switch
3102 * with no other ports present. Heartbeat error??
3103 */
3104 static void skge_mac_parity(struct skge_hw *hw, int port)
3105 {
3106 struct net_device *dev = hw->dev[port];
3107
3108 if (dev) {
3109 struct skge_port *skge = netdev_priv(dev);
3110 ++skge->net_stats.tx_heartbeat_errors;
3111 }
3112
3113 if (hw->chip_id == CHIP_ID_GENESIS)
3114 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3115 MFF_CLR_PERR);
3116 else
3117 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3118 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3119 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3120 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3121 }
3122
3123 static void skge_mac_intr(struct skge_hw *hw, int port)
3124 {
3125 if (hw->chip_id == CHIP_ID_GENESIS)
3126 genesis_mac_intr(hw, port);
3127 else
3128 yukon_mac_intr(hw, port);
3129 }
3130
3131 /* Handle device specific framing and timeout interrupts */
3132 static void skge_error_irq(struct skge_hw *hw)
3133 {
3134 struct pci_dev *pdev = hw->pdev;
3135 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3136
3137 if (hw->chip_id == CHIP_ID_GENESIS) {
3138 /* clear xmac errors */
3139 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3140 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3141 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3142 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3143 } else {
3144 /* Timestamp (unused) overflow */
3145 if (hwstatus & IS_IRQ_TIST_OV)
3146 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3147 }
3148
3149 if (hwstatus & IS_RAM_RD_PAR) {
3150 dev_err(&pdev->dev, "Ram read data parity error\n");
3151 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3152 }
3153
3154 if (hwstatus & IS_RAM_WR_PAR) {
3155 dev_err(&pdev->dev, "Ram write data parity error\n");
3156 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3157 }
3158
3159 if (hwstatus & IS_M1_PAR_ERR)
3160 skge_mac_parity(hw, 0);
3161
3162 if (hwstatus & IS_M2_PAR_ERR)
3163 skge_mac_parity(hw, 1);
3164
3165 if (hwstatus & IS_R1_PAR_ERR) {
3166 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3167 hw->dev[0]->name);
3168 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3169 }
3170
3171 if (hwstatus & IS_R2_PAR_ERR) {
3172 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3173 hw->dev[1]->name);
3174 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3175 }
3176
3177 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3178 u16 pci_status, pci_cmd;
3179
3180 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3181 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3182
3183 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3184 pci_cmd, pci_status);
3185
3186 /* Write the error bits back to clear them. */
3187 pci_status &= PCI_STATUS_ERROR_BITS;
3188 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3189 pci_write_config_word(pdev, PCI_COMMAND,
3190 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3191 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3192 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3193
3194 /* if error still set then just ignore it */
3195 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3196 if (hwstatus & IS_IRQ_STAT) {
3197 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3198 hw->intr_mask &= ~IS_HW_ERR;
3199 }
3200 }
3201 }
3202
3203 /*
3204 * Interrupt from PHY are handled in tasklet (softirq)
3205 * because accessing phy registers requires spin wait which might
3206 * cause excess interrupt latency.
3207 */
3208 static void skge_extirq(unsigned long arg)
3209 {
3210 struct skge_hw *hw = (struct skge_hw *) arg;
3211 int port;
3212
3213 for (port = 0; port < hw->ports; port++) {
3214 struct net_device *dev = hw->dev[port];
3215
3216 if (netif_running(dev)) {
3217 struct skge_port *skge = netdev_priv(dev);
3218
3219 spin_lock(&hw->phy_lock);
3220 if (hw->chip_id != CHIP_ID_GENESIS)
3221 yukon_phy_intr(skge);
3222 else if (hw->phy_type == SK_PHY_BCOM)
3223 bcom_phy_intr(skge);
3224 spin_unlock(&hw->phy_lock);
3225 }
3226 }
3227
3228 spin_lock_irq(&hw->hw_lock);
3229 hw->intr_mask |= IS_EXT_REG;
3230 skge_write32(hw, B0_IMSK, hw->intr_mask);
3231 skge_read32(hw, B0_IMSK);
3232 spin_unlock_irq(&hw->hw_lock);
3233 }
3234
3235 static irqreturn_t skge_intr(int irq, void *dev_id)
3236 {
3237 struct skge_hw *hw = dev_id;
3238 u32 status;
3239 int handled = 0;
3240
3241 spin_lock(&hw->hw_lock);
3242 /* Reading this register masks IRQ */
3243 status = skge_read32(hw, B0_SP_ISRC);
3244 if (status == 0 || status == ~0)
3245 goto out;
3246
3247 handled = 1;
3248 status &= hw->intr_mask;
3249 if (status & IS_EXT_REG) {
3250 hw->intr_mask &= ~IS_EXT_REG;
3251 tasklet_schedule(&hw->phy_task);
3252 }
3253
3254 if (status & (IS_XA1_F|IS_R1_F)) {
3255 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3256 netif_rx_schedule(hw->dev[0]);
3257 }
3258
3259 if (status & IS_PA_TO_TX1)
3260 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3261
3262 if (status & IS_PA_TO_RX1) {
3263 struct skge_port *skge = netdev_priv(hw->dev[0]);
3264
3265 ++skge->net_stats.rx_over_errors;
3266 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3267 }
3268
3269
3270 if (status & IS_MAC1)
3271 skge_mac_intr(hw, 0);
3272
3273 if (hw->dev[1]) {
3274 if (status & (IS_XA2_F|IS_R2_F)) {
3275 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3276 netif_rx_schedule(hw->dev[1]);
3277 }
3278
3279 if (status & IS_PA_TO_RX2) {
3280 struct skge_port *skge = netdev_priv(hw->dev[1]);
3281 ++skge->net_stats.rx_over_errors;
3282 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3283 }
3284
3285 if (status & IS_PA_TO_TX2)
3286 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3287
3288 if (status & IS_MAC2)
3289 skge_mac_intr(hw, 1);
3290 }
3291
3292 if (status & IS_HW_ERR)
3293 skge_error_irq(hw);
3294
3295 skge_write32(hw, B0_IMSK, hw->intr_mask);
3296 skge_read32(hw, B0_IMSK);
3297 out:
3298 spin_unlock(&hw->hw_lock);
3299
3300 return IRQ_RETVAL(handled);
3301 }
3302
3303 #ifdef CONFIG_NET_POLL_CONTROLLER
3304 static void skge_netpoll(struct net_device *dev)
3305 {
3306 struct skge_port *skge = netdev_priv(dev);
3307
3308 disable_irq(dev->irq);
3309 skge_intr(dev->irq, skge->hw);
3310 enable_irq(dev->irq);
3311 }
3312 #endif
3313
3314 static int skge_set_mac_address(struct net_device *dev, void *p)
3315 {
3316 struct skge_port *skge = netdev_priv(dev);
3317 struct skge_hw *hw = skge->hw;
3318 unsigned port = skge->port;
3319 const struct sockaddr *addr = p;
3320 u16 ctrl;
3321
3322 if (!is_valid_ether_addr(addr->sa_data))
3323 return -EADDRNOTAVAIL;
3324
3325 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3326
3327 if (!netif_running(dev)) {
3328 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3329 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3330 } else {
3331 /* disable Rx */
3332 spin_lock_bh(&hw->phy_lock);
3333 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3334 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3335
3336 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3337 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3338
3339 if (hw->chip_id == CHIP_ID_GENESIS)
3340 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3341 else {
3342 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3343 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3344 }
3345
3346 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3347 spin_unlock_bh(&hw->phy_lock);
3348 }
3349
3350 return 0;
3351 }
3352
3353 static const struct {
3354 u8 id;
3355 const char *name;
3356 } skge_chips[] = {
3357 { CHIP_ID_GENESIS, "Genesis" },
3358 { CHIP_ID_YUKON, "Yukon" },
3359 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3360 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3361 };
3362
3363 static const char *skge_board_name(const struct skge_hw *hw)
3364 {
3365 int i;
3366 static char buf[16];
3367
3368 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3369 if (skge_chips[i].id == hw->chip_id)
3370 return skge_chips[i].name;
3371
3372 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3373 return buf;
3374 }
3375
3376
3377 /*
3378 * Setup the board data structure, but don't bring up
3379 * the port(s)
3380 */
3381 static int skge_reset(struct skge_hw *hw)
3382 {
3383 u32 reg;
3384 u16 ctst, pci_status;
3385 u8 t8, mac_cfg, pmd_type;
3386 int i;
3387
3388 ctst = skge_read16(hw, B0_CTST);
3389
3390 /* do a SW reset */
3391 skge_write8(hw, B0_CTST, CS_RST_SET);
3392 skge_write8(hw, B0_CTST, CS_RST_CLR);
3393
3394 /* clear PCI errors, if any */
3395 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3396 skge_write8(hw, B2_TST_CTRL2, 0);
3397
3398 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3399 pci_write_config_word(hw->pdev, PCI_STATUS,
3400 pci_status | PCI_STATUS_ERROR_BITS);
3401 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3402 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3403
3404 /* restore CLK_RUN bits (for Yukon-Lite) */
3405 skge_write16(hw, B0_CTST,
3406 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3407
3408 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3409 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3410 pmd_type = skge_read8(hw, B2_PMD_TYP);
3411 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3412
3413 switch (hw->chip_id) {
3414 case CHIP_ID_GENESIS:
3415 switch (hw->phy_type) {
3416 case SK_PHY_XMAC:
3417 hw->phy_addr = PHY_ADDR_XMAC;
3418 break;
3419 case SK_PHY_BCOM:
3420 hw->phy_addr = PHY_ADDR_BCOM;
3421 break;
3422 default:
3423 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3424 hw->phy_type);
3425 return -EOPNOTSUPP;
3426 }
3427 break;
3428
3429 case CHIP_ID_YUKON:
3430 case CHIP_ID_YUKON_LITE:
3431 case CHIP_ID_YUKON_LP:
3432 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3433 hw->copper = 1;
3434
3435 hw->phy_addr = PHY_ADDR_MARV;
3436 break;
3437
3438 default:
3439 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3440 hw->chip_id);
3441 return -EOPNOTSUPP;
3442 }
3443
3444 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3445 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3446 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3447
3448 /* read the adapters RAM size */
3449 t8 = skge_read8(hw, B2_E_0);
3450 if (hw->chip_id == CHIP_ID_GENESIS) {
3451 if (t8 == 3) {
3452 /* special case: 4 x 64k x 36, offset = 0x80000 */
3453 hw->ram_size = 0x100000;
3454 hw->ram_offset = 0x80000;
3455 } else
3456 hw->ram_size = t8 * 512;
3457 }
3458 else if (t8 == 0)
3459 hw->ram_size = 0x20000;
3460 else
3461 hw->ram_size = t8 * 4096;
3462
3463 hw->intr_mask = IS_HW_ERR;
3464
3465 /* Use PHY IRQ for all but fiber based Genesis board */
3466 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3467 hw->intr_mask |= IS_EXT_REG;
3468
3469 if (hw->chip_id == CHIP_ID_GENESIS)
3470 genesis_init(hw);
3471 else {
3472 /* switch power to VCC (WA for VAUX problem) */
3473 skge_write8(hw, B0_POWER_CTRL,
3474 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3475
3476 /* avoid boards with stuck Hardware error bits */
3477 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3478 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3479 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3480 hw->intr_mask &= ~IS_HW_ERR;
3481 }
3482
3483 /* Clear PHY COMA */
3484 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3485 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3486 reg &= ~PCI_PHY_COMA;
3487 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3488 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3489
3490
3491 for (i = 0; i < hw->ports; i++) {
3492 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3493 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3494 }
3495 }
3496
3497 /* turn off hardware timer (unused) */
3498 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3499 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3500 skge_write8(hw, B0_LED, LED_STAT_ON);
3501
3502 /* enable the Tx Arbiters */
3503 for (i = 0; i < hw->ports; i++)
3504 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3505
3506 /* Initialize ram interface */
3507 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3508
3509 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3510 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3511 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3512 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3513 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3514 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3515 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3516 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3517 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3518 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3519 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3520 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3521
3522 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3523
3524 /* Set interrupt moderation for Transmit only
3525 * Receive interrupts avoided by NAPI
3526 */
3527 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3528 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3529 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3530
3531 skge_write32(hw, B0_IMSK, hw->intr_mask);
3532
3533 for (i = 0; i < hw->ports; i++) {
3534 if (hw->chip_id == CHIP_ID_GENESIS)
3535 genesis_reset(hw, i);
3536 else
3537 yukon_reset(hw, i);
3538 }
3539
3540 return 0;
3541 }
3542
3543 /* Initialize network device */
3544 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3545 int highmem)
3546 {
3547 struct skge_port *skge;
3548 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3549
3550 if (!dev) {
3551 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3552 return NULL;
3553 }
3554
3555 SET_MODULE_OWNER(dev);
3556 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3557 dev->open = skge_up;
3558 dev->stop = skge_down;
3559 dev->do_ioctl = skge_ioctl;
3560 dev->hard_start_xmit = skge_xmit_frame;
3561 dev->get_stats = skge_get_stats;
3562 if (hw->chip_id == CHIP_ID_GENESIS)
3563 dev->set_multicast_list = genesis_set_multicast;
3564 else
3565 dev->set_multicast_list = yukon_set_multicast;
3566
3567 dev->set_mac_address = skge_set_mac_address;
3568 dev->change_mtu = skge_change_mtu;
3569 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3570 dev->tx_timeout = skge_tx_timeout;
3571 dev->watchdog_timeo = TX_WATCHDOG;
3572 dev->poll = skge_poll;
3573 dev->weight = NAPI_WEIGHT;
3574 #ifdef CONFIG_NET_POLL_CONTROLLER
3575 dev->poll_controller = skge_netpoll;
3576 #endif
3577 dev->irq = hw->pdev->irq;
3578
3579 if (highmem)
3580 dev->features |= NETIF_F_HIGHDMA;
3581
3582 skge = netdev_priv(dev);
3583 skge->netdev = dev;
3584 skge->hw = hw;
3585 skge->msg_enable = netif_msg_init(debug, default_msg);
3586
3587 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3588 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3589
3590 /* Auto speed and flow control */
3591 skge->autoneg = AUTONEG_ENABLE;
3592 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3593 skge->duplex = -1;
3594 skge->speed = -1;
3595 skge->advertising = skge_supported_modes(hw);
3596
3597 if (pci_wake_enabled(hw->pdev))
3598 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3599
3600 hw->dev[port] = dev;
3601
3602 skge->port = port;
3603
3604 /* Only used for Genesis XMAC */
3605 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3606
3607 if (hw->chip_id != CHIP_ID_GENESIS) {
3608 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3609 skge->rx_csum = 1;
3610 }
3611
3612 /* read the mac address */
3613 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3614 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3615
3616 /* device is off until link detection */
3617 netif_carrier_off(dev);
3618 netif_stop_queue(dev);
3619
3620 return dev;
3621 }
3622
3623 static void __devinit skge_show_addr(struct net_device *dev)
3624 {
3625 const struct skge_port *skge = netdev_priv(dev);
3626
3627 if (netif_msg_probe(skge))
3628 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3629 dev->name,
3630 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3631 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3632 }
3633
3634 static int __devinit skge_probe(struct pci_dev *pdev,
3635 const struct pci_device_id *ent)
3636 {
3637 struct net_device *dev, *dev1;
3638 struct skge_hw *hw;
3639 int err, using_dac = 0;
3640
3641 err = pci_enable_device(pdev);
3642 if (err) {
3643 dev_err(&pdev->dev, "cannot enable PCI device\n");
3644 goto err_out;
3645 }
3646
3647 err = pci_request_regions(pdev, DRV_NAME);
3648 if (err) {
3649 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3650 goto err_out_disable_pdev;
3651 }
3652
3653 pci_set_master(pdev);
3654
3655 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3656 using_dac = 1;
3657 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3658 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3659 using_dac = 0;
3660 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3661 }
3662
3663 if (err) {
3664 dev_err(&pdev->dev, "no usable DMA configuration\n");
3665 goto err_out_free_regions;
3666 }
3667
3668 #ifdef __BIG_ENDIAN
3669 /* byte swap descriptors in hardware */
3670 {
3671 u32 reg;
3672
3673 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3674 reg |= PCI_REV_DESC;
3675 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3676 }
3677 #endif
3678
3679 err = -ENOMEM;
3680 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3681 if (!hw) {
3682 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3683 goto err_out_free_regions;
3684 }
3685
3686 hw->pdev = pdev;
3687 spin_lock_init(&hw->hw_lock);
3688 spin_lock_init(&hw->phy_lock);
3689 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
3690
3691 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3692 if (!hw->regs) {
3693 dev_err(&pdev->dev, "cannot map device registers\n");
3694 goto err_out_free_hw;
3695 }
3696
3697 err = skge_reset(hw);
3698 if (err)
3699 goto err_out_iounmap;
3700
3701 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3702 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3703 skge_board_name(hw), hw->chip_rev);
3704
3705 dev = skge_devinit(hw, 0, using_dac);
3706 if (!dev)
3707 goto err_out_led_off;
3708
3709 /* Some motherboards are broken and has zero in ROM. */
3710 if (!is_valid_ether_addr(dev->dev_addr))
3711 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3712
3713 err = register_netdev(dev);
3714 if (err) {
3715 dev_err(&pdev->dev, "cannot register net device\n");
3716 goto err_out_free_netdev;
3717 }
3718
3719 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3720 if (err) {
3721 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3722 dev->name, pdev->irq);
3723 goto err_out_unregister;
3724 }
3725 skge_show_addr(dev);
3726
3727 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3728 if (register_netdev(dev1) == 0)
3729 skge_show_addr(dev1);
3730 else {
3731 /* Failure to register second port need not be fatal */
3732 dev_warn(&pdev->dev, "register of second port failed\n");
3733 hw->dev[1] = NULL;
3734 free_netdev(dev1);
3735 }
3736 }
3737 pci_set_drvdata(pdev, hw);
3738
3739 return 0;
3740
3741 err_out_unregister:
3742 unregister_netdev(dev);
3743 err_out_free_netdev:
3744 free_netdev(dev);
3745 err_out_led_off:
3746 skge_write16(hw, B0_LED, LED_STAT_OFF);
3747 err_out_iounmap:
3748 iounmap(hw->regs);
3749 err_out_free_hw:
3750 kfree(hw);
3751 err_out_free_regions:
3752 pci_release_regions(pdev);
3753 err_out_disable_pdev:
3754 pci_disable_device(pdev);
3755 pci_set_drvdata(pdev, NULL);
3756 err_out:
3757 return err;
3758 }
3759
3760 static void __devexit skge_remove(struct pci_dev *pdev)
3761 {
3762 struct skge_hw *hw = pci_get_drvdata(pdev);
3763 struct net_device *dev0, *dev1;
3764
3765 if (!hw)
3766 return;
3767
3768 flush_scheduled_work();
3769
3770 if ((dev1 = hw->dev[1]))
3771 unregister_netdev(dev1);
3772 dev0 = hw->dev[0];
3773 unregister_netdev(dev0);
3774
3775 tasklet_disable(&hw->phy_task);
3776
3777 spin_lock_irq(&hw->hw_lock);
3778 hw->intr_mask = 0;
3779 skge_write32(hw, B0_IMSK, 0);
3780 skge_read32(hw, B0_IMSK);
3781 spin_unlock_irq(&hw->hw_lock);
3782
3783 skge_write16(hw, B0_LED, LED_STAT_OFF);
3784 skge_write8(hw, B0_CTST, CS_RST_SET);
3785
3786 free_irq(pdev->irq, hw);
3787 pci_release_regions(pdev);
3788 pci_disable_device(pdev);
3789 if (dev1)
3790 free_netdev(dev1);
3791 free_netdev(dev0);
3792
3793 iounmap(hw->regs);
3794 kfree(hw);
3795 pci_set_drvdata(pdev, NULL);
3796 }
3797
3798 #ifdef CONFIG_PM
3799 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3800 {
3801 struct skge_hw *hw = pci_get_drvdata(pdev);
3802 int i, err, wol = 0;
3803
3804 if (!hw)
3805 return 0;
3806
3807 err = pci_save_state(pdev);
3808 if (err)
3809 return err;
3810
3811 for (i = 0; i < hw->ports; i++) {
3812 struct net_device *dev = hw->dev[i];
3813 struct skge_port *skge = netdev_priv(dev);
3814
3815 if (netif_running(dev))
3816 skge_down(dev);
3817 if (skge->wol)
3818 skge_wol_init(skge);
3819
3820 wol |= skge->wol;
3821 }
3822
3823 skge_write32(hw, B0_IMSK, 0);
3824 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3825 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3826
3827 return 0;
3828 }
3829
3830 static int skge_resume(struct pci_dev *pdev)
3831 {
3832 struct skge_hw *hw = pci_get_drvdata(pdev);
3833 int i, err;
3834
3835 if (!hw)
3836 return 0;
3837
3838 err = pci_set_power_state(pdev, PCI_D0);
3839 if (err)
3840 goto out;
3841
3842 err = pci_restore_state(pdev);
3843 if (err)
3844 goto out;
3845
3846 pci_enable_wake(pdev, PCI_D0, 0);
3847
3848 err = skge_reset(hw);
3849 if (err)
3850 goto out;
3851
3852 for (i = 0; i < hw->ports; i++) {
3853 struct net_device *dev = hw->dev[i];
3854
3855 if (netif_running(dev)) {
3856 err = skge_up(dev);
3857
3858 if (err) {
3859 printk(KERN_ERR PFX "%s: could not up: %d\n",
3860 dev->name, err);
3861 dev_close(dev);
3862 goto out;
3863 }
3864 }
3865 }
3866 out:
3867 return err;
3868 }
3869 #endif
3870
3871 static void skge_shutdown(struct pci_dev *pdev)
3872 {
3873 struct skge_hw *hw = pci_get_drvdata(pdev);
3874 int i, wol = 0;
3875
3876 if (!hw)
3877 return;
3878
3879 for (i = 0; i < hw->ports; i++) {
3880 struct net_device *dev = hw->dev[i];
3881 struct skge_port *skge = netdev_priv(dev);
3882
3883 if (skge->wol)
3884 skge_wol_init(skge);
3885 wol |= skge->wol;
3886 }
3887
3888 pci_enable_wake(pdev, PCI_D3hot, wol);
3889 pci_enable_wake(pdev, PCI_D3cold, wol);
3890
3891 pci_disable_device(pdev);
3892 pci_set_power_state(pdev, PCI_D3hot);
3893
3894 }
3895
3896 static struct pci_driver skge_driver = {
3897 .name = DRV_NAME,
3898 .id_table = skge_id_table,
3899 .probe = skge_probe,
3900 .remove = __devexit_p(skge_remove),
3901 #ifdef CONFIG_PM
3902 .suspend = skge_suspend,
3903 .resume = skge_resume,
3904 #endif
3905 .shutdown = skge_shutdown,
3906 };
3907
3908 static int __init skge_init_module(void)
3909 {
3910 return pci_register_driver(&skge_driver);
3911 }
3912
3913 static void __exit skge_cleanup_module(void)
3914 {
3915 pci_unregister_driver(&skge_driver);
3916 }
3917
3918 module_init(skge_init_module);
3919 module_exit(skge_cleanup_module);
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