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drm/i915: memory leak in __i915_gem_vma_create()
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
blobcbf013fd6b984dc63659b66544adc1d7eb80a777
1 /*
2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
26 #include <linux/seq_file.h>
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "i915_drv.h"
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33
34 /**
35 * DOC: Global GTT views
36 *
37 * Background and previous state
38 *
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
42 *
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
46 *
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
49 * (2x2 pages):
50 *
51 * 12
52 * 34
53 *
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
57 *
58 * 1212
59 * 3434
60 *
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
63 *
64 * Implementation and usage
65 *
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
68 *
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
73 *
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
78 *
79 * Code wanting to add or use a new GGTT view needs to:
80 *
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
84 *
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
88 *
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
92 *
93 */
94
95 const struct i915_ggtt_view i915_ggtt_view_normal;
96
97 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
98 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
99
100 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
101 {
102 bool has_aliasing_ppgtt;
103 bool has_full_ppgtt;
104
105 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
106 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
107
108 if (intel_vgpu_active(dev))
109 has_full_ppgtt = false; /* emulation is too hard */
110
111 /*
112 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
113 * execlists, the sole mechanism available to submit work.
114 */
115 if (INTEL_INFO(dev)->gen < 9 &&
116 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
117 return 0;
118
119 if (enable_ppgtt == 1)
120 return 1;
121
122 if (enable_ppgtt == 2 && has_full_ppgtt)
123 return 2;
124
125 #ifdef CONFIG_INTEL_IOMMU
126 /* Disable ppgtt on SNB if VT-d is on. */
127 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
128 DRM_INFO("Disabling PPGTT because VT-d is on\n");
129 return 0;
130 }
131 #endif
132
133 /* Early VLV doesn't have this */
134 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
135 dev->pdev->revision < 0xb) {
136 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
137 return 0;
138 }
139
140 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
141 return 2;
142 else
143 return has_aliasing_ppgtt ? 1 : 0;
144 }
145
146 static void ppgtt_bind_vma(struct i915_vma *vma,
147 enum i915_cache_level cache_level,
148 u32 flags);
149 static void ppgtt_unbind_vma(struct i915_vma *vma);
150
151 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
152 enum i915_cache_level level,
153 bool valid)
154 {
155 gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
156 pte |= addr;
157
158 switch (level) {
159 case I915_CACHE_NONE:
160 pte |= PPAT_UNCACHED_INDEX;
161 break;
162 case I915_CACHE_WT:
163 pte |= PPAT_DISPLAY_ELLC_INDEX;
164 break;
165 default:
166 pte |= PPAT_CACHED_INDEX;
167 break;
168 }
169
170 return pte;
171 }
172
173 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
174 dma_addr_t addr,
175 enum i915_cache_level level)
176 {
177 gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
178 pde |= addr;
179 if (level != I915_CACHE_NONE)
180 pde |= PPAT_CACHED_PDE_INDEX;
181 else
182 pde |= PPAT_UNCACHED_INDEX;
183 return pde;
184 }
185
186 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
187 enum i915_cache_level level,
188 bool valid, u32 unused)
189 {
190 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
191 pte |= GEN6_PTE_ADDR_ENCODE(addr);
192
193 switch (level) {
194 case I915_CACHE_L3_LLC:
195 case I915_CACHE_LLC:
196 pte |= GEN6_PTE_CACHE_LLC;
197 break;
198 case I915_CACHE_NONE:
199 pte |= GEN6_PTE_UNCACHED;
200 break;
201 default:
202 MISSING_CASE(level);
203 }
204
205 return pte;
206 }
207
208 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
209 enum i915_cache_level level,
210 bool valid, u32 unused)
211 {
212 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
213 pte |= GEN6_PTE_ADDR_ENCODE(addr);
214
215 switch (level) {
216 case I915_CACHE_L3_LLC:
217 pte |= GEN7_PTE_CACHE_L3_LLC;
218 break;
219 case I915_CACHE_LLC:
220 pte |= GEN6_PTE_CACHE_LLC;
221 break;
222 case I915_CACHE_NONE:
223 pte |= GEN6_PTE_UNCACHED;
224 break;
225 default:
226 MISSING_CASE(level);
227 }
228
229 return pte;
230 }
231
232 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
233 enum i915_cache_level level,
234 bool valid, u32 flags)
235 {
236 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
237 pte |= GEN6_PTE_ADDR_ENCODE(addr);
238
239 if (!(flags & PTE_READ_ONLY))
240 pte |= BYT_PTE_WRITEABLE;
241
242 if (level != I915_CACHE_NONE)
243 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
244
245 return pte;
246 }
247
248 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
249 enum i915_cache_level level,
250 bool valid, u32 unused)
251 {
252 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
253 pte |= HSW_PTE_ADDR_ENCODE(addr);
254
255 if (level != I915_CACHE_NONE)
256 pte |= HSW_WB_LLC_AGE3;
257
258 return pte;
259 }
260
261 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
262 enum i915_cache_level level,
263 bool valid, u32 unused)
264 {
265 gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
266 pte |= HSW_PTE_ADDR_ENCODE(addr);
267
268 switch (level) {
269 case I915_CACHE_NONE:
270 break;
271 case I915_CACHE_WT:
272 pte |= HSW_WT_ELLC_LLC_AGE3;
273 break;
274 default:
275 pte |= HSW_WB_ELLC_LLC_AGE3;
276 break;
277 }
278
279 return pte;
280 }
281
282 static void unmap_and_free_pt(struct i915_page_table_entry *pt, struct drm_device *dev)
283 {
284 if (WARN_ON(!pt->page))
285 return;
286 __free_page(pt->page);
287 kfree(pt);
288 }
289
290 static struct i915_page_table_entry *alloc_pt_single(struct drm_device *dev)
291 {
292 struct i915_page_table_entry *pt;
293
294 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
295 if (!pt)
296 return ERR_PTR(-ENOMEM);
297
298 pt->page = alloc_page(GFP_KERNEL | __GFP_ZERO);
299 if (!pt->page) {
300 kfree(pt);
301 return ERR_PTR(-ENOMEM);
302 }
303
304 return pt;
305 }
306
307 /**
308 * alloc_pt_range() - Allocate a multiple page tables
309 * @pd: The page directory which will have at least @count entries
310 * available to point to the allocated page tables.
311 * @pde: First page directory entry for which we are allocating.
312 * @count: Number of pages to allocate.
313 * @dev: DRM device.
314 *
315 * Allocates multiple page table pages and sets the appropriate entries in the
316 * page table structure within the page directory. Function cleans up after
317 * itself on any failures.
318 *
319 * Return: 0 if allocation succeeded.
320 */
321 static int alloc_pt_range(struct i915_page_directory_entry *pd, uint16_t pde, size_t count,
322 struct drm_device *dev)
323 {
324 int i, ret;
325
326 /* 512 is the max page tables per page_directory on any platform. */
327 if (WARN_ON(pde + count > GEN6_PPGTT_PD_ENTRIES))
328 return -EINVAL;
329
330 for (i = pde; i < pde + count; i++) {
331 struct i915_page_table_entry *pt = alloc_pt_single(dev);
332
333 if (IS_ERR(pt)) {
334 ret = PTR_ERR(pt);
335 goto err_out;
336 }
337 WARN(pd->page_table[i],
338 "Leaking page directory entry %d (%p)\n",
339 i, pd->page_table[i]);
340 pd->page_table[i] = pt;
341 }
342
343 return 0;
344
345 err_out:
346 while (i-- > pde)
347 unmap_and_free_pt(pd->page_table[i], dev);
348 return ret;
349 }
350
351 static void unmap_and_free_pd(struct i915_page_directory_entry *pd)
352 {
353 if (pd->page) {
354 __free_page(pd->page);
355 kfree(pd);
356 }
357 }
358
359 static struct i915_page_directory_entry *alloc_pd_single(void)
360 {
361 struct i915_page_directory_entry *pd;
362
363 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
364 if (!pd)
365 return ERR_PTR(-ENOMEM);
366
367 pd->page = alloc_page(GFP_KERNEL | __GFP_ZERO);
368 if (!pd->page) {
369 kfree(pd);
370 return ERR_PTR(-ENOMEM);
371 }
372
373 return pd;
374 }
375
376 /* Broadwell Page Directory Pointer Descriptors */
377 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
378 uint64_t val)
379 {
380 int ret;
381
382 BUG_ON(entry >= 4);
383
384 ret = intel_ring_begin(ring, 6);
385 if (ret)
386 return ret;
387
388 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
389 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
390 intel_ring_emit(ring, (u32)(val >> 32));
391 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
392 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
393 intel_ring_emit(ring, (u32)(val));
394 intel_ring_advance(ring);
395
396 return 0;
397 }
398
399 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
400 struct intel_engine_cs *ring)
401 {
402 int i, ret;
403
404 /* bit of a hack to find the actual last used pd */
405 int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
406
407 for (i = used_pd - 1; i >= 0; i--) {
408 dma_addr_t addr = ppgtt->pdp.page_directory[i]->daddr;
409 ret = gen8_write_pdp(ring, i, addr);
410 if (ret)
411 return ret;
412 }
413
414 return 0;
415 }
416
417 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
418 uint64_t start,
419 uint64_t length,
420 bool use_scratch)
421 {
422 struct i915_hw_ppgtt *ppgtt =
423 container_of(vm, struct i915_hw_ppgtt, base);
424 gen8_gtt_pte_t *pt_vaddr, scratch_pte;
425 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
426 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
427 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
428 unsigned num_entries = length >> PAGE_SHIFT;
429 unsigned last_pte, i;
430
431 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
432 I915_CACHE_LLC, use_scratch);
433
434 while (num_entries) {
435 struct i915_page_directory_entry *pd;
436 struct i915_page_table_entry *pt;
437 struct page *page_table;
438
439 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
440 continue;
441
442 pd = ppgtt->pdp.page_directory[pdpe];
443
444 if (WARN_ON(!pd->page_table[pde]))
445 continue;
446
447 pt = pd->page_table[pde];
448
449 if (WARN_ON(!pt->page))
450 continue;
451
452 page_table = pt->page;
453
454 last_pte = pte + num_entries;
455 if (last_pte > GEN8_PTES_PER_PAGE)
456 last_pte = GEN8_PTES_PER_PAGE;
457
458 pt_vaddr = kmap_atomic(page_table);
459
460 for (i = pte; i < last_pte; i++) {
461 pt_vaddr[i] = scratch_pte;
462 num_entries--;
463 }
464
465 if (!HAS_LLC(ppgtt->base.dev))
466 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
467 kunmap_atomic(pt_vaddr);
468
469 pte = 0;
470 if (++pde == GEN8_PDES_PER_PAGE) {
471 pdpe++;
472 pde = 0;
473 }
474 }
475 }
476
477 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
478 struct sg_table *pages,
479 uint64_t start,
480 enum i915_cache_level cache_level, u32 unused)
481 {
482 struct i915_hw_ppgtt *ppgtt =
483 container_of(vm, struct i915_hw_ppgtt, base);
484 gen8_gtt_pte_t *pt_vaddr;
485 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
486 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
487 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
488 struct sg_page_iter sg_iter;
489
490 pt_vaddr = NULL;
491
492 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
493 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
494 break;
495
496 if (pt_vaddr == NULL) {
497 struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[pdpe];
498 struct i915_page_table_entry *pt = pd->page_table[pde];
499 struct page *page_table = pt->page;
500
501 pt_vaddr = kmap_atomic(page_table);
502 }
503
504 pt_vaddr[pte] =
505 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
506 cache_level, true);
507 if (++pte == GEN8_PTES_PER_PAGE) {
508 if (!HAS_LLC(ppgtt->base.dev))
509 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
510 kunmap_atomic(pt_vaddr);
511 pt_vaddr = NULL;
512 if (++pde == GEN8_PDES_PER_PAGE) {
513 pdpe++;
514 pde = 0;
515 }
516 pte = 0;
517 }
518 }
519 if (pt_vaddr) {
520 if (!HAS_LLC(ppgtt->base.dev))
521 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
522 kunmap_atomic(pt_vaddr);
523 }
524 }
525
526 static void gen8_free_page_tables(struct i915_page_directory_entry *pd, struct drm_device *dev)
527 {
528 int i;
529
530 if (!pd->page)
531 return;
532
533 for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
534 if (WARN_ON(!pd->page_table[i]))
535 continue;
536
537 unmap_and_free_pt(pd->page_table[i], dev);
538 pd->page_table[i] = NULL;
539 }
540 }
541
542 static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
543 {
544 int i;
545
546 for (i = 0; i < ppgtt->num_pd_pages; i++) {
547 if (WARN_ON(!ppgtt->pdp.page_directory[i]))
548 continue;
549
550 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
551 unmap_and_free_pd(ppgtt->pdp.page_directory[i]);
552 }
553 }
554
555 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
556 {
557 struct pci_dev *hwdev = ppgtt->base.dev->pdev;
558 int i, j;
559
560 for (i = 0; i < ppgtt->num_pd_pages; i++) {
561 /* TODO: In the future we'll support sparse mappings, so this
562 * will have to change. */
563 if (!ppgtt->pdp.page_directory[i]->daddr)
564 continue;
565
566 pci_unmap_page(hwdev, ppgtt->pdp.page_directory[i]->daddr, PAGE_SIZE,
567 PCI_DMA_BIDIRECTIONAL);
568
569 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
570 struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i];
571 struct i915_page_table_entry *pt;
572 dma_addr_t addr;
573
574 if (WARN_ON(!pd->page_table[j]))
575 continue;
576
577 pt = pd->page_table[j];
578 addr = pt->daddr;
579
580 if (addr)
581 pci_unmap_page(hwdev, addr, PAGE_SIZE,
582 PCI_DMA_BIDIRECTIONAL);
583 }
584 }
585 }
586
587 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
588 {
589 struct i915_hw_ppgtt *ppgtt =
590 container_of(vm, struct i915_hw_ppgtt, base);
591
592 gen8_ppgtt_unmap_pages(ppgtt);
593 gen8_ppgtt_free(ppgtt);
594 }
595
596 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
597 {
598 int i, ret;
599
600 for (i = 0; i < ppgtt->num_pd_pages; i++) {
601 ret = alloc_pt_range(ppgtt->pdp.page_directory[i],
602 0, GEN8_PDES_PER_PAGE, ppgtt->base.dev);
603 if (ret)
604 goto unwind_out;
605 }
606
607 return 0;
608
609 unwind_out:
610 while (i--)
611 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
612
613 return -ENOMEM;
614 }
615
616 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
617 const int max_pdp)
618 {
619 int i;
620
621 for (i = 0; i < max_pdp; i++) {
622 ppgtt->pdp.page_directory[i] = alloc_pd_single();
623 if (IS_ERR(ppgtt->pdp.page_directory[i]))
624 goto unwind_out;
625 }
626
627 ppgtt->num_pd_pages = max_pdp;
628 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPES);
629
630 return 0;
631
632 unwind_out:
633 while (i--)
634 unmap_and_free_pd(ppgtt->pdp.page_directory[i]);
635
636 return -ENOMEM;
637 }
638
639 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
640 const int max_pdp)
641 {
642 int ret;
643
644 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
645 if (ret)
646 return ret;
647
648 ret = gen8_ppgtt_allocate_page_tables(ppgtt);
649 if (ret)
650 goto err_out;
651
652 ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
653
654 return 0;
655
656 err_out:
657 gen8_ppgtt_free(ppgtt);
658 return ret;
659 }
660
661 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
662 const int pd)
663 {
664 dma_addr_t pd_addr;
665 int ret;
666
667 pd_addr = pci_map_page(ppgtt->base.dev->pdev,
668 ppgtt->pdp.page_directory[pd]->page, 0,
669 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
670
671 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
672 if (ret)
673 return ret;
674
675 ppgtt->pdp.page_directory[pd]->daddr = pd_addr;
676
677 return 0;
678 }
679
680 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
681 const int pd,
682 const int pt)
683 {
684 dma_addr_t pt_addr;
685 struct i915_page_directory_entry *pdir = ppgtt->pdp.page_directory[pd];
686 struct i915_page_table_entry *ptab = pdir->page_table[pt];
687 struct page *p = ptab->page;
688 int ret;
689
690 pt_addr = pci_map_page(ppgtt->base.dev->pdev,
691 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
692 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
693 if (ret)
694 return ret;
695
696 ptab->daddr = pt_addr;
697
698 return 0;
699 }
700
701 /**
702 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
703 * with a net effect resembling a 2-level page table in normal x86 terms. Each
704 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
705 * space.
706 *
707 * FIXME: split allocation into smaller pieces. For now we only ever do this
708 * once, but with full PPGTT, the multiple contiguous allocations will be bad.
709 * TODO: Do something with the size parameter
710 */
711 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
712 {
713 const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
714 const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
715 int i, j, ret;
716
717 if (size % (1<<30))
718 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size);
719
720 /* 1. Do all our allocations for page directories and page tables.
721 * We allocate more than was asked so that we can point the unused parts
722 * to valid entries that point to scratch page. Dynamic page tables
723 * will fix this eventually.
724 */
725 ret = gen8_ppgtt_alloc(ppgtt, GEN8_LEGACY_PDPES);
726 if (ret)
727 return ret;
728
729 /*
730 * 2. Create DMA mappings for the page directories and page tables.
731 */
732 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
733 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
734 if (ret)
735 goto bail;
736
737 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
738 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
739 if (ret)
740 goto bail;
741 }
742 }
743
744 /*
745 * 3. Map all the page directory entires to point to the page tables
746 * we've allocated.
747 *
748 * For now, the PPGTT helper functions all require that the PDEs are
749 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
750 * will never need to touch the PDEs again.
751 */
752 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
753 struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i];
754 gen8_ppgtt_pde_t *pd_vaddr;
755 pd_vaddr = kmap_atomic(ppgtt->pdp.page_directory[i]->page);
756 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
757 struct i915_page_table_entry *pt = pd->page_table[j];
758 dma_addr_t addr = pt->daddr;
759 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
760 I915_CACHE_LLC);
761 }
762 if (!HAS_LLC(ppgtt->base.dev))
763 drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
764 kunmap_atomic(pd_vaddr);
765 }
766
767 ppgtt->switch_mm = gen8_mm_switch;
768 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
769 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
770 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
771 ppgtt->base.start = 0;
772
773 /* This is the area that we advertise as usable for the caller */
774 ppgtt->base.total = max_pdp * GEN8_PDES_PER_PAGE * GEN8_PTES_PER_PAGE * PAGE_SIZE;
775
776 /* Set all ptes to a valid scratch page. Also above requested space */
777 ppgtt->base.clear_range(&ppgtt->base, 0,
778 ppgtt->num_pd_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE,
779 true);
780
781 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
782 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
783 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n",
784 ppgtt->num_pd_entries,
785 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
786 return 0;
787
788 bail:
789 gen8_ppgtt_unmap_pages(ppgtt);
790 gen8_ppgtt_free(ppgtt);
791 return ret;
792 }
793
794 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
795 {
796 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
797 struct i915_address_space *vm = &ppgtt->base;
798 gen6_gtt_pte_t __iomem *pd_addr;
799 gen6_gtt_pte_t scratch_pte;
800 uint32_t pd_entry;
801 int pte, pde;
802
803 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
804
805 pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
806 ppgtt->pd.pd_offset / sizeof(gen6_gtt_pte_t);
807
808 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm,
809 ppgtt->pd.pd_offset,
810 ppgtt->pd.pd_offset + ppgtt->num_pd_entries);
811 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
812 u32 expected;
813 gen6_gtt_pte_t *pt_vaddr;
814 dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr;
815 pd_entry = readl(pd_addr + pde);
816 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
817
818 if (pd_entry != expected)
819 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
820 pde,
821 pd_entry,
822 expected);
823 seq_printf(m, "\tPDE: %x\n", pd_entry);
824
825 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page);
826 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
827 unsigned long va =
828 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
829 (pte * PAGE_SIZE);
830 int i;
831 bool found = false;
832 for (i = 0; i < 4; i++)
833 if (pt_vaddr[pte + i] != scratch_pte)
834 found = true;
835 if (!found)
836 continue;
837
838 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
839 for (i = 0; i < 4; i++) {
840 if (pt_vaddr[pte + i] != scratch_pte)
841 seq_printf(m, " %08x", pt_vaddr[pte + i]);
842 else
843 seq_puts(m, " SCRATCH ");
844 }
845 seq_puts(m, "\n");
846 }
847 kunmap_atomic(pt_vaddr);
848 }
849 }
850
851 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
852 {
853 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
854 gen6_gtt_pte_t __iomem *pd_addr;
855 uint32_t pd_entry;
856 int i;
857
858 WARN_ON(ppgtt->pd.pd_offset & 0x3f);
859 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
860 ppgtt->pd.pd_offset / sizeof(gen6_gtt_pte_t);
861 for (i = 0; i < ppgtt->num_pd_entries; i++) {
862 dma_addr_t pt_addr;
863
864 pt_addr = ppgtt->pd.page_table[i]->daddr;
865 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
866 pd_entry |= GEN6_PDE_VALID;
867
868 writel(pd_entry, pd_addr + i);
869 }
870 readl(pd_addr);
871 }
872
873 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
874 {
875 BUG_ON(ppgtt->pd.pd_offset & 0x3f);
876
877 return (ppgtt->pd.pd_offset / 64) << 16;
878 }
879
880 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
881 struct intel_engine_cs *ring)
882 {
883 int ret;
884
885 /* NB: TLBs must be flushed and invalidated before a switch */
886 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
887 if (ret)
888 return ret;
889
890 ret = intel_ring_begin(ring, 6);
891 if (ret)
892 return ret;
893
894 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
895 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
896 intel_ring_emit(ring, PP_DIR_DCLV_2G);
897 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
898 intel_ring_emit(ring, get_pd_offset(ppgtt));
899 intel_ring_emit(ring, MI_NOOP);
900 intel_ring_advance(ring);
901
902 return 0;
903 }
904
905 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
906 struct intel_engine_cs *ring)
907 {
908 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
909
910 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
911 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
912 return 0;
913 }
914
915 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
916 struct intel_engine_cs *ring)
917 {
918 int ret;
919
920 /* NB: TLBs must be flushed and invalidated before a switch */
921 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
922 if (ret)
923 return ret;
924
925 ret = intel_ring_begin(ring, 6);
926 if (ret)
927 return ret;
928
929 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
930 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
931 intel_ring_emit(ring, PP_DIR_DCLV_2G);
932 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
933 intel_ring_emit(ring, get_pd_offset(ppgtt));
934 intel_ring_emit(ring, MI_NOOP);
935 intel_ring_advance(ring);
936
937 /* XXX: RCS is the only one to auto invalidate the TLBs? */
938 if (ring->id != RCS) {
939 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
940 if (ret)
941 return ret;
942 }
943
944 return 0;
945 }
946
947 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
948 struct intel_engine_cs *ring)
949 {
950 struct drm_device *dev = ppgtt->base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952
953
954 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
955 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
956
957 POSTING_READ(RING_PP_DIR_DCLV(ring));
958
959 return 0;
960 }
961
962 static void gen8_ppgtt_enable(struct drm_device *dev)
963 {
964 struct drm_i915_private *dev_priv = dev->dev_private;
965 struct intel_engine_cs *ring;
966 int j;
967
968 for_each_ring(ring, dev_priv, j) {
969 I915_WRITE(RING_MODE_GEN7(ring),
970 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
971 }
972 }
973
974 static void gen7_ppgtt_enable(struct drm_device *dev)
975 {
976 struct drm_i915_private *dev_priv = dev->dev_private;
977 struct intel_engine_cs *ring;
978 uint32_t ecochk, ecobits;
979 int i;
980
981 ecobits = I915_READ(GAC_ECO_BITS);
982 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
983
984 ecochk = I915_READ(GAM_ECOCHK);
985 if (IS_HASWELL(dev)) {
986 ecochk |= ECOCHK_PPGTT_WB_HSW;
987 } else {
988 ecochk |= ECOCHK_PPGTT_LLC_IVB;
989 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
990 }
991 I915_WRITE(GAM_ECOCHK, ecochk);
992
993 for_each_ring(ring, dev_priv, i) {
994 /* GFX_MODE is per-ring on gen7+ */
995 I915_WRITE(RING_MODE_GEN7(ring),
996 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
997 }
998 }
999
1000 static void gen6_ppgtt_enable(struct drm_device *dev)
1001 {
1002 struct drm_i915_private *dev_priv = dev->dev_private;
1003 uint32_t ecochk, gab_ctl, ecobits;
1004
1005 ecobits = I915_READ(GAC_ECO_BITS);
1006 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1007 ECOBITS_PPGTT_CACHE64B);
1008
1009 gab_ctl = I915_READ(GAB_CTL);
1010 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1011
1012 ecochk = I915_READ(GAM_ECOCHK);
1013 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1014
1015 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1016 }
1017
1018 /* PPGTT support for Sandybdrige/Gen6 and later */
1019 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1020 uint64_t start,
1021 uint64_t length,
1022 bool use_scratch)
1023 {
1024 struct i915_hw_ppgtt *ppgtt =
1025 container_of(vm, struct i915_hw_ppgtt, base);
1026 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
1027 unsigned first_entry = start >> PAGE_SHIFT;
1028 unsigned num_entries = length >> PAGE_SHIFT;
1029 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
1030 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
1031 unsigned last_pte, i;
1032
1033 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
1034
1035 while (num_entries) {
1036 last_pte = first_pte + num_entries;
1037 if (last_pte > I915_PPGTT_PT_ENTRIES)
1038 last_pte = I915_PPGTT_PT_ENTRIES;
1039
1040 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1041
1042 for (i = first_pte; i < last_pte; i++)
1043 pt_vaddr[i] = scratch_pte;
1044
1045 kunmap_atomic(pt_vaddr);
1046
1047 num_entries -= last_pte - first_pte;
1048 first_pte = 0;
1049 act_pt++;
1050 }
1051 }
1052
1053 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1054 struct sg_table *pages,
1055 uint64_t start,
1056 enum i915_cache_level cache_level, u32 flags)
1057 {
1058 struct i915_hw_ppgtt *ppgtt =
1059 container_of(vm, struct i915_hw_ppgtt, base);
1060 gen6_gtt_pte_t *pt_vaddr;
1061 unsigned first_entry = start >> PAGE_SHIFT;
1062 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
1063 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
1064 struct sg_page_iter sg_iter;
1065
1066 pt_vaddr = NULL;
1067 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1068 if (pt_vaddr == NULL)
1069 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
1070
1071 pt_vaddr[act_pte] =
1072 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1073 cache_level, true, flags);
1074
1075 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
1076 kunmap_atomic(pt_vaddr);
1077 pt_vaddr = NULL;
1078 act_pt++;
1079 act_pte = 0;
1080 }
1081 }
1082 if (pt_vaddr)
1083 kunmap_atomic(pt_vaddr);
1084 }
1085
1086 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
1087 {
1088 int i;
1089
1090 for (i = 0; i < ppgtt->num_pd_entries; i++)
1091 pci_unmap_page(ppgtt->base.dev->pdev,
1092 ppgtt->pd.page_table[i]->daddr,
1093 4096, PCI_DMA_BIDIRECTIONAL);
1094 }
1095
1096 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
1097 {
1098 int i;
1099
1100 for (i = 0; i < ppgtt->num_pd_entries; i++)
1101 unmap_and_free_pt(ppgtt->pd.page_table[i], ppgtt->base.dev);
1102
1103 unmap_and_free_pd(&ppgtt->pd);
1104 }
1105
1106 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1107 {
1108 struct i915_hw_ppgtt *ppgtt =
1109 container_of(vm, struct i915_hw_ppgtt, base);
1110
1111 drm_mm_remove_node(&ppgtt->node);
1112
1113 gen6_ppgtt_unmap_pages(ppgtt);
1114 gen6_ppgtt_free(ppgtt);
1115 }
1116
1117 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1118 {
1119 struct drm_device *dev = ppgtt->base.dev;
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121 bool retried = false;
1122 int ret;
1123
1124 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1125 * allocator works in address space sizes, so it's multiplied by page
1126 * size. We allocate at the top of the GTT to avoid fragmentation.
1127 */
1128 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1129 alloc:
1130 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1131 &ppgtt->node, GEN6_PD_SIZE,
1132 GEN6_PD_ALIGN, 0,
1133 0, dev_priv->gtt.base.total,
1134 DRM_MM_TOPDOWN);
1135 if (ret == -ENOSPC && !retried) {
1136 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1137 GEN6_PD_SIZE, GEN6_PD_ALIGN,
1138 I915_CACHE_NONE,
1139 0, dev_priv->gtt.base.total,
1140 0);
1141 if (ret)
1142 return ret;
1143
1144 retried = true;
1145 goto alloc;
1146 }
1147
1148 if (ret)
1149 return ret;
1150
1151 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1152 DRM_DEBUG("Forced to use aperture for PDEs\n");
1153
1154 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
1155 return 0;
1156 }
1157
1158 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1159 {
1160 int ret;
1161
1162 ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1163 if (ret)
1164 return ret;
1165
1166 ret = alloc_pt_range(&ppgtt->pd, 0, ppgtt->num_pd_entries,
1167 ppgtt->base.dev);
1168
1169 if (ret) {
1170 drm_mm_remove_node(&ppgtt->node);
1171 return ret;
1172 }
1173
1174 return 0;
1175 }
1176
1177 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1178 {
1179 struct drm_device *dev = ppgtt->base.dev;
1180 int i;
1181
1182 for (i = 0; i < ppgtt->num_pd_entries; i++) {
1183 struct page *page;
1184 dma_addr_t pt_addr;
1185
1186 page = ppgtt->pd.page_table[i]->page;
1187 pt_addr = pci_map_page(dev->pdev, page, 0, 4096,
1188 PCI_DMA_BIDIRECTIONAL);
1189
1190 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1191 gen6_ppgtt_unmap_pages(ppgtt);
1192 return -EIO;
1193 }
1194
1195 ppgtt->pd.page_table[i]->daddr = pt_addr;
1196 }
1197
1198 return 0;
1199 }
1200
1201 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1202 {
1203 struct drm_device *dev = ppgtt->base.dev;
1204 struct drm_i915_private *dev_priv = dev->dev_private;
1205 int ret;
1206
1207 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1208 if (IS_GEN6(dev)) {
1209 ppgtt->switch_mm = gen6_mm_switch;
1210 } else if (IS_HASWELL(dev)) {
1211 ppgtt->switch_mm = hsw_mm_switch;
1212 } else if (IS_GEN7(dev)) {
1213 ppgtt->switch_mm = gen7_mm_switch;
1214 } else
1215 BUG();
1216
1217 if (intel_vgpu_active(dev))
1218 ppgtt->switch_mm = vgpu_mm_switch;
1219
1220 ret = gen6_ppgtt_alloc(ppgtt);
1221 if (ret)
1222 return ret;
1223
1224 ret = gen6_ppgtt_setup_page_tables(ppgtt);
1225 if (ret) {
1226 gen6_ppgtt_free(ppgtt);
1227 return ret;
1228 }
1229
1230 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1231 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1232 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1233 ppgtt->base.start = 0;
1234 ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1235 ppgtt->debug_dump = gen6_dump_ppgtt;
1236
1237 ppgtt->pd.pd_offset =
1238 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1239
1240 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1241
1242 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1243 ppgtt->node.size >> 20,
1244 ppgtt->node.start / PAGE_SIZE);
1245
1246 gen6_write_pdes(ppgtt);
1247 DRM_DEBUG("Adding PPGTT at offset %x\n",
1248 ppgtt->pd.pd_offset << 10);
1249
1250 return 0;
1251 }
1252
1253 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1254 {
1255 struct drm_i915_private *dev_priv = dev->dev_private;
1256
1257 ppgtt->base.dev = dev;
1258 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1259
1260 if (INTEL_INFO(dev)->gen < 8)
1261 return gen6_ppgtt_init(ppgtt);
1262 else
1263 return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1264 }
1265 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1266 {
1267 struct drm_i915_private *dev_priv = dev->dev_private;
1268 int ret = 0;
1269
1270 ret = __hw_ppgtt_init(dev, ppgtt);
1271 if (ret == 0) {
1272 kref_init(&ppgtt->ref);
1273 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1274 ppgtt->base.total);
1275 i915_init_vm(dev_priv, &ppgtt->base);
1276 }
1277
1278 return ret;
1279 }
1280
1281 int i915_ppgtt_init_hw(struct drm_device *dev)
1282 {
1283 struct drm_i915_private *dev_priv = dev->dev_private;
1284 struct intel_engine_cs *ring;
1285 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1286 int i, ret = 0;
1287
1288 /* In the case of execlists, PPGTT is enabled by the context descriptor
1289 * and the PDPs are contained within the context itself. We don't
1290 * need to do anything here. */
1291 if (i915.enable_execlists)
1292 return 0;
1293
1294 if (!USES_PPGTT(dev))
1295 return 0;
1296
1297 if (IS_GEN6(dev))
1298 gen6_ppgtt_enable(dev);
1299 else if (IS_GEN7(dev))
1300 gen7_ppgtt_enable(dev);
1301 else if (INTEL_INFO(dev)->gen >= 8)
1302 gen8_ppgtt_enable(dev);
1303 else
1304 MISSING_CASE(INTEL_INFO(dev)->gen);
1305
1306 if (ppgtt) {
1307 for_each_ring(ring, dev_priv, i) {
1308 ret = ppgtt->switch_mm(ppgtt, ring);
1309 if (ret != 0)
1310 return ret;
1311 }
1312 }
1313
1314 return ret;
1315 }
1316 struct i915_hw_ppgtt *
1317 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1318 {
1319 struct i915_hw_ppgtt *ppgtt;
1320 int ret;
1321
1322 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1323 if (!ppgtt)
1324 return ERR_PTR(-ENOMEM);
1325
1326 ret = i915_ppgtt_init(dev, ppgtt);
1327 if (ret) {
1328 kfree(ppgtt);
1329 return ERR_PTR(ret);
1330 }
1331
1332 ppgtt->file_priv = fpriv;
1333
1334 trace_i915_ppgtt_create(&ppgtt->base);
1335
1336 return ppgtt;
1337 }
1338
1339 void i915_ppgtt_release(struct kref *kref)
1340 {
1341 struct i915_hw_ppgtt *ppgtt =
1342 container_of(kref, struct i915_hw_ppgtt, ref);
1343
1344 trace_i915_ppgtt_release(&ppgtt->base);
1345
1346 /* vmas should already be unbound */
1347 WARN_ON(!list_empty(&ppgtt->base.active_list));
1348 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1349
1350 list_del(&ppgtt->base.global_link);
1351 drm_mm_takedown(&ppgtt->base.mm);
1352
1353 ppgtt->base.cleanup(&ppgtt->base);
1354 kfree(ppgtt);
1355 }
1356
1357 static void
1358 ppgtt_bind_vma(struct i915_vma *vma,
1359 enum i915_cache_level cache_level,
1360 u32 flags)
1361 {
1362 /* Currently applicable only to VLV */
1363 if (vma->obj->gt_ro)
1364 flags |= PTE_READ_ONLY;
1365
1366 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1367 cache_level, flags);
1368 }
1369
1370 static void ppgtt_unbind_vma(struct i915_vma *vma)
1371 {
1372 vma->vm->clear_range(vma->vm,
1373 vma->node.start,
1374 vma->obj->base.size,
1375 true);
1376 }
1377
1378 extern int intel_iommu_gfx_mapped;
1379 /* Certain Gen5 chipsets require require idling the GPU before
1380 * unmapping anything from the GTT when VT-d is enabled.
1381 */
1382 static inline bool needs_idle_maps(struct drm_device *dev)
1383 {
1384 #ifdef CONFIG_INTEL_IOMMU
1385 /* Query intel_iommu to see if we need the workaround. Presumably that
1386 * was loaded first.
1387 */
1388 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1389 return true;
1390 #endif
1391 return false;
1392 }
1393
1394 static bool do_idling(struct drm_i915_private *dev_priv)
1395 {
1396 bool ret = dev_priv->mm.interruptible;
1397
1398 if (unlikely(dev_priv->gtt.do_idle_maps)) {
1399 dev_priv->mm.interruptible = false;
1400 if (i915_gpu_idle(dev_priv->dev)) {
1401 DRM_ERROR("Couldn't idle GPU\n");
1402 /* Wait a bit, in hopes it avoids the hang */
1403 udelay(10);
1404 }
1405 }
1406
1407 return ret;
1408 }
1409
1410 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1411 {
1412 if (unlikely(dev_priv->gtt.do_idle_maps))
1413 dev_priv->mm.interruptible = interruptible;
1414 }
1415
1416 void i915_check_and_clear_faults(struct drm_device *dev)
1417 {
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 struct intel_engine_cs *ring;
1420 int i;
1421
1422 if (INTEL_INFO(dev)->gen < 6)
1423 return;
1424
1425 for_each_ring(ring, dev_priv, i) {
1426 u32 fault_reg;
1427 fault_reg = I915_READ(RING_FAULT_REG(ring));
1428 if (fault_reg & RING_FAULT_VALID) {
1429 DRM_DEBUG_DRIVER("Unexpected fault\n"
1430 "\tAddr: 0x%08lx\n"
1431 "\tAddress space: %s\n"
1432 "\tSource ID: %d\n"
1433 "\tType: %d\n",
1434 fault_reg & PAGE_MASK,
1435 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1436 RING_FAULT_SRCID(fault_reg),
1437 RING_FAULT_FAULT_TYPE(fault_reg));
1438 I915_WRITE(RING_FAULT_REG(ring),
1439 fault_reg & ~RING_FAULT_VALID);
1440 }
1441 }
1442 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1443 }
1444
1445 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1446 {
1447 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1448 intel_gtt_chipset_flush();
1449 } else {
1450 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1451 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1452 }
1453 }
1454
1455 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1456 {
1457 struct drm_i915_private *dev_priv = dev->dev_private;
1458
1459 /* Don't bother messing with faults pre GEN6 as we have little
1460 * documentation supporting that it's a good idea.
1461 */
1462 if (INTEL_INFO(dev)->gen < 6)
1463 return;
1464
1465 i915_check_and_clear_faults(dev);
1466
1467 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1468 dev_priv->gtt.base.start,
1469 dev_priv->gtt.base.total,
1470 true);
1471
1472 i915_ggtt_flush(dev_priv);
1473 }
1474
1475 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1476 {
1477 struct drm_i915_private *dev_priv = dev->dev_private;
1478 struct drm_i915_gem_object *obj;
1479 struct i915_address_space *vm;
1480
1481 i915_check_and_clear_faults(dev);
1482
1483 /* First fill our portion of the GTT with scratch pages */
1484 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1485 dev_priv->gtt.base.start,
1486 dev_priv->gtt.base.total,
1487 true);
1488
1489 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1490 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1491 &dev_priv->gtt.base);
1492 if (!vma)
1493 continue;
1494
1495 i915_gem_clflush_object(obj, obj->pin_display);
1496 /* The bind_vma code tries to be smart about tracking mappings.
1497 * Unfortunately above, we've just wiped out the mappings
1498 * without telling our object about it. So we need to fake it.
1499 *
1500 * Bind is not expected to fail since this is only called on
1501 * resume and assumption is all requirements exist already.
1502 */
1503 vma->bound &= ~GLOBAL_BIND;
1504 WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND));
1505 }
1506
1507
1508 if (INTEL_INFO(dev)->gen >= 8) {
1509 if (IS_CHERRYVIEW(dev))
1510 chv_setup_private_ppat(dev_priv);
1511 else
1512 bdw_setup_private_ppat(dev_priv);
1513
1514 return;
1515 }
1516
1517 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1518 /* TODO: Perhaps it shouldn't be gen6 specific */
1519 if (i915_is_ggtt(vm)) {
1520 if (dev_priv->mm.aliasing_ppgtt)
1521 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1522 continue;
1523 }
1524
1525 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1526 }
1527
1528 i915_ggtt_flush(dev_priv);
1529 }
1530
1531 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1532 {
1533 if (obj->has_dma_mapping)
1534 return 0;
1535
1536 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1537 obj->pages->sgl, obj->pages->nents,
1538 PCI_DMA_BIDIRECTIONAL))
1539 return -ENOSPC;
1540
1541 return 0;
1542 }
1543
1544 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1545 {
1546 #ifdef writeq
1547 writeq(pte, addr);
1548 #else
1549 iowrite32((u32)pte, addr);
1550 iowrite32(pte >> 32, addr + 4);
1551 #endif
1552 }
1553
1554 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1555 struct sg_table *st,
1556 uint64_t start,
1557 enum i915_cache_level level, u32 unused)
1558 {
1559 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1560 unsigned first_entry = start >> PAGE_SHIFT;
1561 gen8_gtt_pte_t __iomem *gtt_entries =
1562 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1563 int i = 0;
1564 struct sg_page_iter sg_iter;
1565 dma_addr_t addr = 0; /* shut up gcc */
1566
1567 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1568 addr = sg_dma_address(sg_iter.sg) +
1569 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1570 gen8_set_pte(&gtt_entries[i],
1571 gen8_pte_encode(addr, level, true));
1572 i++;
1573 }
1574
1575 /*
1576 * XXX: This serves as a posting read to make sure that the PTE has
1577 * actually been updated. There is some concern that even though
1578 * registers and PTEs are within the same BAR that they are potentially
1579 * of NUMA access patterns. Therefore, even with the way we assume
1580 * hardware should work, we must keep this posting read for paranoia.
1581 */
1582 if (i != 0)
1583 WARN_ON(readq(&gtt_entries[i-1])
1584 != gen8_pte_encode(addr, level, true));
1585
1586 /* This next bit makes the above posting read even more important. We
1587 * want to flush the TLBs only after we're certain all the PTE updates
1588 * have finished.
1589 */
1590 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1591 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1592 }
1593
1594 /*
1595 * Binds an object into the global gtt with the specified cache level. The object
1596 * will be accessible to the GPU via commands whose operands reference offsets
1597 * within the global GTT as well as accessible by the GPU through the GMADR
1598 * mapped BAR (dev_priv->mm.gtt->gtt).
1599 */
1600 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1601 struct sg_table *st,
1602 uint64_t start,
1603 enum i915_cache_level level, u32 flags)
1604 {
1605 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1606 unsigned first_entry = start >> PAGE_SHIFT;
1607 gen6_gtt_pte_t __iomem *gtt_entries =
1608 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1609 int i = 0;
1610 struct sg_page_iter sg_iter;
1611 dma_addr_t addr = 0;
1612
1613 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1614 addr = sg_page_iter_dma_address(&sg_iter);
1615 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1616 i++;
1617 }
1618
1619 /* XXX: This serves as a posting read to make sure that the PTE has
1620 * actually been updated. There is some concern that even though
1621 * registers and PTEs are within the same BAR that they are potentially
1622 * of NUMA access patterns. Therefore, even with the way we assume
1623 * hardware should work, we must keep this posting read for paranoia.
1624 */
1625 if (i != 0) {
1626 unsigned long gtt = readl(&gtt_entries[i-1]);
1627 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1628 }
1629
1630 /* This next bit makes the above posting read even more important. We
1631 * want to flush the TLBs only after we're certain all the PTE updates
1632 * have finished.
1633 */
1634 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1635 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1636 }
1637
1638 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1639 uint64_t start,
1640 uint64_t length,
1641 bool use_scratch)
1642 {
1643 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1644 unsigned first_entry = start >> PAGE_SHIFT;
1645 unsigned num_entries = length >> PAGE_SHIFT;
1646 gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1647 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1648 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1649 int i;
1650
1651 if (WARN(num_entries > max_entries,
1652 "First entry = %d; Num entries = %d (max=%d)\n",
1653 first_entry, num_entries, max_entries))
1654 num_entries = max_entries;
1655
1656 scratch_pte = gen8_pte_encode(vm->scratch.addr,
1657 I915_CACHE_LLC,
1658 use_scratch);
1659 for (i = 0; i < num_entries; i++)
1660 gen8_set_pte(&gtt_base[i], scratch_pte);
1661 readl(gtt_base);
1662 }
1663
1664 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1665 uint64_t start,
1666 uint64_t length,
1667 bool use_scratch)
1668 {
1669 struct drm_i915_private *dev_priv = vm->dev->dev_private;
1670 unsigned first_entry = start >> PAGE_SHIFT;
1671 unsigned num_entries = length >> PAGE_SHIFT;
1672 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1673 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1674 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1675 int i;
1676
1677 if (WARN(num_entries > max_entries,
1678 "First entry = %d; Num entries = %d (max=%d)\n",
1679 first_entry, num_entries, max_entries))
1680 num_entries = max_entries;
1681
1682 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1683
1684 for (i = 0; i < num_entries; i++)
1685 iowrite32(scratch_pte, &gtt_base[i]);
1686 readl(gtt_base);
1687 }
1688
1689
1690 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1691 enum i915_cache_level cache_level,
1692 u32 unused)
1693 {
1694 const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1695 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1696 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1697
1698 BUG_ON(!i915_is_ggtt(vma->vm));
1699 intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags);
1700 vma->bound = GLOBAL_BIND;
1701 }
1702
1703 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1704 uint64_t start,
1705 uint64_t length,
1706 bool unused)
1707 {
1708 unsigned first_entry = start >> PAGE_SHIFT;
1709 unsigned num_entries = length >> PAGE_SHIFT;
1710 intel_gtt_clear_range(first_entry, num_entries);
1711 }
1712
1713 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1714 {
1715 const unsigned int first = vma->node.start >> PAGE_SHIFT;
1716 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1717
1718 BUG_ON(!i915_is_ggtt(vma->vm));
1719 vma->bound = 0;
1720 intel_gtt_clear_range(first, size);
1721 }
1722
1723 static void ggtt_bind_vma(struct i915_vma *vma,
1724 enum i915_cache_level cache_level,
1725 u32 flags)
1726 {
1727 struct drm_device *dev = vma->vm->dev;
1728 struct drm_i915_private *dev_priv = dev->dev_private;
1729 struct drm_i915_gem_object *obj = vma->obj;
1730 struct sg_table *pages = obj->pages;
1731
1732 /* Currently applicable only to VLV */
1733 if (obj->gt_ro)
1734 flags |= PTE_READ_ONLY;
1735
1736 if (i915_is_ggtt(vma->vm))
1737 pages = vma->ggtt_view.pages;
1738
1739 /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1740 * or we have a global mapping already but the cacheability flags have
1741 * changed, set the global PTEs.
1742 *
1743 * If there is an aliasing PPGTT it is anecdotally faster, so use that
1744 * instead if none of the above hold true.
1745 *
1746 * NB: A global mapping should only be needed for special regions like
1747 * "gtt mappable", SNB errata, or if specified via special execbuf
1748 * flags. At all other times, the GPU will use the aliasing PPGTT.
1749 */
1750 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1751 if (!(vma->bound & GLOBAL_BIND) ||
1752 (cache_level != obj->cache_level)) {
1753 vma->vm->insert_entries(vma->vm, pages,
1754 vma->node.start,
1755 cache_level, flags);
1756 vma->bound |= GLOBAL_BIND;
1757 }
1758 }
1759
1760 if (dev_priv->mm.aliasing_ppgtt &&
1761 (!(vma->bound & LOCAL_BIND) ||
1762 (cache_level != obj->cache_level))) {
1763 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1764 appgtt->base.insert_entries(&appgtt->base, pages,
1765 vma->node.start,
1766 cache_level, flags);
1767 vma->bound |= LOCAL_BIND;
1768 }
1769 }
1770
1771 static void ggtt_unbind_vma(struct i915_vma *vma)
1772 {
1773 struct drm_device *dev = vma->vm->dev;
1774 struct drm_i915_private *dev_priv = dev->dev_private;
1775 struct drm_i915_gem_object *obj = vma->obj;
1776
1777 if (vma->bound & GLOBAL_BIND) {
1778 vma->vm->clear_range(vma->vm,
1779 vma->node.start,
1780 obj->base.size,
1781 true);
1782 vma->bound &= ~GLOBAL_BIND;
1783 }
1784
1785 if (vma->bound & LOCAL_BIND) {
1786 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1787 appgtt->base.clear_range(&appgtt->base,
1788 vma->node.start,
1789 obj->base.size,
1790 true);
1791 vma->bound &= ~LOCAL_BIND;
1792 }
1793 }
1794
1795 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1796 {
1797 struct drm_device *dev = obj->base.dev;
1798 struct drm_i915_private *dev_priv = dev->dev_private;
1799 bool interruptible;
1800
1801 interruptible = do_idling(dev_priv);
1802
1803 if (!obj->has_dma_mapping)
1804 dma_unmap_sg(&dev->pdev->dev,
1805 obj->pages->sgl, obj->pages->nents,
1806 PCI_DMA_BIDIRECTIONAL);
1807
1808 undo_idling(dev_priv, interruptible);
1809 }
1810
1811 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1812 unsigned long color,
1813 u64 *start,
1814 u64 *end)
1815 {
1816 if (node->color != color)
1817 *start += 4096;
1818
1819 if (!list_empty(&node->node_list)) {
1820 node = list_entry(node->node_list.next,
1821 struct drm_mm_node,
1822 node_list);
1823 if (node->allocated && node->color != color)
1824 *end -= 4096;
1825 }
1826 }
1827
1828 static int i915_gem_setup_global_gtt(struct drm_device *dev,
1829 unsigned long start,
1830 unsigned long mappable_end,
1831 unsigned long end)
1832 {
1833 /* Let GEM Manage all of the aperture.
1834 *
1835 * However, leave one page at the end still bound to the scratch page.
1836 * There are a number of places where the hardware apparently prefetches
1837 * past the end of the object, and we've seen multiple hangs with the
1838 * GPU head pointer stuck in a batchbuffer bound at the last page of the
1839 * aperture. One page should be enough to keep any prefetching inside
1840 * of the aperture.
1841 */
1842 struct drm_i915_private *dev_priv = dev->dev_private;
1843 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1844 struct drm_mm_node *entry;
1845 struct drm_i915_gem_object *obj;
1846 unsigned long hole_start, hole_end;
1847 int ret;
1848
1849 BUG_ON(mappable_end > end);
1850
1851 /* Subtract the guard page ... */
1852 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1853
1854 dev_priv->gtt.base.start = start;
1855 dev_priv->gtt.base.total = end - start;
1856
1857 if (intel_vgpu_active(dev)) {
1858 ret = intel_vgt_balloon(dev);
1859 if (ret)
1860 return ret;
1861 }
1862
1863 if (!HAS_LLC(dev))
1864 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1865
1866 /* Mark any preallocated objects as occupied */
1867 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1868 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1869
1870 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1871 i915_gem_obj_ggtt_offset(obj), obj->base.size);
1872
1873 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1874 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1875 if (ret) {
1876 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
1877 return ret;
1878 }
1879 vma->bound |= GLOBAL_BIND;
1880 }
1881
1882 /* Clear any non-preallocated blocks */
1883 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1884 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1885 hole_start, hole_end);
1886 ggtt_vm->clear_range(ggtt_vm, hole_start,
1887 hole_end - hole_start, true);
1888 }
1889
1890 /* And finally clear the reserved guard page */
1891 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1892
1893 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
1894 struct i915_hw_ppgtt *ppgtt;
1895
1896 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1897 if (!ppgtt)
1898 return -ENOMEM;
1899
1900 ret = __hw_ppgtt_init(dev, ppgtt);
1901 if (ret != 0)
1902 return ret;
1903
1904 dev_priv->mm.aliasing_ppgtt = ppgtt;
1905 }
1906
1907 return 0;
1908 }
1909
1910 void i915_gem_init_global_gtt(struct drm_device *dev)
1911 {
1912 struct drm_i915_private *dev_priv = dev->dev_private;
1913 unsigned long gtt_size, mappable_size;
1914
1915 gtt_size = dev_priv->gtt.base.total;
1916 mappable_size = dev_priv->gtt.mappable_end;
1917
1918 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1919 }
1920
1921 void i915_global_gtt_cleanup(struct drm_device *dev)
1922 {
1923 struct drm_i915_private *dev_priv = dev->dev_private;
1924 struct i915_address_space *vm = &dev_priv->gtt.base;
1925
1926 if (dev_priv->mm.aliasing_ppgtt) {
1927 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1928
1929 ppgtt->base.cleanup(&ppgtt->base);
1930 }
1931
1932 if (drm_mm_initialized(&vm->mm)) {
1933 if (intel_vgpu_active(dev))
1934 intel_vgt_deballoon();
1935
1936 drm_mm_takedown(&vm->mm);
1937 list_del(&vm->global_link);
1938 }
1939
1940 vm->cleanup(vm);
1941 }
1942
1943 static int setup_scratch_page(struct drm_device *dev)
1944 {
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct page *page;
1947 dma_addr_t dma_addr;
1948
1949 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1950 if (page == NULL)
1951 return -ENOMEM;
1952 set_pages_uc(page, 1);
1953
1954 #ifdef CONFIG_INTEL_IOMMU
1955 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1956 PCI_DMA_BIDIRECTIONAL);
1957 if (pci_dma_mapping_error(dev->pdev, dma_addr))
1958 return -EINVAL;
1959 #else
1960 dma_addr = page_to_phys(page);
1961 #endif
1962 dev_priv->gtt.base.scratch.page = page;
1963 dev_priv->gtt.base.scratch.addr = dma_addr;
1964
1965 return 0;
1966 }
1967
1968 static void teardown_scratch_page(struct drm_device *dev)
1969 {
1970 struct drm_i915_private *dev_priv = dev->dev_private;
1971 struct page *page = dev_priv->gtt.base.scratch.page;
1972
1973 set_pages_wb(page, 1);
1974 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1975 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1976 __free_page(page);
1977 }
1978
1979 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1980 {
1981 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1982 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1983 return snb_gmch_ctl << 20;
1984 }
1985
1986 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1987 {
1988 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1989 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1990 if (bdw_gmch_ctl)
1991 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1992
1993 #ifdef CONFIG_X86_32
1994 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1995 if (bdw_gmch_ctl > 4)
1996 bdw_gmch_ctl = 4;
1997 #endif
1998
1999 return bdw_gmch_ctl << 20;
2000 }
2001
2002 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2003 {
2004 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2005 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2006
2007 if (gmch_ctrl)
2008 return 1 << (20 + gmch_ctrl);
2009
2010 return 0;
2011 }
2012
2013 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2014 {
2015 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2016 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2017 return snb_gmch_ctl << 25; /* 32 MB units */
2018 }
2019
2020 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2021 {
2022 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2023 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2024 return bdw_gmch_ctl << 25; /* 32 MB units */
2025 }
2026
2027 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2028 {
2029 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2030 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2031
2032 /*
2033 * 0x0 to 0x10: 32MB increments starting at 0MB
2034 * 0x11 to 0x16: 4MB increments starting at 8MB
2035 * 0x17 to 0x1d: 4MB increments start at 36MB
2036 */
2037 if (gmch_ctrl < 0x11)
2038 return gmch_ctrl << 25;
2039 else if (gmch_ctrl < 0x17)
2040 return (gmch_ctrl - 0x11 + 2) << 22;
2041 else
2042 return (gmch_ctrl - 0x17 + 9) << 22;
2043 }
2044
2045 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2046 {
2047 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2048 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2049
2050 if (gen9_gmch_ctl < 0xf0)
2051 return gen9_gmch_ctl << 25; /* 32 MB units */
2052 else
2053 /* 4MB increments starting at 0xf0 for 4MB */
2054 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2055 }
2056
2057 static int ggtt_probe_common(struct drm_device *dev,
2058 size_t gtt_size)
2059 {
2060 struct drm_i915_private *dev_priv = dev->dev_private;
2061 phys_addr_t gtt_phys_addr;
2062 int ret;
2063
2064 /* For Modern GENs the PTEs and register space are split in the BAR */
2065 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2066 (pci_resource_len(dev->pdev, 0) / 2);
2067
2068 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2069 if (!dev_priv->gtt.gsm) {
2070 DRM_ERROR("Failed to map the gtt page table\n");
2071 return -ENOMEM;
2072 }
2073
2074 ret = setup_scratch_page(dev);
2075 if (ret) {
2076 DRM_ERROR("Scratch setup failed\n");
2077 /* iounmap will also get called at remove, but meh */
2078 iounmap(dev_priv->gtt.gsm);
2079 }
2080
2081 return ret;
2082 }
2083
2084 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2085 * bits. When using advanced contexts each context stores its own PAT, but
2086 * writing this data shouldn't be harmful even in those cases. */
2087 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2088 {
2089 uint64_t pat;
2090
2091 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2092 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2093 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2094 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2095 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2096 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2097 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2098 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2099
2100 if (!USES_PPGTT(dev_priv->dev))
2101 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2102 * so RTL will always use the value corresponding to
2103 * pat_sel = 000".
2104 * So let's disable cache for GGTT to avoid screen corruptions.
2105 * MOCS still can be used though.
2106 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2107 * before this patch, i.e. the same uncached + snooping access
2108 * like on gen6/7 seems to be in effect.
2109 * - So this just fixes blitter/render access. Again it looks
2110 * like it's not just uncached access, but uncached + snooping.
2111 * So we can still hold onto all our assumptions wrt cpu
2112 * clflushing on LLC machines.
2113 */
2114 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2115
2116 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2117 * write would work. */
2118 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2119 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2120 }
2121
2122 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2123 {
2124 uint64_t pat;
2125
2126 /*
2127 * Map WB on BDW to snooped on CHV.
2128 *
2129 * Only the snoop bit has meaning for CHV, the rest is
2130 * ignored.
2131 *
2132 * The hardware will never snoop for certain types of accesses:
2133 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2134 * - PPGTT page tables
2135 * - some other special cycles
2136 *
2137 * As with BDW, we also need to consider the following for GT accesses:
2138 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2139 * so RTL will always use the value corresponding to
2140 * pat_sel = 000".
2141 * Which means we must set the snoop bit in PAT entry 0
2142 * in order to keep the global status page working.
2143 */
2144 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2145 GEN8_PPAT(1, 0) |
2146 GEN8_PPAT(2, 0) |
2147 GEN8_PPAT(3, 0) |
2148 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2149 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2150 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2151 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2152
2153 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2154 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2155 }
2156
2157 static int gen8_gmch_probe(struct drm_device *dev,
2158 size_t *gtt_total,
2159 size_t *stolen,
2160 phys_addr_t *mappable_base,
2161 unsigned long *mappable_end)
2162 {
2163 struct drm_i915_private *dev_priv = dev->dev_private;
2164 unsigned int gtt_size;
2165 u16 snb_gmch_ctl;
2166 int ret;
2167
2168 /* TODO: We're not aware of mappable constraints on gen8 yet */
2169 *mappable_base = pci_resource_start(dev->pdev, 2);
2170 *mappable_end = pci_resource_len(dev->pdev, 2);
2171
2172 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2173 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2174
2175 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2176
2177 if (INTEL_INFO(dev)->gen >= 9) {
2178 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2179 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2180 } else if (IS_CHERRYVIEW(dev)) {
2181 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2182 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2183 } else {
2184 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2185 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2186 }
2187
2188 *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
2189
2190 if (IS_CHERRYVIEW(dev))
2191 chv_setup_private_ppat(dev_priv);
2192 else
2193 bdw_setup_private_ppat(dev_priv);
2194
2195 ret = ggtt_probe_common(dev, gtt_size);
2196
2197 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2198 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2199
2200 return ret;
2201 }
2202
2203 static int gen6_gmch_probe(struct drm_device *dev,
2204 size_t *gtt_total,
2205 size_t *stolen,
2206 phys_addr_t *mappable_base,
2207 unsigned long *mappable_end)
2208 {
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210 unsigned int gtt_size;
2211 u16 snb_gmch_ctl;
2212 int ret;
2213
2214 *mappable_base = pci_resource_start(dev->pdev, 2);
2215 *mappable_end = pci_resource_len(dev->pdev, 2);
2216
2217 /* 64/512MB is the current min/max we actually know of, but this is just
2218 * a coarse sanity check.
2219 */
2220 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2221 DRM_ERROR("Unknown GMADR size (%lx)\n",
2222 dev_priv->gtt.mappable_end);
2223 return -ENXIO;
2224 }
2225
2226 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2227 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2228 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2229
2230 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2231
2232 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2233 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
2234
2235 ret = ggtt_probe_common(dev, gtt_size);
2236
2237 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2238 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2239
2240 return ret;
2241 }
2242
2243 static void gen6_gmch_remove(struct i915_address_space *vm)
2244 {
2245
2246 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2247
2248 iounmap(gtt->gsm);
2249 teardown_scratch_page(vm->dev);
2250 }
2251
2252 static int i915_gmch_probe(struct drm_device *dev,
2253 size_t *gtt_total,
2254 size_t *stolen,
2255 phys_addr_t *mappable_base,
2256 unsigned long *mappable_end)
2257 {
2258 struct drm_i915_private *dev_priv = dev->dev_private;
2259 int ret;
2260
2261 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2262 if (!ret) {
2263 DRM_ERROR("failed to set up gmch\n");
2264 return -EIO;
2265 }
2266
2267 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2268
2269 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2270 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2271
2272 if (unlikely(dev_priv->gtt.do_idle_maps))
2273 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2274
2275 return 0;
2276 }
2277
2278 static void i915_gmch_remove(struct i915_address_space *vm)
2279 {
2280 intel_gmch_remove();
2281 }
2282
2283 int i915_gem_gtt_init(struct drm_device *dev)
2284 {
2285 struct drm_i915_private *dev_priv = dev->dev_private;
2286 struct i915_gtt *gtt = &dev_priv->gtt;
2287 int ret;
2288
2289 if (INTEL_INFO(dev)->gen <= 5) {
2290 gtt->gtt_probe = i915_gmch_probe;
2291 gtt->base.cleanup = i915_gmch_remove;
2292 } else if (INTEL_INFO(dev)->gen < 8) {
2293 gtt->gtt_probe = gen6_gmch_probe;
2294 gtt->base.cleanup = gen6_gmch_remove;
2295 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2296 gtt->base.pte_encode = iris_pte_encode;
2297 else if (IS_HASWELL(dev))
2298 gtt->base.pte_encode = hsw_pte_encode;
2299 else if (IS_VALLEYVIEW(dev))
2300 gtt->base.pte_encode = byt_pte_encode;
2301 else if (INTEL_INFO(dev)->gen >= 7)
2302 gtt->base.pte_encode = ivb_pte_encode;
2303 else
2304 gtt->base.pte_encode = snb_pte_encode;
2305 } else {
2306 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2307 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2308 }
2309
2310 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2311 &gtt->mappable_base, &gtt->mappable_end);
2312 if (ret)
2313 return ret;
2314
2315 gtt->base.dev = dev;
2316
2317 /* GMADR is the PCI mmio aperture into the global GTT. */
2318 DRM_INFO("Memory usable by graphics device = %zdM\n",
2319 gtt->base.total >> 20);
2320 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2321 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2322 #ifdef CONFIG_INTEL_IOMMU
2323 if (intel_iommu_gfx_mapped)
2324 DRM_INFO("VT-d active for gfx access\n");
2325 #endif
2326 /*
2327 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2328 * user's requested state against the hardware/driver capabilities. We
2329 * do this now so that we can print out any log messages once rather
2330 * than every time we check intel_enable_ppgtt().
2331 */
2332 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2333 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2334
2335 return 0;
2336 }
2337
2338 static struct i915_vma *
2339 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
2340 struct i915_address_space *vm,
2341 const struct i915_ggtt_view *ggtt_view)
2342 {
2343 struct i915_vma *vma;
2344
2345 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2346 return ERR_PTR(-EINVAL);
2347 vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2348 if (vma == NULL)
2349 return ERR_PTR(-ENOMEM);
2350
2351 INIT_LIST_HEAD(&vma->vma_link);
2352 INIT_LIST_HEAD(&vma->mm_list);
2353 INIT_LIST_HEAD(&vma->exec_list);
2354 vma->vm = vm;
2355 vma->obj = obj;
2356
2357 if (INTEL_INFO(vm->dev)->gen >= 6) {
2358 if (i915_is_ggtt(vm)) {
2359 vma->ggtt_view = *ggtt_view;
2360
2361 vma->unbind_vma = ggtt_unbind_vma;
2362 vma->bind_vma = ggtt_bind_vma;
2363 } else {
2364 vma->unbind_vma = ppgtt_unbind_vma;
2365 vma->bind_vma = ppgtt_bind_vma;
2366 }
2367 } else {
2368 BUG_ON(!i915_is_ggtt(vm));
2369 vma->ggtt_view = *ggtt_view;
2370 vma->unbind_vma = i915_ggtt_unbind_vma;
2371 vma->bind_vma = i915_ggtt_bind_vma;
2372 }
2373
2374 list_add_tail(&vma->vma_link, &obj->vma_list);
2375 if (!i915_is_ggtt(vm))
2376 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2377
2378 return vma;
2379 }
2380
2381 struct i915_vma *
2382 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2383 struct i915_address_space *vm)
2384 {
2385 struct i915_vma *vma;
2386
2387 vma = i915_gem_obj_to_vma(obj, vm);
2388 if (!vma)
2389 vma = __i915_gem_vma_create(obj, vm,
2390 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2391
2392 return vma;
2393 }
2394
2395 struct i915_vma *
2396 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2397 const struct i915_ggtt_view *view)
2398 {
2399 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
2400 struct i915_vma *vma;
2401
2402 if (WARN_ON(!view))
2403 return ERR_PTR(-EINVAL);
2404
2405 vma = i915_gem_obj_to_ggtt_view(obj, view);
2406
2407 if (IS_ERR(vma))
2408 return vma;
2409
2410 if (!vma)
2411 vma = __i915_gem_vma_create(obj, ggtt, view);
2412
2413 return vma;
2414
2415 }
2416
2417
2418 static inline
2419 int i915_get_ggtt_vma_pages(struct i915_vma *vma)
2420 {
2421 if (vma->ggtt_view.pages)
2422 return 0;
2423
2424 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2425 vma->ggtt_view.pages = vma->obj->pages;
2426 else
2427 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2428 vma->ggtt_view.type);
2429
2430 if (!vma->ggtt_view.pages) {
2431 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2432 vma->ggtt_view.type);
2433 return -EINVAL;
2434 }
2435
2436 return 0;
2437 }
2438
2439 /**
2440 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2441 * @vma: VMA to map
2442 * @cache_level: mapping cache level
2443 * @flags: flags like global or local mapping
2444 *
2445 * DMA addresses are taken from the scatter-gather table of this object (or of
2446 * this VMA in case of non-default GGTT views) and PTE entries set up.
2447 * Note that DMA addresses are also the only part of the SG table we care about.
2448 */
2449 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2450 u32 flags)
2451 {
2452 if (i915_is_ggtt(vma->vm)) {
2453 int ret = i915_get_ggtt_vma_pages(vma);
2454
2455 if (ret)
2456 return ret;
2457 }
2458
2459 vma->bind_vma(vma, cache_level, flags);
2460
2461 return 0;
2462 }
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