| blob | 5c63ceb463d669702dba269d1f121200fc77040f |
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
35 #include <linux/delay.h>
41 /**
42 * t4_wait_op_done_val - wait until an operation is completed
43 * @adapter: the adapter performing the operation
44 * @reg: the register to check for completion
45 * @mask: a single-bit field within @reg that indicates completion
46 * @polarity: the value of the field when the operation is completed
47 * @attempts: number of check iterations
48 * @delay: delay in usecs between iterations
49 * @valp: where to store the value of the register at completion time
50 *
51 * Wait until an operation is completed by checking a bit in a register
52 * up to @attempts times. If @valp is not NULL the value of the register
53 * at the time it indicated completion is stored there. Returns 0 if the
54 * operation completes and -EAGAIN otherwise.
55 */
58 {
66 }
71 }
72 }
76 {
79 }
81 /**
82 * t4_set_reg_field - set a register field to a value
83 * @adapter: the adapter to program
84 * @addr: the register address
85 * @mask: specifies the portion of the register to modify
86 * @val: the new value for the register field
87 *
88 * Sets a register field specified by the supplied mask to the
89 * given value.
90 */
92 u32 val)
93 {
98 }
100 /**
101 * t4_read_indirect - read indirectly addressed registers
102 * @adap: the adapter
103 * @addr_reg: register holding the indirect address
104 * @data_reg: register holding the value of the indirect register
105 * @vals: where the read register values are stored
106 * @nregs: how many indirect registers to read
107 * @start_idx: index of first indirect register to read
108 *
109 * Reads registers that are accessed indirectly through an address/data
110 * register pair.
111 */
115 {
119 start_idx++;
120 }
121 }
123 /**
124 * t4_write_indirect - write indirectly addressed registers
125 * @adap: the adapter
126 * @addr_reg: register holding the indirect addresses
127 * @data_reg: register holding the value for the indirect registers
128 * @vals: values to write
129 * @nregs: how many indirect registers to write
130 * @start_idx: address of first indirect register to write
131 *
132 * Writes a sequential block of registers that are accessed indirectly
133 * through an address/data register pair.
134 */
138 {
142 }
143 }
145 /*
146 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
147 * mechanism. This guarantees that we get the real value even if we're
148 * operating within a Virtual Machine and the Hypervisor is trapping our
149 * Configuration Space accesses.
150 */
152 {
157 else
166 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
167 * Configuration Space read. (None of the other fields matter when
168 * ENABLE is 0 so a simple register write is easier than a
169 * read-modify-write via t4_set_reg_field().)
170 */
172 }
174 /*
175 * t4_report_fw_error - report firmware error
176 * @adap: the adapter
177 *
178 * The adapter firmware can indicate error conditions to the host.
179 * If the firmware has indicated an error, print out the reason for
180 * the firmware error.
181 */
183 {
193 };
194 u32 pcie_fw;
200 }
202 /*
203 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
204 */
206 u32 mbox_addr)
207 {
210 }
212 /*
213 * Handle a FW assertion reported in a mailbox.
214 */
216 {
224 }
227 {
238 }
240 /**
241 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
242 * @adap: the adapter
243 * @mbox: index of the mailbox to use
244 * @cmd: the command to write
245 * @size: command length in bytes
246 * @rpl: where to optionally store the reply
247 * @sleep_ok: if true we may sleep while awaiting command completion
248 * @timeout: time to wait for command to finish before timing out
249 *
250 * Sends the given command to FW through the selected mailbox and waits
251 * for the FW to execute the command. If @rpl is not %NULL it is used to
252 * store the FW's reply to the command. The command and its optional
253 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
254 * to respond. @sleep_ok determines whether we may sleep while awaiting
255 * the response. If sleeping is allowed we use progressive backoff
256 * otherwise we spin.
257 *
258 * The return value is 0 on success or a negative errno on failure. A
259 * failure can happen either because we are not able to execute the
260 * command or FW executes it but signals an error. In the latter case
261 * the return value is the error code indicated by FW (negated).
262 */
265 {
268 };
270 u32 v;
271 u64 res;
280 /*
281 * If the device is off-line, as in EEH, commands will time out.
282 * Fail them early so we don't waste time waiting.
283 */
307 delay_idx++;
317 }
325 }
331 }
332 }
339 }
343 {
345 FW_CMD_MAX_TIMEOUT);
346 }
349 {
350 u32 edc_ecc_err_addr_reg;
351 u32 rdata_reg;
356 }
360 }
371 rdata_reg,
383 }
385 /**
386 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
387 * @adap: the adapter
388 * @win: PCI-E Memory Window to use
389 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
390 * @addr: address within indicated memory type
391 * @len: amount of memory to transfer
392 * @hbuf: host memory buffer
393 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
394 *
395 * Reads/writes an [almost] arbitrary memory region in the firmware: the
396 * firmware memory address and host buffer must be aligned on 32-bit
397 * boudaries; the length may be arbitrary. The memory is transferred as
398 * a raw byte sequence from/to the firmware's memory. If this memory
399 * contains data structures which contain multi-byte integers, it's the
400 * caller's responsibility to perform appropriate byte order conversions.
401 */
404 {
409 /* Argument sanity checks ...
410 */
415 /* It's convenient to be able to handle lengths which aren't a
416 * multiple of 32-bits because we often end up transferring files to
417 * the firmware. So we'll handle that by normalizing the length here
418 * and then handling any residual transfer at the end.
419 */
423 /* Offset into the region of memory which is being accessed
424 * MEM_EDC0 = 0
425 * MEM_EDC1 = 1
426 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
427 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
428 */
434 MA_EXT_MEMORY0_BAR_A));
436 }
438 /* Determine the PCIE_MEM_ACCESS_OFFSET */
441 /* Each PCI-E Memory Window is programmed with a window size -- or
442 * "aperture" -- which controls the granularity of its mapping onto
443 * adapter memory. We need to grab that aperture in order to know
444 * how to use the specified window. The window is also programmed
445 * with the base address of the Memory Window in BAR0's address
446 * space. For T4 this is an absolute PCI-E Bus Address. For T5
447 * the address is relative to BAR0.
448 */
451 win));
458 /* Calculate our initial PCI-E Memory Window Position and Offset into
459 * that Window.
460 */
464 /* Set up initial PCI-E Memory Window to cover the start of our
465 * transfer. (Read it back to ensure that changes propagate before we
466 * attempt to use the new value.)
467 */
474 /* Transfer data to/from the adapter as long as there's an integral
475 * number of 32-bit transfers to complete.
476 *
477 * A note on Endianness issues:
478 *
479 * The "register" reads and writes below from/to the PCI-E Memory
480 * Window invoke the standard adapter Big-Endian to PCI-E Link
481 * Little-Endian "swizzel." As a result, if we have the following
482 * data in adapter memory:
483 *
484 * Memory: ... | b0 | b1 | b2 | b3 | ...
485 * Address: i+0 i+1 i+2 i+3
486 *
487 * Then a read of the adapter memory via the PCI-E Memory Window
488 * will yield:
489 *
490 * x = readl(i)
491 * 31 0
492 * [ b3 | b2 | b1 | b0 ]
493 *
494 * If this value is stored into local memory on a Little-Endian system
495 * it will show up correctly in local memory as:
496 *
497 * ( ..., b0, b1, b2, b3, ... )
498 *
499 * But on a Big-Endian system, the store will show up in memory
500 * incorrectly swizzled as:
501 *
502 * ( ..., b3, b2, b1, b0, ... )
503 *
504 * So we need to account for this in the reads and writes to the
505 * PCI-E Memory Window below by undoing the register read/write
506 * swizzels.
507 */
512 else
518 /* If we've reached the end of our current window aperture,
519 * move the PCI-E Memory Window on to the next. Note that
520 * doing this here after "len" may be 0 allows us to set up
521 * the PCI-E Memory Window for a possible final residual
522 * transfer below ...
523 */
532 win));
533 }
534 }
536 /* If the original transfer had a length which wasn't a multiple of
537 * 32-bits, now's where we need to finish off the transfer of the
538 * residual amount. The PCI-E Memory Window has already been moved
539 * above (if necessary) to cover this final transfer.
540 */
543 u32 word;
561 }
562 }
565 }
567 /* Return the specified PCI-E Configuration Space register from our Physical
568 * Function. We try first via a Firmware LDST Command since we prefer to let
569 * the firmware own all of these registers, but if that fails we go for it
570 * directly ourselves.
571 */
573 {
576 /* If fw_attach != 0, construct and send the Firmware LDST Command to
577 * retrieve the specified PCI-E Configuration Space register.
578 */
585 FW_CMD_REQUEST_F |
586 FW_CMD_READ_F |
587 ldst_addrspace);
594 /* If the LDST Command succeeds, return the result, otherwise
595 * fall through to reading it directly ourselves ...
596 */
601 else
602 /* Read the desired Configuration Space register via the PCI-E
603 * Backdoor mechanism.
604 */
607 }
609 /* Get the window based on base passed to it.
610 * Window aperture is currently unhandled, but there is no use case for it
611 * right now
612 */
614 u32 memwin_base)
615 {
616 u32 ret;
619 u32 bar0;
621 /* Truncation intentional: we only read the bottom 32-bits of
622 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
623 * mechanism to read BAR0 instead of using
624 * pci_resource_start() because we could be operating from
625 * within a Virtual Machine which is trapping our accesses to
626 * our Configuration Space and we need to set up the PCI-E
627 * Memory Window decoders with the actual addresses which will
628 * be coming across the PCI-E link.
629 */
636 /* For T5, only relative offset inside the PCIe BAR is passed */
638 }
640 }
642 /* Get the default utility window (win0) used by everyone */
644 {
647 }
649 /* Set up memory window for accessing adapter memory ranges. (Read
650 * back MA register to ensure that changes propagate before we attempt
651 * to use the new values.)
652 */
654 {
661 }
663 /**
664 * t4_get_regs_len - return the size of the chips register set
665 * @adapter: the adapter
666 *
667 * Returns the size of the chip's BAR0 register space.
668 */
670 {
680 }
685 }
687 /**
688 * t4_get_regs - read chip registers into provided buffer
689 * @adap: the adapter
690 * @buf: register buffer
691 * @buf_size: size (in bytes) of register buffer
692 *
693 * If the provided register buffer isn't large enough for the chip's
694 * full register range, the register dump will be truncated to the
695 * register buffer's size.
696 */
698 {
919 };
1359 };
1699 };
1706 /* Select the right set of register ranges to dump depending on the
1707 * adapter chip type.
1708 */
1729 }
1731 /* Clear the register buffer and insert the appropriate register
1732 * values selected by the above register ranges.
1733 */
1740 /* Iterate across the register range filling in the register
1741 * buffer but don't write past the end of the register buffer.
1742 */
1746 }
1747 }
1748 }
1750 #define EEPROM_STAT_ADDR 0x7bfc
1751 #define VPD_BASE 0x400
1752 #define VPD_BASE_OLD 0
1753 #define VPD_LEN 1024
1754 #define CHELSIO_VPD_UNIQUE_ID 0x82
1756 /**
1757 * t4_seeprom_wp - enable/disable EEPROM write protection
1758 * @adapter: the adapter
1759 * @enable: whether to enable or disable write protection
1760 *
1761 * Enables or disables write protection on the serial EEPROM.
1762 */
1764 {
1768 }
1770 /**
1771 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
1772 * @adapter: adapter to read
1773 * @p: where to store the parameters
1774 *
1775 * Reads card parameters stored in VPD EEPROM.
1776 */
1778 {
1788 /* Card information normally starts at VPD_BASE but early cards had
1789 * it at 0.
1790 */
1795 /* The VPD shall have a unique identifier specified by the PCI SIG.
1796 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
1797 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
1798 * is expected to automatically put this entry at the
1799 * beginning of the VPD.
1800 */
1811 }
1822 }
1830 }
1832 #define FIND_VPD_KW(var, name) do { \
1833 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
1834 if (var < 0) { \
1836 ret = -EINVAL; \
1837 goto out; \
1838 } \
1839 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
1840 } while (0)
1851 }
1857 #undef FIND_VPD_KW
1872 out:
1875 }
1877 /**
1878 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
1879 * @adapter: adapter to read
1880 * @p: where to store the parameters
1881 *
1882 * Reads card parameters stored in VPD EEPROM and retrieves the Core
1883 * Clock. This can only be called after a connection to the firmware
1884 * is established.
1885 */
1887 {
1891 /* Grab the raw VPD parameters.
1892 */
1897 /* Ask firmware for the Core Clock since it knows how to translate the
1898 * Reference Clock ('V2') VPD field into a Core Clock value ...
1899 */
1910 }
1912 /* serial flash and firmware constants */
1916 /* flash command opcodes */
1926 };
1928 /**
1929 * sf1_read - read data from the serial flash
1930 * @adapter: the adapter
1931 * @byte_cnt: number of bytes to read
1932 * @cont: whether another operation will be chained
1933 * @lock: whether to lock SF for PL access only
1934 * @valp: where to store the read data
1935 *
1936 * Reads up to 4 bytes of data from the serial flash. The location of
1937 * the read needs to be specified prior to calling this by issuing the
1938 * appropriate commands to the serial flash.
1939 */
1942 {
1955 }
1957 /**
1958 * sf1_write - write data to the serial flash
1959 * @adapter: the adapter
1960 * @byte_cnt: number of bytes to write
1961 * @cont: whether another operation will be chained
1962 * @lock: whether to lock SF for PL access only
1963 * @val: value to write
1964 *
1965 * Writes up to 4 bytes of data to the serial flash. The location of
1966 * the write needs to be specified prior to calling this by issuing the
1967 * appropriate commands to the serial flash.
1968 */
1971 {
1980 }
1982 /**
1983 * flash_wait_op - wait for a flash operation to complete
1984 * @adapter: the adapter
1985 * @attempts: max number of polls of the status register
1986 * @delay: delay between polls in ms
1987 *
1988 * Wait for a flash operation to complete by polling the status register.
1989 */
1991 {
1993 u32 status;
2005 }
2006 }
2008 /**
2009 * t4_read_flash - read words from serial flash
2010 * @adapter: the adapter
2011 * @addr: the start address for the read
2012 * @nwords: how many 32-bit words to read
2013 * @data: where to store the read data
2014 * @byte_oriented: whether to store data as bytes or as words
2015 *
2016 * Read the specified number of 32-bit words from the serial flash.
2017 * If @byte_oriented is set the read data is stored as a byte array
2018 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2019 * natural endianness.
2020 */
2023 {
2043 }
2045 }
2047 /**
2048 * t4_write_flash - write up to a page of data to the serial flash
2049 * @adapter: the adapter
2050 * @addr: the start address to write
2051 * @n: length of data to write in bytes
2052 * @data: the data to write
2053 *
2054 * Writes up to a page of data (256 bytes) to the serial flash starting
2055 * at the given address. All the data must be written to the same page.
2056 */
2059 {
2081 }
2088 /* Read the page to verify the write succeeded */
2096 addr);
2098 }
2101 unlock:
2104 }
2106 /**
2107 * t4_get_fw_version - read the firmware version
2108 * @adapter: the adapter
2109 * @vers: where to place the version
2110 *
2111 * Reads the FW version from flash.
2112 */
2114 {
2118 }
2120 /**
2121 * t4_get_tp_version - read the TP microcode version
2122 * @adapter: the adapter
2123 * @vers: where to place the version
2124 *
2125 * Reads the TP microcode version from flash.
2126 */
2128 {
2132 }
2134 /**
2135 * t4_get_exprom_version - return the Expansion ROM version (if any)
2136 * @adapter: the adapter
2137 * @vers: where to place the version
2138 *
2139 * Reads the Expansion ROM header from FLASH and returns the version
2140 * number (if present) through the @vers return value pointer. We return
2141 * this in the Firmware Version Format since it's convenient. Return
2142 * 0 on success, -ENOENT if no Expansion ROM is present.
2143 */
2145 {
2169 }
2171 /* Is the given firmware API compatible with the one the driver was compiled
2172 * with?
2173 */
2175 {
2177 /* short circuit if it's the exact same firmware version */
2181 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2185 #undef SAME_INTF
2188 }
2190 /* The firmware in the filesystem is usable, but should it be installed?
2191 * This routine explains itself in detail if it indicates the filesystem
2192 * firmware should be installed.
2193 */
2196 {
2202 }
2207 }
2211 install:
2220 }
2226 {
2233 /* Read the header of the firmware on the card */
2243 }
2251 }
2255 /* Common case: the firmware on the card is an exact match and
2256 * the filesystem one is an exact match too, or the filesystem
2257 * one is absent/incompatible.
2258 */
2269 }
2271 /* Installed successfully, update the cached header too. */
2275 }
2285 "chip state %d, "
2286 "driver compiled with %d.%d.%d.%d, "
2288 state,
2297 }
2299 /* We're using whatever's on the card and it's known to be good. */
2303 bye:
2305 }
2307 /**
2308 * t4_flash_erase_sectors - erase a range of flash sectors
2309 * @adapter: the adapter
2310 * @start: the first sector to erase
2311 * @end: the last sector to erase
2312 *
2313 * Erases the sectors in the given inclusive range.
2314 */
2316 {
2331 }
2332 start++;
2333 }
2336 }
2338 /**
2339 * t4_flash_cfg_addr - return the address of the flash configuration file
2340 * @adapter: the adapter
2341 *
2342 * Return the address within the flash where the Firmware Configuration
2343 * File is stored.
2344 */
2346 {
2349 else
2351 }
2353 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
2354 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
2355 * and emit an error message for mismatched firmware to save our caller the
2356 * effort ...
2357 */
2360 {
2361 /* The expression below will return FALSE for any unsupported adapter
2362 * which will keep us "honest" in the future ...
2363 */
2373 }
2375 /**
2376 * t4_load_fw - download firmware
2377 * @adap: the adapter
2378 * @fw_data: the firmware image to write
2379 * @size: image size
2380 *
2381 * Write the supplied firmware image to the card's serial flash.
2382 */
2384 {
2385 u32 csum;
2398 }
2403 }
2408 }
2411 FW_MAX_SIZE);
2413 }
2424 }
2431 /*
2432 * We write the correct version at the end so the driver can see a bad
2433 * version if the FW write fails. Start by writing a copy of the
2434 * first page with a bad version.
2435 */
2449 }
2454 out:
2457 ret);
2458 else
2461 }
2463 /**
2464 * t4_phy_fw_ver - return current PHY firmware version
2465 * @adap: the adapter
2466 * @phy_fw_ver: return value buffer for PHY firmware version
2467 *
2468 * Returns the current version of external PHY firmware on the
2469 * adapter.
2470 */
2472 {
2486 }
2488 /**
2489 * t4_load_phy_fw - download port PHY firmware
2490 * @adap: the adapter
2491 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
2492 * @win_lock: the lock to use to guard the memory copy
2493 * @phy_fw_version: function to check PHY firmware versions
2494 * @phy_fw_data: the PHY firmware image to write
2495 * @phy_fw_size: image size
2496 *
2497 * Transfer the specified PHY firmware to the adapter. If a non-NULL
2498 * @phy_fw_version is supplied, then it will be used to determine if
2499 * it's necessary to perform the transfer by comparing the version
2500 * of any existing adapter PHY firmware with that of the passed in
2501 * PHY firmware image. If @win_lock is non-NULL then it will be used
2502 * around the call to t4_memory_rw() which transfers the PHY firmware
2503 * to the adapter.
2504 *
2505 * A negative error number will be returned if an error occurs. If
2506 * version number support is available and there's no need to upgrade
2507 * the firmware, 0 will be returned. If firmware is successfully
2508 * transferred to the adapter, 1 will be retured.
2509 *
2510 * NOTE: some adapters only have local RAM to store the PHY firmware. As
2511 * a result, a RESET of the adapter would cause that RAM to lose its
2512 * contents. Thus, loading PHY firmware on such adapters must happen
2513 * after any FW_RESET_CMDs ...
2514 */
2519 {
2525 /* If we have version number support, then check to see if the adapter
2526 * already has up-to-date PHY firmware loaded.
2527 */
2538 }
2539 }
2541 /* Ask the firmware where it wants us to copy the PHY firmware image.
2542 * The size of the file requires a special version of the READ coommand
2543 * which will pass the file size via the values field in PARAMS_CMD and
2544 * retrieve the return value from firmware and place it in the same
2545 * buffer values
2546 */
2559 /* Copy the supplied PHY Firmware image to the adapter memory location
2560 * allocated by the adapter firmware.
2561 */
2566 T4_MEMORY_WRITE);
2572 /* Tell the firmware that the PHY firmware image has been written to
2573 * RAM and it can now start copying it over to the PHYs. The chip
2574 * firmware will RESET the affected PHYs as part of this operation
2575 * leaving them running the new PHY firmware image.
2576 */
2584 /* If we have version number support, then check to see that the new
2585 * firmware got loaded properly.
2586 */
2594 "version on adapter %#x, "
2598 }
2599 }
2602 }
2604 /**
2605 * t4_fwcache - firmware cache operation
2606 * @adap: the adapter
2607 * @op : the operation (flush or flush and invalidate)
2608 */
2610 {
2626 }
2631 {
2653 req++;
2654 rsp++;
2655 }
2658 }
2660 }
2663 {
2664 u32 cfg;
2678 }
2679 }
2681 }
2684 {
2695 }
2696 }
2698 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
2699 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
2700 FW_PORT_CAP_ANEG)
2702 /**
2703 * t4_link_l1cfg - apply link configuration to MAC/PHY
2704 * @phy: the PHY to setup
2705 * @mac: the MAC to setup
2706 * @lc: the requested link configuration
2707 *
2708 * Set up a port's MAC and PHY according to a desired link configuration.
2709 * - If the PHY can auto-negotiate first decide what to advertise, then
2710 * enable/disable auto-negotiation as desired, and reset.
2711 * - If the PHY does not auto-negotiate just reset it.
2712 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2713 * otherwise do it later based on the outcome of auto-negotiation.
2714 */
2717 {
2737 fc);
2746 }
2748 /**
2749 * t4_restart_aneg - restart autonegotiation
2750 * @adap: the adapter
2751 * @mbox: mbox to use for the FW command
2752 * @port: the port id
2753 *
2754 * Restarts autonegotiation for the selected port.
2755 */
2757 {
2769 }
2779 };
2781 /**
2782 * t4_handle_intr_status - table driven interrupt handler
2783 * @adapter: the adapter that generated the interrupt
2784 * @reg: the interrupt status register to process
2785 * @acts: table of interrupt actions
2786 *
2787 * A table driven interrupt handler that applies a set of masks to an
2788 * interrupt status word and performs the corresponding actions if the
2789 * interrupts described by the mask have occurred. The actions include
2790 * optionally emitting a warning or alert message. The table is terminated
2791 * by an entry specifying mask 0. Returns the number of fatal interrupt
2792 * conditions.
2793 */
2796 {
2805 fatal++;
2814 }
2819 }
2821 /*
2822 * Interrupt handler for the PCIE module.
2823 */
2825 {
2833 };
2845 };
2879 };
2919 };
2925 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
2926 sysbus_intr_info) +
2928 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
2929 pcie_port_intr_info) +
2931 pcie_intr_info);
2932 else
2934 t5_pcie_intr_info);
2938 }
2940 /*
2941 * TP interrupt handler.
2942 */
2944 {
2949 };
2953 }
2955 /*
2956 * SGE interrupt handler.
2957 */
2959 {
2960 u64 v;
2961 u32 err;
2985 };
2993 };
3002 }
3007 t4t5_sge_intr_info);
3017 UNCAPTURED_ERROR_F);
3018 }
3022 }
3024 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3025 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3026 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3027 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3029 /*
3030 * CIM interrupt handler.
3031 */
3033 {
3043 };
3074 };
3082 cim_intr_info) +
3084 cim_upintr_info);
3087 }
3089 /*
3090 * ULP RX interrupt handler.
3091 */
3093 {
3098 };
3102 }
3104 /*
3105 * ULP TX interrupt handler.
3106 */
3108 {
3120 };
3124 }
3126 /*
3127 * PM TX interrupt handler.
3128 */
3130 {
3143 };
3147 }
3149 /*
3150 * PM RX interrupt handler.
3151 */
3153 {
3163 };
3167 }
3169 /*
3170 * CPL switch interrupt handler.
3171 */
3173 {
3182 };
3186 }
3188 /*
3189 * LE interrupt handler.
3190 */
3192 {
3201 };
3210 };
3216 }
3218 /*
3219 * MPS interrupt handler.
3220 */
3222 {
3226 };
3238 };
3245 };
3249 };
3253 };
3257 };
3263 };
3268 mps_rx_intr_info) +
3270 mps_tx_intr_info) +
3272 mps_trc_intr_info) +
3274 mps_stat_sram_intr_info) +
3276 mps_stat_tx_intr_info) +
3278 mps_stat_rx_intr_info) +
3280 mps_cls_intr_info);
3286 }
3288 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
3289 ECC_UE_INT_CAUSE_F)
3291 /*
3292 * EDC/MC interrupt handler.
3293 */
3295 {
3310 }
3314 }
3330 }
3338 }
3340 /*
3341 * MA interrupt handler.
3342 */
3344 {
3355 MA_PARITY_ERROR_STATUS2_A));
3356 }
3363 }
3366 }
3368 /*
3369 * SMB interrupt handler.
3370 */
3372 {
3378 };
3382 }
3384 /*
3385 * NC-SI interrupt handler.
3386 */
3388 {
3395 };
3399 }
3401 /*
3402 * XGMAC interrupt handler.
3403 */
3405 {
3410 else
3421 port);
3424 port);
3427 }
3429 /*
3430 * PL interrupt handler.
3431 */
3433 {
3438 };
3442 }
3444 #define PF_INTR_MASK (PFSW_F)
3445 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
3446 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
3447 CPL_SWITCH_F | SGE_F | ULP_TX_F)
3449 /**
3450 * t4_slow_intr_handler - control path interrupt handler
3451 * @adapter: the adapter
3452 *
3453 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
3454 * The designation 'slow' is because it involves register reads, while
3455 * data interrupts typically don't involve any MMIOs.
3456 */
3458 {
3510 /* Clear the interrupts just processed for which we are the master. */
3514 }
3516 /**
3517 * t4_intr_enable - enable interrupts
3518 * @adapter: the adapter whose interrupts should be enabled
3519 *
3520 * Enable PF-specific interrupts for the calling function and the top-level
3521 * interrupt concentrator for global interrupts. Interrupts are already
3522 * enabled at each module, here we just enable the roots of the interrupt
3523 * hierarchies.
3524 *
3525 * Note: this function should be called only when the driver manages
3526 * non PF-specific interrupts from the various HW modules. Only one PCI
3527 * function at a time should be doing this.
3528 */
3530 {
3547 }
3549 /**
3550 * t4_intr_disable - disable interrupts
3551 * @adapter: the adapter whose interrupts should be disabled
3552 *
3553 * Disable interrupts. We only disable the top-level interrupt
3554 * concentrators. The caller must be a PCI function managing global
3555 * interrupts.
3556 */
3558 {
3565 }
3567 /**
3568 * hash_mac_addr - return the hash value of a MAC address
3569 * @addr: the 48-bit Ethernet MAC address
3570 *
3571 * Hashes a MAC address according to the hash function used by HW inexact
3572 * (hash) address matching.
3573 */
3575 {
3582 }
3584 /**
3585 * t4_config_rss_range - configure a portion of the RSS mapping table
3586 * @adapter: the adapter
3587 * @mbox: mbox to use for the FW command
3588 * @viid: virtual interface whose RSS subtable is to be written
3589 * @start: start entry in the table to write
3590 * @n: how many table entries to write
3591 * @rspq: values for the response queue lookup table
3592 * @nrspq: number of values in @rspq
3593 *
3594 * Programs the selected part of the VI's RSS mapping table with the
3595 * provided values. If @nrspq < @n the supplied values are used repeatedly
3596 * until the full table range is populated.
3597 *
3598 * The caller must ensure the values in @rspq are in the range allowed for
3599 * @viid.
3600 */
3603 {
3615 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
3641 }
3646 }
3648 }
3650 /**
3651 * t4_config_glbl_rss - configure the global RSS mode
3652 * @adapter: the adapter
3653 * @mbox: mbox to use for the FW command
3654 * @mode: global RSS mode
3655 * @flags: mode-specific flags
3656 *
3657 * Sets the global RSS mode.
3658 */
3661 {
3678 }
3680 /**
3681 * t4_config_vi_rss - configure per VI RSS settings
3682 * @adapter: the adapter
3683 * @mbox: mbox to use for the FW command
3684 * @viid: the VI id
3685 * @flags: RSS flags
3686 * @defq: id of the default RSS queue for the VI.
3687 *
3688 * Configures VI-specific RSS properties.
3689 */
3692 {
3703 }
3705 /* Read an RSS table row */
3707 {
3711 }
3713 /**
3714 * t4_read_rss - read the contents of the RSS mapping table
3715 * @adapter: the adapter
3716 * @map: holds the contents of the RSS mapping table
3717 *
3718 * Reads the contents of the RSS hash->queue mapping table.
3719 */
3721 {
3722 u32 val;
3731 }
3733 }
3736 {
3738 }
3740 /**
3741 * t4_fw_tp_pio_rw - Access TP PIO through LDST
3742 * @adap: the adapter
3743 * @vals: where the indirect register values are stored/written
3744 * @nregs: how many indirect registers to read/write
3745 * @start_idx: index of first indirect register to read/write
3746 * @rw: Read (1) or Write (0)
3747 *
3748 * Access TP PIO registers through LDST
3749 */
3752 {
3760 FW_CMD_REQUEST_F |
3762 FW_CMD_WRITE_F) |
3771 }
3772 }
3774 /**
3775 * t4_read_rss_key - read the global RSS key
3776 * @adap: the adapter
3777 * @key: 10-entry array holding the 320-bit RSS key
3778 *
3779 * Reads the global 320-bit RSS key.
3780 */
3782 {
3785 else
3787 TP_RSS_SECRET_KEY0_A);
3788 }
3790 /**
3791 * t4_write_rss_key - program one of the RSS keys
3792 * @adap: the adapter
3793 * @key: 10-entry array holding the 320-bit RSS key
3794 * @idx: which RSS key to write
3795 *
3796 * Writes one of the RSS keys with the given 320-bit value. If @idx is
3797 * 0..15 the corresponding entry in the RSS key table is written,
3798 * otherwise the global RSS key is written.
3799 */
3801 {
3805 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
3806 * allows access to key addresses 16-63 by using KeyWrAddrX
3807 * as index[5:4](upper 2) into key table
3808 */
3815 else
3817 TP_RSS_SECRET_KEY0_A);
3824 else
3827 }
3828 }
3830 /**
3831 * t4_read_rss_pf_config - read PF RSS Configuration Table
3832 * @adapter: the adapter
3833 * @index: the entry in the PF RSS table to read
3834 * @valp: where to store the returned value
3835 *
3836 * Reads the PF RSS Configuration Table at the specified index and returns
3837 * the value found there.
3838 */
3841 {
3845 else
3848 }
3850 /**
3851 * t4_read_rss_vf_config - read VF RSS Configuration Table
3852 * @adapter: the adapter
3853 * @index: the entry in the VF RSS table to read
3854 * @vfl: where to store the returned VFL
3855 * @vfh: where to store the returned VFH
3856 *
3857 * Reads the VF RSS Configuration Table at the specified index and returns
3858 * the (VFL, VFH) values found there.
3859 */
3862 {
3871 }
3873 /* Request that the index'th VF Table values be read into VFL/VFH.
3874 */
3880 /* Grab the VFL/VFH values ...
3881 */
3890 }
3891 }
3893 /**
3894 * t4_read_rss_pf_map - read PF RSS Map
3895 * @adapter: the adapter
3896 *
3897 * Reads the PF RSS Map register and returns its value.
3898 */
3900 {
3901 u32 pfmap;
3905 else
3909 }
3911 /**
3912 * t4_read_rss_pf_mask - read PF RSS Mask
3913 * @adapter: the adapter
3914 *
3915 * Reads the PF RSS Mask register and returns its value.
3916 */
3918 {
3919 u32 pfmask;
3923 else
3927 }
3929 /**
3930 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
3931 * @adap: the adapter
3932 * @v4: holds the TCP/IP counter values
3933 * @v6: holds the TCP/IPv6 counter values
3934 *
3935 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
3936 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
3937 */
3940 {
3943 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
3944 #define STAT(x) val[STAT_IDX(x)]
3945 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
3954 }
3962 }
3963 #undef STAT64
3964 #undef STAT
3965 #undef STAT_IDX
3966 }
3968 /**
3969 * t4_tp_get_err_stats - read TP's error MIB counters
3970 * @adap: the adapter
3971 * @st: holds the counter values
3972 *
3973 * Returns the values of TP's error counters.
3974 */
3976 {
3998 }
4000 /**
4001 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4002 * @adap: the adapter
4003 * @st: holds the counter values
4004 *
4005 * Returns the values of TP's CPL counters.
4006 */
4008 {
4016 }
4018 /**
4019 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4020 * @adap: the adapter
4021 * @st: holds the counter values
4022 *
4023 * Returns the values of TP's RDMA counters.
4024 */
4026 {
4029 }
4031 /**
4032 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4033 * @adap: the adapter
4034 * @idx: the port index
4035 * @st: holds the counter values
4036 *
4037 * Returns the values of TP's FCoE counters for the selected port.
4038 */
4041 {
4051 }
4053 /**
4054 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4055 * @adap: the adapter
4056 * @st: holds the counter values
4057 *
4058 * Returns the values of TP's counters for non-TCP directly-placed packets.
4059 */
4061 {
4065 TP_MIB_USM_PKTS_A);
4069 }
4071 /**
4072 * t4_read_mtu_tbl - returns the values in the HW path MTU table
4073 * @adap: the adapter
4074 * @mtus: where to store the MTU values
4075 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
4076 *
4077 * Reads the HW path MTU table.
4078 */
4080 {
4081 u32 v;
4091 }
4092 }
4094 /**
4095 * t4_read_cong_tbl - reads the congestion control table
4096 * @adap: the adapter
4097 * @incr: where to store the alpha values
4098 *
4099 * Reads the additive increments programmed into the HW congestion
4100 * control table.
4101 */
4103 {
4112 }
4113 }
4115 /**
4116 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
4117 * @adap: the adapter
4118 * @addr: the indirect TP register address
4119 * @mask: specifies the field within the register to modify
4120 * @val: new value for the field
4121 *
4122 * Sets a field of an indirect TP register to the given value.
4123 */
4126 {
4130 }
4132 /**
4133 * init_cong_ctrl - initialize congestion control parameters
4134 * @a: the alpha values for congestion control
4135 * @b: the beta values for congestion control
4136 *
4137 * Initialize the congestion control parameters.
4138 */
4140 {
4174 }
4176 /* The minimum additive increment value for the congestion control table */
4177 #define CC_MIN_INCR 2U
4179 /**
4180 * t4_load_mtus - write the MTU and congestion control HW tables
4181 * @adap: the adapter
4182 * @mtus: the values for the MTU table
4183 * @alpha: the values for the congestion control alpha parameter
4184 * @beta: the values for the congestion control beta parameter
4185 *
4186 * Write the HW MTU table with the supplied MTUs and the high-speed
4187 * congestion control table with the supplied alpha, beta, and MTUs.
4188 * We write the two tables together because the additive increments
4189 * depend on the MTUs.
4190 */
4193 {
4198 };
4207 log2--;
4215 CC_MIN_INCR);
4219 }
4220 }
4221 }
4223 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
4224 * clocks. The formula is
4225 *
4226 * bytes/s = bytes256 * 256 * ClkFreq / 4096
4227 *
4228 * which is equivalent to
4229 *
4230 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
4231 */
4233 {
4237 }
4239 /**
4240 * t4_get_chan_txrate - get the current per channel Tx rates
4241 * @adap: the adapter
4242 * @nic_rate: rates for NIC traffic
4243 * @ofld_rate: rates for offloaded traffic
4244 *
4245 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
4246 * for each channel.
4247 */
4249 {
4250 u32 v;
4258 }
4266 }
4267 }
4269 /**
4270 * t4_pmtx_get_stats - returns the HW stats from PMTX
4271 * @adap: the adapter
4272 * @cnt: where to store the count statistics
4273 * @cycles: where to store the cycle statistics
4274 *
4275 * Returns performance statistics from PMTX.
4276 */
4278 {
4290 PM_TX_DBG_STAT_MSB_A);
4292 }
4293 }
4294 }
4296 /**
4297 * t4_pmrx_get_stats - returns the HW stats from PMRX
4298 * @adap: the adapter
4299 * @cnt: where to store the count statistics
4300 * @cycles: where to store the cycle statistics
4301 *
4302 * Returns performance statistics from PMRX.
4303 */
4305 {
4317 PM_RX_DBG_STAT_MSB_A);
4319 }
4320 }
4321 }
4323 /**
4324 * t4_get_mps_bg_map - return the buffer groups associated with a port
4325 * @adap: the adapter
4326 * @idx: the port index
4327 *
4328 * Returns a bitmap indicating which MPS buffer groups are associated
4329 * with the given port. Bit i is set if buffer group i is used by the
4330 * port.
4331 */
4333 {
4341 }
4343 /**
4344 * t4_get_port_type_description - return Port Type string description
4345 * @port_type: firmware Port Type enumeration
4346 */
4348 {
4366 };
4371 }
4373 /**
4374 * t4_get_port_stats_offset - collect port stats relative to a previous
4375 * snapshot
4376 * @adap: The adapter
4377 * @idx: The port
4378 * @stats: Current stats to fill
4379 * @offset: Previous stats snapshot
4380 */
4384 {
4393 }
4395 /**
4396 * t4_get_port_stats - collect port statistics
4397 * @adap: the adapter
4398 * @idx: the port index
4399 * @p: the stats structure to fill
4400 *
4401 * Collect statistics related to the given port from HW.
4402 */
4404 {
4407 #define GET_STAT(name) \
4408 t4_read_reg64(adap, \
4409 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
4410 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
4411 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
4474 #undef GET_STAT
4475 #undef GET_STAT_COM
4476 }
4478 /**
4479 * t4_get_lb_stats - collect loopback port statistics
4480 * @adap: the adapter
4481 * @idx: the loopback port index
4482 * @p: the stats structure to fill
4483 *
4484 * Return HW statistics for the given loopback port.
4485 */
4487 {
4490 #define GET_STAT(name) \
4491 t4_read_reg64(adap, \
4492 (is_t4(adap->params.chip) ? \
4493 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
4494 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
4495 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
4522 #undef GET_STAT
4523 #undef GET_STAT_COM
4524 }
4526 /* t4_mk_filtdelwr - create a delete filter WR
4527 * @ftid: the filter ID
4528 * @wr: the filter work request to populate
4529 * @qid: ingress queue to receive the delete notification
4530 *
4531 * Creates a filter work request to delete the supplied filter. If @qid is
4532 * negative the delete notification is suppressed.
4533 */
4535 {
4545 }
4547 #define INIT_CMD(var, cmd, rd_wr) do { \
4548 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
4549 FW_CMD_REQUEST_F | \
4550 FW_CMD_##rd_wr##_F); \
4551 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
4552 } while (0)
4556 {
4557 u32 ldst_addrspace;
4563 FW_CMD_REQUEST_F |
4564 FW_CMD_WRITE_F |
4565 ldst_addrspace);
4571 }
4573 /**
4574 * t4_mdio_rd - read a PHY register through MDIO
4575 * @adap: the adapter
4576 * @mbox: mailbox to use for the FW command
4577 * @phy_addr: the PHY address
4578 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
4579 * @reg: the register to read
4580 * @valp: where to store the value
4581 *
4582 * Issues a FW command through the given mailbox to read a PHY register.
4583 */
4586 {
4588 u32 ldst_addrspace;
4595 ldst_addrspace);
4605 }
4607 /**
4608 * t4_mdio_wr - write a PHY register through MDIO
4609 * @adap: the adapter
4610 * @mbox: mailbox to use for the FW command
4611 * @phy_addr: the PHY address
4612 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
4613 * @reg: the register to write
4614 * @valp: value to write
4615 *
4616 * Issues a FW command through the given mailbox to write a PHY register.
4617 */
4620 {
4621 u32 ldst_addrspace;
4628 ldst_addrspace);
4636 }
4638 /**
4639 * t4_sge_decode_idma_state - decode the idma state
4640 * @adap: the adapter
4641 * @state: the state idma is stuck in
4642 */
4644 {
4681 };
4716 };
4718 SGE_DEBUG_DATA_LOW_INDEX_2_A,
4719 SGE_DEBUG_DATA_LOW_INDEX_3_A,
4720 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
4721 };
4732 }
4736 else
4742 }
4744 /**
4745 * t4_sge_ctxt_flush - flush the SGE context cache
4746 * @adap: the adapter
4747 * @mbox: mailbox to use for the FW command
4748 *
4749 * Issues a FW command through the given mailbox to flush the
4750 * SGE context cache.
4751 */
4753 {
4755 u32 ldst_addrspace;
4762 ldst_addrspace);
4768 }
4770 /**
4771 * t4_fw_hello - establish communication with FW
4772 * @adap: the adapter
4773 * @mbox: mailbox to use for the FW command
4774 * @evt_mbox: mailbox to receive async FW events
4775 * @master: specifies the caller's willingness to be the device master
4776 * @state: returns the current device state (if non-NULL)
4777 *
4778 * Issues a command to establish communication with FW. Returns either
4779 * an error (negative integer) or the mailbox of the Master PF.
4780 */
4783 {
4786 u32 v;
4790 retry:
4800 FW_HELLO_CMD_CLEARINIT_F);
4802 /*
4803 * Issue the HELLO command to the firmware. If it's not successful
4804 * but indicates that we got a "busy" or "timeout" condition, retry
4805 * the HELLO until we exhaust our retry limit. If we do exceed our
4806 * retry limit, check to see if the firmware left us any error
4807 * information and report that if so.
4808 */
4816 }
4825 else
4827 }
4829 /*
4830 * If we're not the Master PF then we need to wait around for the
4831 * Master PF Driver to finish setting up the adapter.
4832 *
4833 * Note that we also do this wait if we're a non-Master-capable PF and
4834 * there is no current Master PF; a Master PF may show up momentarily
4835 * and we wouldn't want to fail pointlessly. (This can happen when an
4836 * OS loads lots of different drivers rapidly at the same time). In
4837 * this case, the Master PF returned by the firmware will be
4838 * PCIE_FW_MASTER_M so the test below will work ...
4839 */
4844 /*
4845 * Wait for the firmware to either indicate an error or
4846 * initialized state. If we see either of these we bail out
4847 * and report the issue to the caller. If we exhaust the
4848 * "hello timeout" and we haven't exhausted our retries, try
4849 * again. Otherwise bail with a timeout error.
4850 */
4852 u32 pcie_fw;
4857 /*
4858 * If neither Error nor Initialialized are indicated
4859 * by the firmware keep waiting till we exaust our
4860 * timeout ... and then retry if we haven't exhausted
4861 * our retries ...
4862 */
4870 }
4872 }
4874 /*
4875 * We either have an Error or Initialized condition
4876 * report errors preferentially.
4877 */
4883 }
4885 /*
4886 * If we arrived before a Master PF was selected and
4887 * there's not a valid Master PF, grab its identity
4888 * for our caller.
4889 */
4894 }
4895 }
4898 }
4900 /**
4901 * t4_fw_bye - end communication with FW
4902 * @adap: the adapter
4903 * @mbox: mailbox to use for the FW command
4904 *
4905 * Issues a command to terminate communication with FW.
4906 */
4908 {
4914 }
4916 /**
4917 * t4_init_cmd - ask FW to initialize the device
4918 * @adap: the adapter
4919 * @mbox: mailbox to use for the FW command
4920 *
4921 * Issues a command to FW to partially initialize the device. This
4922 * performs initialization that generally doesn't depend on user input.
4923 */
4925 {
4931 }
4933 /**
4934 * t4_fw_reset - issue a reset to FW
4935 * @adap: the adapter
4936 * @mbox: mailbox to use for the FW command
4937 * @reset: specifies the type of reset to perform
4938 *
4939 * Issues a reset command of the specified type to FW.
4940 */
4942 {
4949 }
4951 /**
4952 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
4953 * @adap: the adapter
4954 * @mbox: mailbox to use for the FW RESET command (if desired)
4955 * @force: force uP into RESET even if FW RESET command fails
4956 *
4957 * Issues a RESET command to firmware (if desired) with a HALT indication
4958 * and then puts the microprocessor into RESET state. The RESET command
4959 * will only be issued if a legitimate mailbox is provided (mbox <=
4960 * PCIE_FW_MASTER_M).
4961 *
4962 * This is generally used in order for the host to safely manipulate the
4963 * adapter without fear of conflicting with whatever the firmware might
4964 * be doing. The only way out of this state is to RESTART the firmware
4965 * ...
4966 */
4968 {
4971 /*
4972 * If a legitimate mailbox is provided, issue a RESET command
4973 * with a HALT indication.
4974 */
4983 }
4985 /*
4986 * Normally we won't complete the operation if the firmware RESET
4987 * command fails but if our caller insists we'll go ahead and put the
4988 * uP into RESET. This can be useful if the firmware is hung or even
4989 * missing ... We'll have to take the risk of putting the uP into
4990 * RESET without the cooperation of firmware in that case.
4991 *
4992 * We also force the firmware's HALT flag to be on in case we bypassed
4993 * the firmware RESET command above or we're dealing with old firmware
4994 * which doesn't have the HALT capability. This will serve as a flag
4995 * for the incoming firmware to know that it's coming out of a HALT
4996 * rather than a RESET ... if it's new enough to understand that ...
4997 */
5001 PCIE_FW_HALT_F);
5002 }
5004 /*
5005 * And we always return the result of the firmware RESET command
5006 * even when we force the uP into RESET ...
5007 */
5009 }
5011 /**
5012 * t4_fw_restart - restart the firmware by taking the uP out of RESET
5013 * @adap: the adapter
5014 * @reset: if we want to do a RESET to restart things
5015 *
5016 * Restart firmware previously halted by t4_fw_halt(). On successful
5017 * return the previous PF Master remains as the new PF Master and there
5018 * is no need to issue a new HELLO command, etc.
5019 *
5020 * We do this in two ways:
5021 *
5022 * 1. If we're dealing with newer firmware we'll simply want to take
5023 * the chip's microprocessor out of RESET. This will cause the
5024 * firmware to start up from its start vector. And then we'll loop
5025 * until the firmware indicates it's started again (PCIE_FW.HALT
5026 * reset to 0) or we timeout.
5027 *
5028 * 2. If we're dealing with older firmware then we'll need to RESET
5029 * the chip since older firmware won't recognize the PCIE_FW.HALT
5030 * flag and automatically RESET itself on startup.
5031 */
5033 {
5035 /*
5036 * Since we're directing the RESET instead of the firmware
5037 * doing it automatically, we need to clear the PCIE_FW.HALT
5038 * bit.
5039 */
5042 /*
5043 * If we've been given a valid mailbox, first try to get the
5044 * firmware to do the RESET. If that works, great and we can
5045 * return success. Otherwise, if we haven't been given a
5046 * valid mailbox or the RESET command failed, fall back to
5047 * hitting the chip with a hammer.
5048 */
5055 }
5068 }
5070 }
5072 }
5074 /**
5075 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
5076 * @adap: the adapter
5077 * @mbox: mailbox to use for the FW RESET command (if desired)
5078 * @fw_data: the firmware image to write
5079 * @size: image size
5080 * @force: force upgrade even if firmware doesn't cooperate
5081 *
5082 * Perform all of the steps necessary for upgrading an adapter's
5083 * firmware image. Normally this requires the cooperation of the
5084 * existing firmware in order to halt all existing activities
5085 * but if an invalid mailbox token is passed in we skip that step
5086 * (though we'll still put the adapter microprocessor into RESET in
5087 * that case).
5088 *
5089 * On successful return the new firmware will have been loaded and
5090 * the adapter will have been fully RESET losing all previous setup
5091 * state. On unsuccessful return the adapter may be completely hosed ...
5092 * positive errno indicates that the adapter is ~probably~ intact, a
5093 * negative errno indicates that things are looking bad ...
5094 */
5097 {
5112 /*
5113 * Older versions of the firmware don't understand the new
5114 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
5115 * restart. So for newly loaded older firmware we'll have to do the
5116 * RESET for it so it starts up on a clean slate. We can tell if
5117 * the newly loaded firmware will handle this right by checking
5118 * its header flags to see if it advertises the capability.
5119 */
5122 }
5124 /**
5125 * t4_fixup_host_params - fix up host-dependent parameters
5126 * @adap: the adapter
5127 * @page_size: the host's Base Page Size
5128 * @cache_line_size: the host's Cache Line Size
5129 *
5130 * Various registers in T4 contain values which are dependent on the
5131 * host's Base Page and Cache Line Sizes. This function will fix all of
5132 * those registers with the appropriate values as passed in ...
5133 */
5136 {
5156 EGRSTATUSPAGESIZE_F,
5158 INGPADBOUNDARY_SHIFT_X) |
5161 /* T5 introduced the separation of the Free List Padding and
5162 * Packing Boundaries. Thus, we can select a smaller Padding
5163 * Boundary to avoid uselessly chewing up PCIe Link and Memory
5164 * Bandwidth, and use a Packing Boundary which is large enough
5165 * to avoid false sharing between CPUs, etc.
5166 *
5167 * For the PCI Link, the smaller the Padding Boundary the
5168 * better. For the Memory Controller, a smaller Padding
5169 * Boundary is better until we cross under the Memory Line
5170 * Size (the minimum unit of transfer to/from Memory). If we
5171 * have a Padding Boundary which is smaller than the Memory
5172 * Line Size, that'll involve a Read-Modify-Write cycle on the
5173 * Memory Controller which is never good. For T5 the smallest
5174 * Padding Boundary which we can select is 32 bytes which is
5175 * larger than any known Memory Controller Line Size so we'll
5176 * use that.
5177 *
5178 * T5 has a different interpretation of the "0" value for the
5179 * Packing Boundary. This corresponds to 16 bytes instead of
5180 * the expected 32 bytes. We never have a Packing Boundary
5181 * less than 32 bytes so we can't use that special value but
5182 * on the other hand, if we wanted 32 bytes, the best we can
5183 * really do is 64 bytes.
5184 */
5188 }
5191 EGRSTATUSPAGESIZE_F,
5197 INGPACKBOUNDARY_SHIFT_X));
5198 }
5199 /*
5200 * Adjust various SGE Free List Host Buffer Sizes.
5201 *
5202 * This is something of a crock since we're using fixed indices into
5203 * the array which are also known by the sge.c code and the T4
5204 * Firmware Configuration File. We need to come up with a much better
5205 * approach to managing this array. For now, the first four entries
5206 * are:
5207 *
5208 * 0: Host Page Size
5209 * 1: 64KB
5210 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
5211 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
5212 *
5213 * For the single-MTU buffers in unpacked mode we need to include
5214 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
5215 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
5216 * Padding boundary. All of these are accommodated in the Factory
5217 * Default Firmware Configuration File but we need to adjust it for
5218 * this host's cache line size.
5219 */
5231 }
5233 /**
5234 * t4_fw_initialize - ask FW to initialize the device
5235 * @adap: the adapter
5236 * @mbox: mailbox to use for the FW command
5237 *
5238 * Issues a command to FW to partially initialize the device. This
5239 * performs initialization that generally doesn't depend on user input.
5240 */
5242 {
5248 }
5250 /**
5251 * t4_query_params_rw - query FW or device parameters
5252 * @adap: the adapter
5253 * @mbox: mailbox to use for the FW command
5254 * @pf: the PF
5255 * @vf: the VF
5256 * @nparams: the number of parameters
5257 * @params: the parameter names
5258 * @val: the parameter values
5259 * @rw: Write and read flag
5260 *
5261 * Reads the value of FW or device parameters. Up to 7 parameters can be
5262 * queried at once.
5263 */
5267 {
5286 p++;
5287 }
5294 }
5299 {
5301 }
5303 /**
5304 * t4_set_params_timeout - sets FW or device parameters
5305 * @adap: the adapter
5306 * @mbox: mailbox to use for the FW command
5307 * @pf: the PF
5308 * @vf: the VF
5309 * @nparams: the number of parameters
5310 * @params: the parameter names
5311 * @val: the parameter values
5312 * @timeout: the timeout time
5313 *
5314 * Sets the value of FW or device parameters. Up to 7 parameters can be
5315 * specified at once.
5316 */
5321 {
5338 }
5341 }
5343 /**
5344 * t4_set_params - sets FW or device parameters
5345 * @adap: the adapter
5346 * @mbox: mailbox to use for the FW command
5347 * @pf: the PF
5348 * @vf: the VF
5349 * @nparams: the number of parameters
5350 * @params: the parameter names
5351 * @val: the parameter values
5352 *
5353 * Sets the value of FW or device parameters. Up to 7 parameters can be
5354 * specified at once.
5355 */
5359 {
5361 FW_CMD_MAX_TIMEOUT);
5362 }
5364 /**
5365 * t4_cfg_pfvf - configure PF/VF resource limits
5366 * @adap: the adapter
5367 * @mbox: mailbox to use for the FW command
5368 * @pf: the PF being configured
5369 * @vf: the VF being configured
5370 * @txq: the max number of egress queues
5371 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
5372 * @rxqi: the max number of interrupt-capable ingress queues
5373 * @rxq: the max number of interruptless ingress queues
5374 * @tc: the PCI traffic class
5375 * @vi: the max number of virtual interfaces
5376 * @cmask: the channel access rights mask for the PF/VF
5377 * @pmask: the port access rights mask for the PF/VF
5378 * @nexact: the maximum number of exact MPS filters
5379 * @rcaps: read capabilities
5380 * @wxcaps: write/execute capabilities
5381 *
5382 * Configures resource limits and capabilities for a physical or virtual
5383 * function.
5384 */
5390 {
5410 }
5412 /**
5413 * t4_alloc_vi - allocate a virtual interface
5414 * @adap: the adapter
5415 * @mbox: mailbox to use for the FW command
5416 * @port: physical port associated with the VI
5417 * @pf: the PF owning the VI
5418 * @vf: the VF owning the VI
5419 * @nmac: number of MAC addresses needed (1 to 5)
5420 * @mac: the MAC addresses of the VI
5421 * @rss_size: size of RSS table slice associated with this VI
5422 *
5423 * Allocates a virtual interface for the given physical port. If @mac is
5424 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
5425 * @mac should be large enough to hold @nmac Ethernet addresses, they are
5426 * stored consecutively so the space needed is @nmac * 6 bytes.
5427 * Returns a negative error number or the non-negative VI id.
5428 */
5432 {
5459 }
5460 }
5464 }
5466 /**
5467 * t4_free_vi - free a virtual interface
5468 * @adap: the adapter
5469 * @mbox: mailbox to use for the FW command
5470 * @pf: the PF owning the VI
5471 * @vf: the VF owning the VI
5472 * @viid: virtual interface identifiler
5473 *
5474 * Free a previously allocated virtual interface.
5475 */
5478 {
5483 FW_CMD_REQUEST_F |
5484 FW_CMD_EXEC_F |
5491 }
5493 /**
5494 * t4_set_rxmode - set Rx properties of a virtual interface
5495 * @adap: the adapter
5496 * @mbox: mailbox to use for the FW command
5497 * @viid: the VI id
5498 * @mtu: the new MTU or -1
5499 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
5500 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
5501 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
5502 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
5503 * @sleep_ok: if true we may sleep while awaiting command completion
5504 *
5505 * Sets Rx properties of a virtual interface.
5506 */
5510 {
5513 /* convert to FW values */
5537 }
5539 /**
5540 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
5541 * @adap: the adapter
5542 * @mbox: mailbox to use for the FW command
5543 * @viid: the VI id
5544 * @free: if true any existing filters for this VI id are first removed
5545 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
5546 * @addr: the MAC address(es)
5547 * @idx: where to store the index of each allocated filter
5548 * @hash: pointer to hash address filter bitmap
5549 * @sleep_ok: call is allowed to sleep
5550 *
5551 * Allocates an exact-match filter for each of the supplied addresses and
5552 * sets it to the corresponding address. If @idx is not %NULL it should
5553 * have at least @naddr entries, each of which will be set to the index of
5554 * the filter allocated for the corresponding MAC address. If a filter
5555 * could not be allocated for an address its index is set to 0xffff.
5556 * If @hash is not %NULL addresses that fail to allocate an exact filter
5557 * are hashed and update the hash filter bitmap pointed at by @hash.
5558 *
5559 * Returns a negative error number or the number of filters allocated.
5560 */
5564 {
5584 FW_CMD_REQUEST_F |
5585 FW_CMD_WRITE_F |
5596 FW_VI_MAC_ADD_MAC));
5599 }
5601 /* It's okay if we run out of space in our MAC address arena.
5602 * Some of the addresses we submit may get stored so we need
5603 * to run through the reply to see what the results were ...
5604 */
5617 nfilters++;
5621 }
5626 }
5631 }
5633 /**
5634 * t4_change_mac - modifies the exact-match filter for a MAC address
5635 * @adap: the adapter
5636 * @mbox: mailbox to use for the FW command
5637 * @viid: the VI id
5638 * @idx: index of existing filter for old value of MAC address, or -1
5639 * @addr: the new MAC address value
5640 * @persist: whether a new MAC allocation should be persistent
5641 * @add_smt: if true also add the address to the HW SMT
5642 *
5643 * Modifies an exact-match filter and sets it to the new MAC address.
5644 * Note that in general it is not possible to modify the value of a given
5645 * filter so the generic way to modify an address filter is to free the one
5646 * being used by the old address value and allocate a new filter for the
5647 * new address value. @idx can be -1 if the address is a new addition.
5648 *
5649 * Returns a negative error number or the index of the filter with the new
5650 * MAC value.
5651 */
5654 {
5679 }
5681 }
5683 /**
5684 * t4_set_addr_hash - program the MAC inexact-match hash filter
5685 * @adap: the adapter
5686 * @mbox: mailbox to use for the FW command
5687 * @viid: the VI id
5688 * @ucast: whether the hash filter should also match unicast addresses
5689 * @vec: the value to be written to the hash filter
5690 * @sleep_ok: call is allowed to sleep
5691 *
5692 * Sets the 64-bit inexact-match hash filter for a virtual interface.
5693 */
5696 {
5708 }
5710 /**
5711 * t4_enable_vi_params - enable/disable a virtual interface
5712 * @adap: the adapter
5713 * @mbox: mailbox to use for the FW command
5714 * @viid: the VI id
5715 * @rx_en: 1=enable Rx, 0=disable Rx
5716 * @tx_en: 1=enable Tx, 0=disable Tx
5717 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
5718 *
5719 * Enables/disables a virtual interface. Note that setting DCB Enable
5720 * only makes sense when enabling a Virtual Interface ...
5721 */
5724 {
5736 }
5738 /**
5739 * t4_enable_vi - enable/disable a virtual interface
5740 * @adap: the adapter
5741 * @mbox: mailbox to use for the FW command
5742 * @viid: the VI id
5743 * @rx_en: 1=enable Rx, 0=disable Rx
5744 * @tx_en: 1=enable Tx, 0=disable Tx
5745 *
5746 * Enables/disables a virtual interface.
5747 */
5750 {
5752 }
5754 /**
5755 * t4_identify_port - identify a VI's port by blinking its LED
5756 * @adap: the adapter
5757 * @mbox: mailbox to use for the FW command
5758 * @viid: the VI id
5759 * @nblinks: how many times to blink LED at 2.5 Hz
5760 *
5761 * Identifies a VI's port by blinking its LED.
5762 */
5765 {
5775 }
5777 /**
5778 * t4_iq_free - free an ingress queue and its FLs
5779 * @adap: the adapter
5780 * @mbox: mailbox to use for the FW command
5781 * @pf: the PF owning the queues
5782 * @vf: the VF owning the queues
5783 * @iqtype: the ingress queue type
5784 * @iqid: ingress queue id
5785 * @fl0id: FL0 queue id or 0xffff if no attached FL0
5786 * @fl1id: FL1 queue id or 0xffff if no attached FL1
5787 *
5788 * Frees an ingress queue and its associated FLs, if any.
5789 */
5793 {
5806 }
5808 /**
5809 * t4_eth_eq_free - free an Ethernet egress queue
5810 * @adap: the adapter
5811 * @mbox: mailbox to use for the FW command
5812 * @pf: the PF owning the queue
5813 * @vf: the VF owning the queue
5814 * @eqid: egress queue id
5815 *
5816 * Frees an Ethernet egress queue.
5817 */
5820 {
5831 }
5833 /**
5834 * t4_ctrl_eq_free - free a control egress queue
5835 * @adap: the adapter
5836 * @mbox: mailbox to use for the FW command
5837 * @pf: the PF owning the queue
5838 * @vf: the VF owning the queue
5839 * @eqid: egress queue id
5840 *
5841 * Frees a control egress queue.
5842 */
5845 {
5856 }
5858 /**
5859 * t4_ofld_eq_free - free an offload egress queue
5860 * @adap: the adapter
5861 * @mbox: mailbox to use for the FW command
5862 * @pf: the PF owning the queue
5863 * @vf: the VF owning the queue
5864 * @eqid: egress queue id
5865 *
5866 * Frees a control egress queue.
5867 */
5870 {
5881 }
5883 /**
5884 * t4_handle_fw_rpl - process a FW reply message
5885 * @adap: the adapter
5886 * @rpl: start of the FW message
5887 *
5888 * Processes a FW message, such as link state change messages.
5889 */
5891 {
5925 }
5929 }
5930 }
5932 }
5935 {
5936 u16 val;
5942 }
5943 }
5945 /**
5946 * init_link_config - initialize a link's SW state
5947 * @lc: structure holding the link state
5948 * @caps: link capabilities
5949 *
5950 * Initializes the SW state maintained for each link, including the link's
5951 * capabilities and default speed/flow-control/autonegotiation settings.
5952 */
5954 {
5966 }
5967 }
5969 #define CIM_PF_NOACCESS 0xeeeeeeee
5972 {
5973 u32 whoami;
5982 }
5985 u32 vendor_and_model_id;
5986 u32 size_mb;
5987 };
5990 {
5991 /* Table for non-Numonix supported flash parts. Numonix parts are left
5992 * to the preexisting code. All flash parts have 64KB sectors.
5993 */
5996 };
5999 u32 info;
6014 }
6023 else
6033 }
6036 {
6037 u16 val;
6038 u32 pcie_cap;
6048 }
6049 }
6051 /**
6052 * t4_prep_adapter - prepare SW and HW for operation
6053 * @adapter: the adapter
6054 * @reset: if true perform a HW reset
6055 *
6056 * Initialize adapter SW state for the various HW modules, set initial
6057 * values for some adapter tunables, take PHYs out of reset, and
6058 * initialize the MDIO interface.
6059 */
6061 {
6064 u32 pl_rev;
6073 }
6075 /* Retrieve adapter's device ID
6076 */
6085 NUM_MPS_CLS_SRAM_L_INSTANCES;
6094 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6103 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6110 device_id);
6112 }
6117 /*
6118 * Default port for debugging in case we can't reach FW.
6119 */
6124 /* Set pci completion timeout value to 4 seconds. */
6127 }
6129 /**
6130 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
6131 * @adapter: the adapter
6132 * @qid: the Queue ID
6133 * @qtype: the Ingress or Egress type for @qid
6134 * @user: true if this request is for a user mode queue
6135 * @pbar2_qoffset: BAR2 Queue Offset
6136 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
6137 *
6138 * Returns the BAR2 SGE Queue Registers information associated with the
6139 * indicated Absolute Queue ID. These are passed back in return value
6140 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
6141 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
6142 *
6143 * This may return an error which indicates that BAR2 SGE Queue
6144 * registers aren't available. If an error is not returned, then the
6145 * following values are returned:
6146 *
6147 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
6148 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
6149 *
6150 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
6151 * require the "Inferred Queue ID" ability may be used. E.g. the
6152 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
6153 * then these "Inferred Queue ID" register may not be used.
6154 */
6161 {
6166 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
6170 /* Get our SGE Page Size parameters.
6171 */
6175 /* Get the right Queues per Page parameters for our Queue.
6176 */
6182 /* Calculate the basics of the BAR2 SGE Queue register area:
6183 * o The BAR2 page the Queue registers will be in.
6184 * o The BAR2 Queue ID.
6185 * o The BAR2 Queue ID Offset into the BAR2 page.
6186 */
6191 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
6192 * hardware will infer the Absolute Queue ID simply from the writes to
6193 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
6194 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
6195 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
6196 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
6197 * from the BAR2 Page and BAR2 Queue ID.
6198 *
6199 * One important censequence of this is that some BAR2 SGE registers
6200 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
6201 * there. But other registers synthesize the SGE Queue ID purely
6202 * from the writes to the registers -- the Write Combined Doorbell
6203 * Buffer is a good example. These BAR2 SGE Registers are only
6204 * available for those BAR2 SGE Register areas where the SGE Absolute
6205 * Queue ID can be inferred from simple writes.
6206 */
6212 }
6217 }
6219 /**
6220 * t4_init_devlog_params - initialize adapter->params.devlog
6221 * @adap: the adapter
6222 *
6223 * Initialize various fields of the adapter's Firmware Device Log
6224 * Parameters structure.
6225 */
6227 {
6229 u32 pf_dparams;
6234 /* If we're dealing with newer firmware, the Device Log Paramerters
6235 * are stored in a designated register which allows us to access the
6236 * Device Log even if we can't talk to the firmware.
6237 */
6238 pf_dparams =
6251 }
6253 /* Otherwise, ask the firmware for it's Device Log Parameters.
6254 */
6264 devlog_meminfo =
6271 }
6273 /**
6274 * t4_init_sge_params - initialize adap->params.sge
6275 * @adapter: the adapter
6276 *
6277 * Initialize various fields of the adapter's SGE Parameters structure.
6278 */
6280 {
6285 /* Extract the SGE Page Size for our PF.
6286 */
6292 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
6293 */
6302 }
6304 /**
6305 * t4_init_tp_params - initialize adap->params.tp
6306 * @adap: the adapter
6307 *
6308 * Initialize various fields of the adapter's TP Parameters structure.
6309 */
6311 {
6313 u32 v;
6319 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
6323 /* Cache the adapter's Compressed Filter Mode and global Incress
6324 * Configuration.
6325 */
6334 TP_VLAN_PRI_MAP_A);
6337 TP_INGRESS_CONFIG_A);
6338 }
6340 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
6341 * shift positions of several elements of the Compressed Filter Tuple
6342 * for this adapter which we need frequently ...
6343 */
6348 PROTOCOL_F);
6350 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
6351 * represents the presence of an Outer VLAN instead of a VNIC ID.
6352 */
6357 }
6359 /**
6360 * t4_filter_field_shift - calculate filter field shift
6361 * @adap: the adapter
6362 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
6363 *
6364 * Return the shift position of a filter field within the Compressed
6365 * Filter Tuple. The filter field is specified via its selection bit
6366 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
6367 */
6369 {
6409 }
6410 }
6412 }
6415 {
6433 }
6435 }
6438 {
6452 j++;
6492 j++;
6493 }
6495 }
6497 /**
6498 * t4_read_cimq_cfg - read CIM queue configuration
6499 * @adap: the adapter
6500 * @base: holds the queue base addresses in bytes
6501 * @size: holds the queue sizes in bytes
6502 * @thres: holds the queue full thresholds in bytes
6503 *
6504 * Returns the current configuration of the CIM queues, starting with
6505 * the IBQs, then the OBQs.
6506 */
6508 {
6517 /* value is in 256-byte units */
6521 }
6526 /* value is in 256-byte units */
6529 }
6530 }
6532 /**
6533 * t4_read_cim_ibq - read the contents of a CIM inbound queue
6534 * @adap: the adapter
6535 * @qid: the queue index
6536 * @data: where to store the queue contents
6537 * @n: capacity of @data in 32-bit words
6538 *
6539 * Reads the contents of the selected CIM queue starting at address 0 up
6540 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
6541 * error and the number of 32-bit words actually read on success.
6542 */
6544 {
6556 /* It might take 3-10ms before the IBQ debug read access is allowed.
6557 * Wait for 1 Sec with a delay of 1 usec.
6558 */
6563 IBQDBGEN_F);
6569 }
6572 }
6574 /**
6575 * t4_read_cim_obq - read the contents of a CIM outbound queue
6576 * @adap: the adapter
6577 * @qid: the queue index
6578 * @data: where to store the queue contents
6579 * @n: capacity of @data in 32-bit words
6580 *
6581 * Reads the contents of the selected CIM queue starting at address 0 up
6582 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
6583 * error and the number of 32-bit words actually read on success.
6584 */
6586 {
6606 OBQDBGEN_F);
6612 }
6615 }
6617 /**
6618 * t4_cim_read - read a block from CIM internal address space
6619 * @adap: the adapter
6620 * @addr: the start address within the CIM address space
6621 * @n: number of words to read
6622 * @valp: where to store the result
6623 *
6624 * Reads a block of 4-byte words from the CIM intenal address space.
6625 */
6628 {
6640 }
6642 }
6644 /**
6645 * t4_cim_write - write a block into CIM internal address space
6646 * @adap: the adapter
6647 * @addr: the start address within the CIM address space
6648 * @n: number of words to write
6649 * @valp: set of values to write
6650 *
6651 * Writes a block of 4-byte words into the CIM intenal address space.
6652 */
6655 {
6666 }
6668 }
6672 {
6674 }
6676 /**
6677 * t4_cim_read_la - read CIM LA capture buffer
6678 * @adap: the adapter
6679 * @la_buf: where to store the LA data
6680 * @wrptr: the HW write pointer within the capture buffer
6681 *
6682 * Reads the contents of the CIM LA buffer with the most recent entry at
6683 * the end of the returned data and with the entry at @wrptr first.
6684 * We try to leave the LA in the running state we find it in.
6685 */
6687 {
6699 }
6720 }
6725 }
6726 restart:
6732 }
6734 }
6736 /**
6737 * t4_tp_read_la - read TP LA capture buffer
6738 * @adap: the adapter
6739 * @la_buf: where to store the LA data
6740 * @wrptr: the HW write pointer within the capture buffer
6741 *
6742 * Reads the contents of the TP LA buffer with the most recent entry at
6743 * the end of the returned data and with the entry at @wrptr first.
6744 * We leave the LA in the running state we find it in.
6745 */
6747 {
6772 }
6774 /* Wipe out last entry if it isn't valid */
6781 }
6783 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
6784 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
6785 * state for more than the Warning Threshold then we'll issue a warning about
6786 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
6787 * appears to be hung every Warning Repeat second till the situation clears.
6788 * If the situation clears, we'll note that as well.
6789 */
6790 #define SGE_IDMA_WARN_THRESH 1
6791 #define SGE_IDMA_WARN_REPEAT 300
6793 /**
6794 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
6795 * @adapter: the adapter
6796 * @idma: the adapter IDMA Monitor state
6797 *
6798 * Initialize the state of an SGE Ingress DMA Monitor.
6799 */
6802 {
6803 /* Initialize the state variables for detecting an SGE Ingress DMA
6804 * hang. The SGE has internal counters which count up on each clock
6805 * tick whenever the SGE finds its Ingress DMA State Engines in the
6806 * same state they were on the previous clock tick. The clock used is
6807 * the Core Clock so we have a limit on the maximum "time" they can
6808 * record; typically a very small number of seconds. For instance,
6809 * with a 600MHz Core Clock, we can only count up to a bit more than
6810 * 7s. So we'll synthesize a larger counter in order to not run the
6811 * risk of having the "timers" overflow and give us the flexibility to
6812 * maintain a Hung SGE State Machine of our own which operates across
6813 * a longer time frame.
6814 */
6818 }
6820 /**
6821 * t4_idma_monitor - monitor SGE Ingress DMA state
6822 * @adapter: the adapter
6823 * @idma: the adapter IDMA Monitor state
6824 * @hz: number of ticks/second
6825 * @ticks: number of ticks since the last IDMA Monitor call
6826 */
6830 {
6833 /* Read the SGE Debug Ingress DMA Same State Count registers. These
6834 * are counters inside the SGE which count up on each clock when the
6835 * SGE finds its Ingress DMA State Engines in the same states they
6836 * were in the previous clock. The counters will peg out at
6837 * 0xffffffff without wrapping around so once they pass the 1s
6838 * threshold they'll stay above that till the IDMA state changes.
6839 */
6847 /* If the Ingress DMA Same State Counter ("timer") is less
6848 * than 1s, then we can reset our synthesized Stall Timer and
6849 * continue. If we have previously emitted warnings about a
6850 * potential stalled Ingress Queue, issue a note indicating
6851 * that the Ingress Queue has resumed forward progress.
6852 */
6861 }
6863 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
6864 * domain. The first time we get here it'll be because we
6865 * passed the 1s Threshold; each additional time it'll be
6866 * because the RX Timer Callback is being fired on its regular
6867 * schedule.
6868 *
6869 * If the stall is below our Potential Hung Ingress Queue
6870 * Warning Threshold, continue.
6871 */
6878 }
6883 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
6884 */
6889 /* Read and save the SGE IDMA State and Queue ID information.
6890 * We do this every time in case it changes across time ...
6891 * can't be too careful ...
6892 */
6907 }
6908 }